TWI281216B - Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer - Google Patents

Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer Download PDF

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TWI281216B
TWI281216B TW94115631A TW94115631A TWI281216B TW I281216 B TWI281216 B TW I281216B TW 94115631 A TW94115631 A TW 94115631A TW 94115631 A TW94115631 A TW 94115631A TW I281216 B TWI281216 B TW I281216B
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Taiwan
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plasma
conductor layer
layer
copper
conductor
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TW94115631A
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Chinese (zh)
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TW200607025A (en
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Chao-Hsien Peng
Jing-Cheng Lin
Ching-Hua Hsieh
Shau-Lin Shue
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Taiwan Semiconductor Mfg
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Abstract

A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

Description

1281216 九、發明說明: 【發明所屬之技術領域】 且特冽 方法有 本發明是有關於一種製造微電子產品之方法, 是與一種在製造微電子產品時,清除氧化導體層之 關。 【先前技術】 微電子產品之作法,係在一基板上形成多層圖案化導 體層,而各導體層間則以介電層加以隔離。 當微電子產品之積體化程度越高,使用包含導電材料 層之圖案化銅來製造微電子產品變得越來越盛行,而這此 導電材料層則以低介電常數之介電層來進行隔離。當 微電子產品時,常使用含導電材料之銅,用以提供導電效 率之改善。而所謂低介電常數介電材料,係指介電常數約 低於4之介電材料,而藉由使用這些低介電常數之介電材 料可降低彼此導體層間之干擾。 雖然在製造微電子產品中,使用包含導電材料之銅和 低介電常數介電材料係相當普遍的,然而並非完全沒有問 題存在。特料,在製造微電子產品時,制包含導電材 料之銅,對於低介電常數之介電材料内擴散相當不利。除 此之外’由於低介電常數之介電材料具易碎之機械性質, 因此包含導電材料之銅易受侵人與氧化之影響。上述材料 之限制’常會影響微電子產品電性和可信度之表現。 因此對於一種製造具改善電性和可信度表現之微電子 1281216 95. a 產品存有一需求,且此 銅並藉由低介電常數介 本案即是針對上述 之 从電子產品係使用包含導電材料 電材料來進行導體層隔離。 目的所為之發明。 【發明内容】 本么月之第一目的係提供製造微電子產品之方法,里 中此微電子產品具有包含導電材料層之圖㈣銅,且各導 電材料層間係藉由低介電常數介電材料層來彼此隔離。 、本發明之第二目的係根據本發明之第-目的所提供之 方法’其中所製造之微電子產品具有改善之電性和可庐度 表現。 口 根據本^ a月之目的,本發明提供一種製造微電子產品 之方法。 根據本發明之-實施例,首先提供一基板。一含導體 層之銅形成於此基板上。接著,此含㈣層之㈣㈣— 含氫電漿進行處理,用㈣成_經過含氫㈣處理後之含 導體層之銅。最後,此經過含氫電漿處理後之含導體層之 銅會再經由—含氬電㈣行處理1㈣成-經全處i後 之含導體層之銅。 接著-第二導體層,例如一導體阻障層,會形成於此 經全處理後之含導體層銅上方’用以進__步製程微電子產 品。此第二導體層可利肢積之方法,例如化學氣相沈積 法或更特別地原子層沈積法,仙金屬和含揮發原材料之 碳來加以形成之。此最後所形成之第二導體層具有改盖 1281216 電性特性,因此可提供微電子產品更好之可信度。 一在一通常之實施例中,本發明最主要之目的為,提供 一利用連續還原電漿和鈍氣電漿處理方法來清潔_氧化導 體層。然後第二導體層即可形成於此經過—系列電聚 處理後之氧化導體層上方,當此第二導體層利用化學氣相 沈積法,例如原子層沈積法,並使用金屬和含揮發原材料 之石厌來加以形成時,此最後所形成之第二導體層具有改盖 電性特性和可信度。 ° 本發明之方法係考量一根據本發明方法製造之微電子 σα ° 本發明提供一製造一微電子產品之方法,其中此微電 子產:具有包含導電材料層之圖案化銅,且各導電材料層 ^係藉由低介電常數介電材料層來彼此隔離,此微電子產 品具有改善之可信度表現。 一本發明為了實現上述之目的,對於位於微電子產品中 W導電材料層之銅,會先使用一含氫電聚(通常為一低 電漿j進行處理後,接著再使用一含氬電漿(通常為一鈍 氣電漿)進行處理。在經過此一系列之電漿處理後,一第 一導體層,例如一導體阻障層,會沈積於此經全處理後之 否導體層銅上方,用以使得此第二導體層具有改善之導電 寺矛了 L度。當此第二導體層係利用化學氣相沈積法, 例士原子層沈積法,並使用金屬和含揮發原材料之碳來加 以形成時,本發明之方法特別有用。1281216 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of manufacturing a microelectronic product, which is related to the removal of an oxide conductor layer in the manufacture of a microelectronic product. [Prior Art] A microelectronic product is a method in which a plurality of patterned conductor layers are formed on a substrate, and dielectric layers are separated by dielectric layers. When the degree of integration of microelectronic products is higher, it is becoming more and more popular to manufacture microelectronic products using patterned copper containing a layer of conductive material, which is a dielectric layer with a low dielectric constant. Isolation. In the case of microelectronics, copper containing conductive materials is often used to provide improved conductivity. The so-called low-k dielectric material refers to a dielectric material having a dielectric constant of less than about 4, and the use of these low dielectric constant dielectric materials can reduce the interference between the conductor layers of each other. Although the use of copper and low dielectric constant dielectric materials containing conductive materials is quite common in the manufacture of microelectronic products, it is not entirely problem free. In particular, in the manufacture of microelectronic products, the preparation of copper containing electrically conductive materials is quite disadvantageous for diffusion in dielectric materials of low dielectric constant. In addition, since a low dielectric constant dielectric material has a fragile mechanical property, copper containing a conductive material is susceptible to intrusion and oxidation. The limitations of the above materials often affect the performance of the electrical and reliability of microelectronic products. Therefore, there is a need for a microelectronics 1281216 95. a product that has improved electrical and reliability performance, and the copper is used in the electronic product system to contain conductive materials by using a low dielectric constant. Electrical material for conductor layer isolation. The purpose of the invention. SUMMARY OF THE INVENTION The first object of the present month is to provide a method for manufacturing a microelectronic product, wherein the microelectronic product has a picture (4) of copper comprising a layer of a conductive material, and each of the layers of the conductive material is dielectrically bonded by a low dielectric constant. The layers of material are isolated from each other. A second object of the present invention is the method according to the first aspect of the present invention, wherein the microelectronic product produced has improved electrical and achievable performance. According to the purpose of the present invention, the present invention provides a method of manufacturing a microelectronic product. According to an embodiment of the invention, a substrate is first provided. A copper layer containing a conductor layer is formed on the substrate. Next, the (four) (four)-hydrogen-containing plasma of the (four) layer is treated, and the copper containing the conductor layer after the treatment with hydrogen (four) is used. Finally, the copper containing the conductor layer after the treatment with the hydrogen-containing plasma is further processed through the argon-containing (four) row to form the copper of the conductor-containing layer after the first (four)-through. Next, a second conductor layer, such as a conductor barrier layer, is formed over the fully processed copper layer containing the conductor layer to process the microelectronic product. This second conductor layer can be formed by a method of prosthesis, such as chemical vapor deposition or, more particularly, atomic layer deposition, a metal of a volatile metal and a volatile raw material. This last formed second conductor layer has the electrical characteristics of the cover 1281216, thus providing better confidence in the microelectronics. In a typical embodiment, the primary object of the present invention is to provide a method of cleaning a oxidized conductor layer using a continuous reduction plasma and a blunt plasma treatment. Then, the second conductor layer can be formed above the oxidation conductor layer after the series electropolymerization treatment, and the second conductor layer is formed by chemical vapor deposition, such as atomic layer deposition, using metal and volatile raw materials. When the stone is formed, the second conductor layer formed at the end has the electrical property and reliability of the cover. The method of the present invention contemplates a microelectronic σα ° manufactured according to the method of the present invention. The present invention provides a method of fabricating a microelectronic product, wherein the microelectronic product: patterned copper having a layer of conductive material, and each conductive material The layers are isolated from each other by a layer of low dielectric constant dielectric material, and the microelectronic product has improved reliability performance. In order to achieve the above object, in the case of copper in a layer of W conductive material in a microelectronic product, a hydrogen-containing electropolymerization (usually a low plasma j treatment followed by an argon-containing plasma) is used. (usually a blunt gas plasma). After a series of plasma treatments, a first conductor layer, such as a conductor barrier layer, is deposited over the fully processed copper layer of the conductor layer. In order to make the second conductor layer have an improved conductivity, the second conductor layer is formed by chemical vapor deposition, atomic layer deposition, and using metal and carbon containing volatile raw materials. The method of the invention is particularly useful when formed.

1281216 【實施方式】 本發明提供一種製造微電子產品之方法,其中此微電 子產品具有包含導電材料層之圖案化銅,且各導電材料層 間係藉由低介電常數介電材料層來彼此隔離,藉以增進微 電子產品之電性和可信度表現。 在一特定實施例中,本發明為了實現上述之目的,對 於位於微電子產品中之包含導電材料層之銅,會先使用一 含氫電漿進行處理後,接著再使用一含氬電漿進行處理。 在經過此一系列之電漿處理後,一第二導體層,例如一導 體阻障層,會沈積於此經全處理後之含導體層銅上方,用 以使彳于此位於微電子產品中之第二導體層具有改善之導電 特性和可信度。 在一通常之實施例中,本發明利用還原電漿和鈍氣電 漿來處理一氧化導體層。然後,一第二導體層即可形成於 此經過一系列電漿處理後之氧化導體層上方,此形成之第 二導體層具有改善電性特性和可信度。 第1圖至第6圖展示一系列之概略剖視圖,其係根據 本t明較佳具體實施例來製造一微電子產品時每一進行階 ^又之圖不。第1圖展示製造微電子產品時之最初階段概略 剖視圖。 榮 1 门 圖展示一基板10。一含導體層圖案銅12形成於此 中 又鎮敗孔(dual damascene aperture ) 11 暴 導體層圖案化鋼12之-部分。此雙職孔U是藉 下述之結構來加以定義,(1) 一對圖案化之第一阻障層14 a 1281216 95·爭1281216 [Embodiment] The present invention provides a method of manufacturing a microelectronic product, wherein the microelectronic product has patterned copper comprising a layer of conductive material, and each layer of conductive material is isolated from each other by a layer of low dielectric constant dielectric material In order to enhance the electrical and credibility of microelectronic products. In a specific embodiment, in order to achieve the above object, the copper containing the conductive material layer in the microelectronic product is treated with a hydrogen-containing plasma followed by an argon-containing plasma. deal with. After the series of plasma treatments, a second conductor layer, such as a conductor barrier layer, is deposited over the fully processed copper containing conductor layer for use in the microelectronics. The second conductor layer has improved electrical conductivity and reliability. In a typical embodiment, the present invention utilizes a reducing plasma and a blunt plasma to treat an oxidized conductor layer. Then, a second conductor layer can be formed over the series of plasma-treated oxide conductor layers, and the second conductor layer formed has improved electrical characteristics and reliability. Figures 1 through 6 show a series of schematic cross-sectional views of each of the steps of fabricating a microelectronic product in accordance with a preferred embodiment of the present invention. Figure 1 shows a schematic cross-sectional view of the initial stage of manufacturing a microelectronic product. Rong 1 The door shows a substrate 10. A conductor layer-containing pattern copper 12 is formed therein and a dual damascene aperture 11 is a portion of the conductor layer patterned steel 12. The double-hole U is defined by the following structure: (1) a pair of patterned first barrier layers 14 a 1281216 95·

El 替-換頁 和14b ; (2)—對圖案化之第一介電層i6a和16b,形成且排 列於此對圖案化之第一阻障層14a和14b之上;(3)—對圖 案化之餘刻停止層18a和18b,形成且排列於此對圖案化之 弟一 ’丨電層16a和16b之上;(4) 一對圖案化之第二介電層 20a和20b,形成且嵌入進此對圖案化之蝕刻停止層i8a和 18b之上’並排成一列;(5) 一對圖案化平坦停止層22a和 22b ’形成且排列於此對圖案化之第二介電層2〇a和2〇b之El for the page change and 14b; (2) - for the patterned first dielectric layers i6a and 16b, formed and arranged on the first patterned barrier layers 14a and 14b; (3) - the pattern The remaining stop layers 18a and 18b are formed and arranged on the pair of patterned dielectric layers 16a and 16b; (4) a pair of patterned second dielectric layers 20a and 20b are formed and formed Embedded in the patterned etch stop layers i8a and 18b' side by side in a row; (5) a pair of patterned flat stop layers 22a and 22b' formed and arranged in the pair of patterned second dielectric layers 2 〇a and 2〇b

上。 使用於微電子產品中之基板1 〇,係選自於由積體電路 產口α陶兗基板產品和光電基板產品所形成之群組中,但 不以此為限,一般而言,基板1〇包括一半導體基板。 此第一含導體層圖案化銅12可由銅或銅合金來形成, 一般而言,第一含導體層圖案化銅12之線寬約微米至 10微米’而厚度約4000埃至8000埃。on. The substrate 1 使用 used in the microelectronic product is selected from the group consisting of an integrated circuit of a ceramic substrate and a photovoltaic substrate product, but is not limited thereto. Generally, the substrate 1 The crucible includes a semiconductor substrate. The first conductor-containing patterned copper 12 may be formed of copper or a copper alloy. Generally, the first conductor-containing patterned copper 12 has a line width of about micrometers to 10 micrometers and a thickness of about 4000 angstroms to 8,000 angstroms.

圖案化之第一介電層16a和16b,和圖案化之第二介電 層20a和20b可使用任何之介電材料形成。如此之介電層 =括一般高介電常數之介電材料,亦即介電常數高於4之 電材料例如,氧化石夕介電材料和氮化石夕介電材料,但 不以此為限。如此之介電層亦可包括一般低介電常數之介 電材料,亦即介電常數低於4之介電材料,例如,旋塗式 玻璃(SPin_〇n_Glass )介電材料、旋塗式高分子 (Spin-〇n-p〇lymer)介電材料、氟化物玻璃(fWosilicate glass);丨電材料和非晶炭_〇η)介電材料, 但不以此為限。 1281216The patterned first dielectric layers 16a and 16b, and the patterned second dielectric layers 20a and 20b may be formed using any dielectric material. Such a dielectric layer = a dielectric material having a generally high dielectric constant, that is, an electrical material having a dielectric constant higher than 4, for example, a oxidized oxide dielectric material and a nitride dielectric material, but not limited thereto . Such a dielectric layer may also comprise a dielectric material having a generally low dielectric constant, that is, a dielectric material having a dielectric constant lower than 4, for example, a spin-on glass (SPin_〇n_Glass) dielectric material, a spin coating type. Polymer (Spin-〇np〇lymer) dielectric material, fluoride glass (fWosilicate glass); tantalum electrical material and amorphous carbon _〇η) dielectric material, but not limited to this. 1281216

11 3 ο 月曰修(更)正替換頁 當圖案化之第一介電層16a和16b對和圖案化之第二 電層20a和20b董十,係以具有相對較低介電常數之介電 材料所形成時,圖案化之第_阻障層14_⑽對、圖案 化之姓刻停止| l8a和18b對和圖案化之平坦停止層❿ # 22b對中之每-個,—般則係以高介電常數之介電材料 來加以形成。 —一般而言,(1)圖案化之第一阻障層i4a和i4b對中之 母-個,所形成之厚度約埃至湖埃;⑺圖案化之第 一介電層16M 口 l6b對中之每_個,所形成之厚度約咖 ,至4_埃;(3)圖案化之餘刻停止層18a和l8b對中之 母個,所形成之厚度約2〇〇埃至5〇〇埃;⑷目案化之第 二介電層20M, 2〇b對中之每_個,所形成之厚度約顧 ,至4000埃,(3)圖案化之平坦停止層a。和22b對令之 每個,所形成之厚度約200埃至500埃。 =2圖展示於雙鑲嵌孔u中之側邊表面上形成一系列 =側邊間隙„ 24之結果圖。此系列選擇性側邊間 =土層24,-般係以沈積和非等向㈣刻之方法來加以形 之方=此等形成方法在微電子產品之製造技術中係屬傳統 >。此系列選擇性侧邊間隙壁層24 一般係以具高介電 二C電嶋加以形成,L材m化 弟^圖展示使用—含氫電漿26來對第2圖中之微電子 一:進仃處理後之結果圖。當此含導體層圖案化銅U經由 一 3氧電漿26進行處理後,會形成-經過含氫電漿處理後 11 1281216 Γ —力。胗(¾正雜頁] 之含導體層銅12,。-般而言,藉由此含氫電聚26之處理 過程,其主要係用以化學性降低或消除形成於含導體層圖 案化銅12上之氧化物殘留。 #供此含氫電m 26之條件為:⑴反應室壓力約在i 至lOOmtorr(陶爾);(2)無線電波波頻源能量約1〇〇至ι〇〇〇 瓦,而偏麼能量、約1〇〇至1000瓦;(3)一基板上具有含導體 層圖案化銅丨2之溫度約攝氏1〇〇至2〇〇度;(4)氫氣流量率 約為1〇0至5000標準立方公分每分鐘(standard cubic11 3 ο月曰修(more) replacement page when the patterned first dielectric layers 16a and 16b are paired with the patterned second electrical layers 20a and 20b, with a relatively low dielectric constant When the electrical material is formed, the patterned first _ barrier layer 14_(10) pair, the patterned surname stops | l8a and 18b pairs and the patterned flat stop layer ❿ # 22b pair each, generally A high dielectric constant dielectric material is formed. - In general, (1) the patterned first barrier layer i4a and i4b are centered, forming a thickness of about angstrom to lake ang; (7) patterning the first dielectric layer 16M port l6b is centered Each thickness of the film is about 4 angstroms to angstroms; (3) the patterning of the remaining layers 18a and 18b is the center of the pair, forming a thickness of about 2 angstroms to 5 angstroms. (4) The second dielectric layer 20M of the meshed dielectric layer 20M, each of the 2 〇b pairs is formed to have a thickness of about 4,000 angstroms, and (3) a patterned flat stop layer a. And 22b, each of which has a thickness of about 200 angstroms to 500 angstroms. The =2 figure shows the result of forming a series of = side gaps „ 24 on the side surfaces of the double inlaid holes u. This series of selective sides = soil layer 24, generally with deposition and non-isotropic (4) The method of engraving is to form the form = these formation methods are traditional in the manufacturing technology of microelectronic products. This series of selective side spacer layers 24 are generally formed by high dielectric two C electricity. , L material m 弟 ^ 展示 展示 展示 使用 使用 使用 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 含 含 含 含 含After the treatment of 26, it will form - after the treatment with hydrogen-containing plasma, 11 1281216 Γ - force. 胗 (3⁄4 正杂页) containing the conductor layer of copper 12, in general, by this hydrogen-containing electropolymerization 26 The treatment process is mainly used to chemically reduce or eliminate the oxide residue formed on the patterned layer 12 containing the conductor layer. # The condition for supplying the hydrogen-containing electricity m 26 is: (1) the pressure of the reaction chamber is about i to 100 mtorr ( Taur); (2) The energy of the radio wave source is about 1 〇〇 to ι〇〇〇瓦, and the energy is about 1〇〇 to 1000 watts; (3) a substrate having a patterned layer of copper ruthenium 2 having a temperature of about 1 to 2 degrees Celsius; (4) a hydrogen flow rate of about 1 to 0 to 5,000 standard cubic centimeters per minute (standard cubic

Centimeters Per Minute,SCCM);以及(5)處理時間約為 ι〇 至200秒。此含氫電漿亦可用其他種類之還原氣體,如氨 氣。 第4圖展示使用一含氬電漿28來對第3圖中之微電子 產品進行處理後之結果圖。經過含氫電漿處理後之含導體 層圖案化銅12’,會再經由一含氬電漿28進行處理,用以 形成一經含氫和含氬電漿處理後之含導體層銅12,,,此可 丨被視為經全電漿處理後之含導體層銅。於其後之例子中將 展不出,經過含氫電漿處理後之含導體層圖案化銅12,,再 經由一含氬電漿28進行處理後,可提供一優良之表面情形 來用以形成一導體層,例如一導體阻障層,使其具有優良 之電性特性。 提供此含氬電漿28之條件為:(1)反應室壓力約在丄 至10 mt〇rr(陶爾);(2)無線電波波頻源能量約6〇〇至8〇〇 瓦(而較佳的能量係約從650至750瓦),一偏壓能量約1〇 至100瓦(而較佳的能量係約從20至50瓦);(3)一基板, 12 1281216 日修(更)正皆換 其上經過含氳電漿處理後之含導體層圖案化銅12,,之溫度 約攝氏10至200度;(4)氬氣流量率約為1至2〇 SCCM(而 較佳的流量係約從5至1〇 SCCM);以及(5)處理時間約為i 至20秒(而較佳的處理時間係約從5至1〇秒)。上述之處理 條件,一般係用以提供一 “軟式,,氬電漿來處理一經過含 氫電漿處理後之含導體層圖案化銅12,。亦可用其他種類Centimeters Per Minute, SCCM); and (5) processing time is approximately ι〇 to 200 seconds. The hydrogen-containing plasma can also be used with other types of reducing gases such as ammonia. Figure 4 is a graph showing the results of processing the microelectronic product of Figure 3 using an argon-containing plasma 28. The conductive layer patterned copper 12' after being treated with hydrogen plasma is further processed through an argon-containing plasma 28 to form a conductor layer containing copper 12 after treatment with hydrogen and argon containing plasma, This can be regarded as the copper containing conductor layer after the full plasma treatment. In a subsequent example, the patterned copper layer 12 containing the conductor layer after hydrogen-containing plasma treatment, after treatment with an argon-containing plasma 28, provides an excellent surface condition for use. A conductor layer, such as a conductor barrier layer, is formed to provide excellent electrical properties. The conditions for providing the argon-containing plasma 28 are as follows: (1) the pressure in the reaction chamber is about 10 〇 〇 rr (Tayl); (2) the energy of the radio wave source is about 6 〇〇 to 8 〇〇 ( Preferably, the energy system is from about 650 to 750 watts, a bias energy is about 1 〇 to 100 watts (and the preferred energy is about 20 to 50 watts); (3) a substrate, 12 1281216 is repaired (more) The patterning copper 12 containing the conductor layer after being treated with the tantalum plasma is replaced by a temperature of about 10 to 200 degrees Celsius; (4) the flow rate of the argon gas is about 1 to 2 〇 SCCM (and preferably The flow rate is from about 5 to 1 〇 SCCM); and (5) the processing time is about i to 20 seconds (and the preferred processing time is about 5 to 1 sec). The above processing conditions are generally used to provide a "soft, argon plasma to treat a patterned layer of copper 12 after treatment with a hydrogen-containing plasma. Other types may also be used.

之鈍態氣體電漿,例如氦、氖、氪和氙之鈍態氣體電漿, 但不以此為限。 第5圖展示了在第4圖中之微電子產品上,特別係在 雙鑲嵌孔中且與一經含氫和含氬電漿處理後之含導體層銅 12’’接觸位置上,來形成一毯狀阻障層3()之結果圖。第$ 圖亦展示了毯狀含導體層之第二銅32,其係形成在毯狀阻 障層30之上。Passive gas plasmas, such as helium, neon, xenon, and krypton, are not limited to this. Figure 5 shows the microelectronics in Figure 4, particularly in a dual damascene hole and in contact with a copper-containing conductor layer 12'' after treatment with hydrogen and argon-containing plasma to form a The result of the blanket barrier layer 3 (). Figure # also shows a second copper 32 of a blanket-like conductor layer formed over the blanket barrier layer 30.

此毯狀阻障層30為一毯狀導體阻障層,可使用任何方 法和材料來加以形成。此毯狀阻障層3〇可使用物理氣相沈 積法、化學氣相沈積法和原子層沈積法(可被視為數位化 之化學氣相沈積法)來加以形成。此毯狀阻障層3〇可使用 導體之阻障材料來形成,例如鎢、鈦、鈕和其氮化物,但 不以此為限。較佳地,此毯狀阻障層3〇可使用鈕氮化物導 體阻障材料來形成,其係使用五二甲基胺鈕 (penta-dimethylamino_tantalum,Ta((CH3)2N)5)作為一氣相 金屬和一碳原材料,並利用原子層沈積法來加以形成之。 此原子層沈積法之條件為:(1)無電漿活化情形下,反 應室壓力約在1至10 mtorr(陶爾);(2)—基板10,包括一 13 1281216The blanket barrier layer 30 is a blanket conductor barrier layer that can be formed using any method and material. The blanket barrier layer 3 can be formed by physical vapor deposition, chemical vapor deposition, and atomic layer deposition (which can be regarded as a digital chemical vapor deposition method). The blanket barrier layer 3 can be formed using a barrier material of a conductor, such as tungsten, titanium, a button, and a nitride thereof, but is not limited thereto. Preferably, the blanket barrier layer 3 is formed using a nitride nitride conductor barrier material, which uses a penta-dimethylamino-tantalum (Ta((CH3)2N)5) as a gas phase. Metal and one carbon raw materials are formed by atomic layer deposition. The conditions of the atomic layer deposition method are as follows: (1) in the absence of plasma activation, the reaction chamber pressure is about 1 to 10 mtorr (Tayl); (2) - the substrate 10, including a 13 1281216

9¥T 日修(更)正替换頁丨 經含氫和含氬電漿處理後之含導體層銅12,,,之溫度約攝 、 氏100至200度;(3)五二甲基胺组源,在載氣=率約 'Ο至2000 SCCM情況下,其材料濃度約〇 5至i體積百 - 分率。—般而言,此毯狀阻障層3〇之形成厚度約在5〇至 5〇〇埃。此原子層沈積方法係採用階梯式沈積上述具階梯式 空乏之纽源材料,並選擇性進行階梯式氣處理來提供一如 氮層。 • 錄含導體層第二銅32 ’―般係使用與形成含導體層 圖案化銅12類似、相似或完全相同之方法或材料來加以形 成°_般而言’毯狀含導體層第二銅32所形成之厚度約在 1000 至 8000 埃。 第6圖展示平坦化毯狀含導體層第二銅32和毯狀阻障 層30之結果圖,其係在圖案化阻障層3〇a上形成一含導體 層圖案化第二銅32a,並使其與位於雙鑲礙孔中之一經含氯 和含氬電漿處理後之含導體層銅12,,彼此接觸。這種平坦 _ 4方法可使用傳統用以製造微電子產品技藝中所使用之方 法’特別如化學機械研磨法。 第6圖展示-根據本發明較佳具體實施例所製造之微 電子產品之概略剖視圖。此微電子產品包括一含導體層圖 案化第-銅12”、-形成於其上之阻障層術和—含導體 層之圖案化第二銅32a,其中此含導體層之圖案化第二銅 32a形成於微電子產品中之阻障層恤上。形成於含導體層 圖案化第-銅12”上方之含導體層之圖案化第二銅仏和 圖案化阻障層3〇a,具有改善之電性特性,此種改善之電性 14 1281216 I IL· 〇V ;9¥T 日修(more) is replacing the page containing copper and 12 with conductor layer treated with hydrogen and argon-containing plasma, and the temperature is about 100 to 200 degrees; (3) pentadimethylamine The group source, in the case of carrier gas = rate about 'Ο to 2000 SCCM, its material concentration is about 至5 to i volume hundred-minute. In general, the blanket barrier layer 3 is formed to a thickness of about 5 Å to 5 Å. The atomic layer deposition method uses a stepwise deposition of the above-mentioned stepped source material and selectively performs a step gas treatment to provide a nitrogen layer. • Recording the second copper 32' of the conductor layer is generally formed by a method or material similar to, similar or identical to the formation of the patterned copper 12 with a conductor layer. 32 is formed to a thickness of about 1000 to 8000 angstroms. Figure 6 is a view showing the result of flattening the blanket-like conductor layer second copper 32 and the blanket barrier layer 30, which is formed on the patterned barrier layer 3a to form a patterned second copper 32a containing a conductor layer. And contacting the conductor-containing layer copper 12, which is treated with chlorine and argon-containing plasma in one of the double-inserted holes, in contact with each other. This flat _ 4 method can use the methods conventionally used in the art of manufacturing microelectronics, particularly such as chemical mechanical polishing. Figure 6 shows a schematic cross-sectional view of a microelectronic product made in accordance with a preferred embodiment of the present invention. The microelectronic product includes a conductor layer-patterned copper- 12", a barrier layer formed thereon, and a patterned second copper 32a including a conductor layer, wherein the conductor layer is patterned second The copper 32a is formed on the barrier layer of the microelectronic product, and the patterned second copper layer and the patterned barrier layer 3〇a formed on the conductor layer including the conductor layer patterned copper-12" have Improved electrical properties, such improved electrical properties 14 1281216 I IL · 〇V;

I丰—修(更)正替換頁I Γ可改善微電子產品之可信度,而這種電性特性和可信 又之改善係來自於,將含導體層圖案化第—銅12 含氫電漿和一含氬電漿進行處理之結果。 例子: 一人根據本發明較佳實施例來製造微電子產品,同時應用 「含氳電漿和一含氬電漿對含導體層圖案化第一鋼12:,進 行處理。而此含氫電漿之處理條件為:⑴反應室壓力約在 β mtorr(陶爾),(2)無線電波波頻源能量約⑼瓦,而偏 壓此ϊ約100瓦;(3)一基板之溫度約攝氏2〇〇度;(句氫氣 流量率約為_標準立方公分每分鐘(standard cubic 匸她軸⑽Per黯*,SCCM );以及⑺處理時間約為削 ^而含氬電漿之處理條件為··(1)反應室壓力約在50 mt〇IT(陶爾);(2)無線電波波頻源能量、約700瓦,而偏壓能 /里約1〇〇瓦;(3)—基板之溫度約攝氏200度;(4)氬氣流量 率約為1 〇SCCM;以及(5)處理時間為1,4, 10和14秒。 、胃為了比較之目的,使用一額外之微電子產品,讓其含 ‘體層圖案化第一銅僅經含氫電漿進行處理,而不再經一 含氬電漿來處理此含導體層圖案化第一銅。 使用一習知之技術,來計算一與微電子產品串聯之電 阻於第7圖中展示了計算之結果。在第7圖中,參考數 子7〇所指示之資料點是代表,微電子產品中之含導體層圖 案化第一銅’經由含氫電漿和含氬電漿兩者處理過。而參 考數字72所指示之資料點是代表,微電子產品中之含導體 15 1281216 β织幻正督換頁 層圖案化第一銅,僅經由含氫電漿處理過。 人—女同第7圖所展示之比較結果可出,經由含氫電漿和 電漿兩者處理過之含導體層圖案化第一銅,比僅經由 含乳電漿處理過之含導體層圖案化第一銅,具有較低且較 平均之接觸電阻。 卜错由檢測根據本發明形成於含導體層圖案化銅上方之 Γ θ之原子輪射頻譜圖,來更進一步檢測高接觸電阻I Feng-Xiu (more) is replacing page I Γ to improve the credibility of microelectronic products, and this electrical property and reliability are improved by patterning the conductor-containing layer - copper 12 hydrogen The result of treatment with plasma and an argon-containing plasma. EXAMPLES: One person manufactures a microelectronic product according to a preferred embodiment of the present invention, and simultaneously applies a "containing yttrium plasma and an argon-containing plasma to pattern the first steel 12 containing the conductor layer: and the hydrogen-containing plasma is processed. The processing conditions are: (1) the pressure in the reaction chamber is about β mtorr (Tower), (2) the energy of the radio wave source is about (9) watts, and the bias voltage is about 100 watts; (3) the temperature of a substrate is about Celsius 2 〇〇 degree; (sentence hydrogen flow rate is about _ standard cubic centimeters per minute (standard cubic 匸 her axis (10) Per 黯 *, SCCM); and (7) processing time is about cutting and argon plasma processing conditions are ... 1) The pressure in the reaction chamber is about 50 mt〇IT (Tayl); (2) The energy of the radio wave source is about 700 watts, and the bias energy is about 1 watt; (3) The temperature of the substrate is about 200 degrees Celsius; (4) argon flow rate is about 1 〇SCCM; and (5) treatment time is 1, 4, 10 and 14 seconds. For the purpose of comparison, the stomach uses an additional microelectronic product to make it The first copper containing the 'body layer patterning is treated only by the hydrogen-containing plasma, and the patterned layer containing the conductor layer is no longer treated by an argon-containing plasma. A copper. Using a conventional technique to calculate the resistance in series with a microelectronic product, the result of the calculation is shown in Fig. 7. In Fig. 7, the data point indicated by reference numeral 7〇 is representative, micro The conductor-containing patterned first copper in the electronic product is treated via both a hydrogen-containing plasma and an argon-containing plasma. The data points indicated by reference numeral 72 are representative, and the conductors in the microelectronic product 15 1281216 β The first layer of copper is patterned by the fascinating layer, which has only been treated with hydrogen-containing plasma. The comparison results shown in Figure 7 of the Human-Matrix can be obtained through the treatment of both hydrogen-containing plasma and plasma. The conductor layer patterning the first copper has a lower and more uniform contact resistance than patterning the first copper via the conductor layer containing the milk-containing plasma. The error is detected by the conductor layer pattern formed according to the present invention. The atomic round spectrum of Γ θ above the copper to further detect high contact resistance

2來源。此含導體層圖案化銅若非:(1)沈積後·,(2)僅使用 各氫電氷處理,就是(3)僅使用含氬電漿處理。其所顯示之 原Τ輻射頻譜圖如第8圖所示。在第8圖中,參考數字8〇 所指示之曲線是代表,含導體層圖案化銅未經任何電漿處 多考數子82所指示之曲線是代表,含導體層圖案化銅 僅經由含氫電漿處理過。參考數纟84所指示之曲線是代 表3導體層圖案化銅僅經由含氬電漿處理過。所有之曲 ^在275ev之能量下均顯示有對應之外在碳吸收光譜。但 疋,參考數字82所指示之曲線,於278ev之能量下有一額 外之吸收光譜83。此額外之吸收光譜尖端被認為是因為组 和碳間之鍵結所造成。 因此,本發明雖然不願意與任何之操作定理有關,然 而,藉由含氫電漿來處理含導體層圖案化銅,使得含導體 層圖案化銅具有-氫化表面,而此氫化表面可藉由含氣(或 I氣)電漿加以移除。假如未移除,此氫化表面會阻礙利 ^ atomic layer deposition chemical Vapor depositi〇n)來形成導體層,尤其是當此原 162 sources. The patterned copper layer containing the conductor layer is not: (1) after deposition, (2) treatment with only hydrogen electro-ice, or (3) treatment with only argon-containing plasma. The spectrum of the original radiation shown is shown in Figure 8. In Fig. 8, the curve indicated by reference numeral 8 is representative, and the curve containing the conductor layer patterned copper is not represented by any of the electrodes 82, and the patterned layer containing copper is only included. Hydrogen plasma treatment. The curve indicated by reference numeral 84 is that the patterned copper of the conductor layer is treated only by the argon-containing plasma. All of the songs ^ showed a corresponding carbon absorption spectrum at 275 ev. However, 曲线, with reference to the curve indicated by numeral 82, has an additional absorption spectrum 83 at an energy of 278 ev. This additional absorption spectral tip is believed to be caused by the bond between the group and the carbon. Thus, although the present invention is not intended to be associated with any operational theorem, however, the patterned layer containing copper is treated by a hydrogen-containing plasma such that the patterned layer-containing copper has a hydrogenated surface, and the hydrogenated surface can be Gas-containing (or I-gas) plasma is removed. If not removed, the hydrogenated surface will hinder the formation of the conductor layer, especially when the original 16

I281216 子層沈積化學氣相沈積方法使用金屬和含碳物質作為源材 料(source material)。 根據上述描述,本發明之範圍非僅用以在含導體層銅 上形成一氮化鈕阻障層,而是,本發明更可用於處理任何 化成有氧化物或其他殘留物之導體基層,這些氧化物或殘 邊物可藉由含氫電漿來加以移除。本發明亦可用於在含導 體層銅上,藉由金屬和含碳物質作為源材料來形成一第二 導體層,例如為一導體阻障層。 雖;^本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作各種之更動與潤飾,因此本發明之保 濩範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目㈤、特徵、優點與實施例 能更明顯易懂,所附圖式之詳細說明如下: 第1圖至第6圖展不一系列之概略剖視圖,其係根據 本發明較佳具體實施例來製造一微電子產品時每一進行階 段之圖示。 第7圖是根據本發明之方法和非根據發明之方法來製 造微電子產品時’其累積機率與接觸電阻間之關係圖。 第8圖是根據本發明之方法和非根據發明之方法來製 造氮化钽層’其-系列之原子輻射頻譜圖。 17 95, ίΐ. 3 0The I281216 sublayer deposition chemical vapor deposition method uses metals and carbonaceous materials as source materials. According to the above description, the scope of the present invention is not only for forming a nitride button barrier layer on the conductor-containing layer copper, but the present invention is more applicable to the treatment of any conductor base layer formed into an oxide or other residue. The oxide or residue can be removed by a hydrogen-containing plasma. The present invention can also be used to form a second conductor layer, such as a conductor barrier layer, by using a metal and a carbonaceous material as a source material on the copper containing the conductor layer. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and various modifications and changes may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects (five), features, advantages and embodiments of the present invention more apparent, the detailed description of the drawings is as follows: Figure 1 to Figure 6 show a series of A schematic cross-sectional view of each stage of the fabrication of a microelectronic product in accordance with a preferred embodiment of the present invention. Fig. 7 is a graph showing the relationship between the cumulative probability and the contact resistance when the microelectronic product is manufactured according to the method of the present invention and the method according to the invention. Figure 8 is a diagram showing the atomic radiation spectrum of a tantalum nitride layer according to the method of the present invention and the method according to the invention. 17 95, ίΐ. 3 0

1281216 【主要元件符號說明】 10基板 11鑲嵌孔 12含導體層圖案銅 12’含氫電漿處理後之含導體層圖案化銅 12’’經含氫和含氬電漿處理後之含導體層銅 14a和14b圖案化之第一阻障層 16a和16b圖案化之第一介電層 18a和18b圖案化之蝕刻停止層 20a和20b圖案化之第二介電層 22a和22b圖案化平坦停止層 24側邊間隙壁層 26含氫電漿 28含氬電漿 3 0毯狀阻障層 30a阻障層 32毯狀含導體層之第二銅 32a含導體層圖案化第二銅 181281216 [Description of main component symbols] 10 substrate 11 inlaid hole 12 containing conductor layer pattern copper 12' hydrogen-containing plasma treated conductor layer containing patterned copper 12'' containing hydrogen and argon-containing plasma treated conductor layer Copper 14a and 14b patterned first barrier layers 16a and 16b patterned first dielectric layers 18a and 18b patterned etch stop layers 20a and 20b patterned second dielectric layers 22a and 22b patterned flat stop Layer 24 side spacer layer 26 hydrogen-containing plasma 28 argon-containing plasma 30 blanket-like barrier layer 30a barrier layer 32 blanket-like conductor layer second copper 32a with conductor layer patterned second copper 18

Claims (1)

1281216 十、申請專利範圍·· 1.一種製造微電子產品之方法,至少包含: 提供一基板,其中該基板具有一氧化之第一導體層· 使用一還原電漿處理該第一導體層用以形成一還^電 漿處理後之第一導體層;以及 使用一純氣電漿處理該還原電漿處理後之第一導體声 用以形成一經全處理後之第一導體層。 2·如申請專利範圍第1項所述之方法,更包含在該經 全處理後之第一導體層上形成一第二導體層。 心 3·如申請專利範圍第2項所述之方法,其中該第二導 體層係以氣相沈積方法,利用一金屬和含碳物質為源材料 來加以形成。 4 ·如申明專利範圍第3項所述之方法,其中形成具改 σ電f生特性之该苐二導體層係先利用一還原電漿,再使用 一鈍氣電漿,而非僅使甩一還原電漿。 5·如申請專利範圍第1項所述之方法,其中該還原電 漿為含氫電漿。 6·如申睛專利範圍第1項所述之方法,其中該鈍氣電 19 1281216 組中之一 漿係選自由氦、氖、氬、氪和氙氣電漿所組成群 個0 、7.如申請專利範圍! i項所述之方法,其中該純氣電 漿為含氬電漿。 =㈡專韻圍帛丨項所述之方法,其中提供該純 乳電及之條件為: 無、線電波波頻源能量600至800瓦, 100 瓦; 偏壓能量10至 純氣流量率為mo標準立方公分每分鐘;以及 反應室壓力約在1至100毫陶爾。 9·一種製造微電子產品之方法,至少包含· :以及 板’其中該基板上具有-含導體層銅; 使用-含虱電漿處理該含導體層鋼 漿處理後之含導體層銅· 、. „ 形成一 3氣電 二處理後之含 經全處理後之含導體層鋼上形成’更包含在該 如申請專利範圍第9項所述之方法, 體層 法,其中該第 lh如申請專利範圍第10項所述 , 20 1281216 導體層係以氣相沈積方法,利用一金屬和含碳物質為源材 料來加以形成。 . 12·如申請專利範圍第11項所述之方法,其中形成具 改善電性特性之該第二導體層係先利用一含氫電漿,再使 用一含氬電漿,而非僅使用一含氫電漿。 φ 13·如申請專利範圍第9項所述之方法,其中該含氣 電漿係選自由氫電漿和氨電漿所組成群組中之一個。 14·如申請專利範圍第9項所述之方法,其中提供該 氬氣電漿之條件為: X 無線電波波頻源能量600至800瓦,一偏壓能量ι〇至 100 瓦; 鈍氣流量率為!至20標準立方公分每分鐘;以及 φ 反應室壓力約在1至100毫陶爾。 \ 15· 一種微電子產品,至少包含: : —基板’其上具有一氧化之第—導體層,其中該第— 導體層已先使用-還原錢,接著再使用—鈍氣電聚處理。 16.如中請專利範圍第15項所述之微電子產品,更包 含一形成在該第一導體層上之第二導體層。 21 1281216 17·如申請專利範圍第16項所述之微電子產品,其中 /弟一導體層係以氣相沈積方法,利用一金屬和含碳物質 、 為源材料來加以形成。 W 18·如申請專利範圍第15項所述之微電子產品,其中 該還原電漿為含氫電漿。 φ 19·如申請專利範圍第15項所述之微電子產品,其中 該鈍氣電漿為含氛電漿。 20·如申請專利範圍第15項所述之微電子產品,其中 提供該氬氣電漿之條件為: 無線電波波頻源能量600至800瓦,一偏壓能量1〇至 100 瓦; 鈍氣流量率為1至20標準立方公分每分鐘;以及 反應室壓力約在1至1〇〇毫陶爾。 221281216 X. Patent Application Range 1. A method for manufacturing a microelectronic product, comprising: providing a substrate, wherein the substrate has an oxidized first conductor layer; treating the first conductor layer with a reducing plasma for Forming a first conductor layer after the plasma treatment; and treating the first conductor sound after the reduction plasma treatment with a pure gas plasma to form a fully processed first conductor layer. 2. The method of claim 1, further comprising forming a second conductor layer on the fully processed first conductor layer. The method of claim 2, wherein the second conductor layer is formed by a vapor deposition method using a metal and a carbonaceous material as a source material. 4. The method of claim 3, wherein the bismuth conductor layer having the sigma-electricity characteristic is formed by first using a reducing plasma and then using a blunt gas plasma instead of only 甩A reduced plasma. 5. The method of claim 1, wherein the reducing plasma is a hydrogen-containing plasma. 6. The method of claim 1, wherein the one of the group of the blunt gas 19 1281216 is selected from the group consisting of ruthenium, osmium, argon, krypton and xenon plasma, 0, 7. Apply for a patent range! The method of item i, wherein the pure gas plasma is an argon-containing plasma. = (2) The method described in the special rhyme article, wherein the pure milk power is provided and the conditions are: no, line wave source energy 600 to 800 watts, 100 watts; bias energy 10 to pure gas flow rate mo Standard cubic centimeters per minute; and reaction chamber pressures from approximately 1 to 100 milli-tons. 9. A method of manufacturing a microelectronic product, comprising: at least: a plate having a conductor layer copper on the substrate; and treating the conductor layer containing copper with a cerium-containing plasma treatment; „ Forming a 3 gas-electric two-processed process comprising forming a fully processed conductor-containing layer steel, further comprising the method described in claim 9 of the patent application, wherein the lh patent is applied for In the scope of the tenth item, the 20 1281216 conductor layer is formed by a vapor deposition method using a metal and a carbonaceous material as a source material. The method of claim 11, wherein the method is formed. The second conductor layer for improving electrical properties first utilizes a hydrogen-containing plasma, and then uses an argon-containing plasma instead of using only one hydrogen-containing plasma. φ 13 · as described in claim 9 The method, wherein the gas-containing plasma is selected from the group consisting of hydrogen plasma and ammonia plasma. The method of claim 9, wherein the condition of providing the argon plasma is : X Radio Wave Source Energy 600 to 800 watts, a biasing energy ι〇 to 100 watts; an blunt gas flow rate of ! to 20 standard cubic centimeters per minute; and a φ reaction chamber pressure of about 1 to 100 millitorns. \ 15· A microelectronic product , comprising at least: - a substrate having an oxidized first-conductor layer thereon, wherein the first-conductor layer has been used first - reducing money, and then using - blunt gas electropolymerization. The microelectronic product of claim 15 further comprising a second conductor layer formed on the first conductor layer. 21 1281216. The microelectronic product according to claim 16, wherein the conductor layer A microelectronic product according to claim 15 wherein the reduced plasma is a hydrogen-containing plasma. The microelectronic product of claim 15 is obtained by a vapor deposition method using a metal and a carbonaceous material. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The conditions of the plasma are: radio Wave frequency energy source 600 to 800 W, a bias power to 100 watts 1〇; noble gas flow rate of 1 to 20 standard cubic centimeter per minute; and a chamber pressure of about 1 torr to 22 milli 1〇〇.
TW94115631A 2004-08-02 2005-05-13 Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer TWI281216B (en)

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