TWI280642B - Leadframe and semiconductor package - Google Patents

Leadframe and semiconductor package Download PDF

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Publication number
TWI280642B
TWI280642B TW094102050A TW94102050A TWI280642B TW I280642 B TWI280642 B TW I280642B TW 094102050 A TW094102050 A TW 094102050A TW 94102050 A TW94102050 A TW 94102050A TW I280642 B TWI280642 B TW I280642B
Authority
TW
Taiwan
Prior art keywords
lead frame
tin
semiconductor package
leadframe
lead
Prior art date
Application number
TW094102050A
Other languages
Chinese (zh)
Other versions
TW200627601A (en
Inventor
Ya-Ling Hung
Tzu-Bin Lin
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094102050A priority Critical patent/TWI280642B/en
Publication of TW200627601A publication Critical patent/TW200627601A/en
Application granted granted Critical
Publication of TWI280642B publication Critical patent/TWI280642B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor package includes a leadframe, a chip, an encapsulant and a Tin layer. The leadframe includes a plurality of leads and a die pad. The chip is mounted on the die pad of the leadframe and electrically connected to the leads of the leadframe. The encapsulant encapsulates the chip and the leadframe and exposes out the portion of leads. The Tin layer is formed on the leads, wherein the leadframe has copper (Cu) of which the weight percentage is more than 96.2% and has no zirconium (Zr) for decreasing the formation of intermetallic compound (IMC).

Description

12806421280642

Leads Plated With Tin Alloy For Increased Wettability And Method For Plating The Leads)” ，揭示—種增潤濕性之導 線架，其係於導線架之外引腳上電鍍一層錫合金，使該導 線架具有抗高溫及高潤濕性等特性，而該導線架之電鍍繁 程包含下列步驟：提供一導線架，其金屬材料係為銅、銅 合金或鎳合金’並具有一晶片承座及複數個内引腳及外引 腳；將該導線架之晶片承座及内引腳電鑛一層銀，以增進 導電性；將該導線架之外引腳上電鍍一層錫合金，諸如錫 録合金或錫㈣合金，使該導線架具有抗高溫 :特性；將該晶片黏固於該晶片承座上，並將該晶片電性 =於該内引腳；以及藉由一封膠體密封該晶片、該晶片 7丄及忒内引腳。上述習知電鍍製程所使用之錫合金，豆 :力有抗高溫、高潤濕性、防氧化或防腐蝕等特性，使該導 HI腳表面容易接合於一外部印刷電路板。然而， 白知电鍍製程並無揭示避免產生錫鬚。 台灣專利公報公告第4959 外引腳發生鬚晶之半導體封農方,ΐ” Γ肖止導線架 襄方法，其包含牛2 ::方法’揭示-種半導體封 /、匕S步驟有•提供一導绩 腳，以供電性連接.後數個引 勒貼禮… 導體封裝，其係在該導線架上 黏貼複數個半導體晶片，在 後，以封膠體密封該半導體日日片與導線架之引腳 或錫形成—金屬層…該金屬層係為錫 ^ 0…、導線架’其係在非活性氣鈐之气气ΊΓ 4批 該金属層；以及切割導線架 孔體：…加熱 構。上述習知半導體封裳方法之半導體封裝結 无係利用在非活性氣體之氣氛Leads Plated With Tin Alloy For Increased Wettability And Method For Plating The Leads), reveals a lead frame for increasing wettability, which is plated with a tin alloy on the pins outside the lead frame, so that the lead frame has high temperature resistance And high wettability and other characteristics, and the lead plating process includes the following steps: providing a lead frame, the metal material is copper, copper alloy or nickel alloy 'and has a wafer holder and a plurality of inner pins And the outer lead; the wafer holder and the inner lead of the lead frame are electroplated with a layer of silver to enhance conductivity; the outer lead of the lead frame is plated with a tin alloy such as tin alloy or tin (tetra) alloy, The lead frame is made to have a high temperature resistance characteristic; the wafer is adhered to the wafer holder, and the wafer is electrically connected to the inner lead; and the wafer is sealed by a gel, and the wafer is sealed. In-situ pin. The tin alloy used in the above-mentioned electroplating process, the bean has the characteristics of high temperature resistance, high wettability, oxidation resistance or corrosion resistance, so that the surface of the HI foot is easily bonded to an external printed circuit board. However, It is known that the electroplating process does not disclose the avoidance of tin whiskers. Taiwan Patent Bulletin No. 4959 The external pin occurs in the semiconductor wafer of the whisker, ΐ Γ 止 止 导线 导线 导线 , , :: :: :: :: :: :: :: :: :: :: :: The semiconductor package /, 匕 S step has a • provide a guide foot, connected by power supply. After several attracting stickers... Conductor package, which is attached to the lead frame by a plurality of semiconductor wafers, after the sealing body Sealing the semiconductor day piece and the lead of the lead frame or tin forming - metal layer ... the metal layer is tin ^ 0 ..., the lead frame ' is in the inert gas atmosphere ΊΓ 4 batches of the metal layer; Cutting the lead frame hole body: ... heating structure. The semiconductor package of the above conventional semiconductor sealing method is not utilized in an atmosphere of an inert gas

00992-TW/ASEK-1W 1280642 顯示一單晶針狀之錫鬚。 第3&及讣圖為本於 ;—1 X 3之一實施例之導線架之剖面及平 面不意圖。 第4圖為本發明之一實施例之半導體封裝構造之剖面 示意圖。00992-TW/ASEK-1W 1280642 shows a single crystal needle tin whisker. The 3 & and the drawings are based on; the profile and plane of the lead frame of one embodiment of the X 3 are not intended. Fig. 4 is a schematic cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention.

【主要元件符號說明】 10 介金屬化合物 12 錫層 14 錫晶粒 16 錫鬚 20 外引腳 120 導線架 122 外引腳 124 内引腳 126 晶片承座 128 支撐肋條 140 含錫金屬層 200 半導體#裝構造 210 晶片 214 黏膠 216 銲線 218 打線接墊 220 導線架 222 外弓丨腳 224 内引腳 226 晶片承座 230 封膠體 240 含錫金屬廣 00992-TW/ASEK-1164 11[Main component symbol description] 10 Intermetallic compound 12 Tin layer 14 Tin die 16 Tin whisker 20 External pin 120 Lead frame 122 External pin 124 Inner pin 126 Wafer holder 128 Support rib 140 Tin metal layer 200 Semiconductor # Mounting 210 Chip 214 Adhesive 216 Bonding wire 218 Wire bonding pad 220 Lead frame 222 Outer bow foot 224 Inner pin 226 Wafer bearing 230 Sealing body 240 Tin metal 00992-TW/ASEK-1164 11

Claims (1)

1280642 月日修(影正#換頁 十、申請專利範圍： 1、 一種導線架，包含複數個引腳，其中該導線架係含有銅 (Cu)成份重量百分比係大於96.2%，且不含有锆成 份，該導線架係摻雜有微量金屬，且該微量金屬包含鎳 (Ni)、矽（Si)及鎂（Mg)。 2、 依申請專利範圍第1項之導線架，更包含一含錫金屬層 形成於該些引腳之表面上。 _ 3、一種半導體封裝構造，包含： 一導線架，包含複數個引腳； 一晶片，固定於該導線架上，並電性連接於該導線架 之引腳； 一封膠體，封裝該晶片及該導線架，並裸露出該引腳 之部分；以及 一含錫金屬層，形成於該引腳上，其中該導線架係含 有銅（Cu)成份重量百分比係約大於96·2%，且不含有錯 (Zr)成份，該導線架係摻雜有微量金屬，且該微量金屬 包含鎳（Ni)、矽（Si)及鎂（Mg)。 4、 依申請專利範圍第3項之半導體封裝構造，其中該含錫 金屬層係藉由一電鍍製程依序形成於該引腳上。 5、 依申請專利範圍第3項之半導體封裝構造，更包含一晶 片承座以承接該晶片。 6、 依申請專利範圍第3項之半導體封裝構造，其中該含錫 金屬層係形成於暴露於該封膠體外之該些引腳表面。 00992-TW/ASEK-1164 121280642 月日修 (影正# 换页10, the scope of application patent: 1, a lead frame, including a plurality of pins, wherein the lead frame contains copper (Cu) component weight percentage greater than 96.2%, and does not contain zirconium The lead frame is doped with a trace amount of metal, and the trace metal comprises nickel (Ni), bismuth (Si) and magnesium (Mg). 2. The lead frame according to claim 1 of the patent scope further comprises a tin-containing metal The layer is formed on the surface of the pins. _ 3. A semiconductor package structure comprising: a lead frame comprising a plurality of pins; a wafer fixed on the lead frame and electrically connected to the lead frame a pin; a gel encapsulating the wafer and the lead frame and exposing a portion of the lead; and a tin-containing metal layer formed on the lead, wherein the lead frame contains a copper (Cu) component weight The percentage is greater than about 96. 2% and does not contain a (Zr) component. The leadframe is doped with a trace amount of metal, and the trace metal comprises nickel (Ni), cerium (Si), and magnesium (Mg). According to the semiconductor package structure of the third application patent scope, The tin-containing metal layer is sequentially formed on the lead by an electroplating process. 5. The semiconductor package structure according to item 3 of the patent application scope further includes a wafer holder to receive the wafer. The semiconductor package structure of claim 3, wherein the tin-containing metal layer is formed on the surface of the leads exposed to the outside of the sealant. 00992-TW/ASEK-1164 12
TW094102050A 2005-01-24 2005-01-24 Leadframe and semiconductor package TWI280642B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094102050A TWI280642B (en) 2005-01-24 2005-01-24 Leadframe and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094102050A TWI280642B (en) 2005-01-24 2005-01-24 Leadframe and semiconductor package

Publications (2)

Publication Number Publication Date
TW200627601A TW200627601A (en) 2006-08-01
TWI280642B true TWI280642B (en) 2007-05-01

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TW200627601A (en) 2006-08-01

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