TWI279883B - Improved pillar connections for semiconductor chips and method of manufacture - Google Patents

Abstract

A flip chip interconnect system comprises an elongated pillar comprising two elongated portions, a first portion including solder with or without lead and a second portion including copper or gold or other material having a higher reflow temperature than the first portion. The second portion is to be connected to the semiconductor chip and has a length preferably of more than 55 microns to reduce the effect of alpha particles from the solder from affecting electronic devices on the chip. The total length of the pillar is preferably in the range of 80 to 120 microns.

Description

Ϊ279883 A7

V. INSTRUCTIONS (!) The present invention generally relates to a method for interconnecting semiconductor wafers to a columnar junction of a semiconductor wafer to a substrate, and in particular, from and to the fabrication of the contacts. Reduced, faulty. Solder based on tin-lead is a preferred choice for interconnects for flip chip bonding of cascading circuits. As the size of the electronic components on the hoarding circuit continues to decrease, the emission of alpha particles produced by lead can cause significant problems. The fault has three stable isotopes that form the product of the tail end of the natural radiation decay bond. However, these stable isotopes usually contain a small amount of residual (X-particle radioactivity. As the size of the electronic device in the slab circuit is getting smaller, the distance between the lead-based solder and the component is the same. Thus, the alpha particle radiation generated from the solder enables such elements to reduce the radiation effects of the alpha particles from the solder by providing a passivation layer that covers the electronic components on the twins. Some serve as the passivation layer. The material provides more effective protection for the electronic component against the integrity of the 01 particle than other materials. In addition, the alpha particle radiation from the solder is radiated from the basic point source in the solder, so that the electronic component is subjected to it ( The intensity of the X-particle radiation is rapidly reduced as the distance of the elements away from the solder. A table is shown below which presents five different materials as a vehicle for isolating the electronic components from the solder.

.1279883 V. INSTRUCTIONS (2) Vehicle (Compound) Air Polythionimide Oxide - Oxidation Broken Si2N4 Density P lg/cm 3) 1.161e-03 1.61 1.20 Molecular Weight Μ i g) 39.11 38.0 40.0 60.0 140.0 (eVcm2/Iel5 atmospheric pressure) 20.96 18.91 19.68 27.42 28.18 Effective thickness d (cm) 10.83 0.0084 0.0114 0.0055 0.0105 As shown in the above table, if the air is the only medium for isolating electronic components from solder, then in order to make these f subcomponents It is not expected to have a significant effect on the emission of alpha particles from the solder. The effective thickness of the air vehicle that isolates the electronic components from the solder should be at least 1 (.83 cm), which is unacceptable for most applications. . It should be noted from the above table that in terms of absorbing the minimum absorption length of the particles from the solder, the oxidized silica is the best barrier layer, followed by the polythioimide. Where a dioxide dioxide or other solid material is used as the passivation layer, only a portion of the medium separating the electronic component from the solder is occupied by the material, and the remainder occupied by air or other material is not the same in absorbing alpha particles. effectiveness. However, it can be noted from the table that even if cerium oxide is used as a compound for the passivation layer covering the electronic components on the twins, the electronic components are preferably at least 0.0055 cm apart from the solder or 55 microns. For the polythioimine passivation layer, the spacing is preferably at least 84 microns. 4 The interconnect method uses a fault-based solder to connect the flip chip to the substrate. In addition to the above-mentioned problems of alpha particle emission, since the size of electronic components is getting smaller and smaller, the use of lead-based solder bumps has no benefit 'because it is difficult to use bridges that cause electronic shorts to be bridged between two adjacent contacts. Paper scale applies to Chinese National Standard (CNS) Α4 specification (210X297 mm) 1279883

A fine spacing is achieved between them. When a solder bump is formed by electroplating, and wherein the photoresist has a thickness of not less than 60 μm, the bump size in a horizontal plane of the solder ball of ι μm high is about 120 μm, and the electroplated solder bump is It is shaped like a mushroom. Therefore, if the distance between adjacent points of the solder bump using this height is reduced to less than 〇5 〇 micrometer (in the form of an array or the surrounding), bump bridging is apt to occur. Accordingly, there is a need to provide an improved interconnect system that achieves finer pitches and minimizes the likelihood of bump bridging, and wherein alpha particle radiation does not significantly affect the electronic components located on the semiconductor wafer. Features. In the document entitled "Wire Interconnect Technology, a New and Highly Reliable Close-Pitch Interconnect Technology" by Fujitsu Computer Packaging Technologies, Inc., L〇ve, et al. A pure copper interconnected column. The flip-chip is attached to a substrate by a pure copper pillar instead of a lead-based solder having a length of about 45 or 50 microns. Although this copper-based interconnect may be able to achieve a finer spacing between adjacent interconnects, the proposed solution still fails to avoid the above-mentioned alpha particle emission problems. As in the first diagram of the article by Löve et al., it is to attach the copper pillar to the substrate using solder. Since the southness of the copper pillar is greater than 50 micrometers, even if cerium oxide is used as a passivation layer covering the electronic components on the flip chip, the electronic components are still subjected to solder for attaching the copper pillar to the substrate. The adverse effects of alpha particle emissions produced. Moreover, as is well known to those skilled in the art, the distance between the semiconductor flip chip and the substrate is typically filled with the underfill material to provide support and stability to the interconnect structure. Typically, the underfill material process is provided by injecting 1127883. / A7 ______B7 V. Invention Note (4), which requires a specific minimum gate distance between the semiconductor wafer and the substrate for the large number of implantation processes. That is, the minimum pitch is about ^μm. Therefore, using the interconnect structure proposed by Laffer et al. in the article, the spacing between the half-body b-plate and the substrate is obviously insufficient to inject the underfill material. The material used by the puller clearly limits the possible height of the copper column to 'not exceed 50 microns. L. None of the above described interconnect systems are fully satisfactory, and it is therefore desirable to provide an improved interconnect system that eliminates the difficulties described above. SUMMARY OF THE INVENTION The present invention is based on the recognition that the use of an elongated pillar facilitates the attachment of a semiconductor wafer to a matrix system, wherein the pillar comprises two elongated portions, one of which comprises a metallic material (excluding ships), such as solder or gold that includes copper, a higher reflow temperature; and another portion includes solder or other wettable materials. The portion comprising the non-lead metal material is in contact with the semiconductor wafer and has a length of not less than 5 Å. Preferably, the total length of the column is not less than about 55 microns. In a more preferred embodiment, the length of the pillar is not less than 84 microns and the portion of the pillar comprising copper is not less than about 55 microns. Using the elongated pillars of the present invention, the spacing between the solder located in the pillar and any other solder used in the interconnection and on the other hand for the electronic components on the semiconductor wafer is exceeded 55 microns or even 84 microns, so that the adverse effects of alpha radiation from the solder of the electronic components on the semiconductor wafer will be reduced. This is especially true for the use of ruthenium dioxide or polythioimine as the passivation layer. This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) ----------------------- Loading......... .........tr------------------Line. (Please read the notes on the back and fill out this page.) 5. Invention Description (5) In the case where alpha particles are not valued, all parts of the interconnect can be made of lead-like solder to produce elongated columns. In the case where the length of the pillars exceeds 75 microns, a sufficient spacing is provided between the semiconductor wafer and the substrate for injection into the underfill material. In addition, by providing the semiconductor crystal # with a sufficient length and an appropriate cross-sectional dimension, the semiconductor crystal # is connected to the county f, since the curl greatly reduces the stress introduced between the semiconductor wafer and the pillar, which is also lowered by curling. The probability of wafer errors due to shear forces. The elongated pillars can first be formed by depositing a layer of metal for electroplating, then forming a layer of photosensitive material on the wafer, and exposing the layer of photosensitive material to radiation in a predetermined area. The portion of the layer exposed to the light shot is removed to form a through hole in the layer, the portions of the hole being filled with a metal-containing material to form an elongated pillar in contact with the wafer . The metal material is different (and preferably free of ruthenium) from the top metal (4) and then filled with a material containing any splashable metal to form an elongated metal column in contact with the bottom portion of the material. And forming a synthetic pillar, a portion of which comprises the metallic material, and other portions comprising - a splashable metal. The photosensitive layer and the deposited layer of the metal used for the money are then removed to form the elongated pillar. After the formation of the pillars, the pillars may or may not be refluxed prior to attachment to the matrix. Preferably, filling the holes with a layer of photosensitive material having copper, gold, non-lead or solder is carried out by electroplating. Further, the thickness of the photosensitive layer and the depth of the holes are preferably sufficient to form pillars having a sufficient height, such as those described above. Piece of the piece

----------Book....... -Line 丨 (please read the note on the back and then fill out this page) 1279883 V. Invention Description (6 欲力二崎类 includes metal materials Part of the reliability = «The material of this part, the metal material is different from the solder, . . . , 匕 包括 包括 包括 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A layer of copper is applied. The copper emulsion is also reduced during the reflow of the solder. (4) The surface of the material is controlled during the solder reflow to control at least the height of the portion of the column. The other side of the invention is WJb. » 蚬 曰 曰 一种 一种 一种 一种 一种 一种 一种 一种 一种 一种 用于 用于 用于 用于 用于 用于 用于 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体A wettable material, comprising a gold-and-di-part, comprising a material having a reflow temperature that is higher than the first portion, and (d) two portions being in contact with the semiconductor wafer, the second portion may or may not Lead-containing. Another aspect of the present invention is directed to a semiconductor wafer flip-chip interconnection The system includes an elongated portion that is in contact with the semiconductor, and a spherical portion. The elongated portion includes copper or a solder metal having a higher reflow temperature than the spherical portion; the spherical portion includes a solder material The elongated portion may or may not contain lead. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the use of the elongated dendrites of the present invention to join a flip chip to a substrate to show the present invention; An exploded view of a portion (7) of the system of Figure 1, which shows in more detail the interconnection between the elongated pillars, the germanium wafer and the substrate. The 2A~2G diagram is a part of the semiconductor wafer and in each stage. Paper scale applicable to China National Standard (CNS) A4 specification (210X297 public) 1279883 A7 _________B7_ V. Invention description (7) (Please read the note on the back and fill in this page) Cross section of different layers related to the wafer Figure for illustrating the fabrication of the elongated pillars attached to the wafer and the attachment of the pillars to a substrate, showing an embodiment of the invention; Figure 3A is a flip-chip perspective view The flip chip has an elongated pillar on one side thereof to show an embodiment of the present invention; and FIG. 3B is a cross-sectional view of a portion 3B of the flip chip of FIG. 3A to show the present invention This embodiment; FIG. 3C is a cross-sectional view of a portion of the flip chip, and a substrate after attaching the flip chip to the substrate and implanting the underfill material to show an embodiment of the present invention; FIG. 4A A cross-sectional view of a flip chip attached to a substrate, wherein the flip chip and the substrate are both crimped to show shear stress in the wafer; FIG. 4B is a top view of the flip chip of FIG. 4A; The plot with the 5B plot is a plot showing the shear stress distribution of a 2 〇 Amy wafer where the wafer is used at a height of 1 μm and the bump diameter is 6 〇 and 100 μm (100/120/1 60) The elongated pillar of the present invention having a bump spacing of 225 microns is attached to a substrate to show the present invention; FIGS. 6A and 6B are diagrams showing the semiconductor wafers similar to those shown in FIGS. 5a and 5B. Shear stress in the middle, but the height of the slender column is 125 microns instead of 100 M; for the sake of simplicity of description, the same system components to be expressed by the same numbers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1A is a cross-sectional view of a semiconductor wafer in the form of a flip chip 12, 1279883. A7 __ B7 5. Inventive Description (8) A plan view of the crystallized by a slender column The article 16 is attached to a substrate 14 to illustrate an embodiment of the present invention. As shown in FIG. 1A, wafer 12 and substrate 14 are filled with an underfill material 18 (such as is well known in the art) for interconnection to wafer 12 and by such elongated pillars 16. Construction provides support and stability. Figure 1B is an exploded view of a portion 1b of the system of Figure 1A, showing in more detail an elongated column connecting one portion of the wafer to the substrate. As shown in Fig. 1B, the pillar 16 comprises two sections. The minute 16a' contains copper of a south degree H1 and a second elongated portion of height H2, which contains lead-based solder, and the joint between the two portions 16a, 16b is at 16c. The bottom of portion 16b is enlarged compared to its upper portion and has a generally conical shape wherein the bottom portion of solder portion 6b is produced by a reflow process as described below for bonding to a copper contact layer on top of substrate 14. 22 produces a physical electronic contact that is attached to a copper contact 24 on the wafer 12 with the upper end. In this manner, the circuitry on wafer 12 is electronically coupled through post 16 to an electronic contact 22 on substrate 14. As shown in Figures 1A and 1B, the semiconductor wafer i 2 and the substrate 14 are filled with a lower filling material 丨8. As shown in Fig. 1B, the circuit (not shown) on the germanium wafer 12 is separated from the solder portion 16b by the length or height of the copper containing portion 16a. The surface of the wafer 12 facing the substrate is coated with a passivation layer (not shown) which is made of a suitable material such as cerium oxide or polythioimide. Therefore, if the length or height HI of the portion i6a exceeds the effective thickness shown in the above table, the circuit on the wafer 12 will not be significantly affected by the unfavorable tensile scale of the particle radiation from the solder crucible ((^Α4) · (following 297 public love) : - .......................----- (Please read the notes on the back and fill out this page ) 丨 线 线 线 线 线 线 五 五 五 五 五 五 五 五 五 五 五 五 五 五 五 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 Preferably, the height is greater than 84 microns when the sulfilimine is used as the passivation layer. To allow for multiple injection procedures to be used to inject the underfill material 18, the total height of the pillars between the wafer 12 and the substrate 14 is at least It is 75 microns (such as about 8 〇 to 1 〇〇 microns). For the sake of the following description, the larger the value of Η, the lower the shear stress of the 矽 wafer and the joint between the wafer 12 and the pillar 16 Therefore, the total height Η of the pillars is preferably at least 丨〇〇 micrometers, and preferably 120 micrometers or more. 125 μm. The ratio of H1 to H2 is preferably about 3 to 1. The second Α 2 GI1 is a cross-sectional view of the semiconductor wafer and the layers associated therewith, for display to produce the image as shown in Figures 1 and 1 The process of interconnecting the elongated pillars and the procedure of attaching the pillars to the substrate to illustrate the invention. As shown in Figure 2, a photosensitive layer 32 is formed over the wafer 12. To simplify this In the drawings, the 2A to 2G drawings only show a portion of the wafer and the layers. Each designated area of the photosensitive layer is exposed to light, and the portions exposed to the ray are then removed to generate a A layer 32 having a pattern of penetrating holes 34, as shown in the second BS, wherein the penetrating holes reach the wafer all the time. Part of the penetrating holes 34 are filled with a copper-containing material, such as placing the entire structure In a copper bath, a current is passed through the electroplating of the copper material to fill at least a portion of each of the holes 34, as shown in the buckle. As shown in Fig. 2C, 'copper material-filling each Hole "~ part. Then transport the entire structure to - contain solder material The bath, and then the paper size applies to the Chinese National Standard (CNS) A4 specifications (2) 0X297^7

----- (Please read the precautions on the back and fill in the nest page) .囔-1279883 V. Inventories Explain the use of electric it to fill the parts of the holes 34 to produce the structure shown in Figure 2D. Thereafter, a solder material 16b' fills a portion of the holes 34. The remaining photosensitive layer 32 is then removed to form the structure of the second map. As shown in the top view, two elongated pillars 16 are formed, each of which includes a copper portion 16a and a solder portion 16b. To connect the pillars to the substrate, the portion 16b is brought into contact with the copper contacts 22 on the substrate 14, as shown in the 2F#. The solder-containing knives 16b are then heated in a manner well known in the art to reflow the solder 16b to form the solder portions 16b and pillars 16 shown in Figures 18 and 2. An underfill material 18 is then implanted to fill the space between the wafer 12 and the substrate 14. Thus, the contacts 24 located above the sheet 12 are physically and electronically connected and attached to the contacts 22 above the substrate. The resulting structure is shown in the 2nd (} diagram. To provide a metal point between the pillars and the semiconductor wafer, a lower bump metallization layer (typically consisting of a titanium (Ti), Titanium tungsten (Tiw) or chromium (Cr) and copper are used as an adhesive layer during the above procedure. This layer also acts as a metal, contacting the copper portion of the pillars for the above plating process. Except for the photosensitive layer 32, all portions of the underlying bump metallization layer are removed except for the underside of the pillars. For the sake of clarification, each pattern is omitted from this layer. 1A and 2E The figure shows the gap spacing P between adjacent elongated pillars 16. Using the above procedure, a fine pitch of less than 100 microns can be achieved. Fortunately, the gap or spacing between the pillars is about 1 Since the micron is formed as a part of the pillar, there is no need for an additional procedure for bonding the solder to the substrate, and the connection between the pillar and the substrate can be connected to the simple or simplified

(Please read the precautions on the back and then fill out this page) 奉, v"· :线丨1279883 A7 B7 V. Invention Description (11) The single ground is formed by the reflow of the solder portion of the pillar. In addition, it is not necessary to form mushroom-like solder bumps through this private sequence, so that a fine pitch can be achieved. The solder compound is elastic and has a tin to lead ratio of 63/37 or 5/95 or a non-lead solder. The copper material and solder material used in the above plating process may be only copper metal and solder. Figure 3A is a flip-chip perspective view showing an embodiment of the invention having elongated pillars on one side of the wafer. Figure 3B is a cross-sectional view of a portion 3B of the wafer of Figure 3A to illustrate this embodiment of the invention. Figure 3C is a cross-sectional view of a portion of the flip chip and the substrate, wherein the flip chip has been attached to the substrate and the underfill material is injected to show an embodiment of the invention, as indicated by arrow 100. Another advantage of the elongated pillar interconnect of the present invention is that it reduces the shear stress experienced by the crimped wafer and the joints of the wafers and interconnects. This is shown in Figures 4A and 4B, which is a cross-sectional view of the flip-chip attached to a substrate wherein the flip-chip and the substrate are crimped to show the shear stress in the wafer. Figure 4B is a top view of the 4a. As shown in Figure 4A, the wafer 丨 2, with the substrate! 4, curled for some reason, such as thermal effects. The crimping system calculates the Y-axis displacement from the center 12&, to the center 12b of the wafer, as shown in Figure 4A. Figures 5A and 5B show the male stress distribution in a wafer measuring 2 cm in size, wherein the elongated column has a length of 〇〇μm, a diameter of 60 and 100 μm, and a bump pitch of 1 〇〇, 12〇, 16〇, 225 microns. In the private drawing, the spacing is denoted by p and the diameter is denoted by D. As shown in Figures 5A and 5B, the peak shear stress at the edge of the wafer is the same as that of the copper.

(Please read the precautions on the back and fill in this page) .,訇丨.Mouth | ..1279883 A7 B7 V. Invention description (l2)

The strength of the II is so low that the elongated pillars of the present invention having a particular geometric appearance (or similar geometrical appearance) should not be destroyed by shear stress. Figures 6A and 6B show similar data as shown in Figures 5A and 5B, but wherein the column height or length is 120 microns instead of 1 〇〇 microns. Comparing the data of Figures 6A and 6B and Figures 5A and 5B shows that if the column is longer, it will experience less shear stress at the edge of the wafer and the interconnecting points connected to the wafer. One of the layers of organic or metallic material 5 shown in Fig. 1B can be used to cover the copper portion 16a, which reduces the reliability problem. The material used may be Entek or palladium' and may be formed by dipping only the entire construction into a bath of such materials, wherein the material will only adhere to the copper portion 16a. It has been found that the sidewall surface of the copper portion 16a may be splashed by the solder during reflow of the solder as described above to connect the wafer to the substrate. When this happens, the solder portion changes height and even collapses, making the return flow and connection procedure more difficult to control. Preferably, the sidewall surface of the copper portion 16a of the pillar 16 is oxidized to form a layer of copper oxide on the sidewall surface. This reduces the possibility that the sidewall surface of the portion 16a is wetted by the solder during reflow. The copper oxide layer can be heated by a temperature such that the pillars and wafers (such as the components shown in FIG. 2E) are heated in an oven to about Celsius to 12 degrees Celsius (such as 100 degrees Celsius). Exposure to an oxygen-containing environment, such as air, is formed for a period of about 15 to 60 minutes, such as 30 minutes. Although the above embodiments use copper as the non-lead metal material to form portions of the pillars in contact with the semiconductor wafer, it is understood that it is also possible to use metals other than copper (such as gold, tin/silver and tin/copper). "This and other changes in this paper scale apply to the Chinese National Standard (CNS) A4 specification (21〇><297 mm) 15 (please read the note on the back and fill the nest page)丨1279883 A7 -_____ B7___ V. Inventive Note (I3) is a stipulation of the present invention. As shown in Figure 1B, the bottom portion of the 1 sen is enlarged due to the solder reflow procedure, so 'the initial part The shape of 16b can be an elongated column. The column can be reflowed to form a spherical shape (shown as dotted line 16b in Figure 1B) before it is placed in contact with the substrate system, followed by the spherical material. It is reflowed to form the shape shown in Fig. 1B. Other variations are possible, so that the above-mentioned program is feasible and can be advantageously used as long as the reflow temperature of the material in part of the crucible is higher than the part. So part 16 a may comprise copper or a solder material having such a higher reflow temperature. The alpha particle emission is not important, and part of it may also be included, and part 16b may contain _ material with or without error. Inclusion-dehumidified material, including town and gold. Any of these characteristics can be advantageously combined with the above features. While the invention has been described with reference to various embodiments, it will be understood that changes and modifications can be made without departing from the invention. The invention is defined by the scope of the appended patent application and its equivalents. .1279883 Α7 Β7 V. Invention description (Μ) Component label control Ρ··· Spacing 16 c... joint D... diameter 16b'...solder part 12... flip chip 18... underfill material 12'···矽 wafer 22...contact 14...matrix 24···contact 14'...matrix 32...photosensitive layer 16...column 32'...photosensitive layer 16 a... Upper part 34···through hole 16b···solder part 50···Organic or metallic material layer〇----------------------- -----------------, 玎------------------ line (please read the notes on the back and fill in P) This paper scale applicable Chinese National Standard (CNS) Α4 size (210X297 mm) 17

Claims (1)

No. 911 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A first portion comprising a lead-free metal material and a second portion comprising solder; the first portion being in contact with the semiconductor wafer and having a length of no less than 50 microns. 2. 3. 4. 5. 6. 7. 8. If the patent claims a column of item i, the length of the column is not less than about 55 microns. The column of claim 2, wherein the column has a length greater than about 100 microns. The pillar of claim i, further comprising a layer of material covering the first portion. A pillar according to claim 4, wherein the material of the layer comprises an oxide of a metal in the first portion. Such as the scope of patent application! Column of the item, (4) - part of which includes steel. The pillar of claim 6, further comprising a layer of copper oxide covering the first portion. A semiconductor device comprising: a semiconductor wafer; and a plurality of pillars connected to the wafer, the pillars each comprising at least two elongated portions: a first portion comprising a lead-free portion A metal material, and - a second portion comprising solder; the two-way trowel being in contact with the semiconductor wafer and having a length of not less than about %. 29 1279883 丨6. Patent Application Scope 9. The components of claim 8 wherein the length of the pillars is not less than about 55 microns. The component of claim 8 wherein the length of the pillars is greater than about 1 micron. 11. The component of claim 8 of the patent scope, wherein the step comprises: covering the plurality of pillars at least the material of the first portion of the pillar. α is an element of the mountain ranger of the patent application, wherein the layer material comprises an oxide of a metal in the first part. 13. The fourth part of the patent scope of claim 4, wherein the first portion of at least one of the plurality of pillars comprises copper. (4) The element of claim 13 wherein the step comprises a layer of copper oxide covering at least the first of the plurality of pillars. 15. A method for making an electrical connection to a semiconductor wafer, the method forming a layer of photosensitive material on the wafer; exposing a predetermined region of the layer of material to radiation, and removing a portion of the static exposure to the radiation to Forming a through hole in the layer, from: exposing the area of the wafer through the holes; filling a portion of the holes with a metal to form an elongated column of all material materials such that the metal material is in contact with the wafer. The portions of the holes are filled with solder to form an elongated solder pillar such that the solder is in contact with the metallic material and 30!279883, the patented scope removes the layer of material. 16. The method of claim 15, wherein the filling is carried out by a program comprising money. 17. The method of claim 16, wherein the forming step forms a layer of photosensitive material having a depth of not less than about 50 microns, and is filled with a metal material such that the length of the elongated column of the metal material is quite large. At about 50 microns. 18. The method of claim 15, wherein the forming step forms a photosensitive material having a depth of not less than about 5 micrometers, and is filled with a metal material and a solder so that the elongated pillars of the metallic material are The length of the solder pillars is not less than about 55 microns. 20. The method of claim 15, wherein the forming step forms a photosensitive material having a depth of not less than about 50 μm, and is filled with a metal material and a fresh material so as to make the elongated column of the metal material The total length of the material and the k-pillar is not less than about j 〇〇 micrometers. For example, the method of claim 15 includes the step of contacting the solder with a substrate and heating the solder to cause reflow of the solder. 21. The method of claim 20 is as disclosed in Patent Application No. 20. It further reflows the pillars of solder to form a spherical body prior to contacting it with the substrate. 22. The method of claim 15, further comprising forming a layer of material on a side surface of one of the metal materials. 23. A method for making an electrical connection to a semiconductor wafer, the method comprising: 31 1279883 6. The patent application scope forms a plurality of pillars connected to a semiconductor wafer, each of the pillars comprising at least two a slender portion · a first portion comprising - a metallic material, and - a second portion comprising solder; the metallic material having a reflow temperature of the material in the second portion of the high material - the first portion and The semiconductor wafer is in contact with each other; and a layer of material is provided on a side surface of the first boring tool of at least one of the plurality of pillars, wherein the providing step is performed in 3 oxygen; The metal material is heated to a high temperature to oxidize the metal material. Μ · "The method of claim 23, the second spherical shape of the towel. ...;, the flip chip interconnect structure of the bulk wafer, which comprises two fine second portions, including solder, no oblique solder Or a material, including nickel and gold; and a second part, comprising a neighbor: the material has a reflow temperature higher than that of the first portion, and the brother is in contact with the semiconductor wafer. 26·^ Please refer to the structure of claim 25, wherein (4) 2 27 steel, gold or solder metal includes: a flip-chip interconnect structure for a semiconductor w, which comprises an elongated portion in contact with the wafer, and a The long part includes copper, the 戋 is _ 回 、, the production car / knife, the fine material is all, ^ _ spherical part of the high welding, 蜀 the spherical part includes a solder material. As claimed in the scope of the 27th Structure 'where the spherical part does not contain 28 1279883 VI. Patent application scope error 0 33 1279, 8§®ίρ! Patent Revision No. 91108801 95.08.0^ 3Θ 12 16 16 16 丄 6 30 丄 2 18 3C