TWI278752B - Disk array controller and fast method of executing stripped-data operations in disk array controller - Google Patents

Abstract

A disk array controller apparatus (10) is disclosed having at least two logical ports (Logical Port #0-Logical Port #3) for interfacing with a host (12) and having one or more physical ports (Physical Port #0-Physical Port #4), each physical port arranged for attaching at least one disk drive to the controller, and the controller including a switch (26), said switch providing dynamically configurable data paths (30) between the logical data ports and physical data ports, responsive to the contents of a Mapping Register (24). The Mapping Register defines a desired array disk drive array by specifying an association of each logical port to one of the physical ports. The mapping register can be organized as a logical mapping register, comprising a field for each logical port of the controller, and includes provision for designating a redundant array for RAID operations.

Description

1278.752 "}..., : -,, / '~.一...'(1)... 玖, invention description [Technical field of invention] The present invention relates to a digital data storage system, in particular, It is an improvement on the technology of disc array controller for digital data storage and retrieval. [Prior Art] A typical RAID controller for a small computer system includes an interface to the main system and an interface to the disc controller array. 1 is a simplified block diagram of a disc array controller 1 that provides interaction between the main interface 16 and the main bus 12 and the interaction of the disc controller interface 22 with a plurality of connected disc controllers 14. effect. The controller includes a control processor 20 and a buffer memory 8 for temporarily storing data moving from the main bus to the disc controller. The physical port is like a disc controller for the system to connect to a huge amount of storage. Although some interfaces can support parallel data transfer to most devices, there is a tendency to become a bottleneck. Therefore, the high-efficiency RAID controller has physical storage as shown in Figure 2A for each of the massive storage devices. Figure 2A also shows the contents of the mapping register, which will be described in detail below with reference to Figure 4 . One of the advantages of R AID efficiency comes from the striping of data across the array disc controller. For example, reading data from four disc controllers at the same time is four times faster than transferring from a single disc controller. In the example of Fig. 2A, the sixteen bit data conveyed from the four disc controllers are merged in the order of the logical disc controller into sixty-four bits of data to be transferred to the buffer (Fig. 1). User data is stripped, that is, segmented into segments -4- 1218753⁄423^ (2)

(for example, 16-bit words) pass through the array of disc controllers in a predetermined order. We determine that the sequence starts from logical disc controller #0 and then proceeds to logical disc controller #n-l, where n is the number of the disc controller in the array. This strip order is repeated such that the kth user profile corresponds to the logical disc controller (K m 〇 d η ). So, we use the logical disc controller encoding to reflect the strip order. Therefore, the logical group of the four groups shown in the figure simply represents the order combination of the four strip segments. Each , logical 埠 " corresponds to a strip segment, and the entire group corresponds to the order of the four segments. The transfer rate of each disc controller 100 MBPS becomes a transfer rate of 400 MBPS when it reaches the buffer. The dashed box 26 represents a data path switch. The data path switch 26 provides a logically programmable data path between the logical data and the physical data. Figure 2 The direct connection between the logical data and the physical data is only a commemorative map. In practical applications, the amount of available physical data will be more than the number of logical data. There may be some 埠 reserved as, hot spare Qin

〃 or entities may be aggregated into different independent access subarrays. Figure 2B shows one of the possible assignments of four logical data 埠 (logic 埠 # 〇 - Logic 璋 # 3 ) to the available five physical data 埠 (entity 埠 (4) _ entity data). For example, the large arrow 30 simply represents the assignment of logical 埠 #1 to entity 埠#2. FIG. 2B also shows the content corresponding to the mapping register 24. Here, the second field on the right side of the I register corresponds to the logical 璋#1, and contains the number 値', 2 表示 indicating the actual 埠#2, as indicated by the arrow 3 〇. Next, the data path switch 26 will be fully described to realize the allocation of the logical_to entity. -5- I,8f52_| (3)

Figure 2C shows an example in which each of the two disc controller arrays is assigned to one of five available physical data, called Entity #1 and Entity #2. In order to assemble a 64-bit word to be supplied to the buffer, every 16-bit disc controller must be read twice. 'At the first reading, the logical 埠# 〇 and #1 are each by the entity 埠# 2和# 1 obtained. At the second reading, the logical 埠#2 and #3 are each acquired by the entities 埠#2 and #1. These operations are all organized by the controller 20. Again, the map register displays the assignments of entities 埠#1 and #2. Figure 2D shows an example of a single disc controller connected to an array of physical 埠 #3. In this plan, the data from the logical 埠#〇 to 埠#3 is obtained by repeatedly reading the same disc controller four times.

One of the synchronous redundant data transfer characteristics described in U.S. Patent No. 6,0 1,8,7,8 8 is that it allows redundant data to be processed at a rapid rate as described in U.S. Patent No. 6,23,. Figure 3A shows the four disc controller arrays of Figure 2A plus logic 36 to complete the redundant data pattern stored in the physical port #4 disc controller. Although various arithmetic and logic operations can be used to create a redundant mode, the logical mutual exclusion between the corresponding bits of the data is obtained from the logical data, or it is advantageous in arithmetic operations because the mutual exclusion or operation does not need to transmit a carry. Due to the exclusive use or use, the fifth disc controller is usually referred to as a 'redundant disc controller or a 'co-located disc controller. The 16-bit wide buffers shown in the figure are mutually exclusive or equivalent to sixteen mutually exclusive or gates, each with four inputs. As can be seen in Figure 3B, the mutual exclusion or function is also symmetrical in the use of the disc controller read and the disc controller write. Figure 3B shows the same four disc controller arrays as defined in Figure 3A, while the data -6-(4) paths 40, 42 etc. show the disc controller reading direction. In this example, the disc controller connected to entity 埠#2 is invalid. Therefore, the corresponding non-functional data path 4 4 is shown by a broken line. Mutual exclusions or functions are calculated from existing data disc controllers (Entity 〇# 〇, #1 and #3) and Redundant Disc Controller Entity 埠#4. This calculation fixes the data stored in the invalid disc controller and the result is transferred directly to the logical port #2 via the data path 46 to replace the useless data from the invalid disc controller. The previous paragraph specifies some examples of some of the relationships between a set of logic and a set of physical devices that may exist in a RAID controller. In general, the high efficiency RA ID controller is forced to process a majority of the arrays consisting of various subgroups connected to the physical mass storage device. In one aspect of the invention, a novel mapping register is used and associated logic to make software planning of the array of storage devices feasible, and efficiency is improved, which will be further explained below. [Invention] The present invention provides a The disc array controller includes: a main interface connected to the main system; a buffer for storing read and write data; and a disc interface including a plurality of physical boards for attaching the disc controller; the disc interface additionally Included is a switch that implements a data path selectable between the entity and the buffer; and a mapping register that stores the mapping data, wherein the switch is dynamically planable, in response to the mapping data stored in the mapping register. Disc Array 0 1278752 / (5) [Embodiment] A typical RAID controller for mapping a small computer system includes an interface to the main system and an interface to the disc controller array. 1 is a simplified block diagram of a disc array controller 1 that provides interaction between the main interface 16 and the main bus 12, and the interaction of the disc controller interface 22 with a plurality of connected disc controllers 14. . The controller includes a control processor 20 and a buffer memory 18 for temporarily storing data moving from the main bus to the disc controller. The φ entity is like a disc controller for the system to connect to a huge storage device. While some interfaces can support parallel data transfer to most devices, there is a tendency for entities to become bottlenecks. Therefore, the high-efficiency RAID controller has a physical port for each of the massive storage devices shown in Figure 2A. Figure 2A also shows the contents of the mapping register, which will be described in detail below with reference to Figure 4 . One of the advantages of RAID efficiency comes from the striping of data through the array disc controller. For example, reading data from four disc controllers at the same time is four times faster than a single disc controller. In the example of Figure 2A, the sixteen-bit data conveyed from the four disc controllers are combined in the order of the logical disc controllers into sixty-four bits of data to be transmitted to the buffer (1 in Figure 1). . The user data is striped, i.e., segmented into segments (e.g., 16-bit words) and passed through the array of disk controllers in a predetermined order. We determine that the sequence starts from the logical disc controller #〇 and then proceeds to the logical disc controller #n-1, where n is the number of the disc controller in the array. This strip order is repeated such that the kth user data segment corresponds to the logical winter view / (6) disc controller (Κ m ο d η ). So we use the logical disc controller code to reflect the strip order. Therefore, the logical group of the four groups shown in the figure simply represents the order combination of the four strip segments. Each ''logic 埠〃 corresponds to one strip segment' and the entire group corresponds to the order of four segments. The transfer rate of each disk controller is 100 MBPS and becomes the transfer rate when it reaches the buffer. 4 〇〇Μ BPS . The dashed box 2 6 represents a data path switch. The data path switch 26 provides a logically programmable data path between the logical data and the physical data. The direct connection between the logical data and the physical data in Figure 2 is only a commemorative map. In practical applications, the amount of available physical data will be more than the number of logical data. There may be some 埠 reserved, hot spares, or entities that may be aggregated into different independent access subarrays. Figure 2 shows an example of the possible assignment of four logical data 埠 (logic 埠 # 0 - 埠 埠 # 3 ) to the available five physical data 埠 (entity 埠 #0 - entity 埠 #4). For example, the large arrow 30 simply represents the assignment of logical 埠 #1 to entity 埠#2. Figure 2 Β also shows the content corresponding to the mapping register 24. Here, the second field on the right side of the register corresponds to the logical 埠#1, and contains the number 实'' 2〃 indicating the actual 埠#2, as indicated by the arrow 30. The data path switch 26 is then fully described to implement the logical to physical allocation. Figure 2C shows an example of each of the two disc controller arrays assigned to one of five available physical data, called Entity !# ! and Entity 埠#2. In order to assemble a 64-bit word to be supplied to the buffer, every 16-bit 兀 disc controller must be read twice, at the first reading (2f87i52i (7), logic 埠#0 and #1 Each is obtained by entities 埠#2 and #1. At the second reading, logic 埠#2 and #3 are each obtained by entities 埠#2 and #1. These operations are all performed by controller 20 Organization. Again, the mapping of the scratchpad display entities 埠#1 and #2. Figure 2D shows an example of a single disc controller connected to the array of entities 玮# 3. In this plan, the logic 埠# The data of logic #3 is obtained by repeatedly reading the same disc controller four times.

One of the synchronous redundant data transfer characteristics described in U.S. Patent No. 6,018,778 is that it allows redundant data to be processed at a rapid rate as described in U.S. Patent No. 6,237,052. Figure 3A shows the four disc controller arrays in Figure 2A plus logic 3 6 to make the redundant data pattern stored in the physical port #4 disc controller complete. Although various arithmetic and logic 3 calculations can be used to create a redundant mode, the logical mutual exclusion between the corresponding bits of the data is obtained from the logical data, or it is advantageous in arithmetic operations because the mutual exclusion or operation does not need to transmit a carry. Due to the exclusive use or use, the fifth disc controller is usually referred to as a 'redundant 〃 disc controller or ', a co-located disc controller. The 丨6-bit wide buffers shown in the figure are mutually exclusive or equivalent to sixteen mutually exclusive or gates, each with four inputs. As can be seen in Figure 3B, the mutual exclusion or function is also symmetrical in the operation of the disc controller read and the disc controller write. Figure 3B shows the same array of four disc controllers as defined in Figure 3A, while the data path 40, 4 2, etc. shows the disc controller read direction. In this example, the disc controller connected to entity 埠# 2 is invalid. Therefore, the corresponding non-functional data path 4 4 is shown by a broken line. Mutually exclusive or function is from the existing data disc controller (entity 埠# 0, # I and # 3) and redundant disc control -10- 1278752: 1 - „ ·.., ' ------ - -I ....., (8) Controller entity 埠 #4 calculated. This calculation fixes the data stored in the invalid disc controller and the result is directly transferred to the logic 埠#2 via the data path 46. The useless data from the invalid disc controller. The previous paragraph specifies some examples of the various relationships between a set of logic and a set of physical devices that may exist in a RAID controller. In general, high-efficiency RAI D controllers are forced to process A plurality of arrays consisting of various subgroups of entities connected to a mass storage device. In one aspect of the invention, a novel mapping register is associated with logic to make software planning of the storage device array feasible, and The efficiency is improved, which will be further explained below. According to an embodiment of the invention, Figure 4 shows the structure of a mapping register 24, which controls the planning of the data path between the logical and physical data. (The mapping register also has Other features and advantages that will be described later.) Here In the embodiment, the mapping register is composed of five fields, each of which gives five logical data, in this case L0-L4. The logical data corresponding to each field in the register is connected to the entity. The number of the data is loaded. The data of the logical data field is represented by the symbol PP_LO to represent the entity 埠 associated logic 埠 0. Then the four fields are PP_L1, PP_L2, PP_L3 and PP-L4. The five logical data is a false alarm. PP is used to allocate a physical data to the same-level disc controller. The mapping register field can be almost any size. For example, the octet field can be used. Supports an array of 256 entities. For an embodiment with only five entities, the three-bit field is sufficient. The five fields are cleverly made into a six-bit scratchpad, with one spare The element is marked as '' r 〃 -11 - (9) 1278^ in the figure. ''Retained 。. Any form of non-volatile memory can be used to store the mapping register data. To specify the mapping temporary storage For the function of the device, we will briefly review the plan described in each project. 2 A is not mapped to the register 2 4. The PP_LO is 〇 indicates that the logical data 埠#0 is connected to the entity 埠#〇. Then three 値1, 2 and 3 indicate that the next three logical data are connected to the next Three entity data 埠. The difference between PP_L4 is 7. In this example, this is not a legal entity 埠 number. '' 7 〃 値 is to indicate that there is no co-located disc controller in this plan. Strictly required, as long as it is not the actual entity number. Referring again to Figure 2B, stored in the map register indicates that the entity data 埠 1, 2, 4 and 0 support logic 埠 0 g [J 3 . Again, 'Ί' means that the co-located disc controller is not being used. Figure 2C shows the mapping register for two disc controller array plans. The logical data 埠#2 and #3 are associated with the same physical entity as the logical disk controllers #〇 and #1. The first two logics transmit data when the first entity loops, while the next two logics transmit data when the second entity loops. Figure 2D shows the mapping register as a single disc controller plan. Logic 〇#〇 to #3 continuously transfers data to entity 埠#3. All of the changes in Figure 2 are independent of redundant data logic for different data path planning displays. Figure 3A shows the disc write direction of the mutual exclusion or logic in the same data disc controller as in Figure 2A. Mutually exclusive or calculated from the data of four logical data. The result is stored in the disc controller connected to the entity specified by the mapping register logic 埠#4 field. In this example, PP_L4 is 、, 12-'' 4 〃 instead of w 7 〃 indicates that there is a co-located disc controller connected to #4埠. Figure 3B shows that the mutual exclusion or logic has the same data path as Figures 2A and 3A except that the disc controller connected to the actual 埠#2 is now invalid in the disc reading direction. The logical data 埠 2 field content is replaced by P P_L2 as '' 5 〃 . The legal entity 编号 is numbered 〇 to 4. , , 5 〃 is a reserved 以 to indicate that the disc controller is invalid. Any logical data entered into the number 5 false entity will obtain data from the exclusive or output. Data Path Switch In the previous discussion, we specified that the four fields loaded in the Map Register field can be used to represent all possible plans between the four logical data, and connected to five entities, whether or not there is A 1 '2 or 4 disc controller array for redundant disc controllers; and an array with redundant disc controllers and with or without an invalid disc controller. Next, we will describe how to use the map scratchpad content to plan hardware blocks and data paths. The discussion that follows, in other words, introduces the details of the current preferred data path switch implementation and how it is planned by mapping the contents of the scratchpad. Referring now to Figure 5A, each of the four logical data must be capable of receiving data from any of the five physical data, but if the disc controller is invalid, the mutual exclusion or acquisition must be read from the disc. The six possible sources of data provide a six-to-one multiplexer 50 for each entity data. Figure 5 shows the multiplexer 50 of logic 埠1, but the others (for logic 埠#〇, #2, and #3) are the same. The multiplexer selector or the input of ', S〃 is connected to the mapping register logic 埠 #1 field one '' PP — L1 〃 . PP —L] 0 to 4 -13-

(11) The data from the entity 埠#〇 to #4 is selected separately. However, the '5 〃 选取 selects the disc to read the exclusive or the output. Figure 5B shows disc read exclusive or logic 52. Disc read mutexes or 52 is a mutexes or circuit of five inputs, which in this preferred embodiment is sixteen bits wide (corresponding to the connected disc controller data path). (This is equivalent to sixteen mutually exclusive or each with five inputs). Each of the five inputs is logically matched or blocked by the corresponding gate, and the gate is also hexadecimal. (This is equivalent to sixteen anti-gates, each with two inputs). The five inverse gates are matched by the corresponding five entities 埠 selection signals, PP〇_SEL to PP4_SEL. The generation of these signals will be described below. Entity 埠 Each data path can be from any of the four logical data, or from the disc writes to each other. This example is shown with reference to Figures 2A-2D. Although the mapping register field specifies the source of each logical data, we do not have a field to provide information for each entity. This information can be obtained from the fields we have. Each three-bit binary encoding field of the mapping register is decoded using a ', a pair of gossip decoders. Figure 6 shows the decoder 66 of the logical 埠#1 field. P P _ L 1 is decoded into L1_P0, LI_PI, L1_P2...L1_P7, and the name represents the path from the origin to the end. Taking L1__P2 as an example, the path from logical 埠#1 to entity 埠#2 is indicated. Referring now to Figure 7A', there is shown a circuit diagram example of a multiplexed data path 70 from a logical data to a physical data # (#0^4). The figure shows the multiplexer 72 of the actual 埠#2, and the remaining four multiplexers (not shown) are identical. Each multiplexer 72 includes one and/or an array and five and gates 74 - 14 - 1278752 (12), all of which are sixteen-bit wide and one corresponding or gate 76. (Each gate is equivalent to sixteen gates, each with two inputs. The gate is equivalent to sixteen or gates, each with five inputs.) For entities 埠#2 multiplexer' From the logical data, the gate is corresponding to the output of the five decoders: #, as shown as L0_P2, LI-P2, L2-P2, L3-P2, and L4 P2. At this point, there are two Open issues need to be resolved. In one or two | disc controller arrays, the specified entity receives data from two different logics through different loops. Referring back to Figure 6, each decoder 66 has a start input '' ΕΝ 符合 that matches all of its outputs. For the two disc controllers, only the logic data 埠#〇 and #1 decoders can be used in the first loop, and only the logic data 埠#2 and #3 decoders can be used in the second loop. . For this reason, only one of the gates in Figure 7 can be met at a time. In other words, only the data from the specified logic (in accordance with the mapping register) is input to the corresponding entity. In a single disc controller that receives data from all four logical ports (see Figure 2D) in a single entity, only one decoder 6 6 can be used at a time to cause the gate 74 to select a particular data source each time (logic 埠Only one can be used. Another open question is the ''PPn_SEL" signal source in Figure 5. When there is a data path between the host computer entity and any logic, Figure 6 shows the application of five inputs or gates 68 that can establish the entity 埠'' PPn_SEL signal. This means that the entity is available and can participate in the disc read exclusive or of Figure 5B. -15- (13) Overall read & write According to the details of ATA/ATAPI, the transfer of instructions to the disc controller needs to be programmed. For devices that can only support PI 0 type 0, each access speed may be It will be as slow as 600nS, and for a device with support type 4, the access speed will not exceed 10% of the 120n S or PIO type. A single instruction requires eight or more accesses. If all of the disc controllers need to be controlled sequentially, the time will be multiplied by the number of disc controllers and considerable potential factors will be added throughout the process. This instruction can be issued simultaneously by each of the individual controllers, but this adds a significant amount of complexity and price. When the data is cut into strips by the disc controller array, some of the specified strips will be in the same position for each disc controller. This makes the address of each disc controller data the same as the logical buffer address or LBA. Therefore, the instructions for reading the specified bar for all disc controller arrays are the same. The instructions for writing to the specified bar are also the same. This allows the logic controller (e.g., 20 in Figure 1) to "play" the common command without spending more time than transferring the command to a single disc controller. As mentioned earlier, the disc controller array contains a subset of the connected disc controllers. (One of the advantages of the present invention is that it can be easily utilized to store the appropriate bits to the map register to plan or re-plan the connected disc controller organization and turn it into a clear array.) In the case of a subset of disc controllers, the instructions (like reading and writing) will only be 'played' to the selected subset. The disc controllers must be controlled one by one, otherwise provide some means to ''camouflage the current array.

wWmE (14) Entity data not involved. Figure 8 shows an implementation of this topic. Referring to FIG. 8, the address, pulse, and chip selection signals CSO, CS1, DAO, DA1, D Α2, DIOW, and DIOR of the first two (Ρ0 and Ρ1) of the five entities are displayed. It should be noted that these addresses and pulse signals are common to all five turns. They are buffered independently so that the invalidation of the specified disc controller does not prevent these signals from propagating to other disc controllers. See buffers 8〇, 82. The output disc controllers of the two wafer selection signals CSO#, CS1# of the designated device are matched by the Pn_SEL signal of the chirp; see gates 84 and 86. Any wafer selection that is not selected by the current contents of the mapped scratchpad will not be asserted and therefore the read and write pulses will be ignored. The overall read 〃 means that the potential conflict data is returned by the common stream, which seems to be unreasonable. In the current embodiment, , the overall read " will cause a read pulse, Figure 8 Pn_DIOR#, is, 'played to all physical data埠. Those connected to the memory device that are selected by the chip (Pn-CSO#, Pn-CS1#) will return the data to the physical port of the Pn_D I OR# pulse trailing edge lock. The result of this read cycle is not intended to send data to the local controller. The local controller will use a different address to read each fill one by one without causing Pn_DI0R# pulse loop repetition and any lock data changes. These loops allow the local controller to remove the potentially unique flaws stored in each data latch. The Pn_DIOR# loop that requires 600Ns has only been implemented once. Locked in each .. Each can be taken out in 15 n S with significant time savings by repeating the p n_ D !〇R # cycle five times. -17- 1278752 / (15) ''Overall read and ''integrated writes' devices allow the local controller to transmit instructions and receive status from the current selection array in the shortest possible time. When a different subarray is selected by loading a new port to the map register, the controller interface automatically updates without changing other code. State Sorting Previously, the generation of many entities' output and how they were manipulated by the mapped scratchpad were discussed. Each of these has several input signals. Once again, correlating these signals with a logical disc controller can reduce software expenditure. For example, each disc controller has a broken output to signal the controller's maintenance needs. Figure 9 shows the multiplexer 90 controlled by the mapped register PP-LO値 to select the entity 埠 associated logic data 零 zero. Each logical data has the same multiplexer (not shown here) that uses the corresponding PP_Ln値 to locate the break. In Fig. 9, the buffer 92 obtains a cut from each logical data multiplexer (90, etc.). When the local controller (20 in Figure 1) reads the interrupted state through this buffer, the interrupt will be presented in the logical data sequence starting from the logical data zero of the zero position of the bit. The same technique can be used to sort the internal and external signals obtained from the physical data, including the disc controller cable ID signal and the internal FIFO status signal. This feature allows the native firmware to utilize a common order code of multiple entities in multiple arrays. Once loaded into the burst buffer 92, the required status bits are often the least significant bits in the selected array ''scheduled' registers). The number of bits can be masked into the actual number of turns. -18- 1278752-/ (16)

Breaking ANY and ALL from the logical data 岔 can be logically performed as shown in Figure 9 and 94 or 96 to provide the signal ''Interrupt ALL" and,

Interrupt A N Y 〃 . When the local controller issues an instruction and before any data is transmitted, you may want to know about the disconnection from any of the disc controllers, because one or more disc controllers may reject the instructions or have some Other errors. Once the disc controller begins transmitting data, the local controller will want to know when all disc controllers have established a break signal, as this means the integrity of the instructions. It is to be understood that such an implementation allows the software to be independent of the number of disc controllers. (In one or two disc controller arrays, it is said that the chopping signal from each device appears twice in the single disc controller array and four times in the same disc controller. The and and all signals still function correctly.) Logical Address Mapping Φ Although a large amount of runtime software utilizes the above-described overall instructions and states, it is still necessary to access individual devices to initialize and process specific device errors. To this end, each entity data is presented at a specific location within the local controller address space. During the initialization process, the mapping register is loaded in the ''identity mode'), that is, the logical device 〇 points to the entity 埠 0, the logical device 1 points to the entity 埠 1 , and so on. This causes the entities to be presented in the order beginning with the location of the first entity in the controller address space. In normal operation, the logical and physical disc controller maps are loaded into the map register. If from the logic 埠 -19-

YllWtW^r^^ One-to-one — i (17) 2 Receive a bi ’ local controller accesses the defragmentation disc controller by accessing the specific address space of the 埠 2 when the identity map is loaded. This allows the logical disc controller to be serviced independently of the physical data to which they are connected. Figure 1 shows a hardware implementation of a logical address feature. When the controller accesses the address area of the device space, a pair of eight decoders 1 解码 解码 decodes the controller address five to seven columns and defines thirty-two bit space for each device. The decoding of each space sorts the decoded signal corresponding to 埠N, that is, pn_DEC. The decoding of the code seven actual 提供 provides the overall read signal. The P7_DEC signal and each of the other decoded signals 102 are ORed to establish a result for the two reasons of the specific access and the overall access. The selected signal Pn_SEL (n = 0-4) 〇 each selected signal is mapped to the register PP ^Ln値 is controlled. The one-to-eight decoder 104 transmits the P2_SEL signal according to the mapping register PP_L2 and generates a set of signals in the form of L2_P0-CS to indicate the wafer selection from the logical 埠2 to the physical zero. The other four logical 埠 pairs of eight decoders are also the same (not shown here). There are five inputs or gates per entity, such as 1 0 6 . Here, there is a gate 106 showing the entity 埠#2. Five different sources of wafer selection entities 埠#2 are taken together or together. The wafer selection of a single disc controller sub-array is established by all four logic devices, and the wafer selection of the dual disc controller sub-array is established by two logic devices. The foregoing and the illustrations illustrate several different examples of a formal mapping register; it can be referred to as a logical mapping register. As described, a column defining each logical disc controller of the array is provided, and in the field, the table -20- Ι27_23 Γ -.-,.1,,...^.-^=-. ·?..,.,.,.,.,w..,·,.—..r ., ... ,,^ . - 4 0〇) shows the corresponding entity number. In another embodiment, referred to as entity mapping, a scratchpad provides a field for each entity or connected disc controller, and the corresponding logical number in each field. This other mapping register is described in detail in the next example. Assume that the four disc controllers define an array for the strip data. The strip widths of the individual blocks are stored in a specific order in each of the available disc controllers. This process is repeated next. For example, the first piece of data (5th, 9th, etc.) is also stored in the disc controller connected to entity #1. The second piece of data (6th, 1st, etc.) is also stored in the disc controller connected to entity 玮#2. The third piece of data (7th, 11th, etc.) is also stored in the disc controller connected to entity #4. The first piece of data is placed in the logical disc controller 0, the second piece of data is placed in the logical disc controller 1, the third piece of data is placed in the logical disc controller 2, and the fourth piece of data is placed in the Logical Disc Controller 3. In this case, the two types of mapping registers are as follows: -21 - 1278752 ” / (19) Logical mapping: Logic 璋# 3 2 1 0 値(Entity i阜) 0 4 2 1 Entity 埠# 4 3 2 1 0 値(Logic 埠#) 2 - 1 0 3

The present invention has been modified by those skilled in the art, without departing from the scope of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagram of a disc array controller that provides a main interface for interacting with a main bus and a disc that interacts with a plurality of additional disc controllers. Slice controller interface. Figure 2A is a commemorative diagram illustrating the direct connection between the logical data and the physical data; and the corresponding mapping register contents are displayed. Figure 2B is a commemorative diagram showing four logical 埠 assigned to the five available physical data ; examples; and the corresponding mapping register pg g is displayed. Figure 2C is a conceptual diagram of two disc controller arrays, where each disc controller is assigned to one of five available physical data; | @ 0 maps the scratchpad contents. Figure 2D is a commemorative diagram of a single disc controller system, in which the logical band -22- Γ*> X.:* I278f5f (20) 0-3 continuously transmits data to the entity 埠#3; Map the contents of the scratchpad. Figure 3A illustrates the mutual exclusion or logic in the disc write direction planned by the disc controller of Figure 2a; and the corresponding mapped register contents are displayed. Figure 3B shows the disc read direction of the same data path as the mutual exclusion or logic in the same data path as in Figures 2A and 3A, except that the disc controller attached to the entity 埠#2 is now invalid; and the corresponding map register is similarly displayed. content.

4 is an example of a structure of a map register; a map register control logic of an embodiment of an array controller and a data path of an entity data. 5A is a logic 璋#1 multiplexer circuit for reading a data path. FIG. 5B illustrates a disk read repulsion of an embodiment of the array controller or FIG. 6 illustrates an embodiment for an array controller. The decoder logic that maps the scratchpad logic 埠#1 ( PP_L1 ) field. Figure 7A is a logical to physical data path for an embodiment of the array controller. (Applicable only to entity 埠 #2) Figure 7B illustrates disc write mutexes or logic in an embodiment of the array controller. Figure 8 illustrates the disc address, strobe and wafer selection logic so that the overall access instruction can access the currently selected array. Figure 9 illustrates the chopping signal logic for associating a logical disc controller. Figure 1 shows the hardware implementation of logical addressing. -23- 1278753 (21) [Key component symbol description]

10 Disc Array Controller 12 Main Bus 14 Disc Controller 16 Main Interface 18 Buffered Billion 20 Control Processor 22 Disc Controller Interface 2 4 Map Register 26 Data Path Switch 30 Arrow 5 0 Multiplexer 52 disc read mutual exclusion or logic

5 4 and alarm 66 decoder 6 8 or gate 7 0 data path 72 multiplexer 7 4 and gate 7 6 or gate 80 buffer 82 buffer gate • 24-84

8 6 闹 9 0 multiplexer 92 buffer 94 and gate 96 or gate 10 0 pair of eight decoding benefits 1 0 2 decoding signal

1 〇 4 — to eight decoders 1 0 6 or gates -25-

Claims (1)

Patent application scope 1. A disc array controller comprising: a main interface connected to a main system; a buffer for storing read and write data; and a plurality of physical discs for attaching a disc controller a slice interface; the disk interface additionally includes a switch that implements a data path between the physical volume and the buffer; and A mapping register for storing mapping data, wherein the switch is dynamically planable, in response to the mapping data stored in the mapping register, to implement the desired disc array IJ. 2. For the disc array controller of claim 1, wherein the mapping data reflects a logical strip order, the switch sorts the data segments from the entity into a logical strip order. 3. The disc array controller of claim 1, wherein the mapping data defines a logical strip order in a logical manner, each logical order corresponding to a piece of data. 4. The disc array controller of claim 3, wherein the mapping material comprises a plurality of fields, and the desired disc array is defined by specifying the association of each of the logical entities with one of the entities. 5. The disc array controller of claim 3, wherein the map data is stored in a memory of the controller. 6. The disc array controller of claim 3, wherein the mapping data constitutes a logical mapping register' includes a field for each logical unit and an associated field indicating the corresponding entity. - 26-127875 Sound (2) 7. The disc array controller of claim 3, wherein the mapping data is organized into an entity mapping register, including fields for each controller entity, and indications Corresponding to the logical field associated with the field. 8. The disc array controller of claim 3, wherein the required disc array is defined by the association of the logical sub-sets of the available entities. 9. An execution of the strip data read in the disc array controller a fast method of computing, the controller having at least two logical ports and one or more entities associated with the host computer, each entity configured to attach at least one disk controller to the controller, The method comprises the steps of: storing an indicator in a mapping register defining a disc array by associating each logical unit with one of a plurality of entities; establishing a single general read instruction for all controller entities; In response to the contents of the map register, only the entities included in the defined array are selected, so only the disc controller attached to the selected entity 回应 responds by reading the data to the respective entity. The instruction is fetched; then the read data from the entity is transferred to the buffer without repeating the disc read instruction loop. 1 〇 · A quick method of performing a strip data write operation in a disc array controller 'The controller has at least two logical ports and one or more entities that are interfacing with the host computer, and each entity is configured to For attaching at least one disc controller to the controller, the method includes the following steps: storing the indicator by one of the plurality of entities associated with each logic -27 - 3: ' ''|-τ; , .v Ι 2787$±* ' (3) to define the mapping array of the disc array; transfer the write data from the buffer to all entities included in the defined array; in response to the mapping register Content 'select only the entities contained in the defined array埠; then A single general write command is established for all controller entities' so that only the chip that is attached to the selected entity is written by the selected entity from the selected entity. Force ^ ^ Μ Φ & 0 should be written to the command. -28- The representative representative figure of this case is: Figure 2B. 24 Map Register 26 Data Path Switch 3 0 Arrow 捌 If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: