TWI277983B - Semiconductor memory device performing auto refresh in the self refresh mode - Google Patents

Abstract

Method and apparatus for use with multi-bank synchronous dynamic random access memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

Description

I2779S35Pifd〇c IX. INSTRUCTIONS: This application claims the priority of the Korean Patent Application No. 2004-56967 filed on Jul. 21, 2004, the content of . BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dy_ie access memory (DRAM) semiconductor component and system, and relates to performing a per-record (per >_bank) automatic operation = conversion Method and apparatus for self-refresh mode.先前, [Prior Art] fRAM components are well known, and are generally applied to t which requires read/recall. The reason why the DRAM component is so life is that the data in the mother's memory, mem〇rycell, must be refreshed periodically, otherwise the storage is broken. Synchronous DRAM components (syneh surface US DRAM,

When the heartbeat is started, the 'automatic refresh mode refreshes the DRAM ^ I; (internal refresh&quot;r〇^ ^ ( f〇W } ° ^ ^ ^ ^ tf continued automatic __ increase to do this, as long as the dram33 arrives The bottle (4) is at its top. All of the listed 曰 ΐ 列 列 列 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 70 pieces of SDRAM in the midnight SDRAM contain multiple memory banks, and the high-order column address bits Ι27798#5ρ^ ^ are provided to the SDRAM's. The operation of the gambling county to accept this operation is also provided to the SDRAM. Part of an auto-refresh command is provided on the memory bank (4), and the button performs an auto-refresh operation on the currently refreshed column in the memory of the memory bank, and the executable data is stored in the unselected memory bank. Access operation. This element: cow f is referred to in this specification as each memory bank refresh (_-:=, ship) SDRAM component. The inventor of the present application has proposed a US patent related to the application Chest 5,169, which reveals the structure of PBR SDRAM and The method of operation is in this specification. 'wrm“ Many SDRAM components incorporate a “self-refresh, mode. In self-refresh mode, SDRAM components are generally low SDRAM, ^«(awakened) new mode, requiring SDRAM components based on Refreshing the internal timing itself (4) 'This is to retain the resources stored in the memory element. [Inventive content] Whether or not all the memory banks have completed the current S: 1RSDRAM component can be sure to benefit from the two ^ = in the automatic refresh loop Any time to convert to self-refresh mode i U: in the surplus includes a component that reduces the memory controller's special flexibility, and allows the conversion of the invention in non-critical time, exposing a multi-memory memory (mu She rings 127798&quot;35_. The operation method of the memory component. This and the current column of this external two-column library uemorycella clear bank) read a few arrays: self-new operation. This component is accessed by η: two: Mode = automatic refresh operation of the current column of the column library (if there is ϊί) Wang 2:: The memory of the meta array refresh operation refreshes the current column, refreshing the tj 4 of all memory banks There are one or several of these memory banks before hunting; = my refresh mode book introduces several finishes. #仃疋Automatic refresh. This example illustrates the embodiment of the refresh operation. 侪The component reveals a synchronization. Memory element. This new address generates a two-address memory cell array library; - a flash library; and a note that the i-bank bit is currently refreshed to all memory cell array addresses for refresh operation, and deducts: receives an externally provided memory bank The memory of the bit list is stored in the library. (4) The memory address corresponds to the self-refreshing new column in the current refresh column of the brush county. In the self-refresh mode self-refresh mode ===== memory cell array library, this current refresh column before the completion of all the functions of the memory cell array library, this: This self-refresh circuit can do more. These features are described in detail below. 1277983⁄45^0° Other aspects disclosed herein also include a memory controller, a memory handle set, and a memory system having the memory elements disclosed herein. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment]

The vertical W diagram depicts an SDRAM component 100 in the form of a block diagram. The memory cell array 10 includes a plurality of memory cell array banks 10-1 to l〇-n, where η can be any digit greater than 丨, and is usually a power of 2 jpower). Each memory bank includes a plurality of memory cells mC, each of which is connected to a unique combination of a plurality of bit lines BL and a plurality of characters j (word lme) WL, such as familiarity The artist, the 歹 歹, the address decoding circuit U is based on the provided column address signal radda = - for memory operations. Each of the main character lines is connected to a plurality of word lines (WL) by a control unit (not shown). The column array circuit 12 includes a plurality of column address decodings 1112] to ΐ2·η, and each 10-processor is used to activate the corresponding memory cell array 胄1. The selection message #bbai to ban is used to confirm the address decoder response column address signal radda. The line, = address buffer circuit 14 selects the bit row position according to the row address signal (10), and the device 22277983 releases 10-n. The bit line generator 28 receives the count signal cnt. The refresh address generator 28 provides the current refresh line address RADD to the selector 30. The address latch ( The latch 32 receives a plurality of external address signals ADD and a plurality of external memory address signals BA. The automatic refresh command signals AREF, active (ACT) signals, write (WR) signals, and read (RD) signals are determined. The meaning of ADD and BA. At the start command

During the valid period, the ADD signal is latched and supplied to the selector 30 as a column of address signals radd, and the BA signal is latched and used as a memory address signal.

The ibal is supplied to the first switch 34. While the read or write command is active, the ADD signal (and possibly the BA signal) is flash locked and provided to the row address decoder circuit 14 as a row address signal. During the period when the auto refresh command is valid, the memory bit is located; bl: the signal BA is flash locked and supplied to the first switch 34 as the memory location 31 signal. ▲ The instruction decoder 20 receives the external command signal c〇M and generates various control signals, including ACT, job and RD, AREF, and yang (disconnected telecommunication = then received - automatic refresh command and - power off command, Refers to ^. The code is 2〇 declares the PD signal to the self-refresh control signal generator 22 cry 22 1 cattle into the self ^ refresh the plate knows 'self-refresh control signal generation mouth 22 dens a self-refresh control signal PD when effective The component enters the self-brushing ^^ is also 5 brothers, when the power is turned off to some M fmw I (four). The SREF signal is provided dry (four) (10) (8), including the first switch 34, clock generator (d〇ck I2779835_〇c generator) 24. Selector 3〇 and the second switch 4〇. When the pulse is in self-refresh mode and the _ signal is valid, the time is sdt to generate a refresh pulse signal SCLK. In SCLK loop (4) with a predetermined repetition The sequence contiguously addresses the memory bank HM to 1〇, triggering the logging address to generate the new memory location signal iba2. The self-brushing-switch 34 receives the iba iba2 signal and self.

surface,. When the leak signal is not claimed, the signal passes through the first ^^ 34 to become the memory address signal iba. When #8 is declared, the first switch 34 becomes the memory address signal iba. The memory port address decoder 386 decodes the memory address iba to generate an appropriate memory selection signal based on the packet group bal-ban. The selector 30 determines whether the current refresh address signal or the address latch output address signal radd is passed to the column address decoder circuit 12 as the column address signal radda. When the AREF or SREF signal is asserted, the auto-refresh command signal AREF and the self-refresh control signal SREF are supplied to the selector 30 as a selection signal, so that the RADD signal is selected as the address signal radda to be passed to the column decoder 12, otherwise rad( The HK number is selected as the address signal radda is passed to the column decoder 12. According to the auto refresh command signal AREF or the self refresh control signal SREF, the second switch 40 respectively transfers the memory selection signal bal-ban to make it a buffer memory selection. Signal bbal-bban. When AREF or SREF is asserted, second switch 40 copies each bank select signal to its corresponding buffer memory select signal line. T2779835Pifd〇c Count control signal generator 38 receives buffer memory selection The signal line bbal bban. When the buffer memory selection signals of the refresh column are declared, the count control signal generator 38 declares a count signal cnt to refresh the address generation 28, and sends a signal to the refresh address generator 28 to Update the current refresh column to a new column. As described in an optional structure of this embodiment, the count signal cnt can also be provided to the clock. When the write signal WR is valid, the data input buffer 16 receives the data signal DIN from the external lean bus and provides the data signal din to the memory array 10. When the read signal RD is valid, the data output buffer The device 18 receives the data signal d〇ut from the memory array 1 and provides the data signal DOUT to the external data bus. Figure 1B illustrates another structure of the sdram component 100, except that the dedicated external refresh signal EREF is used instead of the decoding command. AREF determines when to perform an auto-refresh operation, SDRAM component 1〇〇, similar to SDRAM component 1〇〇. Assuming that AREF acts similarly to EREF, the following diagram further illustrates the operation of SDRAM components 1〇〇 and 1〇〇. Figure 2 illustrates an embodiment of a count control signal generator 38. The count control signal generator 38 includes latch circuits LA1 through LAn, each latch circuit receiving a corresponding buffer memory address signal bbal to bban Each buffer memory address signal provides an input signal to an n input n〇R gate NOIU. The NOR gate N0R1 provides an output signal cnt to the generator, and the output signal cnt As a reset signai, it is fed back to each latch circuit. Each latch circuit includes two n-channel MOSFET transistors N1 12 12779 and N2; and - flash lock ϋ L, which consists of two An inverting g (inverter) n is formed by connecting the input terminal to the output terminal. The transistor milk is used as an insulating transistor, and the flash locker is connected to the buffer memory address when the buffer memory address is claimed. On the signal. When the buffer memory address is asserted, the state applied to the flash locker L is that the output of the flash lock circuit is low. When all buffer memory address signals are asserted, the signal input to N〇R1 is low and the N0R1 gate declares the cnt signal. In each flash lock circuit, the transistor is connected to the input of the flash lock L by a pull-down connection, and cnt is provided as a closed signal to N2. Thus, when the cnt signal is asserted, it is applied to the flash locker 1 in such a way that the output of the lock circuit is high and the number of control signals generator % is deactivated and the cnt signal is deasserted. 3 includes a timing diagram showing the operation of the SDRAM elements 1 and 1 having the count control signal generator shown in FIG. 2, assuming that the memory address of the quaternary bank memory array is 〇〇, 〇 1, 1 〇 and u. In the time interval T1, the memory element operates in the normal mode and responds to the automatic refresh command and the start mode command (not shown). The refresh address generator has generated a current refresh column address, RADD, with a value of 0...0111. During the period τι, 'issue the first-auto-refresh command, the provided memory address ba is 〇〇' is flashed by the address flash lock S 32 as the internal memory address. Since the SREF is low, the ibal signal is transmitted. To the memory address decoder 36, the bank address decoder 36 decodes the value 〇〇 and declares the memory address selection signal bal. The AREF asserts that the second switch 4 is activated to cause the count control signal generator 38 to flash the bBL signal. AREF's claim also 13 12779835Pi£d〇c causes selector 30 to pass the current refresh column address 〇...〇1 ... the result, the memory bank 〇 ... 〇 111 column is refreshed. Solution - • V production = During T1, the second automatic refresh command is issued, and the supplied library address BA is 01. By phase (4) response, the count control signal is generated with a2, and the memory track is refreshed. When Tian Di's AREF signal was declared, a power-off command was issued to make the high-level 1 ° signal generator 22 recognize 5 = =^24° at this time interval T1, the time interval 隹Λ 4 Obvious material. Note that when Ϊ 10, only two of the four banks (memory... Spear 2) refresh the refresh column before the precipitation.曰 曰 发生 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 1^2. Since SREF is now passed to the memory address decoder 36 for the decoder 36^, the memory address of the memory address bah °S°REF is decoded and declares that the memory address selection signal is crying 38" The second switch 4 is under-actuated, which causes the count control signal to be sent to the column address selector 30 to pass the current refresh column address 〇.·.0111 ==, 12° result, 〇 in the memory _. The first-time is refreshed in the self-refresh mode. The declaration of the 3h^BmCLK is made to make the memory address address the memory address of 〇1. By similar response, the count I27798^35Pifdoc control signal occurs. The device 38 attempts to latch bba2 again, and the 〇···〇111 column in the memory bank 1〇-2 is refreshed again. The assertion of the third SCLK causes the memory address generator 26 to move to a memory location of value 10. By a similar response, the count control signal generator 38 latches bba3, and the 0...0111 columns in the memory bank 10-3 are finally refreshed. The fourth SCLK assertion moves the memory address generator 26 to Value, memory location of 11. With a similar response, the count control signal generator 38 latches bba4 And the 〇···〇111 column in the memory bank 1〇_4 is finally refreshed. It is noted that after the fourth SCLK is declared, the current brushing of all the memory banks o...oiii is finally refreshed, and the counting control The four flash lock circuits in the signal generator 38 also close their respective memory key selection signals. This = the count control signal generator 38 declares cnt, resets itself and moves the refresh address generator 28 to the next refresh. Column address RADD (value

Production base 1000). The new time interval T3 begins, and during the T3 period, all the new row bit addresses in the library are refreshed in the self_mode. The current —, _ ‘ and, Ϊ 看 ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ According to Memory Prayer, this remaining memory can be brought close to the end of its duration (2 I2779^35Pifdoc time). 4 and 5 illustrate the structure of an embodiment employing such a timing. Μ Figure 4 depicts another self-refreshing clock generator 24 that includes an auto-refresh reference clock (dGekrefe_e) 5G... self-brushing

Reference 52, a NOR closed NOR2, and an inverter 13. Reference = pulses 50 and 52 receive the self-refresh control signal SREF and the count signal cnt. When the SREF is declared, the reference clock is automatically refreshed, and then the benefit time-time signal cm is declared. Automatically refresh the reference clock 5 〇 &&amp; generate a clock signal touch. The self-refresh reference clock 52 ceases to function until two == the third time is simultaneously declared, and then starts until 赃F = action. The self-refresh reference clock 52 is generated after the start-up clock signal. The signal is crying: aclk and scik signals, and provide-output number Luu. "The output signal of /Mesh 13 is the self-refresh clock signal SCLK. In the operation, the slit pulse will generate the timing pulse _SCLK signal. Figure 5 shows that this embodiment has The other is only the timing diagram, at the end of the power-off signal (PD^Tf occurs in the period of T1 during the period - this point, the automatic skin? before the 'Figure 5 is the same as Figure 3. In the clock pulse, start four ^ days The sample 5 starts, and produces four consecutive refreshing operations in the self-brushing copper ^ refreshing operation. The four self-refreshing operation addresses ojm are continuously connected to the current column of the four memory banks (τι This address during the period of the automatic refresh operation is the address of the field queue. After the four memories are refreshed, the 16 1277988» count control signal generator 28 and the self-cancellation-counting signal cnt are refreshed when the address is refreshed. Pulse reference pulse generator 24. In response to the cnt pulse, automatic. Narrow I from #仔止止, and self-refresh clock reference 52 start and start =: New: ^ column new clock generator 24' provides flexibility Sex is 〇...0111 Starts next and then starts c at standard refresh rate. Execute the 9-way self-refresh operation. Compare Figure 3 with Figure 2 = ! The completion of the new division XU, the self-refresh loop of the shouting face is performed at a slower speed t2. The == and 6B are in block diagram form respectively. f shows the simAM component according to the second embodiment. In many respects, the SDRAM device 200 is similar to the SDRAM device (10) and 1 〇〇, the am am 200 200 and 200, and the SDRAM device 1 〇〇 and ι〇〇 will not be repeatedly described in terms of no change. Several pieces of memory memory address generator 26 and first switch 34 in Fig. 1A are not included in Figs. 6A and 6B. According to this, the internal memory address signal ibal is a signal of the only-transmission W-return wire correction. Figure 6A includes a set circuit 6 〇 instead of the memory address generator 'this setting circuit by self The refresh clock signal SCLK is driven to drive. The setting circuit 60 has - the output material is connected to each of the memory bank selection signals bal to ban. When the SCLK is pulsed, the setting circuit 6 〇 declares each memory bank selection signal 'to make all the memory banks The #前刷 column is immediately refreshed. I2779835Pifd〇c switch 40 puts all the memory The selection signal is passed to the count control signal generator 38 to cause cnt to be asserted in each self-refresh loop. Figure 7 illustrates one possible configuration of the setting circuit 60, including a delay device DLC, a NOR gate NOR3, and η p-channel transistors P1-Pn. An input of NOR3 and an input of the delay device Dlc receive SCLK. The output of the delay device DLC, the SCLK delayed form, is supplied to the other input of NOR3. DLC extension

The late time is set to be less than the positive pulse time of SCLK. This causes the positive SCLK • pulse to appear at the output of the DLC while the original pulse is still active. As a result, an extended negative pulse is generated on node b at the NOR3 output. Node b is connected to the gate (g^te) of each p-channel transistor ρι to pn. Each p-channel transistor is coupled between a positive supply voltage and a corresponding line in the memory j selection signal line bal to ban. Thus, when you drive the print b to be low, each P-channel transistor is activated, causing each of the bank select signal lines to be connected to the positive supply voltage. The timing ^8 includes an example of the SDRAM components 200 and 200, (the PDj guard is the same as the timing example described above, when the power-off instruction is issued, the new column of the memory list 1 and 1〇-2 completes the column position. The address is 〇···0111 brush SRHF聍, new operation. When the self-refresh control signal generator 22 is activated, the SCLK pulse is issued by the simultaneous pulse generator 24. The setting circuit 60 responds. Select the signals bal, ba2, ba3, and ba4 to make the address 〇···=, and the four memory banks 1〇_1, 1〇_2, 10_3, and 1〇_4 are automatically refreshed and refreshed. The column address 〇...0111 is selected between J. The switch 4 传递 transmits the four memory bank selection signals 18 1277983⁄45^00 as the buffer memory selection signal bbal-bba4 to the count control signal generator 38. The signal generator 38 generates a positive pulse on the cnt, resets itself and moves the refresh address generator 28 to a new column address RADD having a value of 〇··· 1000. Self-refresh loops T2, T3, Τ4 The four memory banks are refreshed immediately, and Τ2 is being self-refreshed when entering the self-refresh mode. The refreshed columns of all the memories are simultaneously refreshed. The third embodiment of the decoding refresh command sdram 300 and the external refresh signal SDRAM 300 is introduced in Fig. 9 and Fig. 9, respectively, and the setting circuit 60 is replaced by Fig. 9A. The similar setting circuit 6A in Fig. 7 is improved by the SDRAM shown in Fig. 1. Using the self-refresh clock as shown in Fig. 4, the processor 24' provides the clock signals aclk and sdk as the round-trip signals. The pulse signal apk is supplied to the setting circuit 6A, and the clock signal sclk is supplied to the memory address address generator 26.

Figure 1 includes a daily sequence diagram showing the operation of SDRAM components 300 and 300. The timing sequence __ is that, when the power-off command is issued, the memories 10-1 and 10.2 complete the self-φ refresh operation of the refresh column of the column address 〇···〇1η. When the self-refresh control signal generator 22 activates SREF, the syllabus 24 generates a positive pulse on the acik. As in Fig. 8, this positive pulse causes the setting circuit 6 to declare all of the bank selection signals. This causes the four memories HM, 10-2, 10-3, and 1〇_4 to have addresses 0...0111 at the time interval of 2, which are simultaneously refreshed. The switch 40 passes all of the four memory selection signals as the buffer memory selection signal M3al-bba4 to the count control signal generator 38. Counting control signal generation H 38 is generated - positive pulse is given to counting signal _, resetting itself at time interval 19 I2779835pi «〇c Τ3 / month and moving refresh address generator 28 to a new column with value 〇··· 1000 Address RADD. The positive pulse on cnt also causes clock generator 24 to stop generating and begin to generate sclk. After the next four sclk pulses, the memory address generator 26 points to the memory addresses 00, 01, 10, and 11, one by one, such that the memory address decoder 36 sequentially declares the memory selection signals bal, ba2, ba3, and Ba4. Thus, after four sdk pulses during the time interval T3, the four memory banks 1 (the values of M, 1G_2, 10_3, and 10_4 are 〇···1〇〇〇). The column address RADD to be refreshed is sequentially refreshed. After each bank is refreshed, the count control signal generator 38 counts and asserts cnt at the end of the time interval Τ3 to move the column address and initiate the memory address generator loop of the new refresh column. % shows the arrangement of the setting circuit and the count control signal generator shown in Figures 9A and 9B. The layout of the count control signal generator 38, is similar to the count control signal generator 38 shown in Figure 2. Latch LAl- The output signal of LAn (labeled as Sl-Sn) is output to NOR1, and is also output to the setting circuit 60, .

5 history circuit 60" receives signal aclk, which drives n NAND ΝΑ1 to ΝΑ-η input respectively. The other input of NAND gate _1 to ΝΑ-η is respectively controlled by the counting control signal generator The 38" signal S1 to Sn are driven. The output signals of NAND gates _1 to ΝΑ-η drive the gates of the ρ-channel transistors Ρ1 to Ρn, respectively. The same as Figure 7 is that 'Ρ channel transistor Ρ1 to Ρη is connected to the memory bank selection signal line bal to ban 277I277988^d〇c (four) rt, SDRAM components 300 and 300' use counting control two: ^ fixed circuit, when Timing diagram of the operation. When the quotation is issued, the gates LA1 and LA2 are set (low output), because two previous auto-refresh instructions during the time interval T1 refer to the location meta-addresses 〇 and 〇1. Ask the locker seven (not shown) u _ (4) is not set' so it has a high output. , , · 口 果 果 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And P4 (for example, pn shown in Figure u). Therefore, as shown in FIG. 12, the memory selection signals ba3 and ba4 emit pulses, and during the time interval D1, during the period of 5, the memory is 1G-3 and HM instead of the memory 1 (M and 1〇_2). The refresh operation is performed. This completes the RADDG...G111_new operation, causing the count control signal generator 38 to declare the gamma gamma claim that the operation is transferred to the memory address generator for normal self-refresh operation, as above 13A and 13B respectively illustrate a fourth embodiment of a decode refresh instruction SDRAM 4 and an external refresh signal SDRAM 400. For example, the main difference between SDRAM 400 and SDRAM is that The operation of a switch 34' and clock generator 24". These differences are best explained with reference to the timing diagram shown in Figure μ. ', as with the timing diagram above, when the example is automatically refreshed The instruction has been sent to the memory address 00, 01 and the current refresh column ^ to issue a power down command. However, unlike Figure 3, the SREF is self-refreshed and the signal generator declares that the first switch 34 will not be made, selecting internal memory. Location 21 1277980 fills in = iba2 Inversely, the 'first switch 34' continues to select from the address latch %, the internal memory address ibal. Moreover, the clock generator 24, does not start to issue the SCLK pulse when the self-refresh mode is just started. Figure 13A In the embodiment of /13B, even if it has entered self-refresh two: Zfe control reads to complete the refresh operation of the current column. During the time interval 22, the sdram component continues to return to the jREF instruction when the self-refresh mode is started. Therefore, the memory (4) When the new ^ refresh command is sent in the self-learn mode, the remaining memory address 〇〇 and (1) are given to the other columns, which makes the column address RADD of the memory 10_3 and 1〇_4 whose value is 〇〇ιιι is Refresh, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

2S 24”, D pong large, start (in combination with SREF) clock generator gentleman switch 34 from selecting internal memory address ibal switch = SREF) to select internal memory address _ to make (four) recall component into ordinary self Refresh mode. The conversion makes the sequence diagram map the day msDR application component 400 and the shed, another legal time must be tracked, the image 71' enters the self-refresh operation, the memory controller is not reversed, and the 仃^兰新The ship or feature of the memory bank. The order is automatically issued to each new hidden controller. The item is automatically refreshed to indicate that the current library has moved forward, because the current column is moved forward because all memory banks are == (four) addressed before the end of the loop. Then any remaining auto-refresh loops can be ignored. (5) 22 1277983⁄45^ The memory elements described in the above embodiments are described for use with a memory controller in a memory system. The memory controller can be combined in a processor. Or a separate integrated circuit can be used as the interface between the memory and the processor. Several representative memory systems are illustrated in Figures 16-19. Figure 16 depicts a memory system 5 It includes a memory The controller 600 and a memory component 1 根据. According to the illustration, the memory controller 6 provides the instruction COM, the memory address BA, and the column/row address ADD to the memory element 100 bus. For the write command The memory controller deletes the data stream Din to the data bus of the memory element 100. For the read command, the controller 600 receives the read data Dout from the data bus of the memory element 1 When the memory element (10) is in the normal mode, the memory controller provides a per-memory refresh (service) auto-refresh command to the memory element 100. However, the controller_ can make the memory element 1GG into the state without considering the state of the ship's loop. The electrical state is as described above. Of course, the memory element 1GG can also be replaced by, for example, a memory tree thin or = 〇〇 as described above: after entering the power-off state, the shirt becomes the pBR loop of the current refresh column, and the memory component is recorded. 100 can also be replaced by a memory element, a controller _ provides an additional auto-refresh command. s, day is not a single memory component in Figure 16, but many memory systems = by a eve or a memory module Combined Fig. 17 shows a memory system, charging 550, which uses the controller 6〇〇 and a memory module as the memory=piece 100 (or, for example, 2〇〇, 3〇〇, or 4〇〇 above). The memory module 100_m is composed of several memory elements of the same type to (10)^. The function is similar to that of Figure 16, the buffer 23 I2779835pifdoc (buffer) and/or tracker on the module 1〇〇_m ( Trace) assigns c〇M, BA, and ADD signals to each memory element 1004 to 1〇〇_n. Figures 16 and 17 illustrate a memory system using a decode auto-refresh command. Figures 18 and 19 illustrate The analog memory systems 500' and 550' that initiate the auto-refresh operation are initiated using the external auto-refresh signal EREF provided by the memory controller_. The memory system 5〇〇, and 55〇, use the external auto-refresh form of the above-described memory elements (e.g., memory elements 1〇〇', 200, 300, and 400').

Those skilled in the art will recognize that many other component architectures are also contemplated. There are many design parameters that have not been discussed. For example, the various features of the above-described embodiments can be combined with other embodiments. In most cases, the special roads shown in the towel are for demonstration purposes only, and other = can achieve the same or similar functions. The present invention may be modified and modified without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. The above embodiments can be exemplified. Although in the narrative, the words "#", "two", "other", or "some" are used in this example, but this is not a matter of thinking: the person uses the needle _ an embodiment, the feature is only secret The present invention has been disclosed in the preferred embodiments as defined by the preferred embodiments. Anyone who is familiar with this (four) is not in the county: when some changes and retouching can be made, therefore: It is subject to the definition of the patent application scope attached to the following. ', 4 [Simple description of the drawing] 24 127798B5Pifd〇c Figure u, IB shows the synchronous motion according to the first embodiment in a block diagram, respectively, random The automatic decoding and external auto-refresh signal form of the access memory (SDRAM) listening. Figure 2 illustrates the digital control signal generator for the SDRAM component shown in Figure 1B. The figure contains a timing diagram, which shows the figure. The SDRAM elements shown in 1A and 1B are switched from auto-refresh to self-refresh. Figure 4 contains a block diagram of another self-refreshing clock generator for the elements shown in Figure 1B. The figure contains another timing diagram, It shows the SDRAM components shown in Figure 1A and 1β from the automatic New self-refresh conversion. In the form of a block diagram, the decoding of the SDRAM component is automatically refreshed and externally according to the second embodiment. The auto-refresh signal form is shown in Fig. 7. Figure 6 shows the setting circuit of the SDRAM shown in Figure 6. The device ΓλΛ contains a timing diagram, which shows the conversion of 70 pieces from auto-refresh to self-refresh as shown in Figures 6A and 6B. The block diagram shows the decoding auto-refresh and external auto-refresh signals in accordance with the third embodiment of the SDRAM device. The W new includes a timing diagram, and the green diagrams are 9A and 9B. The display of M 70 from automatic refresh to self-refresh conversion. Figure 11 can not draw the count control signal generator and set circuit another 25 f.doc I27798»p*: kind of structure 'use it' 9A/9B f way A synchronous dynamic random access memory (SDRAM) component according to the first column is constructed. (4) A timing chart, wherein 1 shows that the SD self-setting circuit is automatically refreshed to the FIGS. 13A and 13B using the counting self-setting circuit shown in FIG. In the block diagram form the same example Dynamic Pray access fiber (SDRA ^ new and external self_new shouting form. Decoding of parts from fine sdrH containing - day_' its_ Figure 13A and other SDRAM components from automatic refresh to self-refresh conversion Figure 15 contains another timing diagram, the _M component from _new to self: new two according to the present invention - the new axis of the embodiment of the gambling _ _ memory system. $ : IW basis The present invention - a memory system that automatically refreshes the signal by the imaging section. 1θ ^ 19, can not rely on the memory system of the external automatic refresh signal and memory module according to the present invention. [Description of main component symbols] 100, 100', 200, 9rm, ^ (SDRAMS) 〇, marriage: decoding refresh command SDRAM component 26 I27798735Pifdoc 300', 400': external refresh signal SDRAM component 500, 550, 500' 550': Analog memory system 600, 600': memory controller 100_m, 100'-m: memory module 100-1, ..., 100-n, 100'-1, ..., 100, η: memory element 10: memory cell array 10-1, ..., 10·n: memory cell array library WL: word line BL · bit line MC: memory unit 12: column address decoder circuit 12_1, ..., 12-n: column address decoder 14: Row address decoder circuit 14-1, ..., 14-n: column address decoder 16: data input buffer 18: data output buffer 20: command decoder 22: self-refresh control signal generator 24, 24' 24": clock generator 26, 26': memory address generator 28: refresh address generator 30: selector 32: address latch 34, 34, 40: switch 27 I27798Tj5pif.doc 36 Delta memory address decoder 38, 38: count control signal generator 50: automatic refresh clock reference 52: Self-refreshing clock reference 60 '60, 60": setting circuit WR, radd, cadd, din, DIN, dout, DOUT, COM, ACT, RD AREF/EREF, PD, SREF, SCLK, iba, ibal, iba2 RADD, radda, ADD, BA, bbal ~ bban, bal ~ ban cnt, aclk, sclk: signal N1, N2: n channel MOSF1ET transistor II, 12, 13: inverter LA1, ..., LAn · flash lock circuit NOR1 , NOR2, NOR3: NOR gate L: latches a, b: node, T22, Ή, T2, T3, U, t2, ΤΓ, T2', T3', T4' T23: time interval PI, ..., Pn: P-channel transistor DLC: delay device SI, S2, ..., Sn: signal NA-1, NA-2, ···, ΝΑ·η: NAND gate 28

Claims (1)

127798^5Pifd〇c X. Patent application scope: There are many memory components with receiving-external brush=remembering operation methods including: = external refresh memory memory address corresponding to the memory list when the queue is executed - automatic operation; The magic rhyme enters the self-refresh mode in response to the power-off command; and in the self-refresh mode, the current column is first updated to the new ~ method 'where all memory operations are completed, and the current column refresh operation of the library is recalled. Early 歹 库 库 库 库 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3.卩 4 early 4 speed is greater than the self-mode towel # system initial = refresh operation refresh speed. After Lingxin is a new column, the process of the operation of the method is as follows: The process of reading the entire frame of the method of the method of the invention is to start the automatic refresh operation of all =-. _ The current column of the library is at the same time as the fourth method of the patent application scope. 'It is included in the self-refresh mode. Currently 29 I27798^pif.d〇〇: The new current method in the row memory cell array library 6: Shenzhong = The operation refresh operation of the synchronous memory element of 3=5 items: the second self; the refresh operation process includes the memory address of each memory to each memory bank. * Method: Medium =;, the four-synchronization success-sequential refresh operation The new operation process includes each memory in each self • 8 such as “_~ ;^”. After that, the current mode is in the new mode. The column is first updated to a new column operation. The subsequent columns of the ~70 column library perform a continuous self-refresh method. The operation of the synchronous memory element described in item 9: =] and the automatic refresh of all memory cell array libraries After the nmr _ type is executed in the case of the self-riding mode, the column of the library is executed - the refresh operation; 2 each (10) early array line self: two:: the current column in the mode is updated to a new column after the first time The memory of the synchronous memory element r: the number of special, === Shen ^ _ _ 9th summary of the synchronization, the operation of the 12779 (4) c method, in which the number of self-refresh mode memory addresses is equal to Boss &quot;The number of additional external refresh unit array libraries owed. The memory of the refresh operation when it is listed. 12. For the patent application scope method, in the self-refresh mode, before the operation of the synchronous memory element Current column and all memory sheets The initial update to the new-column process includes: initiating a simultaneous refresh operation on the current column of the array library that has not performed the current column auto-refresh operation. All of the memory units 13·--the synchronous memory element has multiple memory cell arrays Library, step by step component = step memory component with an external refresh memory address; ~ _ method includes: the current column is executed ^ (four) memory cell array library, into self-refresh mode in response to power-off instructions; in self-refresh In the mode, the refresh operation is performed in the current column of the parent = memory library. The front column is updated to the new column first. There are a plurality of memory units, the "fourth method of the piece" (the fourth method), the synchronous memory element has a step: the operation method of the memory element includes: the current column memory address corresponding to the memory cell array entry Z, automatic refresh operation; The refresh mode responds to the power-off command; in the mode, the current column 31 12779S^S^pif-doc of all the memory cell array libraries starts the simultaneous refresh operation; and the current column in the second refresh mode is updated to the new bucket. The operation method of the plurality of recording operation methods 'steel step memory element with f-external memory element includes: the current column two brush:: the operation: the self-refresh mode of the memory cell array library corresponding to the address in response to the power-off instruction; Start the simultaneous refresh operation; h after the self-refresh mode towel (4) early: under update to the new same day #1= mode, the current column and column of all memory list (four) column library; with the new operation:: some memory unit The subsequent columns of the array library sequentially perform self-brushing. ================================================================================== , into the self-refresh mode to respond to the power-off command; receive the attached, self-mode, the library address without leaving the self-refresh mode, until each memory unit = J ^ has executed a refresh operation; % after the self The current column in the touch mode is first updated to the new_column; 32 I2779^35Pifd〇c and two are two: the self-refresh operation is performed after the column. There are multiple memory cells 'array;:: operation method' the synchronous memory element And f-outer:::::Recalling the operation method of the component includes: After the current column in the self-refresh mode, the first time: New:: After the new column, the self-refresh is performed. Current: Second? New:: Library: The king of the corresponding memory cell array library. The current column in the meta-array library is the operation of the c-operation and the operation. The memory element has a method of synchronizing the memory of the piece, the synchronization has many = recalling the material, step "Receiving an external refresh request; the method of knowing the spoon includes: executing in the U column of the external library to return to the self-refresh mode in response to the power-off command; in the self-refresh mode, not in the self-refresh mode Refreshing the request and executing the phase St-form until the new operation of the refusal library, and then the current column in the self-refresh mode 33 12779835Pifd〇c after the current column is updated to a new column Perform a self-refresh operation. 19. A method of operating a memory controller, the method of operating the memory controller comprising: transmitting an auto-refresh memory address to a memory unit formed by the n memory banks in an order of addressing the n memory cell array banks And then addressing the n memory banks, so that the memory unit can sequentially refresh the current columns in the n memory banks according to the order of automatically refreshing the memory address addresses before refreshing another column of one of the memory banks; Sending a power-off command to the memory unit; and, if the memory unit is not activated, transmitting an additional auto-refresh memory address to the memory unit to enable the memory unit to complete the refresh operation of the current column before the self-refresh operation begins. 2 (λ) The method of operating the memory controller as described in claim 19, wherein the number of additional auto-refresh memory addresses issued after the power-off command is equal to η. 21. As claimed in claim 19 The method of operating the memory controller, wherein the number of additional auto-refresh memory addresses issued after the power-off command is equal to the number of memory cell array banks that have not performed the current column refresh operation. 22. A memory system comprising: At least one memory unit having n memory banks and an addressable memory bank auto-refresh operation, the memory unit including an auto-refresh circuit that addresses a refresh column of each addressed memory bank to perform an auto-refresh operation until η memory banks have been completed in at least one automatic refresh operation 34 12779835Pifd〇c ==! The circuit in the unit causes the refresh in each memory that has not been addressed to be listed in the self-refresh mode to complete the refresh operation; Address: It claims to start the instruction and provide external refresh memory location t ΙΪΓ 1 1 of n consecutive automatic refresh operations For the n-memory-connection _ 23. The automatic refresh operation of the memory unit is started as described in claim 22 of the patent application. The person described in item 23, wherein the pre-emptive refresh Back to the external refresh signal line on the line has been = when; column instructions, 2 items of the _, system, including the system of the ί 适 适 执 6 6 · · · · · · 丨 丨 丨 丨 , , , , , , , , , , , Solid independent addressable memory cell array library · Current operation = bit address generator, called all memory cell array library 35 12779843⁄43⁄4 d〇c Refresh second bank = stop == to receive - externally provided memory address to The memory cell array library should be used; the clearing should be in the memory address of the memory, and the data in the memory cell _ library will be completed. Generate a new _ new column; and give the refresh address a record of the soap, from the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Operation. The synchronous memory element described in Item 26 of the self-enclosed, refreshing its self-refresh mode The self-reported 1=^ externally provided memory address or the synchronous memory element described in item 27 of the self-brushing, wherein the brother-switch in the self-mode cap selects the self-memory memory location i\V 〇 29. A synchronous memory component as claimed in claim 28, wherein the memory bank = address is generated before the current refresh column is updated from the refresh mode, and the self-forest memory address memory is generated. Array library. 3〇· As stated in the scope of the patent, the synchronous memory component, 36 12779835^^ (4) generator ===: before the column, the memory has not yet executed the address of the current column address for the refresh operation The synchronous memory component described in item 28, wherein the more-array array library selects all the memory sheets including the 28-represented _remembering elements when performing the first ΐ refresh mode, and the refresh operation is selected when entering the self-refresh mode before the executor All memory cell array libraries of the new column address are executed. == Synchronization as described in item 27 of the patent application scope is currently refreshed in the self-refresh mode =/, the switch selects the self-refresh memory location ^ is updated to new - At the time of the first synchronous memory component described in item 33 of the profit range, the new operation of the self-refreshing memory address is selected in the refresher wheel before the new operation, and the cattle continue to receive the externally provided memory. The address is used to brush the _(10) component of the rtf patent (4), item 34, until the person 2 receives the externally provided memory address for refreshing all the H-address operations of the front-end addressing. . The address of the refreshing operation of the ~70 train library is the same as that of the 34th item of the patent. The self-refresh mode receives the n externally provided 37 memory addresses for the refresh operation. 37. As in the scope of the patent application, the first-switch acts as a synchronous memory element of =. Should, ride, 库 address counter wheel 38 · If the application scope of the patent range, I refresh the clock circuit to include -,, the synchronous memory component, provide 1 new from the meaning; the self-refresh clock occurs in the pulse self器 = item memory element, its side 'and - self-lining time 4 refresh mode, the automatic brush special tree occurs two generations - ' "in the self-start refresh clock generator start with the first yarn ^ ^" the self-refresh The clock generator is at the second speed; the raw signal; the self-refreshing clock generator has an output stage (. turns out the clock signal, and the self-clock generator performs the self-refresh with the self-refresh or (OR赖 Operation. U output % pulse from the component, which selects all memory cell array libraries with " ^ &amp; as described in claim 35 of the synchronous memory component, its 38 1277983⁄4^ iloi疋 circuit includes ·· Delay circuit to delay self-refreshing clock; one and one to receive self-refreshing clock and delay self-refreshing clock · to line all fresh (four) solution (four) memory address in the patent application scope mentioned in item 26 Synchronized The new circuit includes a setting ^ Wu member, the entire memory cell = # new work has not been executed when the pepper ^ 39