TWI277299B - Operation circuit of Galois field multiplicative inverse for advanced encryption standard (AES) chip design - Google Patents

Abstract

The present invention provides an operation circuit of Galois field multiplicative inverse for advanced encryption standard (AES) chip design that employs a first operation circuit to conduct fourth-order operation process of the input bytes, a second operation circuit to conduct third-order operation process of the input bytes, a plurality of multiplication circuits to conduct multiplication of the output result of the two preceding circuits, a third operation circuit to conduct second-order operation process of the output result of its preceding circuits, a fourth operation circuit to conduct eighth-order operation process of the output result of its preceding circuits, and a fifth operation circuit to conduct 32th-order operation process of the output result of its preceding circuits. Thus, the operations of Galois Field multiplicative inverse and the function of look-up table for substituting conversion operation by the bytes used in AES encryption process can be accomplished.

Description

1277299 A7 B7 V. INSTRUCTION DESCRIPTION (I) [Technical Field] The present invention relates to an arithmetic circuit, and more particularly to an AES chip design suitable for an operational circuit using a finite multiplication inverse element. [Background of the Invention] According to the continuous advancement of the information industry, the application and methods used in information security are constantly changing, from the early use of Data Encryption Standard (DES) to 2〇〇〇. Wuyi National Institute of Standards and Technology (Nati〇nal μ)

Standard and Technology, NIST) announced the revision of the algorithmic version of the advanced encryption standard (En... called (10) Standard, AES) that will replace DES. However, if AES is used to encrypt data, it must undergo several rounds of operations. Each round of operations includes the following sub-operations: byte substitution conversion, shift conversion, mixed-line conversion, and addition of alloy key. process. Among them, to achieve the most efficient way to replace the conversion of the byte, that is, use an index comparison table (1〇〇k-uptable), but the index comparison table in the byte replacement usually requires 256 bytes in the memory. In the device. Taking the memory capacity of a smart card as an example, cable = occupying a large space in the design of the chip, which causes an increase in production cost. It is not easy to do so, although there is already a way to use the square characteristic, the circuit can also be used to achieve the work of replacing the index comparison table - a private diagram shows the circuit diagram, the delay of using the circuit: force 4 paper size for China National Standard (CNS) A4 Specification (21〇χ 297 mm item t

1277299 A7 V. Description of the invention (again

Tme ) is about 122 nanoseconds, this delay is too high and the area is too large. (4) In terms of its work, its time cost still indicates that people are guilty of this, and it is actively used to solve the above FI %, r + < spirit 'though a kind of crystallizable: finite body multiplication and anti-element operation circuit _ : month After all the research and experiments, the completion of this project will be completed.

[Overview of the present invention] 2] The purpose of the king is to provide a finite body multiplication and anti-element. In the AES chip design, a finite-body inverter is used to achieve the byte of the fine encryption deduction method. Instead of a ByteSub circuit, an index-saving table for storing the replacement box is avoided to achieve a wafer-saving area.

Another object of the present invention is to provide an operation circuit for finite body multiplication and anti-element, which can be separately designed in a wafer, and designed by other people on other large system wafers S〇C (System 〇n Chip). A smaller AES encryption module, and reduce power consumption, or can be used in other systems that require finite body multiplication and anti-element operations, such as RS error correction code (Reed-Ministry of Commerce, Intellectual Property Bureau, Staff Cooperatives, Printing^^

Solomon Code) and so on. In order to achieve the above object, the arithmetic circuit proposed by the present invention mainly comprises: a first arithmetic circuit, which performs a fourth power operation on the input byte and outputs the result to the next stage; a second operation circuit Perform cubic processing on the input byte and output the result to the next stage; a plurality of multiplication circuits multiply the output of the two circuits of the previous stage, and the paper scale applies the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) 1277299 A7 --——--- -B7 ------------ V. Description of invention (3) - Output the result to the lower-level; - third operation The circuit performs quadratic operation on the output result of the pre-stage circuit, and outputs the result to the lower-level; a fourth operation circuit performs the eighth-order operation on the output result of the pre-stage circuit ^ and outputs the result to The next stage; and a fifth operation circuit, performing a thirty-square operation on the output result of the pre-stage circuit, and outputting the result to the lower stage, wherein the output end of the second operation circuit is connected to the fourth operation circuit Input, and the first and second operations The circuit end is connected to the input end of the first multiplication circuit, and the output end of the multiplication circuit is connected to the input end of the fifth operation circuit, and the output ends of the third and fourth operation circuits are connected to the second multiplication method An input end of the circuit, and the output of the multiplication pen is connected to an input end of the third multiplication circuit, the other input end of the third multiplication circuit is connected to an output end of the fifth operation circuit, and the third The output of the multiplication circuit is the result of the operation. Since the invention has novel construction, can provide industrial utilization, and has an improvement effect, it applies for an invention patent according to law. In order to enable the review board to further understand the structure, features and objects of the present invention, the detailed description of the drawings and the preferred embodiments is as follows: (Please read the notes on the back) Pages ϋ 订 订 订 订 订 订 订 订 订 订 订 订 订 订 经济 经济 经济 经济 经济 经济 经济 经济 经济 经济 经济 经济 经济 经济 经济 【 【 【 【 【 【 【 【 【 【 【 【 【 Circuit Diagram 0 Figure 2 shows the AES wafer design diagram of the finite-body multi-element anti-element circuit of the present invention. 6 This paper scale applies to China National Standard (CNS) A4 ^ grid (210 X 297 public) one to five Description of the Invention (Thousands) 2 The figure shows the operation of the finite-body inverter of the present invention, the operation of the multi-element anti-element, and the affine conversion circuit. [Description of the figure], the first operation circuit 21, the second operation circuit 22 The first multiplication circuit 231, the second multiplication circuit 232, the third multiplication circuit 233, the third operation circuit 24, the fourth operation circuit 25, the fifth operation circuit 26, and the detailed description of the specific embodiment of the present invention. Body multiplication For a preferred embodiment of the AES chip design, please refer to the operational diagram shown in FIG. 2, which includes: a first operation circuit 21, a second operation circuit 22, a first multiplication circuit 231, and a second The multiplication circuit 232, the third multiplication circuit 233, the third operation circuit 24, the fourth operation circuit 25, and the fifth operation circuit 26 are all implemented by a finite body inversion operation, wherein 'limited The expression of element A of GF(2m) and its inverse element A-1 can be written as AA~l =1 = ^-1 =A^A2m'2 9 However, the mathematical model used in the AES encryption algorithm is Gf(28), it can be known that the inversion element A·1 is A 2 5 4. In the present embodiment, the trigonometric and quadrilateral characteristics are used to achieve the effect of the inverse element A·1 being 254th power, and the operation thereof The formula can be expressed as the Chinese National Standard (CNS) A4 specification for the paper scale (2) 〇 x 297 mm) 1277299 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing A7 V. Invention description (5 A - A to 54 = ( (/).(/))32.((/)2.(/)8) 〇, the above-mentioned first-operation circuit 21 is used for input byte A The fourth operation circuit 22 is also used to perform three-person operation processing on the input byte A, and the first multiplication circuit 231 is used to calculate the result A4 and the first operation circuit. The output result A3 of the second operation circuit 22 is multiplied to obtain the operation result A7. The third operation circuit μ is used to perform the quadratic operation processing on the output result A3 of the second operation circuit 22 (4) The operation result A6. The operation circuit 25 is configured to perform an eighth-order operation on the output result of the second operation circuit 22 to obtain an operation result AH. The fifth operation circuit 26 is configured to output the result A of the multiplication operation of the first multiplication circuit 23 1 into a twenty-one operation process to obtain the operation result A"4. The second multiplication circuit 232 is used to perform the third operation. The output result a6 of the circuit is multiplied with the output result A24 of the fourth operation circuit 22 to obtain the operation result a3G. The second multiplication circuit 233 is used to output the result A 2 2 4 and the second multiplication circuit 232 to the fifth operation circuit. The output result is multiplied to obtain a final operation result A254, and the multiplication result is outputted to obtain the multiplication inverse element of the operation #limit GF (28), and the result can be used for the AES bit. The group substitution conversion table (ByteSub) replacement table ^ index comparison table function. Of course, the first operation circuit 21, the second operation circuit Μ, the third operation circuit 24, the fourth operation circuit 25, or the fifth operation circuit ^ It can also be achieved by using other finite basic circuit. The circuit of this example can be used in AES chip design system (System 〇n _____ 8 paper scale applicable _石$准 (CNS) aI specification (210 X 297 public i

l·Installation • n n n (Please read the back note on this page first)

Order ---------Line L V. Invention Description (6) Technology, %-type inter-programmable array (Field pr〇gummab e Gate 'FPGA), or complex programmable logic element (CPLD) IC The design technique is implemented on a wafer. After the experiment, the measured delay time is about 65 奈 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋The entire AES encryption process, and the arithmetic circuit of the present embodiment can also be combined with an affine conversion circuit module to become a byte used in the AES design instead of the conversion circuit, as shown in FIG. The group replaces the conversion circuit, and its delay time is only (one) nanoseconds. As can be seen from the above description, the present invention utilizes the first, second, third, fourth, and fifth arithmetic circuits and a plurality of multiplying circuits, and performs the arithmetic operation in the pipeline to cooperate with the affine computing circuit to achieve aes The bytes in the encryption replace the converted index table function and greatly reduce the delay time and area. In summary, the present invention, regardless of its purpose, means, and efficacy, is characterized by its distinctiveness from the prior art, and is a breakthrough in the "AES encryption circuit". You are requested to review the examination and express the patent as soon as possible. The 俾嘉金 Society is truly sensible. It is to be noted that the various embodiments described above are intended to be illustrative only, and the scope of the invention is intended to be limited by the scope of the appended claims. ~

Claims (1)

1277299 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 1. A finite body multiplication and anti-element operation circuit, mainly including: a first-operation circuit, the system, the four-way operation of the input byte and the result is output to the next a second operation circuit, which performs a cubic operation on the input byte and outputs the result to the next stage; a plurality of multiplication circuits process the output of the second circuit of the previous stage, and output the result to the next First stage; / - The third operation circuit performs secondary calculation on the result of the previous stage circuit rotation and outputs the result to the next stage; ^ - The fourth operation circuit performs eight times of the output of the previous stage circuit Calculating the process 'and outputting the result to the next stage; and a fifth arithmetic circuit, performing a thirty-square operation on the output result of the previous stage circuit, and outputting the result to the next stage; /Λ where the second operation The output end of the circuit is connected to the input end of the third and fourth differential circuits, and the output ends of the first and second arithmetic circuits are connected to the input end of the first multiplication circuit, and the multiplication circuit is Output system Connected to the input end of the fifth arithmetic circuit, and the shank ends of the third and fourth operational circuits are connected to the input end of the first multiplication circuit, and the output end of the multiplication circuit is connected to the third multiplication circuit At the input end, the other input end of the third multiplier is connected to the output end of the fifth operation circuit, and the output of the third multiplication circuit is the operation result. Theory 10 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) r Jing Xian read the back of the >it matter and then this page)