TWI275919B - Quick-recovery low dropout linear regulator - Google Patents
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1275919 九、發明說明· 【發明所屬之技術領域】 本發明係有關一種低壓降線性穩壓器(1 〇w dr op-out linear regula1:〇r ; LDO),尤其有關於一種輸出電流突然 有大變化時,可快速回復到穩定電壓輸出之低壓降線性穩 壓器。 【先前技術】 在通訊市場逐漸成熟發展之際,相關1C的應用更是不 # 斷成長。然而隨著如手機等可攜市產品的發展,電池的使 用時間長短更是額外重要。如何提高電池的功率效並且維 持其一定的穩定性是一個相當有挑戰的課題。近年來低壓 降線性穩壓器(low dr〇P—out linear regulator,簡稱 LDO)因為其轉換效率的提昇,加上其小體積、低雜訊的特 性,成為小功率降壓與穩壓電路的主流。在各式由電池供 應電源的可攜式系統以及通訊相關的電子產品上,均被大 量地使用。 在現有的產品(方法)中’為了讓低壓降線性穩壓器 更加地精確,一般而言會採用三級串聯方式的運算放大器 (operational amplifier)來增大其增益’然而卻會因此造 成不穩定的情形。所以,不斷地有人提出各式各樣的頻率 補償方法來達到系統的穩定。一開始’有人提出利用外加 大電容來降低主極點位置而增加相位邊際。不過此卻也有 如以下之缺點: 由於此類電路的主極點落於輸出點’因此需要較大負 1275919 載電容來穩定系統,然而因此不容易將此電容做在晶片内 部,會增加系統整合性上的困難。 一般而言,我們希望較大的系統增益來提升系統的精 準度,然而提升增益相對的卻降低了系統的穩定度,因此 會造成精準度與穩定度之間的取捨。 輸出電流大小會受限於系統的穩定性。因為輸出電流 越大,代表著負載電阻越小,因此相對的位於輸出點的主 極點也越大,因此會使的系統的穩定性越差。 由於此電路的非主極點位於運算放大器的輸出點(一 般而言為高阻抗),因此相對的第一非主極點 non-dominant pole)較低,因而降低了系統的頻寬,也使 得其暫態響應變差。 因此,為了改善以上的缺點,不斷地有人提出了各5 各樣的頻率補償方法,如:巢式米勒補償、阻尼係數(控1275919 IX. INSTRUCTIONS DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a low-dropout linear regulator (1 〇w dr op-out linear regula1: 〇r; LDO), and particularly relates to an output current suddenly large When changing, it can quickly return to a low-dropout linear regulator with a stable voltage output. [Prior Art] As the communication market matures, the application of related 1C is not growing. However, with the development of portable products such as mobile phones, the length of use of batteries is even more important. How to improve the power efficiency of the battery and maintain its stability is a very challenging topic. In recent years, low-drop P-out linear regulator (LDO) has become a low-power buck and regulator circuit because of its improved conversion efficiency and its small size and low noise. Mainstream. It is used in a large number of portable systems and communication-related electronic products that are powered by batteries. In the existing products (methods), in order to make the low-dropout linear regulator more accurate, a three-stage series operation amplifier is generally used to increase its gain, but it will cause instability. The situation. Therefore, various frequency compensation methods have been proposed to achieve system stability. At the beginning, it was proposed to increase the phase margin by using an external capacitor to lower the main pole position. However, this also has the following disadvantages: Since the main pole of such a circuit falls on the output point, it requires a large negative 1275919 load capacitance to stabilize the system. However, it is not easy to make this capacitor inside the chip, which increases system integration. Difficulties. In general, we want a larger system gain to improve the accuracy of the system. However, increasing the gain relative to the system reduces the stability of the system, thus causing a trade-off between accuracy and stability. The magnitude of the output current is limited by the stability of the system. Because the larger the output current, the smaller the load resistance, the larger the main pole at the output point, and the worse the stability of the system. Since the non-primary pole of this circuit is located at the output point of the operational amplifier (generally high impedance), the relative non-dominant pole of the first pole is lower, thus reducing the bandwidth of the system and also making it temporarily The state response is worse. Therefore, in order to improve the above shortcomings, various kinds of frequency compensation methods have been proposed, such as: nested Miller compensation, damping coefficient (control
制:··等。然而這些方法都需要兩個補償電容、因此㈣ 而言’其使狀晶片面積又比簡單的米勒補償方法大,戶) 則 了利用增益放大之單一米勒補償,物 第1圖」所示。此方法雖成功地解決了上述的問題,作 其阻尼係數f卻受輸出電流大小System:··etc. However, these methods require two compensation capacitors, so (4) 'the size of the wafer is larger than the simple Miller compensation method, and the household uses a single Miller compensation using gain amplification, as shown in Figure 1 . Although this method successfully solves the above problem, the damping coefficient f is affected by the output current.
Vout敎的速度。 歧其輸出電塵 请參閱「第2圖」所示,為「第口 模型’其中gml,gm2,gmp分別為。二”戒號 導,gol £〇2 d A楚為, 第一和輸出級的傳 ,’—、、及、第二級和輪出級的輸出電導, 6 .1275919The speed of Vout敎. For the output dust, please refer to "Figure 2", which is "the first model" where gml, gm2, gmp are respectively. Two" ring number guide, gol £〇2 d A Chu, first and output stage Pass, '-,, and, second and round output conductance, 6.1275919
Cpi、Cg分別為第二跟輸出級的輸入寄生電容。c〇叶為負 載電各Re為負載電谷的寄生電阻,cmi、Rm為補償電容 與補償電阻。Adc為系、统的直流增益、為阻尼係數。由「第 ^圖」的小訊號模型(smaU signal贴和丨)可推導得其 系統轉換方程式如下··Cpi and Cg are the input parasitic capacitances of the second and output stages, respectively. C〇 is the negative load. Each Re is the parasitic resistance of the load cell, and cmi and Rm are the compensation capacitor and the compensation resistor. Adc is the DC gain of the system and system, and is the damping coefficient. The system model conversion equation can be derived from the small signal model (smaU signal) and "丨".
Av (s) ^λ 0 + sc out re^\ sc -)-s c mlc ^ m 2 S m p scAv (s) ^λ 0 + sc out re^\ sc -)-s c mlc ^ m 2 S m p sc
社丄At = · 具中 p _ ^mlSmlSm r-3db ~ S〇\S〇2Sl aSociety At = · with p _ ^mlSmlSm r-3db ~ S〇\S〇2Sl a
R S〇2 SmlSi mP J' I SmlSt mp _ f〇f small lb2 aR S〇2 SmlSi mP J' I SmlSt mp _ f〇f small lb2 a
Smr 為了減少所需成本,目前市場傾向使In order to reduce the cost of Smr, the current market tends to
:宜的電容作為負載電容。然而陶究電容本身二= 車乂小’因此由(2)式可簡化得(3)式。 比且:】 阻尼係數'與輸出級傳導⑹成反 、.及放大器之偏壓電流(Ib2)成正比,由於當輸出 電、-變大(例如由〇.lm“> 15〇mA )時,輸 ^著變大)’因此會使得阻尼術變小而^ 附近^ΘΓ、於υ’錢得頻⑽應在單位增益頻率 附近曰有大波’以致於當輸出電流突然變化時,輸出電壓 7 1275919 : Vout的暫態響應上會產生連波而減緩其穩定的速度,而無 法提供一快速穩定之低壓降線性穩壓器。 【發明内容】 爰是,本發明之主要目的係在動態調整第二級放大器 的偏壓電流,來補償輸出電流變化對阻尼係數Γ的影響, 以消除頻率響應的突波並加快輸出電壓的穩定速度。 本發明係為一種快速回復之低壓降線性穩壓器,其具 有一具增益放大單一米勒補償電容之低壓降線性穩壓器 ® 電路,該低壓降線性穩壓器電路具有一第二級放大器(2nd stage amplifier)且具有一輸出電流供一負載使用,其包 含有一電流偵測電路、一比較電路、一控制元件與一加壓 電路,該電流偵測電路用於偵測該補償電路之該輸出電流 • 的大小,以輸出一相對應之比較電流;該比較電路,輸入 該比較電流與一固定之參考電流,以利用該比較電路作大 小比較並產生一比較訊號;該控制元件係由該比較訊號操 • 控’並輸出一控制訊號;該加壓電路’用以改變該第二級 放大器之偏壓電流,該加壓電路接收該控制元件之該控制 訊號,以決定是否改變該第二級放大器之偏壓電流;據此 當該比較電流大於該參考電流,該比較電路即輸出該比較 訊號控制該加壓電路增加該第二級放大器之偏壓電流,據 以抵銷輸出電流變化對阻尼係數Γ的影響以減少暫態響 應上輸出電壓的連波,並加快其穩定速度。 【實施方式】 8 1275919 茲有關本發明之詳細内容及技術說明,現配合圖式說 明如下: 請參閱「第3圖」所示,其為本發明之系統電路圖, 其包含一具增益放大單一米勒補償電容(Miuer capacitor)之低壓降線性穩壓器電路1〇,其係利用高準位 供應電壓Vdd供應所需之驅動電壓,該低壓降線性穩壓器 電路10具有一第二級放大器1〇1且具有一輸出電流^供 φ 一負載使用,其利用電流鏡(current mirror)原理採用兩 個電晶體MP、MPR形成一電流偵測電路2〇,並可再利用放 大器30形成一負回授(feedback)機制,去精準的偵測低 壓降線性穩壓為電路1 〇之輸出電流11G,並輸出一相對應 之比較電流I2。,且為了降低電路之負載與消耗,該比較電 Sil 12。的大小值可以倍數縮小,如讓12。= I iq/k ;其中κ係 為電晶體MP、MPR之特性所決定。 該比較電流與一個固定之參考電流Iref,利用一比 Φ 較電路40作比較,以輸出一比較訊號,該參考電流Iref 係高準位供應電壓Vdd、Vb與電晶體MI所產生,該比較 電路40係可由1比1 NM0S之電流鏡41所構成,其分別 輸入該比較電流12〇與該參考電流Iref,且具有一高阻抗點 Vr,该咼阻抗點Vr之兩端分別為該參考電流I w與1比1 丽0S之電流鏡41依據該比較電流所產生相等之電流 14〇,藉由量測該高阻抗點Vr之電流變化,即可作電流比 較,並產生一比較訊號。 9 1275919 : 該比較訊號係用於輸入於一控制元件50以產生一控 制訊號,而該控制元件50可以利用二串聯之反向器invn、 invp所構成,並與該高阻抗點Vr連接,因而由高阻抗點 Vr的電流變化所產生之該比較訊號,經由該二串聯之反向 器 invn、invp (Inverter),即產生一(invn、invp)之 〇、 1控制訊號。 該控制訊號,係用於控制加壓電路6〇,而加壓電路 Φ 60係用於改變該第二級放大器101之偏壓電流,該加壓電 路60係可由電晶體MSP、M24a、M22a與MSN所構成,以 利用該控制訊號控制電晶體MSP、MSN之導通與否來增加 第二級放大器101之偏壓電流。 本發明在運作前,須先決定該參考電流Iref的大小 值,該參考電流Iref的最佳設計值係與系統之阻尼係數( 小於1日守所具有的輸出電流11〇有_,若輸出電流L。的大 小值為A時,其系統之阻尼係數『即會小於i,則該參考 Φ 電流Iref的數值可設為A/K。 本么月在運作時可以分為兩個狀態,首先當輸出電流 I!。以輕載輸出時’此時系統之阻尼係數於卜該比較 電流KWK)小於參考電流Ire”此時該控制元件5〇二 串聯之反向器之控制訊號為Unvn : 〇、_ : n,讓該電 ^體MSP、MSN之開關關閉而為開路,故此時第二級放大 的偏壓電流沒有變大,然此時系統之阻尼係數Γ仍 其並不需要補償’即可讓輸出電流I1Q之輸出電壓 • 1275919: The capacitor should be used as the load capacitor. However, the ceramic capacitor itself 2 = ruth is small, so the equation (3) can be simplified to (3). Ratio and:] The damping coefficient 'is inversely proportional to the output stage conduction (6), and the bias current (Ib2) of the amplifier, since the output power, - becomes large (for example, by 〇.lm "> 15 mA") , the output will become larger) 'So it will make the damping become smaller and ^ nearby ^ ΘΓ, υ 钱 'money frequency (10) should have a large wave near the unity gain frequency 'so that when the output current suddenly changes, the output voltage 7 1275919: The transient response of Vout will generate a continuous wave to slow down its stability, and it cannot provide a fast and stable low-dropout linear regulator. [Summary content] The main purpose of the present invention is to dynamically adjust the first The bias current of the secondary amplifier compensates for the influence of the output current variation on the damping coefficient , to eliminate the frequency response glitch and accelerate the stable speed of the output voltage. The present invention is a fast recovery low dropout linear regulator, It has a low-dropout linear regulator® circuit with a gain-amplified single Miller compensation capacitor, the low-dropout linear regulator circuit has a second-stage amplifier and has an output current a load is used, comprising a current detecting circuit, a comparing circuit, a control component and a pressurizing circuit, wherein the current detecting circuit is configured to detect the magnitude of the output current of the compensation circuit to output a corresponding one Comparing current; the comparison circuit inputs the comparison current and a fixed reference current to compare the size of the comparison circuit and generate a comparison signal; the control component controls and outputs a control signal by the comparison signal The pressing circuit 'to change the bias current of the second stage amplifier, the pressing circuit receiving the control signal of the control element to determine whether to change the bias current of the second stage amplifier; The comparison current is greater than the reference current, and the comparison circuit outputs the comparison signal to control the pressure circuit to increase the bias current of the second stage amplifier, thereby offsetting the influence of the output current variation on the damping coefficient 以 to reduce the transient response. The output voltage is connected to the wave and accelerates its steady speed. [Embodiment] 8 1275919 Details and technical description of the present invention Now, the following diagram is described as follows: Please refer to "Figure 3", which is a circuit diagram of the system of the present invention, which comprises a low-dropout linear regulator circuit 1 with a gain-amplified single Miller compensation capacitor (Miuer capacitor) That is, it supplies a required driving voltage by using a high-level supply voltage Vdd having a second-stage amplifier 1〇1 and having an output current for use by a load of φ, which utilizes The current mirror principle uses two transistors MP, MPR to form a current detecting circuit 2〇, and can use the amplifier 30 to form a negative feedback mechanism to accurately detect low-dropout linear voltage regulator. It is the output current 11G of circuit 1 and outputs a corresponding comparison current I2. And in order to reduce the load and consumption of the circuit, the comparison is Sil 12. The size value can be reduced by a multiple, such as let 12. = I iq / k ; where κ is determined by the characteristics of the transistors MP and MPR. The comparison current is compared with a fixed reference current Iref by a ratio Φ compared to the circuit 40 to output a comparison signal, the reference current Iref being generated by the high level supply voltages Vdd, Vb and the transistor MI, the comparison circuit The 40 series can be composed of a 1 to 1 NM0S current mirror 41, which respectively inputs the comparison current 12 〇 and the reference current Iref, and has a high impedance point Vr, and the two ends of the 咼 impedance point Vr are respectively the reference current I w and 1 to 1 0 0S current mirror 41 according to the comparison current generated by the same current 14 〇, by measuring the current change of the high impedance point Vr, can be used for current comparison, and generate a comparison signal. 9 1275919: The comparison signal is used for inputting to a control component 50 to generate a control signal, and the control component 50 can be constructed by using two series inverters invn, invp, and connected to the high impedance point Vr. The comparison signal generated by the current change of the high-impedance point Vr is generated by an inverter (invn, invp) and a control signal via the two series inverters invn and invp (Inverter). The control signal is used to control the pressurization circuit 6A, and the pressurization circuit Φ 60 is used to change the bias current of the second stage amplifier 101. The pressurization circuit 60 can be composed of transistors MSP, M24a, M22a and The MSN is configured to increase the bias current of the second stage amplifier 101 by controlling the conduction of the transistors MSP, MSN by the control signal. Before the operation of the invention, the magnitude of the reference current Iref must be determined first. The optimal design value of the reference current Iref is the damping coefficient of the system (the output current of the system is less than 1 守, if the output current is When the size of L is A, the damping coefficient of the system is less than i, then the value of the reference Φ current Iref can be set to A/K. This month can be divided into two states when operating, first Output current I!. At light load output, 'the damping coefficient of the system at this time is less than the reference current IKW' is less than the reference current Ire". At this time, the control signal of the inverter of the control unit 5〇2 series is Unvn: 〇, _ : n, let the switch of the MSP, MSN switch be open, so the bias current of the second stage amplification does not become large, then the damping coefficient of the system Γ still does not need to compensate ' Let the output current I1Q output voltage • 1275919
Vout快速達到穩定。 大=出電流L。改以重载輸出時’其輸出電流ί10變 4統之阻尼係數Μ始變小,㈣電流 開始有不穩定之漣消產生;然當比較電流=Vout is fast and stable. Large = current L. When changing to the heavy-duty output, the output coefficient of the output current ί10 becomes smaller, and the damping coefficient starts to become smaller. (4) The current starts to be unstable and is generated;
哭:机ref的鮮間,此時該控制元件50二串聯之反向 11 in vp之控制訊號轉變為(i n vn : 1、i n Vp : 〇), 而讓電晶體MSP、MSN之開關打開而加大了第二級放大哭 的偏壓電流’又因為阻尼係數Γ與第二級放大器^ 的偏塵電流成正比,故本發明藉由加大第二級放大器ι〇ι 的偏壓電流,即可補償輸出電流[。對阻尼係數Γ的影響, 讓阻尼係數Γ可以簡適㈣值(大於υ。因此當輸出曰電 流L·。由輕载(如〇. lmA)轉換至重載(如15〇mA)時,其輸出 電流I1G之輸出電壓v〇ut亦可快速達到穩定之狀態。 請再參閱「第4圖」與「第5圖」所示,其分別為該 低壓降線性穩壓器電路10未補償時所得 及暫態響應圖。由「第4圖」所示,明顯可見當曰輪: in改以重載輸出時,頻率響應圖在單位增益頻率(uni邙 gain frequency)附近會有突波,也因此「第4圖」的暫 態響應圖上會有不少漣波的產生,以致於其輸出電壓v〇ut 之穩定時間需耗時34微秒。 請再參閱「第6圖」與「第7圖」所示,分別為該低 壓降線性穩壓器電路10補償後所得的頻率響應 (frequency response)圖以及暫態響應(transient 11 • 127591-9 response)圖。由「第6圖」可見,在單位增益頻率附近 並無突波的產生,也因此「第7圖」中可見,暫態響應上 之漣波減少因而得以快速達到穩定(約8微秒);因此本發 明在輸出電流L。改以重載輸出時,其仍然可以快速讓輸』 電流Ιιο之輸出電壓V〇ut回復至穩定之狀態。 惟上述僅為本發明之較佳實施例而已,並非用來限定 本發明實施之範圍,即凡依本發明申請專利範圍所做的均 Φ等變化與修飾,皆為本發明專利範圍所涵蓋。 【圖式簡單說明】 第1圖,係習知之低壓降線性穩壓器。 第2圖,係第1圖之小訊號模型。 第3圖,係本發明之系統電路圖。 第4圖,係本發明未補償時之頻率響應圖。 第5圖,係本發明未補償時之暫態響應圖。 第6圖,係本發明補償後之頻率響應圖。 % 第7圖,係本發明補償後之暫態響應圖。 【主要元件符號說明】 Ιι〇 :輸出電流 I 20 ·比車父電流 140 :電流 invn、invp :反向器Crying: the fresh room of the machine ref, at this time, the control signal 50 in the reverse direction of the 11 in vp control signal is converted into (in vn : 1, in Vp : 〇), and the switches of the transistors MSP, MSN are turned on. By increasing the bias current of the second stage amplification crying, and because the damping coefficient 成 is proportional to the dust current of the second stage amplifier ^, the present invention increases the bias current of the second stage amplifier ι〇ι, The output current can be compensated [. For the influence of the damping coefficient Γ, let the damping coefficient Γ be simple (four) value (greater than υ. Therefore, when the output 曰 current L·. is converted from light load (such as 〇.lmA) to heavy load (such as 15 mA), The output voltage v〇ut of the output current I1G can also quickly reach a stable state. Please refer to "Fig. 4" and "Fig. 5", respectively, which are obtained when the low-dropout linear regulator circuit 10 is not compensated. And the transient response diagram. As shown in Figure 4, it is obvious that when the 曰 wheel: in is changed to the heavy load output, the frequency response diagram will have a glitch near the unit uni frequency (uni邙gain frequency), and therefore There will be a lot of chopping on the transient response graph of "Fig. 4", so that the stabilization time of the output voltage v〇ut takes 34 microseconds. Please refer to "6th" and "7th". The frequency response diagram and the transient response (transient 11 • 127591-9 response) obtained by the low-dropout linear regulator circuit 10 are shown in Fig. 6, which can be seen from Fig. 6. There is no surge near the unity gain frequency, so it can be seen in Figure 7. The chopping on the transient response is reduced so that it can be quickly stabilized (about 8 microseconds); therefore, the present invention can quickly output the output voltage V〇 when the output current L is changed to the heavy load output. The ut is restored to a stable state. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the practice of the present invention, that is, all changes and modifications of the Φ according to the scope of the present invention are The invention is covered by the scope of the invention. [Simplified description of the drawings] Fig. 1 is a conventional low-dropout linear regulator. Fig. 2 is a small signal model of Fig. 1. Fig. 3 is a circuit diagram of the system of the present invention. Fig. 4 is a frequency response diagram of the present invention when uncompensated. Fig. 5 is a transient response diagram of the present invention when uncompensated. Fig. 6 is a diagram of the frequency response after compensation according to the present invention. , is the transient response diagram of the invention after compensation. [Main component symbol description] Ιι〇: output current I 20 · than the parent current 140 : current invn, invp: reverser
Iref :參考電流 MP、MPR、MI :電晶體 12 1275919 MSP、MSN、M24a、M22a :電晶體 Vdd、Vb :高準位供應電壓 Vr :高阻抗點 Vout :輸出電壓 10 :低壓降線性穩壓器電路 101 :第二級放大器 20 :電流偵測電路 30 :放大器 • 40 :比較電路 41 :電流鏡 50 :控制元件 60 :加壓電路Iref: Reference current MP, MPR, MI: Transistor 12 1275919 MSP, MSN, M24a, M22a: Transistor Vdd, Vb: High level supply voltage Vr: High impedance point Vout: Output voltage 10: Low dropout linear regulator Circuit 101: second stage amplifier 20: current detecting circuit 30: amplifier • 40: comparison circuit 41: current mirror 50: control element 60: pressurizing circuit
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TWI407288B (en) * | 2009-05-14 | 2013-09-01 | Sanyo Electric Co | Power source circuit |
TWI668552B (en) * | 2017-03-08 | 2019-08-11 | 大陸商長江存儲科技有限責任公司 | Low-dropout regulators |
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TWI425336B (en) * | 2010-12-06 | 2014-02-01 | Univ Nat Chiao Tung | A low-dropout voltage regulator and a use method thereof |
TWI456425B (en) * | 2012-01-03 | 2014-10-11 | Univ Nat Taipei Technology | Method and system for generating small signal model of voltage converter, computer program product |
TWI494735B (en) * | 2013-04-15 | 2015-08-01 | Novatek Microelectronics Corp | Compensation module and voltage regulation device |
TWI514104B (en) * | 2014-07-11 | 2015-12-21 | Novatek Microelectronics Corp | Current source for voltage regulator and voltage regulator thereof |
TWI668550B (en) * | 2018-06-14 | 2019-08-11 | 華邦電子股份有限公司 | Current regulating circuit and method |
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TWI407288B (en) * | 2009-05-14 | 2013-09-01 | Sanyo Electric Co | Power source circuit |
TWI668552B (en) * | 2017-03-08 | 2019-08-11 | 大陸商長江存儲科技有限責任公司 | Low-dropout regulators |
US10423176B2 (en) | 2017-03-08 | 2019-09-24 | Yangtze Memory Technologies Co., Ltd. | Low-dropout regulators |
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