TWI275279B - Demodulation method based on delay sampling - Google Patents

Abstract

Disclosed is a demodulation method that is based on delay sampling, wherein a signal that is processed by a limiting amplifier is taken as an input signal and the input signal is duplicated of which one is directly fed to an input of a delayed sampler, while the other is transmitted through a delay line so that the signal transmitting through the delay line generates different outputs of different time delays. The delayed output signal is also further fed through a delayed sampler to obtain sampled data; said data are then converted by a temperature code-binary code converter into binary code, which is then fed through and processed by a data determination circuit to obtain and recover the base-band data.

Description

J275279 IX. Description of the Invention: [Technical Field] The present invention relates to a demodulation method for a latent sampling technique, and more particularly to a time-to-bit conversion using a delayed-sampling technique. -digital conversion), phase demodulation (phasedem〇dulati〇n) or frequency demodulation (frequency demodulation) method, which can speed up data output, effectively reducing system complexity, power consumption and cost. [Prior Art] In a general communication system, there are many methods for demodulating a signal (demodulation) modulated by an angle (frequency or phase) into a dice ( Data) 'The common methods are the phase-locked loop & hase-locked loop, PLL, the quadrature detector, or the frequency counter used when the modulation speed is slow enough. The frequency-locked loop is a non-linear closed-loop system. The optimization of its system characteristics is often limited by the stability of the feedback φ loop. Stability, because there is at least one integral term in itself; the digital phase-locked loop needs a much higher frequency than the input signal. These will consume too much power and are not suitable for use by the battery. Provides a battery-powered system. A commonly used quadrature detector produces a frequency dependent phase shift based on a tuned phase-shift network. The quadrature detector is also a non-linear circuit, so that it is often designed to tradeoff between sensitivity and linearity, and the phase shift circuit required by the detector is combined with other components. Not cheap, and J275279 often suffers from the use of individual variations or dependence on temperature and process (pr〇cess). A method for demodulating a non-continuous timing frequency modulation signal is conventionally characterized in that an angular amplitude of an angle-modulated 彳& is first converted to an analog-to-digital converter by an analog-to-digital converter. After sampling, digitally delayed, after different mathematical signals (division), the demodulated data will be obtained. The disadvantage of this method is that it requires high-speed and high-power analog-to-digital converters, and division is required in mathematical operations. It is not suitable for wireless communication requiring low power consumption. In the system. I know how to use the digital frequency ό ten-number device (postal g*equenCy counter) to capture the data. The principle is to use the digital frequency counter (containing a reference oscillator and a counter (counter). )) to measure the time interval of two consecutive zero-crossing. This method requires a very high frequency clock (ci〇ck), which typically consumes a lot of power and is therefore less suitable for applications in the hands-held devices. Figure 1 is a conventional circuit assembly using a similar operating principle as described above. This method also requires a very high frequency clock. The common advantage is that the signal to be demodulated can be directly converted into digital data by using only zero-crossing information. Therefore, no additional analog digital converter is needed (anal〇gt( Miigital converter) ° There are a number of interpolation techniques that can be used to increase the resolution of time interval measurements, while still using clocks (even without the use of clocks). The diagram is conventionally utilized by the tapped delay line J275279

(tapped delay line) A method of composing an interpolator (interp〇iat〇r) to increase the time interval (measurement res〇luti〇n) without increasing too much power consumption, tapped delay The line is used to delay the edge of the signal to be tested, and the cycle time can be measured via the delayed edge and the next edge. This method is not too impractical for two main reasons: the first is when the frequency deviation is very small (such as +_5kHz ' at an intermediate frequency (intermediate freqUenCy) of 455kHz wireless In the communication system, it will be necessary to use a long delay line, such as (1) (10) . and the knife-connected H line 'about this only provides + _ 1 量化 quantified (10) fat also this (10) degree of adjustment k 'to present Semiconductor processes, such long delay lines, if they do not contain a trimming circuit, are not capable of achieving the linearity required for use. The second trick in this killing's operation logic is to assume that the width of the pulse at the delay pin's pulse is - Wei (mosquito), this A hypothesis is difficult to achieve, especially when (4) must also be controllable. It is also known that the same day is combined with the tapped delay line (tapped her (10)) and clock signal (clocksignal) ^^t^^ , ^^^t (frequencym〇dulatedMf complementary gold-oxygen (CMOS) buffer ϋ The delay line material (4) Qing, here the clock is the silky at at — 伽 伽 伽 伽 伽 伽 伽 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e The interpolation (inte_ate) signal goes through the delay, the time of the midpoint of the line. Since the interpolation operation is used in this architecture, the unit delay of the delay line (_dday) does not need to be calibrated.

Mitae) to - shape, but still - some miscellaneous makes this method is not very practical: first - because the total delay of the delay line (10) must be at least greater than two times #^^(clock cycle),; _ The measurable range of 〇(4) is not fixed. In order to _ each two J275279: Cr〇SSmg), each adjustment to the interpolator requires at least three additions and A division (divisi〇n), the hardware required for these instant mathematical operations and the oversized interpolator, make this approach less practical. The conventional method combines a frequency counter with a short (total 8 levels) interpolating delay line demodulation method, and an interpolator implementation (reaiizati〇n) Or the method of calibrating (4) plus (10) is not mentioned, and it is recommended to use a stable high frequency oscillator (9) young frequency oscmator), which is usually difficult to achieve. In order to get the proper resolution > (resolution) 'the input signal is first rectified to double its frequency offset gamma, and then frequency divided to a lower frequency. The cycle time is measured. Although it is easier to measure the time after the frequency multiplication (divided_by_M), it has lost a lot of information about the letter (because it is only detected once every time), especially when the signal is very clean (noisy). The performance of this method is worse than the system that measures two adjacent zerocrossing time intervals. _ A method of using a time interval to achieve a digitally demodulated digitally demodulated signal, which does not require the use of a high-frequency oscillator. The delay line is not too long, the feedback loop does not contain the input signal, so there is no limit to the stabmty, but this method requires an additional reference frequency (referencefreqUency), and it usually It is one level higher than the input signal. In addition, it also needs a delay-locked loop to fix the unit delay of the delay line within a certain range. These additional circuits It increases the complexity, power consumption, and cost of the system. These characteristics are very important for systems with 8-1275279/battery-p0wereci. In addition, this method is applicable when the frequency deviation is much smaller than the system's intermediate ^equency (about one-hundredth of one percent), otherwise the entire architecture needs to be modified considerably. . In view of the above problems, the inventors have utilized a delay sampling technique to perform a frequency or phase demodulation mechanism. SUMMARY OF THE INVENTION The main object of the present invention is to provide a demodulation method that utilizes a delayed sampling technique to speed up data rounding, effectively reduce system complexity, power consumption, and cost. In order to achieve the above object, the present invention provides a method for relieving the delay sampling technique, which takes a signal processed by a limiting amplifier as an input signal, and divides the input signal into two, one for direct input. The output of the delay sampler is passed through a delay line, so that the signal passing through the delay line produces a k-time output with different time delays, and the signal transmitted through the delay line is sampled by a delay sampler to generate a set. The sampled data, and the aforementioned data are converted into a set of binary codes by a temperature code_binary code converter, and then input into a data decision circuit to obtain the restored fundamental frequency data. In order to facilitate a more in-depth understanding of the present invention, an embodiment will be described in detail below: [Embodiment] 'Please refer to FIG. 3, which is a flowchart of a demodulation method using a delay sampling technique according to the present invention. The method comprises the following steps: a, taking a signal processed by a limiting amplifier as an input signal; b, dividing the input input into a one, one for direct input to the input of a delay sampler, and the other for Through a delay line, the signal passing through the delay line generates a signal output that is not delayed at 1275279; C. The money passing through the delay line is sampled by the delay sampler to generate a set of sample data; and d, Describe the shell material, pass the temperature code binary code conversion into a group binary code, and then input the processing of the read and find circuit, then the county's base frequency material can be processed. For implementation, please refer to Figures 3 and 4. This release includes - delay line 1 (which includes a coarse delay line, fine delay line 12), delay observation 3, temperature code, and binary code converter. The body determines the circuit 5. The signal processed by the limiter 2 is the input field of the present invention, which is first divided into two turns (four), and the other is directly input to the input of the delay sampler 3 without going through the delay line. After the signal of the delay line 1, after the t, , and m lines 12, a signal output of different delays will be generated. These signals can be used as the sampling clock of the k-sampling ☆ 3, and the input signal passes through the delay sampler 3 After sampling, the product = sample data will be produced. This will be converted to a temperature code by the binary code converter 4, and the unary code will be input to the data determination circuit 5 to obtain the restored fundamental frequency data. . Referring to Figure 5, which is a timing diagram showing the present invention, as shown, the total delay (10) aldday of the entire delay line 1, 2 is about a mid-frequency job diatef ^ period but not f is very high The accuracy of the operation is that if the base_band signal is 疋〇, the sampled result will contain more than one number, 〇", if the fundamental frequency signal is "丨,, then the result of ^ will contain A small number of T. The 6th bribe 7th shows the waveform of the input signal after the delay, sampling, coding and temperature code_binary code conversion. Figure 8 shows the method of determining the feedstock of the month, which uses the preambie method of the protocol (such as 〇1010) to find the rising and falling edges of the data by using the differentiation method-1275279 (rising and Falling edge) to find the threshold for determining 〇 and 1, which solves the problem of changing the decision threshold when the frequency of the received signal drifts (as shown in Figure 9). As shown in Fig. 8, the line a indicates the judgment level in the normal operation, and when the frequency of the reception signal is shifted, the line b in Fig. 9 changes the determination level. Thereby, in the present invention, the input signal is the only signal source required by the system, and no additional high reference clock is needed, and no delay-locked loop is needed to delay the delay line. The unit delay is fixed within a certain range, and there is no problem that the frequency deviation cannot be too large (compared to the system's intermediate frequency), and there is no closed loop (6) osed_1〇〇p). This can speed up the data output, and can greatly reduce the complexity of the system (C〇mplex), power consumption and cost. The above description is only for the purpose of illustrating the invention, and is not intended to limit the scope of the present invention. Substantive content. According to the above disclosure, the present invention can achieve the intended purpose of the invention, and provides a demodulation method for the I-type paste delayed sampling technique, which has the industrial value and is undoubted, and the Maiyi method proposes an invention patent application. [Simple diagram of the diagram] Figure 1 is a circuit diagram of a method for intercepting data using a digital frequency counter. Figure 2 is a conventional example of using an interpolator consisting of tapped delay lines to increase the time between

A circuit diagram of a method in which Pw measures resolution without adding too much power consumption. Figure 3 is a flow chart of an embodiment of the present invention. 1275279 - Figure 4 is a block diagram of an embodiment of the invention. The fifth diagram is a timing diagram of the delay line of the embodiment of the present invention. Figure 6 is a schematic diagram of sampling and encoding of an input waveform according to an embodiment of the present invention. FIG. 7 is a schematic diagram of temperature code_binary code conversion of an input waveform according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a data determination manner according to an embodiment of the present invention. Figure 9 is a schematic diagram of a method for solving the problem of when the frequency of the received signal is floating and the value of the received signal is changed. • [Main component symbol description] 1. Delay line 11, coarse delay line I2, fine delay line 2, limit amplifier 3, delay sampler 4, Humin Shimin--& bucket/dish code code converter 5 Data decision circuit

Group sampling data

The code 're-inputs a 4 base frequency data to determine the processing of the circuit. After the binary code converter is converted into a set of binary circuits, the restored 12 can be obtained.

Claims (1)

1275279 X. Patent application scope: 1. A demodulation method using delay sampling technology, comprising the following steps: a, taking a signal processed by a limiting amplifier as an input signal; b, the input signal Divided into two, one is directly input to the input of a delayed-sampler, and the other is transmitted through a delay line, so that the signal passing through the delay line produces a signal output with different time delay; After the signal of the line is sampled by a delay sampler, a set of sampled data can be generated; and d, the data is converted into a set of binary codes by a temperature code-binary code converter, and then input. After the data is determined by the processing of the circuit, the restored base-band data is obtained. 〇2. The demodulation method using the delayed sampling technique as described in claim 1, wherein the delay line includes A coarse delay line and a fine delay line, after passing through the signal of the coarse delay line, after passing through the fine delay line, a signal with different time delays can be generated. Output. 3. The demodulation method using the delayed sampling technique as described in claim 1 of the patent application, which utilizes different sized and seiectable delay lines to reduce unit delay and sampling elements ( The number of sampling devices in turn reduces the complexity and power consumption of the system. 13