TWI275171B - Current mode trimming apparatus - Google Patents

Current mode trimming apparatus Download PDF

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Publication number
TWI275171B
TWI275171B TW95104333A TW95104333A TWI275171B TW I275171 B TWI275171 B TW I275171B TW 95104333 A TW95104333 A TW 95104333A TW 95104333 A TW95104333 A TW 95104333A TW I275171 B TWI275171 B TW I275171B
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current
trimming
electrically connected
voltage
gate
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TW95104333A
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TW200731497A (en
Inventor
Chun-Te Lu
Chen-Ting Ko
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Faraday Tech Corp
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Abstract

A current mode trimming apparatus for trimming a desire current is provided. The trimming apparatus includes a first transistor, a first resistor, an operational amplifier, a first controlled current source and a second controlled current source. The first and second controlled current sources adjust the output current thereof respectively in accordance with the trimming data. The desire current through the first transistor is trimmed with the manner of increasing/decreasing current. Therefore, the invention cans linear increase/decrease the desire current by controlling the controlled current sources with the trimming data to achieve the goal of trimming.

Description

1275171 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種修整(trimmins)裝置,且特別 是有關於一種電流模式之修整裝置。 【先前技術】 積體電路(Integrated Circuit,1C)在製造時,會因為报多 製程上的原因,導致了電氣特性的漂移。而這種電氣特性 的漂移,在設計電路上,往往產生了許多的不確定性。所 以要如何降低電氣漂移的因素,除了在製造積體電路的程 序上,繼續求進步,還有一個亡羊補牢的做法,就是藉由 修整(trimming)的步驟,來調整漂移的電氣特性。 習知修整的技術,不外乎多晶矽熔絲(p 〇丨y fu s e)或是雷 射燒斷(Laser Cut)兩種方式。在Poly fuse的技術中,舍:1275171 IX. Description of the Invention: [Technical Field] The present invention relates to a trimins device, and more particularly to a current mode trimming device. [Prior Art] When the integrated circuit (1C) is manufactured, the electrical characteristics drift due to the multi-process. The drift of this electrical characteristic often creates a lot of uncertainty in designing the circuit. Therefore, in order to reduce the electrical drift factor, in addition to continuing to make progress in the process of manufacturing integrated circuits, there is another way to reinforce the drift, by adjusting the electrical characteristics of the drift by trimming steps. The technique of conventional trimming is nothing more than polycrystalline germanium fuse (p 〇丨y fu s e) or laser cut (Laser Cut). In the technology of Poly fuse,

1电堙VKiil·,而其負 N型電晶體120之;:及極 1275171 18657twf.doc/e1 electric 堙VKiil·, and its negative N-type transistor 120;: and pole 1275171 18657twf.doc/e

與閘極。電晶體120之源極電性連接至系統電壓VCCA。 電阻130、141、142、143串接於N型電晶體120之汲極 與接地電壓GND之間。電阻141、142、143分別具有4R Ω、2R Q、R Ω之電阻值。焊墊151〜153與熔絲161〜 • I63亦相互串接於N型電晶體120之汲極與接地電壓GND t 之間。其中,焊墊152與153更分別電性連接至電阻142 的兩端。經由焊墊151〜153,可以選擇將熔絲161〜163 參 中之任何一個熔絲燒毀,進而改變熔絲161〜163之連接狀 ' 態。透過決定熔絲161〜163之連接狀態,而決定電阻串 130、141、142、143之總電阻值Rt〇t。由於目標電流u = VREF/Rtot,因此可以藉由修整電阻串13〇、⑷、142、 之總電阻值Rt〇t,而修整流經電晶體120之目標電流It〇t。 圖1B是說明圖1A之習知修整電路的總電阻值與 目標電流1如之關係圖。請同時參照圖1A與圖1B,其中 圖1B之橫軸表示電阻串13〇、141、142、143之總電阻值With the gate. The source of the transistor 120 is electrically coupled to the system voltage VCCA. The resistors 130, 141, 142, and 143 are connected in series between the drain of the N-type transistor 120 and the ground voltage GND. The resistors 141, 142, and 143 have resistance values of 4R Ω, 2R Q , and R Ω , respectively. The pads 151 to 153 and the fuses 161 to I63 are also connected in series between the drain of the N-type transistor 120 and the ground voltage GND t. The pads 152 and 153 are electrically connected to both ends of the resistor 142, respectively. Via the pads 151 to 153, it is possible to selectively burn any one of the fuses 161 to 163, thereby changing the connection state of the fuses 161 to 163. The total resistance value Rt 〇 t of the resistor strings 130, 141, 142, and 143 is determined by determining the connection state of the fuses 161 to 163. Since the target current u = VREF/Rtot, the target current It〇t of the transistor 120 can be rectified by trimming the resistor strings 13〇, (4), 142, and the total resistance value Rt〇t. Fig. 1B is a diagram showing the relationship between the total resistance value of the conventional trimming circuit of Fig. 1A and the target current 1. Please refer to FIG. 1A and FIG. 1B simultaneously, wherein the horizontal axis of FIG. 1B indicates the total resistance value of the resistor strings 13〇, 141, 142, and 143.

Rt〇t,而縱軸則表示流經電晶體12〇之目標電流〗⑻。由圖 _ 1B中可以很清楚地看出,圖1A中習知修整電路的修整結 果並不是線性的(linear),因此將影響修整之精確性。再 者,由於進行修整前熔絲161〜163皆未被燒斷(此時電阻 串之總電阻值Rt〇t最小),因此習知修整電路必須由目標 電流Itm最大值開始修整。因此,當目標電流Itw比預期: 電流值還小時,此習知修整電路則因為無法將目標電流工_ 加大而無法適用。 〇t 1275171 18657twf.doc/e 【發明内容】 本發明的目的就是提供一種電流模式之修整 (trimming)裝置,以獲得線性(linear)的修整結果,並 可依需要而調升或調降修整結果。 基於上述及其他目的,本發明提出一種電流模式之修 整裝置’用以修整一目標電流。此修整裝置包括第一電晶 體、第一電阻、運算放大器、第一受控電流源以及第二受 ❿ 控電流源。第一電阻與第一電晶體串接於第一電壓與第二 電壓之間。其中,流經第一電晶體之電流即為該目標電流。 運异放大器之第一輸入端接收參考電壓,其第二輸入端電 性連接至第一電阻與第一電晶體之間的共同節點,而運算 放大器之輸出端則電性連接至第一電晶體之閘極。第一受 ,電流源電性連接於共同節點與第一電壓之間,用以提供 第一電流,並依據所接收之第一修整資料而調整第一電 流。第二受控電流源電性連接於共同節點與第二電壓之 間,用以提供第二電流,並依據所接收之第二修整資料而 •調整第二電流。 依照本發明的較佳實施例所述電流模式之修整裝置, 上^之弟义控電流源包括n個定電流源CS1 i以及η個開 關swii,其中csii表示第i個定電流源,swii表示第i 個開關,i為大於等於〇且小於n之整數,n為大於〇之整 數。定電流源CSli提供2Ί安培之電流,其中I為一實數^ 開關SWli與疋電流源csii串接於第一電壓與共同節點之 間。開關SWli依據第一修整資料而各自決定其啟閉狀態。 1275171 18657twf.doc/e 依照本發明的較佳實施例所述電流模式之修整裝置, 上述之第二受控電流源包括n個定電流源CS2i以及n個開 關SW2i,其中cS2i表示第i個定電流源,SW2i表示第i 個開關。定電流源CS2i提供2¾安培之電流。開關 與定電流源CS2i串接於第二電壓與共同節點之間,用以依 據第二修整資料而各自決定其啟閉狀態。 又 本發明因藉由增加或減少電流的方式來改變目標電流 • 值,亦即利用修整資料控制受控電流源,因此可以依照修 _ 整資料之控制而線性地增加或減少目標電流,進而達到修 整的目的。 為瓖本發明之上述和其他目的、特徵和優點能更明顯 易丨董,下文4寸舉較佳實施例,並配合所附圖式,作詳細說 明如下。 【實施方式】 圖2是依照本發明之實施例說明一種電流模式之修整 響 I置。請參照圖2,修整裝置200包括運算放大器210、第 一電晶體220、第一電阻230、第一受控電流源240以及第 二受控電流源250。電晶體220與電阻230串接於第一電 壓與第二電壓之間。於本實施例中,電晶體220例如是N 型電晶體’弟一電壓例如為系統電壓VCCA,而第二電壓 可以是接地電壓GND。運算放大器210之第一輸入端(在 此為正輸入端)接收參考電壓VREF,運算放大器210之 第二輸入端(在此為負輸入端)電性連接至電阻23〇與電 1275171 18657twf.doc/e 晶體220之間的共同節點CN。運算放大器21〇之輸出端 電性連接至電晶體220之閘極。假設電阻23〇之電阻值為 R230,而流經電阻230之電流為Iosc,則U二VREF / R230。Rt〇t, while the vertical axis represents the target current (8) flowing through the transistor 12〇. It can be clearly seen from Fig. 1B that the trimming result of the conventional trimming circuit of Fig. 1A is not linear and therefore will affect the accuracy of the trimming. Furthermore, since the fuses 161 to 163 are not blown before trimming (in this case, the total resistance value of the resistor string Rt 〇 t is the smallest), the conventional trimming circuit must be trimmed from the maximum value of the target current Itm. Therefore, when the target current Itw is smaller than expected: the current value is too small, this conventional trimming circuit cannot be applied because the target current _ cannot be increased. 〇t 1275171 18657twf.doc/e SUMMARY OF THE INVENTION It is an object of the present invention to provide a current mode trimming device for linear trimming results and to adjust or downgrade trimming results as needed . Based on the above and other objects, the present invention provides a current mode trimming device for trimming a target current. The trim device includes a first transistor, a first resistor, an operational amplifier, a first controlled current source, and a second controlled current source. The first resistor is coupled in series with the first transistor between the first voltage and the second voltage. The current flowing through the first transistor is the target current. The first input end of the differential amplifier receives the reference voltage, the second input end is electrically connected to the common node between the first resistor and the first transistor, and the output end of the operational amplifier is electrically connected to the first transistor The gate. The first receiving current source is electrically connected between the common node and the first voltage to provide a first current, and the first current is adjusted according to the received first trimming data. The second controlled current source is electrically connected between the common node and the second voltage to provide a second current, and adjusts the second current according to the received second trimming data. According to a preferred embodiment of the present invention, in the current mode trimming device, the control current source includes n constant current sources CS1 i and n switches swii, wherein csii represents the ith constant current source, swii represents The i-th switch, i is an integer greater than or equal to 〇 and less than n, and n is an integer greater than 〇. The constant current source CSli provides a current of 2 amps, where I is a real number. The switch SWli is connected in series with the 疋 current source csii between the first voltage and the common node. The switch SWli determines its opening and closing state according to the first trimming data. 1275171 18657twf.doc/e In accordance with a preferred embodiment of the present invention, a second mode controlled current source includes n constant current sources CS2i and n switches SW2i, wherein cS2i represents an ith predetermined Current source, SW2i represents the ith switch. The constant current source CS2i provides 23⁄4 amps of current. The switch and the constant current source CS2i are connected in series between the second voltage and the common node to determine the opening and closing state of each of the switches according to the second trimming data. In addition, the present invention changes the target current value by increasing or decreasing the current, that is, using the trimming data to control the controlled current source, so that the target current can be linearly increased or decreased according to the control of the repair data, thereby achieving The purpose of the trimming. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] FIG. 2 is a diagram showing a trimming operation of a current mode in accordance with an embodiment of the present invention. Referring to FIG. 2, the trimming apparatus 200 includes an operational amplifier 210, a first transistor 220, a first resistor 230, a first controlled current source 240, and a second controlled current source 250. The transistor 220 and the resistor 230 are connected in series between the first voltage and the second voltage. In the present embodiment, the transistor 220 is, for example, an N-type transistor. The voltage of the transistor 220 is, for example, the system voltage VCCA, and the second voltage may be the ground voltage GND. The first input terminal (here, the positive input terminal) of the operational amplifier 210 receives the reference voltage VREF, and the second input terminal (here, the negative input terminal) of the operational amplifier 210 is electrically connected to the resistor 23〇 and the electric 1251711 18657twf.doc /e A common node CN between crystals 220. The output of the operational amplifier 21 is electrically connected to the gate of the transistor 220. Assuming that the resistance of the resistor 23 is R230, and the current flowing through the resistor 230 is Iosc, then U is two VREF / R230.

受控電流源240電性連接於共同節點cn與系統電壓 VCCA之間,而受控電流源250則電性連接於共同節點CN v ,接地電壓GND之間。受控電流源24〇與25〇分別依據 •::修整資料S1與第二修整資料S2而提供第-電流1240 • 與第二電流1250。由於流經電晶體220之目標電流1如二1· ~ + 1250 _ 1240,因此可以藉由修整資料S1與S2控制受控電 流源240與250,進而決定電流l25〇與ΐ24〇之大小,因此達 到修整目標電流1_的目的。 例如’可以透過修整資料S1與82控制受控電流源24〇 與250而使電流125〇與l24〇皆為〇安培(或使125。= “, ,時目標電流ItQt = IQse而作為修整裝置2⑻之初始值。當 奴將目標電流1如修整為較小值時,則透過修整資料si控 _ 制艾控電流源24〇而使電流i24〇增加。反之,當欲將目標 電流It〇t修整為較大值時,則可透過修整資料82控制受控 電流源250而使電流125〇增加。 上述受控電流源240與250可以參照圖3實施之。圖 3疋依照本發明說明一種修整裝置之範例電路圖。圖3中 運异放大器210、第一電晶體220、第一電阻230、第一受 控電流源240以及第二受控電流源250可以與圖2相同, 故不再贅述。於本實施例中,受控電流源24〇包括n個定 電凃源CSl〇〜CSln_i與η個開關swi〇〜SWln」,而受控 9 1275171 18657twf.doc/e 電流源250包括n個定電流源cS2〇〜n個開關 SW2〇〜SW2n_;i 〇 定電流源CSli各自提供21安培之電流,其中i為大 於等於0且小於η之整數,n為大於〇之整數,而I為實 數。開關SWli與定電流源以^串接於系統電壓VCCA與 該共同節點CN之間。開關sW2i與定電流源CS2i串接於 接地電壓GND與該共同節點CN之間。開關SWli與開關 φ SW2i各自依據第一修整資料S1與第二修整資料S2而分別 - 決定其啟閉狀態。 圖4A是依照本發明說明一種修整裝置之另一範例電 路圖。圖4A中運算放大器210、第一電晶體220、第一電 阻230、定電流源cSl〇〜CSln]與CS2〇〜CS2W以及開關 SWl〇〜SWln]與SW20〜SW2W可以與圖3相同,故不再 贅述。於本實施例中,第一修整資料S1與第二修整資料 S2各自具有第η+ι位元;亦即,第一修整資料S1具有修 整資料位元S|n]、/S[n-1]、…、/S[l]、/S[0],而第二修整 資料S2具有修整資料位元S[n]、S[n_l]、…、S[l]、S[0]。 其中,/S[n-1]〜/S[0]是S[n_l]〜S[0]之反相資料。 圖4B是依照本發明說明一種溶絲單元410-0、 41(M、···、41〇-n之範例電路圖。請同時參照圖4A與圖 4B,於本實施例中,修整資料位元S[n]、/S[n-1]〜/S[0]與 s[n-l]〜S[0]是由熔絲單元 410-0、410-1、···、410-n 所提 供。熔絲單元41(H)〜410-n依據其内部熔絲之狀態而輸出 第一修整資料S1與第二修整資料S2 ◦以下,僅以熔絲單 1275171 18657twf.doc/e 元410-0為說明例,其餘熔絲單元可以參照 熔絲單元410-0實施之。 熔絲單元410-0包括焊墊411、第二電阻414、第三電 阻413、熔絲412、第一反閘415以及第二反閘416。電阻 414之第一端電性連接至系統電壓vcca。電阻413之第 一立而電性連接至電阻141之第二端,而電阻413之第二端 電性連接至焊墊411。溶絲412之第一端電性連接至電阻 413之弟一ί而,而、丨谷絲412之弟一端電性連接至接地電壓 GND。反閘415之輸入端電性連接至414電阻之第二端, 而反閘415之輸出端輸出修整資料位元/s[〇]。反閘41:之 輸入端電性連接至反閘415之輸出端,而反閘416之輪出 令而輸出修整資料位元S[〇]。 當熔絲412未被燒斷時,修整資料位元s[〇]為邏輯〇, 而修整資料位元/s[o]為邏輯1。當欲將熔絲412燒斷時, 可以經由焊墊411提供一燒斷電流,藉由大量的燒斷電流 通過熔絲412而改變熔絲之狀態。因此,當熔絲412形成 斷路時,由於拉升電阻414而使得修整資料位元s[〇]轉態 為邏輯1,而修整資料位元/S[0]則為邏輯〇。 " 以下,僅以開關SWl〇與SW2◦為說明例,其餘開關 SWll〜Swin-i可以參照開關SWl〇實施之,而開關SW2J 〜SW2lM可以參照開關SW2〇實施之。開關swi◦包括p 型電晶體PT〇以及或閘OR〇。電晶體ρτ〇之源極與汲極分 另J氣性連接至定電流源CSl〇與共同節點CN。或閘〇r〇之 第一輪入端與第二輸入端分別接收修整資料位元§[11]與 11 1275171^ /s[0],而或閘〇R0之輸出端電性連接至電晶體ρτ〇之閘 極。開關SW2G包括贝型電晶體NTg與及閘ANDg。電晶 體NT〇之源極與汲極分別電性連接至定電流源cS2()與共 同谛點CN。及閘AND0之第一輸入端與第二輸入端分別接 收修整資料位元S[n]與s[0],而及閘AND0之輸出端電性 連接至電晶體NT〇之閘極。 為月b更加清楚說明本發明,以下將以n=3為例說明本 發明之貫施方式。圖5A是依照本發明說明圖4A修整裝置 之4寸例。圖5B是依照本發明說明圖4B炼絲單元之一特 例。請同時參照圖5A與圖犯,其中當於焊墊P3〜P0施 3=,1^資料時’則目標電流^可被修整成對 Γ吉姑1L值。表1疋依照本發明實施例說明圖5A與圖5B <具值表。圖6則是依日77丄The controlled current source 240 is electrically connected between the common node cn and the system voltage VCCA, and the controlled current source 250 is electrically connected between the common node CNv and the ground voltage GND. The controlled current sources 24〇 and 25〇 provide the first current 1240 and the second current 1250 according to the ::: trim data S1 and the second trim data S2, respectively. Since the target current 1 flowing through the transistor 220 is such as two 1·~ + 1250 _ 1240, the controlled current sources 240 and 250 can be controlled by the trimming data S1 and S2, thereby determining the magnitudes of the currents l25〇 and ΐ24〇, thus The purpose of trimming the target current 1_ is achieved. For example, 'the controlled current sources 24〇 and 250 can be controlled by the trimming data S1 and 82, and the currents 125〇 and l24〇 are both amps (or 125. = ", , the target current ItQt = IQse as the finishing device 2 (8) The initial value. When the slave adjusts the target current 1 to a small value, the current i24〇 is increased by the trimming data control device. Otherwise, when the target current It〇t is to be trimmed For larger values, the controlled current source 250 can be controlled to increase the current 125 by the trimming data 82. The controlled current sources 240 and 250 can be implemented with reference to Figure 3. Figure 3 illustrates a trimming device in accordance with the present invention. The example circuit diagram of FIG. 3, the different operation amplifier 210, the first transistor 220, the first resistor 230, the first controlled current source 240, and the second controlled current source 250 can be the same as in FIG. 2, and therefore will not be described again. In this embodiment, the controlled current source 24A includes n fixed-coating sources CS1〇~CSln_i and n switches swi〇~SWln", while the controlled 9 1275171 18657twf.doc/e current source 250 includes n constant currents. Source cS2〇~n switches SW2〇~SW2n_;i 〇 constant current The source CSli each provides a current of 21 amps, where i is an integer greater than or equal to 0 and less than η, n is an integer greater than 〇, and I is a real number. The switch SWli and the constant current source are connected in series with the system voltage VCCA. Between the nodes CN, the switch sW2i and the constant current source CS2i are connected in series between the ground voltage GND and the common node CN. The switch SWli and the switch φ SW2i are respectively determined according to the first trimming data S1 and the second trimming data S2. Fig. 4A is a circuit diagram showing another example of a trimming apparatus according to the present invention. The operational amplifier 210, the first transistor 220, the first resistor 230, the constant current source cS1 〇 CS CSln, and CS2 图 in Fig. 4A The second trimming data S1 and the second trimming data S2 each have the η+ι bit in the present embodiment, and the second trimming data S1 and the second trimming data S2 are respectively omitted. That is, the first trimming data S1 has trimming data bits S|n], /S[n-1], . . . , /S[l], /S[0], and the second trimming data S2 has trimming data bits. S[n], S[n_l], ..., S[l], S[0], where /S[n-1]~/S[0] is the inverse of S[n_l]~S[0] Figure 4B is a diagram showing an exemplary circuit diagram of a fuse unit 410-0, 41 (M, ..., 41〇-n in accordance with the present invention. Referring also to Figures 4A and 4B, in the present embodiment, trimming The data bits S[n], /S[n-1]~/S[0] and s[nl]~S[0] are from the fuse units 410-0, 410-1, ..., 410- n provided. The fuse units 41(H) to 410-n output the first trimming data S1 and the second trimming data S2 依据 according to the state of the internal fuse, and only the fuse single 1275171 18657twf.doc/e yuan 410-0 is For example, the remaining fuse units can be implemented with reference to the fuse unit 410-0. The fuse unit 410-0 includes a pad 411, a second resistor 414, a third resistor 413, a fuse 412, a first reverse gate 415, and a second reverse gate 416. The first end of the resistor 414 is electrically coupled to the system voltage vcca. The first end of the resistor 413 is electrically connected to the second end of the resistor 141, and the second end of the resistor 413 is electrically connected to the pad 411. The first end of the wire 412 is electrically connected to the resistor 413, and the other end of the wire 412 is electrically connected to the ground voltage GND. The input of the reverse gate 415 is electrically connected to the second end of the 414 resistor, and the output of the reverse gate 415 outputs the trim data bit /s[〇]. The input terminal of the reverse gate 41 is electrically connected to the output terminal of the reverse gate 415, and the wheel of the reverse gate 416 is outputted to output the trimming data bit S [〇]. When the fuse 412 is not blown, the trim data bit s[〇] is a logical volume, and the trim data bit /s[o] is a logic one. When the fuse 412 is to be blown, a blow current can be supplied via the pad 411, and the state of the fuse is changed by the fuse 412 by a large amount of blow current. Therefore, when the fuse 412 forms an open circuit, the trimming data bit s[〇] transitions to a logic 1 due to the pull-up resistor 414, and the trim data bit /S[0] is a logical chirp. " Hereinafter, only the switches SW1〇 and SW2◦ are used as an illustrative example, and the remaining switches SW11 to Swin-i can be implemented with reference to the switch SW1〇, and the switches SW2J to SW2lM can be implemented with reference to the switch SW2〇. The switch swi◦ includes a p-type transistor PT〇 and or a gate OR〇. The source and the drain of the transistor ρτ〇 are connected to the constant current source CS1〇 and the common node CN. Or the first round input end and the second input end of the gate r〇 receive the trimming data bits §[11] and 11 1275171^ /s[0], respectively, or the output end of the gate R0 is electrically connected to the transistor The gate of ρτ〇. The switch SW2G includes a bay type transistor NTg and a gate ANDg. The source and the drain of the transistor NT are electrically connected to the constant current source cS2() and the common node CN, respectively. The first input end and the second input end of the AND gate AND0 respectively receive the trimming data bits S[n] and s[0], and the output end of the AND gate AND0 is electrically connected to the gate of the transistor NT〇. The present invention will be more clearly explained for the month b. Hereinafter, the mode of the present invention will be described by taking n = 3 as an example. Figure 5A is a 4 inch illustration of the dressing device of Figure 4A in accordance with the present invention. Figure 5B is a diagram showing one example of the wire making unit of Figure 4B in accordance with the present invention. Please refer to FIG. 5A and FIG. 5 at the same time, wherein when the pad P3~P0 is applied to 3=, 1^ data, the target current ^ can be trimmed to the value of Γ吉姑1L. Table 1 shows a numerical table of Figures 5A and 5B in accordance with an embodiment of the present invention. Figure 6 is 77 依

a ▽、本發明實施例說明圖5A與圖5B 加於焊墊Ρ3〜Ρ〇 料與目標電流ItQt之間的關係 圖。士同a ^ k整資料與目4示電流It〇t之關係 圆。由圖6可以看出,修敕〜 是線性的。 1育a ▽, the embodiment of the present invention illustrates the relationship between FIG. 5A and FIG. 5B applied between the pad 3 Ρ〇 3 Ρ〇 and the target current ItQt. The relationship between the same a ^ k whole data and the head 4 shows the current It 〇 t. As can be seen from Figure 6, the repair ~ is linear. 1 education

圖5B之真值表 ρτ〇 nt2 NT! NTo Itot off off off ,off I〇sc on off off off I〇SC"I off off off off I -21 AOSC ϋ on off off off T -31 i〇SC 〇ff_ off off off I -41 lose H ^on off off off I -51 Aosc 12 1275171 18657twf.doc/eTruth table ρτ〇nt2 of FIG. 5B NT! NTo Itot off off off, off I〇sc on off off off I〇SC"I off off off off I -21 AOSC ϋ on off off off T -31 i〇SC 〇 Ff_ off off off I -41 lose H ^on off off off I -51 Aosc 12 1275171 18657twf.doc/e

4上所述,藉由蚊賴^ 接經由焊墊設定修整:諸,而控制第—奸電盘 二受控電流源提供第一電流與第二電流,進::二弟 標電流itQt的目的。本發明因目 改變目標電流值,亦即利二 =可以依照修整資料之控制而線性地增加或減少目原 >瓜’進而達到修整的目的。 ^包 雖然本發明已以較佳實施例揭露如上,㈣並 限定本發明,任何熟習此㈣者,在獨發 和範圍内’當可作些許之更動简,因此本發日】:= 範圍當視後附之申請專利範圍所界定者為準。 呆禮 f圖式簡單說明】 弟1A圖係、繪示習知的修整電路的方塊圖。 13 1275171 18657twf.doc/e 圖IB是說明圖1A之習知修整電路的總電阻值11_與 目標電流It()t之關係圖。 圖2是依照本發明之實施例說明一種電流模式之修整 裝置。 圖3是依照本發明說明一種修整裝置之範例電路圖。 圖4Α是依照本發明說明一種修整裝置之另一範例電 路圖。 - 圖4 Β是依照本發明說明一種熔絲單元之範例電路圖。 * 圖5Α是依照本發明說明圖4Α修整裝置之一特例。 圖5Β是依照本發明說明圖4Β熔絲單元之一特例。 圖6則是依照本發明實施例說明圖5Α與圖5Β中施加 於焊墊Ρ3〜Ρ0之修整資料與目標電流Itot之關係圖。 【主要元件符號說明】 110、210 :運算放大器 120、NT〇〜NT" : N型電晶體 • 130、141、142、143 ··電阻 151 〜153、4H、P0〜P3 :焊墊 161 〜163、412 :熔絲 200 :修整裝置 220 :第一電晶體 230 :第一電阻 240 :第一受控電流源 250 :第二受控電流源 14 1275171 18657twf.doc/e 410-0〜410-n :熔絲單元 414 :第二電阻 413 :第三電阻 415 :第一反閘 416 :第二反閘 AND〇〜ANDn]:及閘 CSl〇〜CSln4、CS2〇〜CS2n]:定電流源 OR〇〜ORn]:或閘 PT〇〜PTw : P型電晶體 swi〇〜swinq、sw2〇〜sway :開關4, according to the mosquito replies through the pad set trimming: and control the first - control electric disk two controlled current source to provide the first current and the second current, into:: two brother standard current itQt purpose . According to the present invention, the target current value is changed, that is, the second value = can be linearly increased or decreased according to the control of the trimming data to achieve the purpose of trimming. Although the present invention has been disclosed above in the preferred embodiments, (4) and the present invention is defined, any person who is familiar with this (four), in the sole and the scope, can be made a little more simple, so this date]: = range when This is subject to the definition of the scope of the patent application. A simple description of the f-style diagram of the brother 1A, showing the block diagram of the conventional trimming circuit. 13 1275171 18657twf.doc/e Figure IB is a diagram illustrating the relationship between the total resistance value 11_ of the conventional trimming circuit of Figure 1A and the target current It()t. 2 is a perspective view of a current mode trimming apparatus in accordance with an embodiment of the present invention. 3 is a circuit diagram showing an example of a finishing device in accordance with the present invention. Figure 4 is a circuit diagram showing another example of a finishing device in accordance with the present invention. - Figure 4 is an exemplary circuit diagram illustrating a fuse unit in accordance with the present invention. * Fig. 5A is a specific example of the Fig. 4 dressing device in accordance with the present invention. Figure 5A is a diagram showing a specific example of the fuse unit of Figure 4 in accordance with the present invention. Fig. 6 is a view showing the relationship between the trimming data applied to the pads Ρ3 to Ρ0 and the target current Itot in Figs. 5A and 5B according to an embodiment of the present invention. [Description of main component symbols] 110, 210: Operational amplifier 120, NT〇~NT" : N-type transistor • 130, 141, 142, 143 · Resistor 151 ~ 153, 4H, P0 to P3: pads 161 to 163 412: fuse 200: trimming device 220: first transistor 230: first resistor 240: first controlled current source 250: second controlled current source 14 1275171 18657twf.doc/e 410-0~410-n : fuse unit 414: second resistor 413: third resistor 415: first reverse gate 416: second reverse gate AND〇~ANDn]: and gate CSl〇~CSln4, CS2〇~CS2n]: constant current source OR〇 ~ORn]: or gate PT〇~PTw: P-type transistor swi〇~swinq, sw2〇~sway: switch

1515

Claims (1)

1275171 18657twf.doc/e 十、申請專利範圍: 1. 一種電流模式之修整裝置,用以修整(trimming) — 目標電流,該修整裝置包括: 一弟一電晶體’其中流經該第一電晶體之電流即為該 目標電流; 一第一電阻,其與該第一電晶體串接於一第一電壓與 一第二電壓之間; 一運算放大器,其第一輸入端接收一參考電壓,其第 二輸入端電性連接至該第一電阻與該第一電晶體之間的一 共同節點,而該運算放大器之輸出端則電性連接至該第一 電晶體之閘極; 一第一受控電流源,電性連接於該共同節點與該第一 電壓之間,用以提供一第一電流,並依據所接收之一第一 修整資料而調整該第一電流;以及 一第二受控電流源,電性連接於該共同節點與該第二 電壓之間,用以提供一第二電流,並依據所接收之一第二 修整資料而調整該第二電流。 2. 如申請專利範圍第1項所述電流模式之修整裝置, 其中該第一電壓為系統電壓,而該第二電壓為接地電壓。 3. 如申請專利範圍第1項所述電流模式之修整裝置, 其中該第一電晶體為N型電晶體,其汲極與源極分別電性 連接至該第一電壓與該共同節點。 16 1275171 18657twf.doc/e 4. 如申請專利範圍第1項所述電流模式之修整裝置, 更包括至少一熔絲單元,其中該熔絲單元依據其内部熔絲 之狀態而輸出該第一修整資料與該第二修整資料。 5. 如申請專利範圍第4項所述電流模式之修整裝置, 其中該熔絲單元包括: 一第二電阻,其第一端電性連接至該第一電壓; 一第三電阻,其第一端電性連接至該第二電阻之第二 端; 一熔絲,其第一端電性連接至該第三電阻之第二端, 而該熔絲之第二端電性連接至該第二電壓; 一第一反閘,其輸入端電性連接至該第三電阻之第二 端,而該第一反閘之輸出端輸出該第一修整資料與該第二 修整資料其中一位元;以及 一第二反閘,其輸入端電性連接至該第一反閘之輸出 端,而該第二反閘之輸出端輸出該第一修整資料與該第二 修整資料其中另一位元。 6. 如申請專利範圍第5項所述電流模式之修整裝置, 其中該熔絲單元更包括一焊墊,該焊墊電性連接至該熔絲 之第一端。 7. 如申請專利範圍第1項所述電流模式之修整裝置, 其中該第一受控電流源包括: 17 1275171 18657twf.doc/e n個定電流源CSli,用以各自提供安培之電流,其 中CSli表示第i個定電流源,i為大於等於0且小於η之 整數,η為大於0之整數,而I為一實數;以及 η個開關SWli,該開關SWli與該定電流源CSli串接 於該第一電壓與該共同節點之間,用以依據該第一修整資 料而各自決定其啟閉狀態,其中SWli表示第i個開關。 8. 如申請專利範圍第7項所述電流模式之修整裝置, 其中該第一修整資料具有第0位元至第η位元,而該開關 SWli包括: 一 P型電晶體PTi,其源極與汲極分別電性連接至該 定電流源CSli與該共同節點,其中PTi表示第i個P型電 晶體;以及 一或閘ORi,其第一輸入端與第二輸入端分別接收該 第一修整資料之第η位元與第i位元,而該或閘0民之輸 出端電性連接至該P型電晶體PTi之閘極,其中ORi表示 第i個或閘。 9. 如申請專利範圍第1項所述電流模式之修整裝置, 其中該第二受控電流源包括: η個定電流源CS2i,用以各自提供2^安培之電流,其 中CS2i表示第i個定電流源,i為大於等於〇且小於η之 整數,η為大於0之整數,而I為一實數;以及 18 1275171 18657twf.doc/e n個開關SW2i,該開關SW2i與該定電流源CS2i串接 於該第二電壓與該共同節點之間,用以依據第二修整資料 而各自決定其啟閉狀態,其中SW2i表示第i個開關。 10.如申請專利範圍第9項所述電流模式之修整裝 置,其中該第二修整資料具有第0位元至第η位元,而該 開關SW2i包括: 一 N型電晶體NTi,其源極與汲極分別電性連接至該 定電流源CS2i與該共同節點,其中NT!表示第i個N型電 晶體,以及 一及閘ANDi,其第一輸入端與第二輸入端分別接收 該第二修整資料之第η位元與第i位元,而該及閘AND; 之輸出端電性連接至該N型電晶體NTi之閘極,其中AND i 表示第i個及閘。 191275171 18657twf.doc/e X. Patent application scope: 1. A current mode trimming device for trimming - target current, the trimming device comprising: a brother-one transistor through which the first transistor flows The current is the target current; a first resistor connected in series with the first transistor between a first voltage and a second voltage; an operational amplifier having a first input receiving a reference voltage The second input end is electrically connected to a common node between the first resistor and the first transistor, and the output end of the operational amplifier is electrically connected to the gate of the first transistor; a current control source electrically connected between the common node and the first voltage for providing a first current, and adjusting the first current according to one of the received first trimming data; and a second controlled The current source is electrically connected between the common node and the second voltage to provide a second current, and the second current is adjusted according to the received one of the second trimming data. 2. The current mode trimming device of claim 1, wherein the first voltage is a system voltage and the second voltage is a ground voltage. 3. The current mode trimming device of claim 1, wherein the first transistor is an N-type transistor, and the drain and the source are electrically connected to the first voltage and the common node, respectively. 16 1275171 18657twf.doc/e 4. The current mode trimming device according to claim 1, further comprising at least one fuse unit, wherein the fuse unit outputs the first trim according to the state of the internal fuse Information and the second trimming information. 5. The current mode trimming device of claim 4, wherein the fuse unit comprises: a second resistor, the first end of which is electrically connected to the first voltage; and a third resistor, the first of which The second end of the fuse is electrically connected to the second end of the third resistor, and the second end of the fuse is electrically connected to the second end a first reverse gate, the input end is electrically connected to the second end of the third resistor, and the output end of the first reverse gate outputs the first trimming data and one of the second trimming data; And a second reverse gate, wherein the input end is electrically connected to the output end of the first reverse gate, and the output end of the second reverse gate outputs the first trimming material and the other trimming material. 6. The current mode trimming device of claim 5, wherein the fuse unit further comprises a pad electrically connected to the first end of the fuse. 7. The current mode trimming device according to claim 1, wherein the first controlled current source comprises: 17 1275171 18657 twf.doc/en a constant current source CSli for respectively providing ampere current, wherein CSli Representing the i-th constant current source, i is an integer greater than or equal to 0 and less than η, η is an integer greater than 0, and I is a real number; and n switches SWli, the switch SWli is connected in series with the constant current source CSli The first voltage and the common node are used to determine the opening and closing state of the first voltage according to the first trimming data, wherein SWli represents the ith switch. 8. The current mode trimming device according to claim 7, wherein the first trimming data has a 0th bit to an nth bit, and the switch SWli comprises: a P-type transistor PTi, the source thereof Electrically connected to the constant current source CSli and the common node, wherein PTi represents an i-th P-type transistor; and a OR gate ORi, the first input end and the second input end respectively receive the first The nth bit and the i th bit of the data are trimmed, and the output of the OR gate is electrically connected to the gate of the P-type transistor PTi, wherein ORi represents the ith or gate. 9. The current mode trimming device according to claim 1, wherein the second controlled current source comprises: n fixed current sources CS2i for respectively supplying 2 amps of current, wherein CS2i represents the ith a constant current source, i is an integer greater than or equal to 〇 and less than η, η is an integer greater than 0, and I is a real number; and 18 1275171 18657 twf.doc/en switches SW2i, the switch SW2i and the constant current source CS2i Connected between the second voltage and the common node, for determining the open/close state according to the second trimming data, wherein SW2i represents the ith switch. 10. The current mode trimming device of claim 9, wherein the second trimming data has a 0th bit to an nth bit, and the switch SW2i comprises: an N-type transistor NTi, the source thereof The first input terminal and the second input terminal respectively receive the first Second, trimming the nth bit and the i th bit, and the output of the AND gate is electrically connected to the gate of the N-type transistor NTi, wherein AND i represents the i-th gate. 19
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