1274氣 doe/r 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製作方法，且特 別是有關於一種封裝基板、晶片封裝結構及上述兩者的赞 作方法。 " 【先前技術】 覆晶技術由於具有縮小晶片封裝面積及縮短訊號傳 輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如 晶片尺寸構裝(Chip Scale Package, CSP)、晶片直接貼附封 裝（Direct Chip Attached，DCA)以及多晶片模組封裝 (Multi-Chip Module，MCM)等型態的封裝模組，均可以利^ 覆晶技術而達到封裝的目的。 習知的覆晶封裝製程係先將多個凸塊(bumps)製作在 曰曰片的接點上，之後再以網板印刷(stencil printing)的方式 形成一鈐料到封裝基板的接點上，接著便翻覆晶片，使晶 片上的凸塊對準鮮料並使凸塊附著在銲料上。之後，再進 行迴鈈的製耘，使得銲料可以與凸塊結合而將晶片固定在 封裝基板上，並使晶片與封裝基板電性連接。此外，封裝 基板的另-側表面可形成有鮮球，以使晶片透過封裝基板 電性連接至銲球，並藉由銲球連接至外部電路， 路板。 〃在習知的覆晶封裝製程中，由於晶片與基板之熱膨服 係數的差異甚大，因此晶片外圍的凸塊無法與封裝基板上 對應的接點形成良好的接合，使得凸塊可能自封裝基板上 doc/r 1274棚喊 ’若封裝基板之組成與外部電路板有太大的差 封u板與外部電路板之間亦可能因為熱膨脹 係數=同而導致銲球脫落的問題。 &電路之積集度的增加，由於晶片、封裝基板 只卜^包路板之間的熱膨脹係數不匹配(mismatch)，其所 產^力(thermal切職)與輕曲(warPage)的現象也曰 漸^:結果將導致晶片與封裝基板之間以及封裝基板 與外口 P電路板之間的可靠度㈣鑛 賴性測試的失敗。 【發明内容】 f監於此，本發_目龍是在提供-種可有效降低 接合^熱膨脹差異的封裝基板，用以提高晶片封裝製程 之良率。 =發_再-目的是提供—種上叙封裝基板 作方法。 的又-目的是提供一種晶片封裝結構，其晶 片、封衣基板與外部電路之間具有較小的 具有較高的可靠度。 〃而 本發明的另一目的是提供一種具有較 射装製程，其可形成上述之晶片封裝結構。日日 基於上述或其他目的，本發明提出 ㈣-石夕基材、-絕緣層、-内連線層、;= 以及，多個銲球墊。其中，石夕基材具有相對應之—第一表面 與一第二表面，且矽基材内具有貫穿第一表面與第二表"面 6 12743 舄 ftvf.doc/r 的多個貫孔。絕緣層係全面性地覆蓋石夕基材之第一表面、 第二表面與貫孔内壁。内連線層係配置於第_表面上方的 絕緣層上，且貫孔暴露出部分之内連線層。導電塊係配置 於貫孔内，而銲球墊係配置於内連線層上，並 層分別電性連接至導電塊。 / 在本發明之較佳實施例中，上述之内連線層例如是依 序由多個圖案化線路層與多個介電層交互疊合而成。舉例 而否’圖案化線路層例如是鈦/銅(Ti/Cu)合金層或鈦/銅/鈦 Cn/Cu/Ti)合金層。此外，介電層之材質可為有機…巧⑽^) 材料，例如聚醯亞胺(p〇lyimide)。 在本發明之較佳實施例中，上述之絕緣層的材質例如 包括二氧化矽(Si02)。 在本發明之較佳實施例中，上述之銲球墊例如包括鎳 /金(Ni/Au)合金層或鎳鈒/金(NiV/Au)合金層。 在本發明之較佳實施例中，上述之各導電塊例如包括 一銅/鎳(Cu/Ni)合金層以及一銲料(solder)塊，其中銅/鎳合 金層係配置於貫孔内，而銲料塊係配置於銅/鎳合金層 並凸出於貫孔外。 在本發明之較佳實施例中，上述之封裝基板例如更包 括一金屬層，其係位於貫孔内，而配置於導電塊與矽基材 之間，以及導電塊與内連線層之間。此金屬層例如是鈦/ 銅合金層。 本發明更提出一種晶片封裝結構，其主要包括上述之 封裝基板以及一晶片，其中晶片係配置於矽基材之第二表 面上==2上，錢料鼓導魏。 p ^ 之一較佳實施例所述，上述之晶片封裝壯 :=多個銲球，其係分別配置於銲球:: 列步驟封裝基板的製作方法，主要包括下 之一第-表面盘第、I基材，其中此秒基材具有相對應 ί:ί=層。接著，在第-絕緣層上形成-内連線 ;成多個貫ί=ΐ多個鲜球塾。然後，在術内 後，猎由貝孔暴露出部分之第一絕緣層。之 層。接1貫孔㈣上形成—第二絕緣 之肉、^移除所暴狀第—絕緣層，以暴露出部份 塊透7^1。然後，在貫孔⑽成多個導電塊，其中導電 鬼透過内連線層分別電性連接至銲球墊。 赤肉，、、本發明之—較佳實施例所述，在第—絕緣層上形 ^内，線層的方法例如是在第—絕緣層上依序形成交互疊 勺夕個圖案化線路層與多個介電層。上述形成每一圖案 路層的方法例如是先形成一導電材料層，再圖案化此 A材料層。其中’形成導電材料層的方法例如是藏鍍， 血圖案化導電材料層的方法例如是對導電材料層進行微影 ^蝕刻製程。此外，上述形成每一介電層的方法例如是先 =成一介電材料層，再圖案化此介電材料層。其中，形成 二電材料層的方法例如是印刷，而圖案化介電材料層的方 〆例如是對介電材料層進行微影製程。 依照本發明之一較佳實施例所述，在内連線層上形成 12 銲球墊的方法例如是先形成一導電材料層，再圖案化此導 電材料層。其中，形成導電材料層的方法例如是賤錢，而 圖案化導電材料層的方法例如是對導電材料層 蝕刻製程。 心^、 依照本發明之一較佳實施例所述，在矽基材内形成貫 孔的方法例如是先形成一圖案化光阻層於矽基材的第二^ =接著關案化光阻層為罩幕，_基材進行感應^ 電水(Inductively Coupled Plasma，ICP)顏刻，以形成貫孔。 之後，再移除圖案化光阻層。 、° 依照本發明之一較佳實施例所述，在矽基材之第二表 面與貝孔内壁形成第二絕緣層的方法包括進行電漿择匕 PECvT^1^ EnhanCCd ChCmiCal VaP〇r DeP〇^^ …依照本發明之一較佳實施例所述，移除貫孔所暴露之 緣層的綠例如是絲成—顧化光崎於於石夕基 出亡方的第二絕緣層上，且圖案化光阻層暴露 :内的弟-絕緣層。接著，關案化光阻層為罩幕， 對第、心緣層進行感應輕合電漿(Inductively Coupled1274 gas doe/r IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a package substrate, a chip package structure, and a method for praising the above . " [Prior Art] Flip chip technology has been widely used in chip packaging fields due to its advantages of shrinking chip package area and shortening signal transmission path, such as chip scale package (CSP), wafer direct attach package (Direct Chip Attached, DCA) and Multi-Chip Module (MCM) and other types of package modules can be used to achieve the purpose of packaging. The conventional flip chip packaging process firstly forms a plurality of bumps on the contacts of the cymbals, and then forms a stencil printing onto the contacts of the package substrate by stencil printing. The wafer is then flipped over to align the bumps on the wafer with the bumps and attach the bumps to the solder. Thereafter, the rewinding process is performed so that the solder can be bonded to the bump to fix the wafer on the package substrate and electrically connect the wafer to the package substrate. In addition, the other side surface of the package substrate may be formed with fresh balls to electrically connect the wafer to the solder ball through the package substrate and to the external circuit and the solder ball by solder balls.习 In the conventional flip chip packaging process, since the thermal expansion coefficient of the wafer and the substrate are very different, the bumps on the periphery of the wafer cannot form a good bond with the corresponding contacts on the package substrate, so that the bumps may be self-packaged. The doc/r 1274 shed on the substrate screams that if the composition of the package substrate is too different from the external circuit board, the difference between the u-plate and the external circuit board may also cause the solder ball to fall off due to the thermal expansion coefficient. The increase in the integration of the circuit, due to the mismatch of the thermal expansion coefficient between the wafer and the package substrate, and the phenomenon of the thermal force (warpage) and the warpage (warpage) Also, the result will result in reliability between the wafer and the package substrate and between the package substrate and the external P board (4) failure of the mineral dependence test. SUMMARY OF THE INVENTION In view of this, the present invention provides a package substrate which can effectively reduce the difference in bonding and thermal expansion to improve the yield of the wafer packaging process. = _ _ re-- the purpose is to provide a description of the package substrate as a method. A further object is to provide a chip package structure with a relatively high reliability between the wafer, the package substrate and the external circuit. Still another object of the present invention is to provide a wafer mounting structure which can form the above described wafer package structure. On the basis of the above or other objects, the present invention proposes (4) - Shi Xi substrate, - insulating layer, - interconnect layer, ; = and a plurality of solder ball pads. Wherein, the Shixi substrate has a corresponding first surface and a second surface, and the tantalum substrate has a plurality of through holes penetrating the first surface and the second surface "surface 6 12743 舄ftvf.doc/r . The insulating layer comprehensively covers the first surface, the second surface and the inner wall of the through hole of the stone substrate. The interconnect layer is disposed on the insulating layer above the first surface, and the through hole exposes a portion of the inner wiring layer. The conductive block is disposed in the through hole, and the solder ball pad is disposed on the interconnect layer, and the layers are electrically connected to the conductive block. In a preferred embodiment of the present invention, the interconnect layer is formed by, for example, a plurality of patterned circuit layers and a plurality of dielectric layers alternately stacked. By way of example, the patterned circuit layer is, for example, a titanium/copper (Ti/Cu) alloy layer or a titanium/copper/titanium Cn/Cu/Ti alloy layer. In addition, the material of the dielectric layer may be an organic (10)^) material such as p〇lyimide. In a preferred embodiment of the invention, the material of the insulating layer includes, for example, cerium oxide (SiO 2 ). In a preferred embodiment of the invention, the solder ball pad described above comprises, for example, a nickel/gold (Ni/Au) alloy layer or a nickel niobium/gold (NiV/Au) alloy layer. In a preferred embodiment of the present invention, each of the conductive blocks includes, for example, a copper/nickel (Cu/Ni) alloy layer and a solder block, wherein the copper/nickel alloy layer is disposed in the through hole. The solder bumps are disposed on the copper/nickel alloy layer and protrude out of the through holes. In a preferred embodiment of the present invention, the package substrate further includes a metal layer disposed in the through hole, disposed between the conductive block and the germanium substrate, and between the conductive block and the interconnect layer. . This metal layer is, for example, a titanium/copper alloy layer. The invention further provides a chip package structure, which mainly comprises the above package substrate and a wafer, wherein the wafer is disposed on the second surface of the base material ==2, and the material is guided by Wei. In a preferred embodiment, the above-mentioned chip package is strong: = a plurality of solder balls, which are respectively disposed on the solder balls:: a method of manufacturing the package substrate, which mainly includes a lower first-surface disk , I substrate, wherein the second substrate has a corresponding ί: ί = layer. Next, an -internal line is formed on the first insulating layer; and a plurality of fresh balls are formed. Then, after the surgery, the hunting exposes a portion of the first insulating layer from the beacon. The layer. A second insulating piece of meat is formed on the through hole (4), and the first insulating layer is removed to expose a portion of the block to penetrate 7^1. Then, a plurality of conductive blocks are formed in the through holes (10), wherein the conductive ghosts are electrically connected to the solder ball pads through the interconnect layers, respectively. In the case of the red meat, the preferred embodiment of the present invention, the method of forming the wire layer on the first insulating layer is, for example, sequentially forming an alternating pattern of patterned circuit layers on the first insulating layer. With multiple dielectric layers. The above method of forming each pattern layer is, for example, forming a layer of a conductive material and then patterning the layer of material A. The method of forming the conductive material layer is, for example, a plating method, and the method of blood patterning the conductive material layer is, for example, a photolithography process for the conductive material layer. In addition, the above method of forming each dielectric layer is, for example, first forming a layer of dielectric material and then patterning the layer of dielectric material. Among them, a method of forming a layer of a second material is, for example, printing, and a method of patterning a layer of a dielectric material is, for example, a lithography process on a layer of a dielectric material. In accordance with a preferred embodiment of the present invention, a method of forming a solder ball pad on an interconnect layer is, for example, first forming a layer of conductive material and then patterning the layer of conductive material. Among them, the method of forming the conductive material layer is, for example, money saving, and the method of patterning the conductive material layer is, for example, an etching process for the conductive material layer. According to a preferred embodiment of the present invention, a method of forming a through hole in a germanium substrate is, for example, first forming a patterned photoresist layer on the second substrate of the germanium substrate. The layer is a mask, and the substrate is inductively inductively charged (ICP) to form a through hole. Thereafter, the patterned photoresist layer is removed. According to a preferred embodiment of the present invention, the method for forming the second insulating layer on the second surface of the crucible substrate and the inner wall of the beak hole comprises performing plasma selection PECvT^1^ EnhanCCd ChCmiCal VaP〇r DeP〇 ^^ In accordance with a preferred embodiment of the present invention, the green color of the edge layer exposed by the through hole is removed, for example, by the wire-forming of the gas on the second insulating layer of the death of Shi Xiji, and The patterned photoresist layer is exposed: the inner-insulation layer. Next, the closed photoresist layer is a mask, and the first and the core layer are inductively coupled to the plasma (Inductively Coupled)
PlaSmMCP)钱刻，以暴露出貫孔内的内連線層。之後，再 移除圖案化光阻層。 心俊冉 依照本發明之—較佳實施例所述，在貫孔内形成 ，的方法包括例如是切基材上形成―圖案化光阻盆 ==光阻!暴露出貫孔。接著，以圖案化光阻層為 貝孑内甩鍍形成導電塊。之後，再移除圖案化光 doc/r 阻層。 依照本發明之一較佳實施例所述，在貫孔内形成導電 塊之則，更包括在矽基材上以及貫孔内全面形成一金屬材 料層，且在貫孔内形成導電塊之後，更包括移除位於貫孔 外的金屬材料層。 依照本發明之一較佳實施例所述，在貫孔内形成導電 塊之後，更包括迴銲這些導電塊。 本發明另提出一種晶片封裝製程，其係在完成上述之 封裝基板製作之後，再配置一晶片於石夕基材之第二表面上 方的第二絕緣層上，並電性連接晶片至導電塊，以形成一 晶片封裝結構。 在本發明之較佳實施例中，上述之晶片封裝製程在形 成銲球塾之後，例如更包括在銲球墊上形成多個鲜球。 /基於上述，本發明之封裝基板主要是由具有不同熱膨 脹係數之⑦基材與㈣線層所構成，其切基材—侧之導 電塊可用以與“連接’㈣連線層—側之銲球塾可夢由 ，球與外界之電路板連接。由树紐與晶片之敎膨^係 數相近’ Μ連闕具有與電路板鐘之組成，因此可大 異所造成之^細餘板或縣基板與 電路板之間接合不㈣情形，進吨高龍製程之良率。 明如下 Μ為之上述料他㈣、触和伽能更明顯 =’下域軸佳實_，魏麵_心作詳細說 【實施方式】 請參考圖卜其綠示為本發明之較佳實施例之一種封 裝基板的不意圖。如圖i所示，封裝基板漏包括一石夕基 材110、-絕緣層120、一内連線層130、多個導電塊14〇 以及多個銲球塾15G。其中，絲材110具有相對應之-第-表面110a與-第二表面u〇b，且石夕基材11〇内具有 貝牙第一表面110a與第二表面_的多個貫孔112。此 外，絕緣層12G係全面性地覆蓋魏材nG之第一表面 110a、第一表面ii〇b與貫孔112之内壁，其中絕緣層⑽ 的材質例如是一氧化石夕或其他絕緣材料。 請再參考圖1，内連線層130係配置於第一表面n〇a 上方的絕緣層12G上，且貫孔112暴露出部分之内連線層 130。在本實施例中’内連線層⑽例如是依序由多個圖案 化線路層m與多個介電層134交互疊合而成’其中圖案 化線路層m的材胃例如可以是鈦/銅合金或鈦/銅/欽合 金。此外，介電層m的材質可為有機材料，例如聚酿亞 胺等。 請再參考圖1，導電塊140係配置於矽基材11〇之貫 孔112内。本實施例之每一導電塊14〇例如包括有一合金 層142(如銅/鎳合金層）以及一銲料塊144,其中合金層142 係配置於貫孔112内，而銲料塊144係配置於合金層142 上，並凸出於貫孔Π2外。此外，銲球墊15〇係配置於内 連線層130上，並透過内連線層13〇分別電性連接至導電 塊140，其中銲球墊15〇的材質例如是鎳/金合金或鎳釩/ 金合金。 μ 11 l274^Qwf.doc/r 值得一提的是’為了提高導電塊140與矽基材110與 内連線層130之間的接合效果，本發明更例如可在矽基材 U0的貫孔II2内配置一金屬層，其中此金屬層16〇 係位於導電塊140與矽基材110之間，以及導電塊140與 内連線層130之間，金屬層16〇的材質例如是鈦/銅合金。 上述實施例所提出之封裝基板1〇〇之矽基材11〇的一 側具有V電塊14G可與晶#(未纟會示)連接，内連、線層⑽ 之一側具有_墊15〇可與外部之電路板(未繪示)連接。 其中，由於矽基材110與晶片之熱膨脹係數相近，而内連 線層130之組成與電路板類似，因此可有效避免接合後晶 片、封裝基板1GG以及電路㈣之鱗㈣數不匹配的問 題0 為了更清楚說明本發明之特徵，下文將再提出上述之 1裝基板的-種製作方法加以說明。圖2a〜2r^示為本 赉明之-難實施狀—種縣絲 ^ ’其中方便制，圖2A〜2R雜__標號標賴 i述目同的70件’且部分70件的材質與配置等亦不再重複 1ί0夕首先’f參相2A ’提供魏材11G，並且在石夕基材 -表面11〇a上形成第一絕緣層122。在本實施例 I ’ 緣層122的材_如是二氧切或其他絕緣材 m 此弟一絕緣層122的方法包括進行化學氣相沉 和(如^心化學氣相沈積)或其他適當的賴製程。 接考’請參考2B〜2G，在第一絕緣層122上形成一 12 12743i9(0ltwf.doc/r 130 ’其中本實施例例如是在第一絕緣層122上 互疊合❹侧案化線路層132與多個介電層 =4。舉例而言，如_麻，本實關 絕緣層122上形成-導電材料層(夂 丁）/、材貝例如疋鈦/銅合金或鈦/鋼/欽合金。之後，再 行例如微影與侧等步驟來圖案化此導電材料層，以形 】ϊΐϊίί132 °接著’如圖2C所示，在形成第一層的 二‘古1132之後’可在圖案化線路層132上藉由例 如印刷的方式形齡電材制(树示） 有機材料。並且，進行微影製程，以圖案化=介PlaSmMCP) is engraved to expose the inner layer of the via. Thereafter, the patterned photoresist layer is removed. According to the preferred embodiment of the present invention, the method of forming in the through hole includes, for example, forming a "patterned photoresist wafer == photoresist" on the cut substrate; exposing the through hole. Next, a conductive block is formed by plating the inner photoresist layer with a patterned photoresist layer. After that, the patterned light doc/r resist layer is removed. According to a preferred embodiment of the present invention, the forming of the conductive block in the through hole further includes forming a metal material layer on the germanium substrate and the through hole, and forming a conductive block in the through hole. It also includes removing the layer of metallic material located outside the through hole. According to a preferred embodiment of the present invention, after the conductive bumps are formed in the via holes, the conductive bumps are further included. The invention further provides a chip packaging process, after completing the fabrication of the package substrate, and then arranging a wafer on the second insulating layer above the second surface of the stone substrate, and electrically connecting the wafer to the conductive block. To form a chip package structure. In a preferred embodiment of the invention, the wafer packaging process described above, after forming the solder balls, includes, for example, forming a plurality of fresh balls on the solder ball pads. / Based on the above, the package substrate of the present invention is mainly composed of 7 substrates and (4) wire layers having different thermal expansion coefficients, and the substrate-side conductive blocks can be used for "connection" (four) wiring layer-side welding. The ball can be dreamed by, the ball is connected to the circuit board of the outside world. The coefficient of the expansion of the tree and the chip is similar to that of the board. The Μ连阙 has the composition of the circuit board clock, so it can be caused by the difference. The joint between the substrate and the circuit board is not (4), and the yield of the high-Dragon process is as follows. The following is the above-mentioned material (4), the touch and the gamma energy are more obvious = 'the lower domain axis is good _, Wei noodle _ heart DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment] Please refer to FIG. 2 for a schematic diagram of a package substrate according to a preferred embodiment of the present invention. As shown in FIG. 1, the package substrate drain includes a stone substrate 110, an insulating layer 120, An inner wiring layer 130, a plurality of conductive bumps 14A, and a plurality of solder balls 15G. wherein the wires 110 have corresponding first-surfaces 110a and -second surfaces u〇b, and the stone substrate 11 The inside of the crucible has a plurality of through holes 112 of the first surface 110a and the second surface of the beryllium. In addition, the insulating layer 12G The first surface 110a of the Wei material nG, the first surface ii〇b and the inner wall of the through hole 112 are comprehensively covered, wherein the material of the insulating layer (10) is, for example, a oxidized stone or other insulating material. Please refer to FIG. The wiring layer 130 is disposed on the insulating layer 12G above the first surface n〇a, and the through hole 112 exposes a portion of the inner wiring layer 130. In the embodiment, the inner wiring layer (10) is sequentially The plurality of patterned circuit layers m and the plurality of dielectric layers 134 are alternately laminated. The material of the patterned circuit layer m may be, for example, a titanium/copper alloy or a titanium/copper/champ alloy. Further, the dielectric layer m The material may be an organic material, such as a poly-imine, etc. Referring again to Figure 1, the conductive block 140 is disposed in the through hole 112 of the substrate 11 . Each of the conductive blocks 14 of the embodiment includes, for example, An alloy layer 142 (such as a copper/nickel alloy layer) and a solder bump 144, wherein the alloy layer 142 is disposed in the through hole 112, and the solder bump 144 is disposed on the alloy layer 142 and protrudes beyond the through hole 2. In addition, the solder ball pads 15 are disposed on the interconnect layer 130 and electrically connected through the interconnect layer 13 To the conductive block 140, wherein the material of the solder ball pad 15 is, for example, a nickel/gold alloy or a nickel vanadium/gold alloy. μ 11 l274^Qwf.doc/r It is worth mentioning that 'in order to improve the conductive block 140 and the germanium substrate For example, a metal layer may be disposed in the through hole II2 of the tantalum substrate U0, wherein the metal layer 16 is located on the conductive block 140 and the tantalum substrate 110. Between the conductive block 140 and the interconnect layer 130, the material of the metal layer 16 is, for example, a titanium/copper alloy. The package substrate 1 of the above embodiment has a side of the substrate 11 具有 having a V The electric block 14G can be connected to the crystal # (not shown), and one side of the interconnecting and line layer (10) has a pad 15 which can be connected to an external circuit board (not shown). Wherein, since the thermal expansion coefficient of the crucible substrate 110 and the wafer are similar, and the composition of the interconnect layer 130 is similar to that of the circuit board, the problem of the number mismatch between the wafer after the bonding, the package substrate 1GG, and the circuit (4) can be effectively avoided. In order to more clearly illustrate the features of the present invention, a method of fabricating the above-described one-substrate substrate will be further described below. Fig. 2a~2r^ show the material-difficulty--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Etc., and the first insulating layer 122 is formed on the stone substrate-surface 11〇a. In the present embodiment I, the material of the edge layer 122, such as a dioxo prior or other insulating material, may be subjected to chemical vapor deposition and (e.g., chemical vapor deposition) or other suitable Process. Referring to 2B to 2G, a 12 12743i9 (0 ltwf.doc/r 130 ' is formed on the first insulating layer 122. The present embodiment is, for example, superimposed on the first insulating layer 122 on the side of the first insulating layer 122. 132 and a plurality of dielectric layers = 4. For example, such as _ hemp, the real insulating layer 122 is formed - a layer of conductive material (jading) /, material shells such as bismuth titanium / copper alloy or titanium / steel / chin After that, the conductive material layer is patterned by, for example, lithography and side steps to form ϊΐϊίί 132 ° and then as shown in FIG. 2C, after forming the first layer of the second '1132', it can be patterned. The organic material is made on the circuit layer 132 by means of, for example, printing, and the lithography process is performed to pattern
層’而形成介電層134’其中介電層134係暴露出 八下方之4分的圖案化線路層132。同理，如圖2D〜2G 所不，本發明更例如可重複上述步驟，以陸續在第一絕緣 層122上形成多個圖案化線路層132與多個介電層134， 以構成内連線層13〇。 曰 、然後’請參考圖2H ’形成内連線層130之後，可在 ΓΪ3Γ0上形成多個鲜球塾150 °在本實施例中，例 口可先猎由缝或其他成膜技術在内連線層13()上形成一 ^材=層(未緣示）’其材質例如是鎳/金合金或鎳飢/金合 進行例如微影與餘刻製程，以圖案化此導電 材枓層，進而形成銲球墊15〇。 1 = 考圖21與2J，在石夕基材110内形成多個 二B ’/、中貝孔112暴露出部分之第-絕緣層122。本 务明用以在石夕基材110内形成貫孔112的方法例如是如圖 13 doc/r I2743QQitWf. 21所示，先形成一圖案化光阻層17〇於矽基材n〇的第二 表面110b。接著，如圖2J所示，再以圖案化光阻層17〇 為罩幕，對矽基材110進行感應耦合電漿(Inductively Coupled Plasma，ICP)蚀刻，以形成貫孔112，之後再移除 圖案化光阻層170。當然，在本發明之其他實施例中，更 例如可採用其他蝕刻技術、雷射鑽孔或機械鑽孔等方式來 形成貫孔112。 然後，請參考圖2K，在矽基材110之第二表面ll〇b 與貫孔112之内壁上形成一第二絕緣層124，其材質例如 同樣是二氧化矽。此外，在矽基材11〇之第二表面n〇b 與貫孔U2之内壁形成第二絕緣層124的方法例如是進行 電漿增盈化學氣相沈積(Plasma Enhanced Chemical v叩听The layer ' forms a dielectric layer 134' in which the dielectric layer 134 exposes a patterned wiring layer 132 of four points below eight. Similarly, as shown in FIGS. 2D to 2G, the present invention can further repeat the above steps, for example, to form a plurality of patterned circuit layers 132 and a plurality of dielectric layers 134 on the first insulating layer 122 to form interconnects. Layer 13〇.曰, then 'please refer to Figure 2H' to form the interconnect layer 130, a plurality of fresh balls 塾 150 ° can be formed on ΓΪ3Γ0. In this embodiment, the mouth can be first hunted by seams or other film forming techniques. A layer of material (not shown) is formed on the layer 13 (), and the material thereof is, for example, a nickel/gold alloy or a nickel/gold alloy for performing, for example, a lithography and a process to pattern the conductive layer. Further, a solder ball pad 15 is formed. 1 = Referring to Figs. 21 and 2J, a plurality of second B'/, and a portion of the first insulating layer 122 exposed by the mesopore 112 are formed in the stone substrate 110. The method for forming the through hole 112 in the stone substrate 110 is, for example, as shown in FIG. 13 doc/r I2743QQitWf. 21, first forming a patterned photoresist layer 17 on the substrate n〇 Two surfaces 110b. Next, as shown in FIG. 2J, the patterned photoresist layer 17 is used as a mask, and the germanium substrate 110 is inductively coupled (ICP) etched to form the through holes 112, and then removed. The photoresist layer 170 is patterned. Of course, in other embodiments of the invention, the through holes 112 may be formed by other etching techniques, laser drilling or mechanical drilling, for example. Then, referring to FIG. 2K, a second insulating layer 124 is formed on the inner surface of the second surface 11b of the crucible substrate 110 and the inner wall of the through hole 112, and the material thereof is, for example, cerium oxide. Further, a method of forming the second insulating layer 124 on the second surface n〇b of the tantalum substrate 11 and the inner wall of the through hole U2 is, for example, performing plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical v.
Deposition，PECVD)。 之後，請參考圖2乙與2]^，移除貫孔112所暴露之第 一絶緣層110a，以暴露出部份之内連線層130。在本實施 例中例如疋如圖2L所示，先形成一圖案化光阻層18〇 ⑩ 於矽基材110之第二表面11〇b上方的第二絕緣層124上， 且圖案化光阻層180暴露出貫孔112内的第一絕緣層 122/接著以圖案化光阻層18〇為罩幕，對第一絕緣層122 進仃感應耦合電漿(Inductivdy C〇Upled piasma，icp)蝕 刻，以暴露出貫孔112内的内連線層l3〇。然後，再如圖 一所示，移除圖案化光阻層180,如此第一絕緣層122與 第二絕緣層124便可構成全面性覆蓋矽基材11〇之第一^ 面〇a苐一表面ll〇b與貫孔112之内壁的絕緣層12〇。 14 12743淞 ltwf.doc/r 本發明可選擇性地在貫孔112 ^ 增加後續形成之導電塊14G(請 屬層160 ’以 内連線層130的接合效果。此步: 夕基板110以及 在石夕基材uo切及貫孔112乂=如疋如圖2N所示， 162,其中形成此全屬材料屏 王面形成一金屬材料層 豆他成肺r 3 的枝例如㈣用賴或 銅合金。 驾何討層162的材質例如是鈦/ 接著，請參考圖20〜2R，在貫孔112内形 】塊=’其中導電塊140透過内連線層13〇分別電性連 在。百先’如圖2〇所示，本實施例例如是先 f夕基材11G上形成-_化光阻層⑽ 光阻層刚暴露出貫孔112。接著，如圖2p所示，^案匕 化光阻層190為罩幕，在貫孔m内電鑛形成導電塊 在此步驟中’例如是先在貫孔112内形成一合金層142(如 銅/鎳合金層），再於合金層142上已例如印刷的方式填入 預銲料(pre-solder)，以形成銲料塊144。值得一提的是， 藉，調整圖案化光阻層190的厚度，將可控制導電塊14〇 的咼度。之後，如圖2Q所示，若先前選擇在矽基材11〇 上以及貫孔112内形成金屬材料層162，則需進行例如姓 刻製程，以移除位於貫孔H2外的金屬材料層162，而形 成金屬層160。然後，如圖2R所示，移除圖案化光阻層 190，而使得銲料塊144凸出於貫孔112外。 當然，在完成上述步驟之後，本發明更例如可迴銲導 電塊140，並可進行清洗的步驟，以形成如圖1所示之封 15 I2743^Qltwfd()c/r 裝基板100。 此外 @ 可猎由上述之封裝基板_進行一晶片 插=厂。θ 3A〜_3B緣示為本發明之—較佳實施例之一 之j封ΐ製程的示意圖’其中為簡化圖示，封裝基板漏 ^兀件的標號並未在圖3Α〜3Β緣出，關於這些元件 =示與說明請參考圖i。如圖Μ與SB所示，此晶片封 衣衣程主要是將上述之縣基板⑽與接合， 並使晶片200透過封裝基板1〇〇電性連接至外部電路。其 中，例如可轉性地明板印刷(stendl响㈣的方式在 晶片細的鮮墊202上形成一鋒料綱，並翻覆晶片200， 使晶片200上的銲料2〇4與封裝基板1〇〇之導電塊14〇上 的杯料144接合。之後，例如可進行迴鮮的製程，使得鲜 料144與204可相互結合而將晶片綱固定在封裝基板觸 上，並使晶片200與封裝基板1〇〇電性連接。 ^另一方面，上述之晶片封裝製程亦可在銲球墊150上 形成多個銲球152，並藉由鲜球152連接封裝基板1〇〇與 外部之電路板300。當然，電路板3〇〇之接點3〇2上亦可 預先行成銲料或其他型態之導電膠(未繪示），在此便不再 詳細說明。封裝基板100與電路板3〇〇接合後，銲球152 係對應連接電路板300之接點302與封裝基板1〇〇之銲球 墊150，而晶片200之銲墊202可透過封裝基板1〇〇與電 路板300之接點302電性連接。 綜上所述，本發明之封裝基板之矽基材的一側可與晶 片連接，其中由於矽基材與晶片之熱膨脹係數相近，因此 16 I2743^ltwf,〇c/r I的與封裝基板之間接合後可能之熱膨服不匹 =1:Γ，本發明之封震基板之之内連線層的-側 係用以與外界之電路柘i表技 粞^ 穴丁門逆琛層具有與電路板 心、」、且成’例如是由圖案化線路層與多個介電層(如聚醯 互疊合而成，同樣可降低縣基板與電路板之間的 異/因此，藉由本發明之聽基板可有效降低晶 /十衣衣程中，由於熱膨脹差異所造成之接合不良的情 y並了減y熱應力(thermai stress)與龜曲(warpage)現象發 生’進而可提升晶㈣裝製程之&率與晶#縣結構之 靠度。 —雖然本發明已以較佳實施例揭露如上，然其並非用以 限本發明，任何熟習此技藝者，在不脫離本發明之精神 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1綠示為本發明之較佳實施例之一種封裝基板的示 意圖。 圖2A〜2R繪示為本發明之一較佳實施例之一種封袭 基板的製作方法的示意圖。 、 圖3A〜3B繪示為本發明之一較佳實施例之一種晶片 封裝製程的示意圖。 【主要元件符號說明】 100 :封裝基板 no :矽基材 17 12743郝 ltwf.doc/r 110a第一表面： 110b :第二表面 112 :貫孔 120 :絕緣層 122 ··第一絕緣層 124 ·•第二絕緣層 130 :内連線層 132 :圖案化線路層 • 134 :介電層 140 :導電塊 142 :合金層 144 ··銲料塊 150 :銲球墊 152 :銲球 160 :金屬層 170、180、190 :圖案化光阻層 φ 200 ·•晶片 202 :銲墊 • 204 :銲料 • 300 :電路板 302 :接點Deposition, PECVD). Thereafter, referring to FIG. 2B and 2], the first insulating layer 110a exposed by the through hole 112 is removed to expose a portion of the inner wiring layer 130. In this embodiment, for example, as shown in FIG. 2L, a patterned photoresist layer 18〇10 is formed on the second insulating layer 124 above the second surface 11〇b of the germanium substrate 110, and the patterned photoresist is patterned. The layer 180 exposes the first insulating layer 122 in the via hole 112 and then etches the first insulating layer 122 by inductively coupling plasma (Inductivdy C〇Upled piasma, icp) with the patterned photoresist layer 18 as a mask. To expose the interconnect layer 13b in the through hole 112. Then, as shown in FIG. 1, the patterned photoresist layer 180 is removed, so that the first insulating layer 122 and the second insulating layer 124 can form a first covering surface of the substrate 11 The surface 11b is insulated from the inner wall of the through hole 112. 14 12743淞ltwf.doc/r The present invention selectively increases the bonding effect of the subsequently formed conductive block 14G (the layer 160 of the layer 160' is formed in the via hole 112. This step: the substrate 110 and the stone夕 substrate uo cut and through hole 112 乂 = as shown in Figure 2N, 162, which forms the whole material of the material screen to form a metal material layer of beans into the lungs r 3 branches such as (four) with Lai or copper alloy The material of the layer 162 is, for example, titanium/following, please refer to FIG. 20 to 2R, and the block is formed in the through hole 112. The block 124 is electrically connected to the conductive layer 140 through the interconnect layer 13 . As shown in FIG. 2A, in this embodiment, for example, a photoresist layer (10) is formed on the substrate 11G, and the photoresist layer just exposes the through hole 112. Then, as shown in FIG. 2p, The photoresist layer 190 is a mask, and the electric ore is formed in the through hole m to form a conductive block. In this step, for example, an alloy layer 142 (such as a copper/nickel alloy layer) is formed in the through hole 112, and then the alloy layer 142 is formed. A pre-solder has been filled, for example, in a printed manner to form a solder bump 144. It is worth mentioning that, by adjusting the thickness of the patterned photoresist layer 190, The degree of twist of the conductive block 14〇 can be controlled. Thereafter, as shown in FIG. 2Q, if the metal material layer 162 is previously formed on the tantalum substrate 11〇 and the through hole 112, for example, a surname process is required to move The metal layer 160 is formed except for the metal material layer 162 located outside the through hole H2. Then, as shown in FIG. 2R, the patterned photoresist layer 190 is removed, so that the solder bumps 144 protrude out of the through holes 112. After the above steps are completed, the present invention further reflows the conductive block 140, for example, and can perform a cleaning step to form a package 15 I2743^Qltwfd()c/r package substrate 100 as shown in FIG. From the above-mentioned package substrate _ a wafer insertion = factory. θ 3A ~ _3B edge is a schematic diagram of the j-sealing process of one of the preferred embodiments of the present invention, wherein the package substrate is omitted for simplicity of illustration The reference numerals are not shown in Figure 3Α~3. For the description of these components, please refer to Figure i. As shown in Figure Μ and SB, the wafer sealing process is mainly to join the above-mentioned county substrate (10), and The wafer 200 is electrically connected to the external circuit through the package substrate 1 . The method of stentl printing (fourth) forms a sharp material on the thin fresh pad 202 of the wafer, and flips the wafer 200, so that the solder 2〇4 on the wafer 200 and the conductive block 14 of the package substrate 1 are turned over. The cup 144 on the crucible is joined. Thereafter, for example, a reflowing process can be performed, so that the fresh materials 144 and 204 can be combined with each other to fix the wafer on the package substrate, and the wafer 200 and the package substrate 1 are electrically connected. On the other hand, the above-described chip packaging process can also form a plurality of solder balls 152 on the solder ball pad 150, and connect the package substrate 1 and the external circuit board 300 by the fresh balls 152. Of course, the solder joints or other types of conductive paste (not shown) may be pre-formed on the contacts 3〇2 of the circuit board 3, and will not be described in detail herein. After the package substrate 100 is bonded to the circuit board 3, the solder balls 152 are corresponding to the solder joints 150 of the connection board 302 and the package substrate 1 , and the solder pads 202 of the wafer 200 can pass through the package substrate 1 . The 〇 is electrically connected to the contact 302 of the circuit board 300. In summary, one side of the germanium substrate of the package substrate of the present invention can be connected to the wafer, wherein the thermal expansion coefficient of the germanium substrate and the wafer are similar, so the ratio of the substrate to the package substrate is 16 I2743^ltwf, 〇c/r I The thermal expansion may not be the same after the jointing: Γ, the inner side of the wiring layer of the sealed substrate of the present invention is used for the circuit with the outside world. And the circuit board core, "and" is, for example, formed by a patterned circuit layer and a plurality of dielectric layers (such as polysilicon), which can also reduce the difference between the substrate and the circuit board of the county. The invention can effectively reduce the poor bonding caused by the difference in thermal expansion in the crystal/decimation process, and reduce the heat stress and the warpage phenomenon, which can further enhance the crystal (4). </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; ^ In the scope, when some changes and retouching can be made, the protection of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a package substrate according to a preferred embodiment of the present invention. FIGS. 2A to 2R are diagrams showing the present invention. A schematic diagram of a method for fabricating a sealed substrate according to a preferred embodiment. 3A to 3B are schematic views showing a process of a chip package according to a preferred embodiment of the present invention. [Description of Main Components] 100: Package Substrate No : 矽 substrate 17 12743 Haoltwf.doc / r 110a first surface: 110b: second surface 112: through hole 120: insulating layer 122 · first insulating layer 124 · second insulating layer 130: interconnect Layer 132: patterned circuit layer • 134: dielectric layer 140: conductive block 142: alloy layer 144 · solder bump 150: solder ball pad 152: solder ball 160: metal layer 170, 180, 190: patterned photoresist layer φ 200 ·• Wafer 202 : Solder Pad • 204 : Solder • 300 : Board 302 : Contact