TWI273485B - Pipeline microprocessor, apparatus, and method for generating early status flags - Google Patents

Abstract

An apparatus and method for generating early status flags in a pipeline microprocessor is disclosed. The apparatus includes early status flag generation logic that receives an instruction, an early result of the instruction, and a valid indicator of the early result and responsively generates the early flags. If the instruction is flag-modifying, then the early status flags are stored in an early flags register. The early flags in the register are invalidated if the early result from which they are generated is invalid. The early status flags and associated valid indicator may be employed by subsequent conditional instructions for early execution to avoid delay in waiting for the architected status flag values to be generated by execution units later in the pipeline. The early flags are revalidated if all flags-modifying instructions in pipeline stages below the early flag generation logic, if any, have already updated the architected status flags.

Description

1273485 IX. Description of the Invention: [Technical Field] The present invention relates to a pipeline microprocessor, and more particularly to an early instruction execution of a pipeline microprocessor. [Prior Art] Today's microprocessors are generally Pipeline microprocessors. That is, multiple instructions are executed simultaneously in different blocks of the microprocessor or in the hierarchy of the pipeline. Hennessy and Patterson define the pipeline as "an execution technique in which multiple instructions overlap in one execution." They use pipelined techniques in Computer Architecture: A Quantitative Approach, 2nd edition, by John L. Hennessy and David A. Patterson, Morgan Kaufmann Publishers, San Francisco, CA, 1966 - The book provides the following instructions: A pipeline is like an assembly line, taking the car assembly line as an example: in the car assembly line, there are many steps, each step There are some contributions to the manufacture of cars, and although they are on different cars, the operations between the steps are parallel. In the computer pipeline, each step in the pipeline is used to complete a portion of the instruction, just like an assembly line, with different steps completing different parts of the different instructions in parallel. Each step is called a pipe stage or a pipe segnient. These stages are interconnected to form a pipeline that is routed from one end of the pipeline to the staged end and exited from the other end as if the car were completed on the assembly line. 1273485 Synchronous microprocessor 11 operates according to the clock cycle (elGek eyde). The blood type is based on a - clock cycle that transfers 1 from one stage of the pipelined micro-treatment crying line to the next stage. In the - car ^i 'if the guardian of the stage of the assembly line - because there is no car (4)

If idle, the results or output of this assembly line will decrease. Similarly, if the I microprocessor, the 'stage is in the -clock cycle, because there is no instruction executable and idle' then the result of this program will be reduced, the general situation is called the pipeline bubble. One potential cause of pipeline bubbles is due to branch instructions. When a branch instruction occurs, the processor must determine the target address of the branch instruction and start fetching the instruction at the destination address instead of fetching the next consecutive address of the branch instruction. In addition, if the branch instruction is a -conditional branch instruction (i.e., whether or not the branch occurs depends on whether the condition exists or not), the processor must determine whether the branch instruction has occurred. In addition, the processor must also determine the target address. Because the pipeline stage finally determines the time of the target address and/or the branch result (i.e., whether the branch occurs), it is usually the fetching of the instructions at many stages after this phase. In response to this problem, modern microprocessors typically utilize a branch prediction mechanism to predict target addresses and branch results early in the pipeline. Microprocessor designers are constantly working to design branch predictors with higher accuracy. However, branch mispredictions will waste a lot of time. As mentioned above, the error prediction must be detected and corrected during the pipeline phase of the branch prediction phase. The loss associated with mispredictions is related to the execution of many pipeline stages between the branch prediction and branch error prediction correction stages. Therefore, an apparatus and method for 1273485 to correct conditional branch instructions mispredicted in the early stages of the pipeline is currently required. In addition, the conditional branch instruction indicates a branch condition, and if so, the microprocessor is instructed to transfer the branch condition to the branch target address; otherwise, the microprocessor continues to fetch the instruction for the next consecutive address. The microprocessor contains a status flag that stores the state of the microprocessor, and the status flag is used to detect if the condition indicated by the conditional branch instruction is asserted. Therefore, in order to determine whether a conditional branch instruction is mispredicted, the microprocessor must check the status of the latest status flag. However, today, the status flag is detected at the end of the pipeline to determine if the branch condition is true and if the branch prediction is correct. Therefore, a device and method for generating a status flag early in the pipeline is currently required. Finally, the state of the status flag is usually affected by the result of the previous conditional branch instruction. For example, the condition may be set by a status flag, a carry flag, whose status may be determined by the most recent addition instruction result. However, the result of the instruction affecting the status flag is generated by the execution unit of the lower pipeline stage of the microprocessor. Therefore, a device or method that can generate instructions early in the pipeline is currently a requirement. SUMMARY OF THE INVENTION In view of the foregoing, the present invention provides an apparatus and method for generating an early state flag for a pipeline microprocessor. Accordingly, an apparatus for generating an early status flag in accordance with an embodiment of the present invention includes an early status flag generation logic circuit for receiving an instruction, 1273485' and to indicate whether an early result is a valid indicator. If you mean: Phase II? The flag generation logic generates an early state flag that is stored in the second:, : = state flag correction instruction, and the early status flag will be generated by the target register. If the early flag is used before the early results, the conditional instruction after the structural formula is used, the flag correction command used in the online phase is after the early flag generation logic is heavily noisy, The age of the new estimate 1 early flag, re-estimation indicates that the structural (four) flag has been updated. The flood season (4) may be used to perform (4) early correction of the knife and branch instructions during pipelined microprocessing. A branch predictor predicts the result of i遽 in the pipeline. This prediction is performed in the pipeline along with the branch instruction: the knives correction logic circuit is executed in a pipeline stage, and the branch period correction logic power is executed at the stage branch instruction to reach the early branch correction logic circuit, = Early: The branch instruction logic circuit will use the branch finger; The early branch correction logic will correct this error if the early, lost, and prior instructions are produced and the heart is valid and mispredicted. In view of the above-described subject matter, in accordance with certain embodiments of the present invention, the early results of the instructions after the condition two 1 are performed by the early execution logic circuit early execution logic circuit in a pipeline stage, and The processing of 1273485 includes 53⁄4, also H,",

The sub-instruction is not designed to execute the previous instruction. The second instruction is a status flag. The second unit 70 is executed early, and the execution unit is used to generate the final instruction and the final flag value. The early execution logic is used to execute most of the instructions in the subset of instructions in the processor instruction set. In particular, the early: 仃J circuit corresponds to one of the pipeline address stages and contains an address. The early processing logic can add to the frequently executed instructions.

The early result is an invalid state flag correction command. This early state flag is in view of the above problem. In an embodiment of the present invention, the early result is stored in the early temporary archive towel. The register corresponds to the microprocessor. After the construction is temporarily stored, the early results are stored in the early temporary savings together with the effective indicators of each temporary register. Early (four) is difficult to be used as the early result of the operand to the early execution logic circuit / address generator, in order to produce early, σ fruit. The right early temporary archive provides an invalid input operand to the early, row logic circuit, and the generation of the county result is invalid. If the instruction is a correction flag of the status flag, the early status flag is invalid. Hereinafter, an apparatus and method for generating an early state flag of a g-line type micro-processed person according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements are denoted by the same reference numerals. Referring to Figure 1, a block diagram of a pipeline microprocessor 100 in accordance with a preferred embodiment of the present invention. The pipelined microprocessor 100 includes a plurality of stages in its pipeline. The diagram shows the pipeline microprocessors of the 12 pipeline stages. The pipelined microprocessor 1A includes an I stage 1〇2 (instruction fetch stage) for fetching instructions, and an I stage 1〇2 includes an instruction cache, which is used to cache program instructions, and the I stage 102 The instruction cache or a system memory of the pipelined microprocessor 100 acquires a program instruction, and the I stage 1〇2 acquires an instruction in a memory address in an instruction index register, and the instruction index is usually incremented after the instruction is fetched. Therefore the instructions can be taken out continuously. However, the instruction index value may be converted to a non-contiguous memory address in accordance with a branch instruction such that the pipelined microprocessor 100 is transferred to a branch target address. The I stage may also include a branch predictor 132, which predicts whether a branch instruction occurs in the fetch instruction stream, whether the branch instruction occurs, and determines the branch target address of the branch instruction when the branch instruction occurs. Therefore, the branch predictor 132 predicting whether the pipelined microprocessor 1 is finally recognized by the branch instruction, whether the pipelined microprocessor 1 is instructed to branch to a branch target address indicated by the branch instruction (occurring), or indicating a pipelined microprocessor 100 to obtain and execute the next consecutive instruction (not occurring) after the branch instruction, the I stage 102 receives the first and second control signals 154 and 156, as detailed below, to indicate that the I stage 102 correction is The branch predictor 132 generates one of the branch instruction predictions. In one embodiment, the branch prediction state 132 includes a branch target 12 1273485 address cache (BTAC) that stores the previously executed branch. The address of the instruction and the identified branch target address. In addition, the branch target address cache store prediction information is based on the history of the branch instruction and is used to predict whether the branch instruction will occur. The remaining embodiments include dynamic branch history tables, static branch predictors, and hybrid static/dynamic branch predictors, which are in the field of branch prediction. The inside is well known. In one embodiment, Phase I 1 〇 2 contains four pipeline stages. The pipelined microprocessor 100 also includes an F stage 1〇4 (instruction formatting stage) that is coupled to the I stage 102. In one embodiment, the instruction set of pipelined microprocessing 100 includes variable iength instructions, such as x86 structured instruction sets, rather than fixed-length instructions, and F stage 104 includes an instruction format. The parser is used to parse the syntax of the instruction byte stream and to separate the instruction byte stream into different instructions. In particular, the instruction formatter determines the length and start position of each instruction in the instruction byte stream. In one embodiment, the F stage 104 includes an instruction queue for storing one of the formatting instructions. The pipelined microprocessor 100 also includes an X stage 1 〇 6 (translation stage) that is coupled to the F stage 104. In one embodiment, pipelined microprocessor 100 includes a reduced instruction set computer (RISC) center. A simple instruction set executes a natural instruction set. Natural instructions (also known as microinstructions) are simpler and more efficient instructions than program instructions (macro instructions) obtained by I stage 102. 13 !273485 For example, the x86 structured instruction set contains macro instructions or complex instruction set computer (CISC) instructions. The X stage l〇6 includes an instruction translation program for translating macro instructions into microinstructions. The instruction translation program retrieves the format macro instruction from the macro instruction queue of the F stage 104, and translates each macro instruction into one or more micro instructions to provide the remaining stages of the pipelined microprocessor 100. Generally referred to as the execution phase of the pipelined microprocessor 100. In one embodiment, the X stage 106 includes a microinstruction queue to store the translated microinstructions. In one embodiment, the X stage 106 includes two pipeline stages. The pipelined microprocessor 100 also includes an R phase 1〇8 (temporary phase) and an A phase 112 (address generation phase), wherein the r phase 1〇8 is connected to the X phase 106, and the A phase 112 is coupled to R stage 1〇8 connection. The R-order 4 and 108 include an architecturally registered register file (ARF) 134 and an early register file (ERF) 136. The structured scratchpad 134 corresponds to a plurality of registers visible when the pipelined microprocessor executes the program. In particular, a program instruction may specify that one of the scratchpads corresponding to the structured temporary archive is a source operand, thereby receiving an input nickname to generate a result by operation; and, similarly, the program instruction may indicate the structure 1 134. The corresponding register is used as a target operand, so that the result of the finger 7 can be written. The instructions may indicate the register explicitly or implicitly. In the Yubei target case, the structural temporary archive 134 corresponds to the χ86 structured temporary storage of the 才, ΕΒΧ, ECX, EDX, EBP, ESI, EDI, and ESP registers (as shown in Figure 3). The temporary temporary archive 136 corresponds to the scratchpad, 1273485 which corresponds to each of the temporary archives in the structured temporary archive 134 (as shown in the figure), in view of the fact that storing the value in the early temporary archive register may result in a total The line microprocessor (10) is in an indeterminate state, so the value is stored in the two-configuration temporary storage slot 134 register to reflect the user-visible S of the pipelined microprocessor. For this reason, when the pipeline processing _丨(8)-stage generates an instruction result and the instruction indicates that the structural temporary storage slot 134 register is regarded as a target, this result does not allow the writer to write to the structural temporary storage slot 134. : The instruction is no longer undefined, that is, until the instruction is determined to be complete ^ is removed (four). As detailed below, in contrast, the result of the instruction may be written to the early temporary archive 136 before the order is determined to be complete. In particular, the result of one of the instructions generated by the early execution logic/address generator 138 (including phase A 112 and detailed below) may be written to the early stage when the instruction is slashed. Temporary filing 136. If the pipelined microprocessor 100 determines that the instruction itself and other instructions prior to the instruction are capable of generating an exception, then the instruction is determined to be complete, and all branch instructions prior to the instruction are eventually eliminated. In other words, the pipelined microprocessor 100 will ultimately determine each branch instruction prior to the instruction (whether or not it occurs correctly), and whether each acquired branch is the correct target address. In addition, the value of the cloud in the early temporary archive 136 may be valid or invalid, except for the uncertainty, so the value of the structured temporary archive 134 is always determined to be valid, as detailed below. Therefore, each of the early temporary archives 136 also includes a corresponding valid bit 218 (shown in Figure 3) for indicating whether the value stored in the register corresponding to 1273485 is valid. When the pipelined microprocessor 1 is reset, the initial temporary archive 136 that was initialized is the same value as the initialized structured temporary archive 134. The R phase 108 of the pipelined microprocessor 100 pipeline also contains a knot

An architected EFLAGS register 162, and an A phase 112 includes an early state register (early eflags reglSter) 142. The structured state register 162 and the early state register i42 configure a status flag to indicate the attributes of the result of the instruction, such as whether the result is zero, whether a carry occurs or a negative value. In one embodiment, each state flag is represented by a single bit. In one embodiment, the structured state register 62 includes an X 8 6 structured state register, and the X 8 6 structured state register contains the following flag: an overflow flag (〇verfl〇) w flag, 〇F), positive and negative flags (S1gn flag, SF), zero flag (zer.flag, ZF), parity flag plus flag 'PF), and carry flag CF (carryflag CF), as shown in item 3 Show. The micro-processing If 1GG is included in the instruction condition setting instruction condition code; - The condition code indicates - or status of multiple status flags. If the current state of the 曰% flag is equivalent to the state in the condition code, then this = true and the pipelined microprocessor 1GG executes - as indicated by the conditional instruction, ',, 'calculate' otherwise, the indicated operation will be Being executed. In the case where the instruction is a conditional branch instruction, if the instruction encounters (4) in the conditional branch instruction 2, then the condition is a jump pointer 〜, ,,. The component command indicates a condition code and a displacement to calculate a branch; and the address. - W example - dish (four) (10) - (four) instruction; ^ 16 1273485 zero condition ''true", the pipelined microprocessor 100 is transferred to the branch target address indicated by the branch instruction (ie, the conditional branch instruction occurs); however If the zero j flag (ZF) is set (ie, non-zero, the condition is false), the % pipelined microprocessor 100 takes the consecutive instructions following the conditional branch instruction. Other examples of the condition x86 |曰7 are SETcc, L〇〇pcc, and [Μονά]. The , , , " configuration cache register 162 includes a privately visible status flag that is executed by the pipelined microprocessor 100. In particular, the conditional program instructions can be based on a status indicator in the structured state register 162 to indicate a condition code. The early (four) temporary storage 11 142 is included in the state flag in the structural state register 162, as shown in FIG. The relationship between the configuration and the temporary archive 134 is similar to that of the early temporary storage 136. The value of the configuration in the structured state register 162 reflects the state in which the pipelined microprocessing is visible to the user of 1〇0. The value configured in the early state register 142 may reflect the indeterminate state of a pipelined microprocessor 100. Thus, when the *offline microprocessor executes an instruction to correct one or more status flags, the status flag is not updated in the structured status register 162 until the private order is no longer indeterminate. Conversely, as detailed below, the status flag can be updated in the early status register 142 before the deduction is completed. In particular, the pipelined microprocessor can be updated in the early state register I42, also referred to as the early execution unit, in accordance with an instruction executed by the early execution logic/(4) processing|| 138 before the instruction determination is completed. 146. In addition, the value of the structured state register 162 is always valid in view of the fact that the early state register ι42 value may be valid or not. 17 Ϊ 273485 ^ as discussed in detail below. Thus, as shown in Figure 3, the early state temporary storage ^42 also includes a valid bit 246 to indicate whether the value of the early state temporary benefit 142 is valid. The early state register 142 is initialized to the same value as the register 162 that was initialized when the pipelined microprocessor was reset. The embodiment of FIG. 3 represents the single-effective bit 246 of the early state === the device i42. However, the rest of the implementation records consider which of the valid values in the early state register 142 are maintained for each bribe flag. The early execution of the AP segment 112 relies on the circuit/address generator 138 system. = - Early results and effective difficulties, money is provided via the early results sink = row 152 back to the 卩 phase (10)' as detailed below. The early execution of the logic circuit 2 generates 1丨38, which is also based on the input operator and addresses the memory address for memory access, such as the structured temporary archive delivery, early temporary archive 136 and/or instructions. What is provided, such as - displacement or offset. The memory address can be implicitly indicated by the instruction ". The read address can also be implicitly indicated by the instruction, >: the address of the stack: - location; and the above actions are implicitly referred to as: the heap binary register (ie ESP) or block indicator register (ie, and 弹 or bounce command towel. (卩咖), such as a send pipeline microprocessor also includes a j-stage 114 link. J-stage... with early branch correction logic II The early knives correction logic circuit 选择性 selectively corrects the branch prediction according to the early state register 142 by the "control signal W, as follows. 18 1273485 The pipelined microprocessor 100 also includes a D stage 116. ,1

Phase 114 is connected, a G phase 118 system is connected, and a system is connected to J, "D" white segment 116; 5 a phase 122 system and a G phase 118 are far away ^ reverse building U and reverse connection. D phase 116, 118 And the data phase cache 122 includes a data storage cache data. In the embodiment, the data storage system memory has three pipeline stages and requires three clock cycles to access the memory area by the early pure logic circuit. The address generator 138 is taken out of the address and executed. The instructions for performing the data maneuver calculation are recorded in (4) segment 116, G phase 118, and Η phase 122. The pipelined microprocessor 100 also includes a stage 124 ( The execution phase) is connected to the η phase m. The m phase m includes an execution unit 146 to perform operations, and the execution unit 146 may include circuitry such as adders, Descendants, multipliers, dividers, shifters, rotations. The logic circuit of the Boolean operation, the logic circuit for performing the transcendental and logarithmic functions, etc., to generate the final result of the instruction. In an embodiment, the execution unit 146 includes an integer unit, a floating point unit, and a ΜΜΧ unit and an SSE unit. The result is an instruction result that is always correct by the execution unit 146. The input operand or source operand received by the execution unit 146 is always valid. The execution unit 146 inputs the source of the operand including the structural temporary storage 134, The structured state register 162, the data access operand, the direct or fixed operand indicated in the finger 7, and the operands sent from other pipelines. In particular, the execution unit 146 does not receive the early temporary archive 136 or The ambiguous operand of the early state register 142. The I273485/pipelined microprocessor 100 also includes an s phase 126 (storage phase), the second phase is connected to the E phase m. The s phase (3) performs a storage operation to store the material to The data storage area and/or system memory, such as the result of the instructions generated by execution unit 146. Additionally, stage 126 includes late branch correction logic 148, according to structured state register, 162 and by second control signal 156 to correct the branch prediction, as detailed below. The pipelined microprocessor 1〇〇 also includes a w phase 128 (result write back phase), which is linked to the s phase 126 The w stage 128 is used to write the result of the instruction to the structured temporary archive 134 and the structured state register 162 by the result bus 158 to update the structural state of the pipelined microprocessor 1 。. In an embodiment, The pipelined microprocessor 100 can be a single instruction dispatch microprocessor, a scalar microprocessor, or a single execution microprocessor. That is, one instruction is dispatched per clock cycle of the pipelined microprocessor 100 from the instruction dispatch, Or the instruction generation phase (I phase 102 through X phase 106) to the instruction execution phase (R phase 108 through W phase 128), which can deliver one or more executions per clock cycle compared to a super-scalar microprocessor instruction. However, the methods and apparatus described herein are not limited to a scalar microprocessor. In one embodiment, the pipelined microprocessor 100 includes a sequential dispatch microprocessor. That is, the instructions are dispatched for execution in the order indicated in the program, unlike some microprocessors having the ability to not dispatch instructions 206 sequentially. Referring to FIG. 2, a R-phase 108, an A-stage 丨12, 1273485, and a J-stage 114 of the pipelined microprocessor 100 of FIG. 1 are illustrated in detail in accordance with a block diagram of the present invention. As shown in FIG. 1, R stage 1 〇 8 includes a structured temporary storage 134, an early temporary archive 136, and a structured state register 162. The structured state register 162 is updated by the w stage 128 by the result bus 158. The R stage 108 receives the command 2〇6 from the stage 1〇6. In addition to its own instruction byte, instruction 2〇6 may include decoding information. The index 206 privately indicates the type of an instruction, such as - addition or branching. The instruction 206 can also refer to a different condition code. The instruction 2〇6 can also indicate a target operand position by a tag. In particular, the target operand may indicate the location in which the temporary register of the structured temporary storage 134 is used as the result of the instruction 206. Figure b1. The structured temporary archive 134 receives the result of the instruction from the w stage 12 8 through the result bus 158. A target operand tag 2 7 8 is provided as a selector to route through the bus to the structured temporary archive 134 to select a temporary update to be updated with the result of the command from the result bus 158. Save. As shown in the figure, the early temporary archive 136 receives the early results 242 from the A stage 112 by the early results bus 152. Instruction 2〇6 includes a "^ operand tag 216, which is provided as a selector as input early temporary archive 136 to select a register to be updated with earlier results 242. The target operand tag 216 provided to the early temporary archive 136 is transferred from the instruction 2〇6 to the pipeline register 232 of the a-stage 112. The instructions 206 can also be via the source operand tag 214 to indicate one or more source operands. In one embodiment, the instructions 206 may indicate three source transport elements. The instruction 206 is via the source operand tag 214 to indicate the scratchpad source operand. The source operand tag 214 is treated as a selector to input 21 1273485 into the structured temporary archive 134 and the early temporary archive 136 for selecting which register will be provided as the source operand to the instruction 2〇6. Instruction 2〇6 may also indicate a direct/fixed (e.g., replace or offset) operand 222. As also shown in FIG. 3, R stage 108 also includes a valid bit 218 for each early temporary file 136 register. The early temporary valid bit 2 is received by the A phase 112 via the early result bus to receive an early result valid L number 244. The early result valid signal 244 is used to update the effect bit 218 corresponding to the early temporary archive 136 register selected by the target operand tag 216. An R stage 108 also includes a multiplexer 226 that selects the source operand to cause the instruction 206 to enter the R stage. The multiplexer 226 receives the source operands input by the structure = , memory 134 and early temporary archive 136. In a practical example, the structured temporary archive 134 includes three read #, and their two rounds are used as inputs to the multiplexer 226 to neck two source operands per clock cycle. In the embodiment, the early temporary storage slot 136 includes two solids 珲' their outputs are used as inputs to the multiplexer 226 to provide (d) source operands per clock cycle. The multi-guard is also received by the direct/solid operator 222' which may be included in the instruction write. The multiplexer 226 also receives the early results 242 from the a stage 112. Additionally, multiplexer 226 receives one of the valid bit inputs associated with each operand input. The effective bit and the early temporary archive provided by the early temporary savings bit 218! 36 received operand related. The early result 242 operand phase _ effective valid signal ice received by the read ιΐ2. (4) Construction temporary storage (4) Money is straightforward ^ Calculation 22 1273485 The effective bits of the operation elements provided by _,, soil, 134 and direct/fixed 222 are Zeng Shuiyuan true, that is, the structural source and system selected by the structural temporary archive Always effective. The multiplexer 226 - source arithmetic unit: register valid bits are provided to 236 for supply to the read 8 and the valid bit pipeline register pipeline register 238 is used. . In one embodiment, the source operand register is used to store: one source and one source, and the effective bits are valid bits of the real ml. ^ 1 As in the example, tube green 4

The row (not shown), the basin spleen: processor 100 also includes the results of the transfer confluence stage 124 and the S stage 126 line unit 146, provided by the E-transfer bus system, to the R stage 108 Supply operands. Households #千一十, input for the 夕工器226. If the R phase 108 is different from the source, the label is not matched with the one that is smothered by the A phase 112 until the ⁄ 13⁄4 half and 122, but it is associated with the E stage 124 or 22 target. The match, followed by 'early flag generation/control field', road 212 controls the multi-guard, 226 to select the transfer bus to provide a new result as an operand. If an operand is on the forwarding bus, it is always valid. The official line microprocessor 1 also includes an early flag generation/control logic circuit 212. The early flag generation/control logic circuit 212 receives the structured state register 162 as an input. Early flag generation/control logic 212 also receives instructions 206 in R stage 1 〇 8 and a stage 112 as inputs. The early flag generation/control logic circuit 212 also receives the output of the multiplexer 226 as an input, i.e., the R stage 1 〇 8 source operand and the associated significant bit. The early flag generation/control logic circuit 212 also receives the output of the pipeline 23 1273485 register 232, the effective bit line register 236, and the register 238 as input, ie, the segment 112; Effective bit. The early flag generation/control logic circuit 212 is early as an input. The early flag generation/control logic circuit 12 also receives the a-phase ii2 under the parent-pipeline stage - the correction command presence signal 2G2 as the input. The flag correction command exists ^ - the true value indicates that the corresponding phase has the correction structure II - the instruction, and the structural state temporary storage is still her". The correction instruction exists in the signal transmission system early = electricity ... receives the new branch correction late: input. In the new branch correction late signal 268, the new late branch correction logic circuit 148 shown in Figure 1 is modified: Pre-two: The line indicates that the pipelined microprocessor 1 has been cleared. As shown in Fig. 5; the speed 'new branch correction late signal 268 is also used to judge == is restored and confirmed. Early flag generation/control 2 = 2 also receives the finger 1 of the finger 1 per pipeline stage present under the segment 112 as input. The target target class (4) is indicated by the instruction 206 indicating whether the source operand = the structured temporary archive 134, the early temporary archive 136 or the A phase 112 early result 242 is as described below with reference to FIG. In one embodiment, the instruction: refers to a memory source-derived element, that is, the location of an operand: kilograms. Usually the memory operation element exists in the pipeline type. You i: handle the handle of the fasting line 1 比f line than the low white P slave of the Lv踝, for example, there may be information about the situation 24 1273485, that is the purpose of the memory address The subject of a previous store instruction that matches the address of the R phase 1〇8 instruction. Although the difference = does not show the memory operand as an input. The early flag production: control circuit 212 also receives the memory operation element signal 266 as a turn-in" to indicate whether the memory source operation element not indicated by the instruction is to be supplied to the multiplexer 226. The memory operation signal plus ‘two: 疋no must turn off the R stage 108 instruction 206 and the early result 2 斲 is valid, as described in FIG. Whether ϋ 2 is based on its input, the early flag generation/control logic circuit 212 has the same control signal. The early flag generation/control logic circuit 212 generates a device control signal 282 that controls the multiplexer 226 to source the appropriate == 々 206 source. Early flag generation/control logic 2 = 钿 Early birth result valid signal 244. Early flag generation/control logic:: A state register 1 262 for storing in the early state register 142 and a control signal 264 for updating the value asserted in the early state. The value in the early state valid register is 4曰6, which is initialized to a valid value when the microprocessor re-sets the text. The early = ^ register 142 and the early state valid register 246 serve as a pipeline register to provide the early state register and the valid bit to the j stage 114. The early flag, raw/control logic circuit 212 also generates a suspend signal 228 that provides g line registers 232, 234, a valid bit line register 236, and a source operand line register 238 to turn off R stage 1 〇 8. In one embodiment, the pipeline registers 232, 234, 236, and 238 include multiplex registers that are used to maintain their current state until the pause signal 228 is true until a clock cycle of 25 1273485. The operation of the pause signal 228 will be described in detail below with reference to FIG. Phase A 112 includes an early execution logic/address generator 138 that receives source operands from source operand pipeline register 238 and produces early results 242 based on source operand pipeline register 238. The early execution logic/address generator 138 includes an arithmetic logic circuit 272, a Boolean operation logic circuit 274, and a displacement logic circuit 276. The early execution logic/address generator 138 is used to generate the actual address for the memory gymnastics. The early execution logic/address generator 138 is also used to execute a subset of the operations required by the instructions of the instruction set of the pipelined microprocessor 100. Thus, the early execution logic/address generator 138 can perform a subset of the operations by the execution unit 146 as shown in FIG. The early execution logic/address generator 138 is used to perform a subset of the operations, which are the most commonly performed operations. In one embodiment, the most commonly performed operations are also substantially overlapping with the fastest performing operations (ie, requiring a relatively short time to execute, so they can be executed in a single clock cycle) and require a relatively small amount of Hardware, especially in hardware, has been required to generate memory addresses. In one embodiment, the arithmetic logic circuit 272 is operative to perform an addition, subtraction, increment, and decrement; however, the arithmetic logic circuit 272 is not a subtraction to perform the addition or borrowing of the carry. In one embodiment, the Boolean logic circuit 274 is configured to perform an AND and OR, OR, XOR, NAND, positive and negative extension, and zero The movement of the bit extension; however, the Boolean logic circuit 274 is not used to perform a one-tuple replacement. In one embodiment, the displacement logic circuit 276 is configured to perform a left bit 26 1273485 shift or right shift; however, the shift logic circuit 276 is not used to perform a spin or rotate carry operation. Although the specific embodiment has been described, the specific subset of operations performed in the logic/address generator 138 is performed earlier, and the present invention is not limited to a particular embodiment, and those skilled in microprocessor design may readily appreciate the early stages. Execution logic/address generator 138 may be based on a particular set of instructions of pipelined microprocessor 100 to perform a particular subset of operations and target execution and circuit actual endpoints. The early results 242 generated by the early execution logic/address generator 138 are provided to an early result pipeline register 254 for storage and subsequent supply to the j stage 114. The J stage includes an early branch correction logic circuit 144 as shown in FIG. The early branch correction logic circuit 144 receives the output of the early state register 142, the early history valid register 246, and the early result pipeline register 254. The early branch correction logic circuit 144 also receives an instruction from the J-stage 114 by a camp line register 248 for pipelined instructions 206 to be pipelined by the pipeline register 232. The pipelined microprocessor 1A also includes a branch prediction generation signal 208, which is passed through the I stage 〇2, the F stage 1〇4, and the χ stage 〇6, and passes through the pipeline register 234 of the R stage 108. The pipeline stage 252 of phase A 112 is transmitted from the pipeline and is provided to the early branch correction remote circuit 144. The true value of the branch prediction occurrence signal 2〇8 refers to the instruction system-branch instruction in the corresponding stage, which is predicted to occur by the branch prediction of FIG. i being 132, that is, the pipelined microprocessor 1 The prediction is based on the prediction made by the branch predictor 132. Based on its input, early branch correction logic 144 generates a first control 154 that is used to provide stage I 102 of FIG. The first control 27 1273485 signal 154 includes an early branch correction signal 258 that is provided to the late branch correction logic circuit 148 of FIG. When the early branch correction logic circuit 144 corrects a branch prediction, the early branch correction signal 258 is true. Please refer to Figure 6 for the operation of the early branch correction logic circuit 144 and as explained in detail below. Referring to FIG. 4, it is a flow chart of the operation of one of the early results and the early state register of FIG. 2 according to the present invention. The flow chart of Figure 4 includes two drawings, Figures 4A and 4B, respectively, and the flow begins at block 402. In block 402, an instruction 206 indicates that a source operand has arrived at the R stage 108 by the structured temporary archive 134. The instruction indicates that one or more of the source temporary operands are via the source operand tag 214. Flow continues to decision block 404. In decision block 404, early flag generation/control logic 212 detects the command type and determines that it must be executed at stage A 112 regardless of the type of instruction. In one embodiment, when an instruction that must be supplied to the data cache in D stage 116 requires the generation of a memory address, the instruction must be executed in stage A 112. If the instruction must be executed in stage A 112, then flow continues to block 406, otherwise flow continues to block 412. In decision block 406, the early flag generation/control logic circuit 212 determines whether all of the source operands indicated by the instruction are present and valid. If the instruction indicates a memory operand, the early flag generation/control logic circuit 212 detects the memory operand presence signal 266 to determine if the indicated memory operand is present and valid. If the instruction indicates a direct operand, the direct operand is always present and valid. If the instruction indicates a 28 1273485 temporary operand, the early flag generation/control logic 212 compares the destination tag 204 and the source operand tag 214 from the lower order pipeline to determine the old instruction generation in the pipelined microprocessor 100. As a result, it is predetermined 1 to indicate the structured temporary archive 134 register by the source operand tag 214. If so, the result is in the early temporary archive, in which case the early generation/control logic 212 will detect the valid bit 218 for the indicated operand to determine if the operand is valid. If an old instruction in the pipelined process is not producing a result, it is used to indicate the structured temporary archive 134 register by the source operand tag 214, and then the operation element It exists and is effective as it will be provided by the structured temporary archive 134. If all of the sources indicated by the instruction are present and valid, then flow continues to decision block 412; otherwise the flow continues to block 4-8. In block 408, the early flag generation/control logic circuit 212 generates a true value on the pause signal 228 for the medium clock period before #= to be reached by the heart or written back to the structural temporary storage 134 Or suspend the instruction in the r stage by forwarding the sink = the source operand obtained. <Course continues from block 408 back to block 4-6. The decision block 412, the early flag generation/control logic circuit 212: the source operand tag 214 is compared with the lower pipe _^^ to determine one of the pipelined microprocessors 1 A result is intended to be used by the source operand tag = structured temporary archive 134 temporary store 11. #这, The results are not valid, but the results will exist in the early temporary storage slot 136. If an old instruction in the pipelined microprocessor 100 is not generated at 29 1273485, the system is scheduled to indicate the structured temporary 134 register by the source operand tag 214, and the flow continues to block 416; otherwise, the flow Following Yu Caitian 414. , Wang Wan block in block 414, the early flag generation/control logic circuit z 12 will generate a value on the control signal, so that the multiplexer 226 selects the Zhazishan +, μ a Wei error from the source The scratchpad source operand indicated by meta tag 214 is provided by store 136. If the early result 242 is generated in the a segment 112 of the same clock cycle, then the instruction reaches the R phase · ι 〇 8 and I ^ is required to source the Zeng Yuan, then the multiplexer 226 will select the early result 242 rounds Into the future: The operand is supplied to the instruction. The multiplexer 226 may be assigned an instruction by an early temporary storage unit to select a multiple temporary storage operation unit, which indicates a multiple temporary storage unit. Flow continues to block 418. # In block 416, the early flag generation/control logic circuit 212 generates a value on the select state control k number 282 to cause the multiplexer 226 to deselect the register indicated by the source transport element label 214. The source operand is provided by the structured temporary archive 134. In addition, the early flag generation/control logic circuit 212 controls the multiplexer 226 to select the non-storing operands indicated by the instructions, such as direct/fixed operands 222 or valid transfer operands, if any. Flow continues to block 418. In block 418, the instruction continues to stage A 112, in which stage early execution logic/address generator 138 produces an early result 242 from the source operand selected by multiplexer 226. In particular, one of the appropriate arithmetic logic circuit 272, Boolean logic circuit 274, or displacement logic circuit 30 1273485 276 will produce an early result 242 based on the command pattern thereon. Flow continues to decision block 422. In decision block 422, the early flag generation/control logic 212 detects the target operand tag of the instruction to determine if the early result 242 is intended to be a register in the structured temporary archive. If so, the flow continues to decision block 424; otherwise, the flow continues to block 434. In decision block 424, the early flag generation/control logic 212 detects the instruction type to determine if the instruction is of a type that can be executed by the early execution logic circuit/address generator 138. That is, assuming that the source operand is valid, the early flag generation/control logic 212 will determine if the instruction is within the subset of the instruction so that the early execution logic/address generator 138 produces the correct early results. If so, the flow continues to decision block 428, otherwise the process continues to block 426. In block 426, the early flag generation/control logic circuit 212 generates a false value from the early result valid signal 244 and does not generate one from the early execution logic/address generator 138 by the target operand tag 216 containing the false value. The instruction pattern of the valid early result 242 is updated to match the valid bit 218 of the early temporary archive 136 register. Flow continues to decision block 434. In decision block 428, since the early execution logic/address generator 138 produces a modified early result 242, the early flag generation/control logic circuit 212 determines whether all of the operands used to generate the early result 242 are valid. It is indicated that if the early flag generation/control logic circuit 212 determines in decision block 404 that the instruction does not need to be executed in phase a, then the instruction is not stored in R stage 1〇8 due to the lack of an operand. Therefore, even if one of the temporary operands is invalid from the early temporary broadcast 136 of 31 1273485, the command is not: stored in the R stage 108. Similarly, when the memory operand has not been loaded by the record, the instruction system will not be stored in the R stage 108. Similarly, the early execution logic/address generator 138 does not generate an effective early instruction type, and the instruction system is not stored in the r stage 1〇8. In contrast, early results 242 are marked as invalid in block 420, and the results of the repairs are evaluated in execution unit 146 of stage E 124. In contrast, if the field transport has not been obtained or is invalid, it must be executed in the A phase 112 (for example, to calculate one of the addresses and use the data cache in the d stage) In the R stage (10) towel. When all of the operands used to generate the early results 242 are valid, the flow continues to block 432; otherwise the flow continues to block 426. In block 432, the early flag generation/control logic circuit 212 generates a true value on the early valid signal 244 and is generated by block 418 by the target operand tag 216 containing the true value - an effective early result indication To update the valid bit 218 corresponding to the early temporary archive 136 register. At the same time, the early temporary archive 136 register indicated by the target operand 216 is validated by the early (four) 242. Flow _ to decision block 434 判断 In the decision block, the early flag generation/control logic will detect the command to determine if the command is a modified structural state register 162. The instruction to correct the status flag is instructed according to the & x86 structured instruction set. When the instruction corrects the contents of the status register (6), the flow continues to block 436; otherwise the flow ends. ° 32 1273485 In block 436, the early flag generation/control logic circuit 212 generates an early state register value 262 that is based on the early results 242 generated by the early execution logic circuit/address generator 138, and Instruction 206, and is updated by early state register value 262 to early state register 142. In one embodiment, a signed integer two-bit complement operation performed by the early execution logic/address generator 138 to produce an early result 242 results in an overflow condition (ie, the early result is too large or too small) Therefore, the early flag generation/control logic circuit 212 generates a true value for the overflow flag (OF), otherwise a false value is generated; early flag generation/ Control logic circuit 212 sets the positive and negative flag (SF) to the most significant bit value of early result 242; when the early result is zero, early flag generation/control logic 212 generates a true value for the zero flag Zero flag (ZF), otherwise a false value is generated; when the least significant digit of the early result 242 contains an even number of 1 bit, the early flag generation/control logic circuit 212 generates a true value for the flag Parity flag (PF), otherwise a false value is generated; when an unsigned integer operation performed by the early execution logic/address generator 138 results in an overflow condition (ie, the arithmetic operand produces a carry or is early Results 242 Borrow bit maximum), the early flag generation / control logic 212 generates a true value for carry flag (carry flag, CF), or will cause a false value. In one embodiment, to be precise, a complete status flag is generated for writing to the early state register 142, and the early flag generation/control logic 212 only updates the particular state that would be affected by the early result 242. Flag. In another embodiment, early flag generation/control logic 212 accumulates the status of the previous instruction 33 1273485 state flag until they are copied by structured state register 162, see Figure 5 and described below. Flow continues to decision block 438. In decision block 438, the early flag generation/control logic circuit 212 determines if the correction of the status flag is dependent on the result of the instruction. For example, in one embodiment, an instruction directly corrects a state register (eg, an x86 structured set STC, a CLC (clear carry), or a CMC (complent carry) instruction, and because, in addition to the status flag In addition to the correction instructions, the correction does not depend on the result of the instruction. When the state register is modified based on the result of the instruction, then flow continues to decision block 442; otherwise the process ends. In decision block 442, early flag generation/control logic 212 detects early result valid signal 244 to determine if early result 242 is valid. If the answer is yes, the process ends; otherwise the process continues to block 444. In block 444, the early flag generation/control logic circuit commits a value-value on the control + L 5 tiger 264 to update the early state valid register register value to refer to the early state temporary 142 Status flag status = two blocks 43 4 to block 444 operation to accumulate early 142 ", effective record": under invalid until the early state register, tir repair as shown in Figure 5 and as follows. The embodiment is because the direct correction state is temporarily crying ♦ & simplifies the early nucleus (four) ^ on the miscellaneous execution (in the flag — - refers to A is encountered, 丨 circuit 212), when the direct update - state please refer to Figure 5 As shown, the operation of the apparatus for reclamation is a flowchart of the present invention to illustrate that the early state register 142 is restored and valid. 34 !273485 : 5 includes two different flowcharts. Each flow chart is different. The touch of U and the effective condition 'to describe the recovery and validity of the early state register (4). The flow of the reference to the first case begins at block 5 〇 2. In block 502, a branch instruction arrives at stage S 126 When the branch ^ v needs to be corrected (ie when the branch predictor 132 mispredicts the branch finger) Regardless of whether the branch has an erroneous prediction or a branch target address error prediction, then the late branch correction logic circuit 148 will clear the pipelined microprocessor 100 in the over-rank of the modified error prediction, please refer to FIG. 7 and described below. The clear-line microprocessor 100 indicates that there is no structural state temporary memory correction instruction that exists in the pipeline phase under the R phase 108, or that any instruction in the pipeline that corrects the structural state register 162 has updated the structural state. The memory 162 has either been cleared. Therefore, the structured state register 162 includes the most recent state, which indicates that the branch instruction may be a branch instruction that may be a conditional or non-conditional type. In addition, the early state register 142 may Other events that cause the pipeline to be cleared are resumed in addition to the correction of the branch instruction. Flow continues to decision block 504. In decision block 504, early flag generation/control logic 212 detects branch correction late signal 268 to determine Whether the S phase 126 branch instruction is modified by the late branch correction logic circuit 148, thus indicating the pipeline type micro The processor 100 is cleared to generate a correction for the erroneous prediction, and if so, the flow continues to block 506; otherwise the flow ends. In block 506, the early flag generation/control logic 212 copies the structural state register 162. The value passes through the early state register value 262 to the early state register 142, and the early state 35 Ϊ 273 485 complaint register 142 is valid via the control signal 264, thus restoring the early state register i42 to the active state, Flow continues to block 506. Referring to the second scenario in Figure 5, the flow begins at block 512. In block 512, the early flag generation/control logic circuit 212 detects the flag correction command presence signal to move all structures. Whether the state correction instruction exists in the Α stage 112, if any, updates the structured state register 162, and if so, the flow continues to block 514; In block 514, the early flag generation/control logic circuit 212 copies the structural state register 162 via the early state register value 262: the value to the early state register 142 and is indicated via the control signal 264. The early sinusoidal temporary state 142 is valid, and therefore, the recovery of the early state temporary boundary 142 is an effective state. Flow ends at block 514. It indicates that the clearing of the pipelined microprocessor 100 is due to one of the branch corrections in the S phase 126 as determined in block 504, which is an event that creates a condition for block 512 to produce a determination. Referring to Figure 6, the operation of the pipelined micro-processing state 100 is illustrated in accordance with one of the flowcharts of the present invention to perform early branch correction, and the flow begins at block 602. "In block 602, a conditional branch instruction arrives at stage j 114, and the flow continues to decision block 604. In block 604, early branch correction logic 144 detects the output of early invalid register 246 to determine the early state. Whether crying is valid, if yes, the flow continues to block 606; otherwise, the process is bundled at 36 1273485. Therefore, when the early state register line is modified, the early conditional branch is corrected. If the σ 142 system is invalid, the device is not in compliance. The ::ear branch correction logic circuit 144 in the :::606 will detect the content of the early heart state temporary state 142 to determine whether the condition of the conditional branch instruction condition is not met. The flow continues to the decision block $卯.

In the decision block 608, the early branch correction logic circuit 144 determines YES = the block 606 is required to correct the prediction of the conditional branch instruction. The conditional branch instruction needs to be modified. When the condition is satisfied with the valid early state register 142, the conditional branch instruction should occur, and the branch predictor predicts that the branch should not occur (eg, the branch prediction signal 2〇8 is under the pipeline) The step ##114 version of one of the false values is indicated), which causes the pipelined microprocessor 1 to pick up the next consecutive instruction; conversely, when the condition is not satisfied with the valid early state register 142, the conditional branch instruction Need to be corrected, such as the conditional branch instruction should not occur, and the branch predictor 132 predicts that the branch should occur (as indicated by the branch prediction generation signal 2〇8 pipeline; the true value of the phase η4 version), which leads to the pipeline type micro The processor 1〇〇 transfers to the predicted branch target address. If the prediction of the modified conditional branch instruction is necessary, the flow continues to decision block 612; otherwise, the flow ends. In decision block 612, it has been determined that the conditional branch instruction needs to be corrected, and the early branch correction logic circuit 144 detects the sub-stage J stage 114 version of the branch prediction occurrence signal 2〇8 to determine whether the conditional branch instruction is predicted to occur, and if so, Flow continues to block 616 •, otherwise flow continues to block 614. 37 1273485 In block 614, the early branch correction logic circuit 144 instructs the I-stage 1〇2 to clear the pipelined microprocessor 100 located on the j-phase i14 and the branch-line microprocessor 1 to the conditional branch instruction via the first control signal 154. The branch target address, in one embodiment, the branch target address of the conditional branch instruction is generated by the early execution logic/address generation 138 in stage A. In addition, the early branch correction logic circuit 144 generates a true value at the early branch correction signal 258 transmitted by the official line to the late branch correction logic circuit 148, the use of which is described below with reference to Figure 7 and the flow ends at block 614. In block 616, the early branch correction logic circuit 144 instructs the I-phase 1〇2 to clear the pipelined microprocessor 100 located on the stage 114 via the first control signal 154, and the branch-line microprocessor 1 to the conditional branch instruction. The next - a continuous instruction. In addition, the early branch correction logic circuit 144 generates a true value at the early branch correction signal 258 transmitted by the official line to the late branch correction logic circuit 148, the use of which is described below with reference to Figure 7 and as follows, and the flow ends at block 616. Referring to Figure 7, the operation of the pipelined microprocessor 1GG is illustrated in accordance with one of the flowcharts of the present invention for late branch correction. The flow begins in block 702 方块 in block 702, a conditional branch instruction is directed to the S stage 126. Flow continues to block 704. In block 704, the late branch correction logic circuit detects the contents of the structured state register 162 to determine if the condition indicated by the condition code of the conditional branch instruction is valid. Flow (4) continues to decision block 7〇6. 38 1273485 In block 706, late branch correction logic 148 determines if = is to rely on block 704 to correct the prediction of the conditional branch instruction. Conditional branching = need to be corrected, when the condition is satisfied with the structure record (4) register (6), such as the conditional branch age (four) H❿ branch Lai ϋ 132 prediction branch should not occur (such as the branch prediction signal 2 〇 8 pipeline s phase version One of the false values is indicated), which causes the pipelined microprocessor 1 to remove: a continuous instruction; conversely, when the condition is not satisfied with the structural sorrow, the memory 162, the conditional branch instruction needs to be corrected. , as if the conditional branch instruction should not occur 'and the branch predictor 132 should branch (as indicated by the branch prediction, the instruction 2 〇8 pipeline s phase 丨26 version of the two true value indication)', resulting in a pipelined microprocessor 1〇〇 Transfer to the predicted branch j. If the prediction of the modified conditional branch instruction is necessary, the flow continues to determine block 708; otherwise the process ends. In decision block 708, the late branch correction logic circuit 148 checks 7 the early branch correction signal 2 58 to determine if the error pre-condition of the conditional branch instruction has been corrected by the early branch correction logic circuit 144, and if so, the flow ends; otherwise Flow continues to decision block 712. In decision block 712, it has been determined that the conditional branch instruction needs to be corrected, and the late branch correction logic circuit 148 detects the sub-stage S-stage 126 version of the branch prediction occurrence signal 2〇8 to determine whether the conditional branch instruction is predicted to occur, if The flow continues to block 716; otherwise the flow continues to block 714, where block 714 indicates that the late branch correction logic 148 instructs the I phase 102 to clear the pipelined 39 1273485 microprocessor loo on the S phase 126 via the first control signal 154. And branching the pipelined microprocessor 10 () to the branch target address of the conditional branch instruction. Flow ends at block 714. In block 716, late branch correction logic 148 instructs I stage 102 to clear pipelined microprocessor 100 on stage 126 via signal 154 and branch pipelined microprocessor 100 to the next consecutive instruction following the conditional branch instruction. Flow ends at block 716. As described above, the described pipelined microprocessor 1 has the ability to advance multiple clock cycles compared to microprocessors that do not have the advantages of early execution logic/address generator 138 and early temporary archive 136. The result of one of the previous instructions is used as a temporary operand to generate or generate a continuous address, thus reducing the number of pipeline bubbles incurred. Reducing the pipeline bubble reduces the average period of each instruction executed by the microprocessor. In addition, early results can be used to update status flags faster than previously, so it is possible to execute conditional instructions faster than previously. Moreover, the described pipelined microprocessor 100 is capable of correcting a erroneously predicted conditional branch instruction by an earlier plurality of clock cycles than a microprocessor without the advantages provided by the early branch correction logic circuit 144. Finally, the demand for high-clock-frequency microprocessors has led micro-processor designers to increase pipelines. The number of pipeline stages increases, and the number of pipeline bubbles results in an increase in the waiting command result and/or status flag update. Similarly, as the number of pipeline stages increases, the delay in correcting the mispredicted branch instruction may also increase. These facts add to the advantages of the microprocessors, devices, and methods described herein. 1273485 While the invention and its objects, features and advantages have been described in detail, any embodiments that do not depart from the spirit and scope of the invention should be included, for example, although one of the microprocessor embodiments described is generally The x86 architecture conforms to 'but the devices and methods described are not limited to x86 architectures and can be used with different microprocessor architectures. Additionally, while one of the described embodiments is modified early, one of the advantages of the early generation status flag can be utilized to execute other instructions early, as in the case of the L00PCC instruction, as described herein. The advantages also occur with Jcc instructions; or x86 SETcc and CMOVcc instructions can be executed early, so the results can be used by subsequent instructions. In addition, in addition to using early results to generate early state flag values, early results can also be used to perform early branch corrections, usually referred to as jump thr〇ugh orders, which indicate that the branch target address is a source. Store the operand value. Moreover, in addition to implementing the invention by hardware, the invention can be implemented in a computer readable code (eg, computer readable code, data, etc.) stored in a computer usable (eg, readable) medium, resulting in a computer code The utility or construction of the invention or both are implemented. For example, it can be implemented by using a general programming language (e.g., C language, C++ language, JAVA, and the like); GDSII database; hardware description language (HDL) includes

VerilogHDL'VHDL, Altera HDL (AHDL), etc.; or other programming and/or circuitry (i.e., pictorial) capture tools available in the art. The computer code can be set to any available computer (eg, readable) media including half-body memory, disk, optical disk (eg cd_r〇m, DVD-ROM and other similar media), and as a usable transmission medium (Example 1273485, such as a carrier or any other medium including digital, optical or analog media) stores (for example, readable) computer data signals in a computer. As a result, computer code can be transmitted over the communications network, including the Internet and the internal network. Thus, it can be appreciated that the present invention can be embodied in computer code (eg, as part of an IP (Intellectual Property) core, like a microprocessor core, or as a system hierarchy design, like a system chip (SOC) and converted to hardware As a part of the overall circuit production, the present invention can be embodied as a combination of a hardware and a computer program. Finally, those skilled in the art can immediately use the concept disclosed by the present invention as well as specific embodiments as a design or The basis of the other structures is modified to achieve the same objectives as the present invention, and the spirit and scope of the present invention are defined by the scope of the appended claims. FIG. 1 is a view showing one of the present invention. FIG. 2 is a block diagram showing one of the R phase, the A phase, and the J phase of the pipeline microprocessor of FIG. 1 according to the present invention; FIG. 3 is a diagram showing FIG. 1 and FIG. 2 block diagram of structural temporary archive, early temporary archive, structured state register and early state register; Figure 4 shows FIG. 2 is a flow chart showing the operation of one of the early results and the early state register of the present invention; FIG. 5 is a flow chart showing the operation of recovering and confirming the early state 42 1273485 state register of the device of FIG. 2 according to the present invention; 6 is a flow chart showing the operation of the early branch correction operation of the pipeline type microprocessor according to the present invention; and FIG. 7 is a flow chart showing the operation of the microprocessor performing the late branch correction according to the present invention. 〇 Component symbol description: 100 Pipeline type micro processing 102 I Phase 104 F Phase 106 X Phase 108 R Phase 112 Phase A 114 J Phase 116 D Phase 118 G Phase 122 Η Phase 124 Ε Phase 126 S Phase 128 W Phase 132 Branch Predictor 134 Structured Temporary 136 Early Stage Archive 138 Early Execution Logic/Address Generator 43 1273485 142 Early State Register 144 Early Branch Correction Logic 146 Execution Unit 148 Late Branch Correction Logic 152 Early Result Bus 154 First Control Signal 156 Second Control Signal 158 Result Bus 162 Structured State Register 202 Flag Correction Instruction Existence Letter No. 204 destination tag 206 instruction 208 branch prediction generation signal 212 early flag generation/control logic circuit 214 source operand tag 216 target operand tag 218 valid bit 222 direct/fixed operand 226 multiplexer 228 pause signal 232, 234 Pipeline Register 236 Valid Bit Pipeline Register 238 Source Operation Element Pipeline Register 242 Early Results 44 1273485 244 Early Result Valid Signal 246 Early State Valid Scratchpad 248~252 Pipeline Register 254 Early Result Pipeline Staging 258 Early branch correction signal 262 Early state register value 264 Control signal 266 Memory operand signal 268 Branch correction late signal 272 Arithmetic logic circuit 274 Boolean logic circuit 276 Displacement logic circuit 278 Target operand tag 282 Selector control signal 402~444 Early results and early flag operation flow 502~514 Early flag recovery operation flow 602~616 Early branch correction process 702~716 Late branch correction process 45

Claims (1)

1273485 X. The scope of application for patents··1; the device of the type and state flag, the system--has to be able to be; the period: V, the standard of the pipeline-type microprocessor refers to the early execution of the device, the device Contains ·· Stores 7L pieces, which is used to accumulate at least one early status flag corresponding to the target, and Γ a logic circuit, which is connected with the basis before the conditional instruction, new_save In the early state flags, the =u corrects at least one of the early state flags, so that one of the two states is invalid. Then the logic circuit system: the flag is invalid. If the early state flags r, 旌ί are used, the pipeline type micro-processing 11 updates the structural formulas 2, and the conditional "execution" is enabled according to the early state flags. The final result of the previous instruction. 2 2 The device described in item i of the patent scope is used to generate the early device, and further includes: a phase-stage of the microprocessor pipeline, wherein the logic generates a status flag; The second stage of one of the official lines, which is used to The structural slogan flag, wherein, in the pipeline microprocessor, the first stage is earlier than the second stage. Μ 46 1273485 = the first aspect of the patent scope is used to generate an early state. A flagged device, wherein the early state flags include one or more state flags of an X86 structured state register. As described in claim 1, the early state flag is used to generate an early state flag. The #early results include the result of the instruction consisting of a subset of the instructions of one of the pipelined microprocessors. The fourth is used to generate the early state flag device. The sub-set includes an instruction to perform a simple arithmetic operation. 6 , :: Please use the instruction described in item 4 of the patent scope to generate an early status flag, wherein the instruction subset includes an instruction to execute the instruction. ΓΓ = used to generate the early state flag as described in item 4;: Operation::::: Subset 嶋^ 8, =τ=ι is used to generate the early state flag structure The second command subset contains the general purpose of updating the Conditional code indicating the condition of the knot. The condition is determined by the conditional branch instruction. 47 1273485 9. The apparatus for generating an early status flag as described in claim 4 of the patent application, wherein the early results are generated in the pipeline. The execution unit of the microprocessor executes the instructions to generate the final result of the instructions. 10. The apparatus for generating an early status flag as described in claim 1 of the patent application, further comprising: an early execution logic circuit Connected to the logic circuit for generating the early results of the prior instructions. 11. The apparatus for generating an early status flag according to claim 10, wherein the instruction indicates Performing the operations performed by the logic circuit early and validating all of the input operation elements of the early execution logic circuit used to generate the early results to correct the early results of the early state flags It is valid. 12. Apparatus for generating an early status flag as described in claim 10, wherein the early execution logic is executed during an address generation phase of the pipelined microprocessor. 13. The apparatus for generating an early status flag as recited in claim 10, wherein the early execution logic is executed in a particular phase of the pipelined microprocessor, the specific phase being immediately adjacent to 48 1273485 The pipelined microprocessor is staged after the stage of the structured archiving of the pipelined microprocessor. 14. The apparatus for generating an early status flag according to claim 10, further comprising: an early register for storing an early temporary archive connected to the early execution logic circuit, The early register has a plurality of registers, and the registers correspond to at least one register of the structured temporary archive of the pipelined microprocessor, wherein the early temporary archives and the corresponding temporary registers are Selectively effective. 15. The apparatus for generating an early status flag as described in claim 14 wherein one of the registers provides an input operand to the early execution logic to generate the early stage. The state flag at least one of the early results of one of the instructions, and the input operand is invalid, the logic circuit invalidates the early state flags. 16. The apparatus for generating an early status flag according to claim 10, wherein the early execution logic circuit is configured to execute a subset of instructions executable by the pipelined microprocessor, wherein at least the If one of the instructions to modify the early status flag does not belong to the subset of instructions, and the input operand is invalid, the logic circuit invalidates the early status flag. 49 I273485 17, 18, 19, 20 21 The apparatus for generating an early status flag as described in claim 1 wherein the pipelined microprocessor is a scalar microprocessor. The apparatus for generating an early status flag as described in claim 1 wherein the pipelined microprocessor issues instructions in a program sequence. A device for generating an early status flag as described in claim 1 wherein the storage element is not indicated by a program instruction. A device for generating an early status flag as described in claim 1, wherein the computer program product comprises a computer usable medium having a computer readable code for causing the computer to implement the device, wherein the computer The program product is used in conjunction with a computing device to form the device. The device for generating an early status flag is described in the patent specification (4), wherein one of the computer data signals recorded in a communication medium includes a readable computer code to enable the computer to implement the device. A type of official line microprocessor having a non-selective (invalid) valid structural state flag, and the instruction set includes a conditional instruction indicating a 50 22 1273485 piece and an operation, wherein Condition, the pipelined microprocessor performs the operation, comprising: at least one early status flag corresponding to the status flags stored in the structural register, wherein the early status flag is selective And an early execution logic circuit coupled to receive the early states, flags, if the early state flags are valid, and if a condition indicated by the conditional instruction is satisfied The early state flag, the early execution logic circuit performs one of the operations indicated by a conditional instruction. 23. The pipelined microprocessor of claim 22, further comprising: a final execution logic circuit coupled to receive the structural state flags, if the condition is satisfied with the structural states The flag is executed and the early execution logic circuit does not perform the operation, and the final 0-line logic circuit performs the operation. 24. The pipelined microprocessor of claim 22, further comprising: a logic circuit that instructs the previous one of the previous instructions to generate the early status flags in accordance with the condition, wherein the prior instruction is Indicates the correction of these structural status flags. 51 1273485 25. The pipelined microprocessor of claim 24, further comprising: an early scratchpad for storing an early temporary archive, which is effectively linked to the logic circuit, the early temporary archive There are a plurality of scratchpads corresponding to one of the pipelined microprocessors, and the temporary temporary archives are selectively valid. 26. The pipelined microprocessor of claim 25, wherein the prior instruction indicates at least one input operand from the structural temporary archive, wherein the logic circuit is based on a result of one of the previous instructions to generate the The early status flag, the result of the previous instruction is generated based on the input operand provided by the early temporary archive rather than being temporarily archived according to the structure. 27. The pipelined microprocessor of claim 26, wherein the early state flag is invalid if the operand provided by the early temporary archive is invalid. 28. The pipelined microprocessor of claim 24, wherein the early status flag is invalid if the input operand to the previous instruction is invalid. 29. The pipelined microprocessor of claim 24, wherein 52 1273485 comprises: an early execution logic circuit coupled to the logic circuit, the early execution logic circuit executing a pipeline microprocessor A subset of instructions executed, wherein the early state flag is invalid if the previous instruction is not in the subset of instructions. 30. The pipeline microprocessor of claim 22, wherein the pipeline microprocessor is a scalar microprocessor. 31. The pipelined microprocessor of claim 22, wherein the pipelined microprocessor issues the instructions in accordance with a program command. 32. The pipelined microprocessor of claim 22, wherein the early execution logic circuit is implemented in an address generation phase of the pipelined microprocessor. 33. A method of generating a status flag early in a pipelined microprocessor for initiating an early execution of an instruction that is conditionally executed in accordance with a condition of the status flag indicated by the instruction An operation, the method comprising: instructing a previous instruction to generate a first request of the status flag according to the condition, wherein the first request may be invalid; after generating the first request, generating the first request according to the previous instruction a second request of the status flag, wherein the second request is always valid; 53 1273485 and when the condition is satisfied by the first request of the status flag and the first request is valid, then The operation is performed before the second request is generated. 34. The method as claimed in claim 33, wherein the pipelined microprocessor generates a status flag early, further comprising: updating a structural register to store the status flag after generating the second request. 35. The method for generating a status flag early in a pipelined microprocessor as described in claim 33, further comprising: generating a result of the previous instruction before generating the first request; determining the result of the previous instruction. Whether it is valid; and invalidating the first request when the result is invalid. 36. The method of generating a status flag early in a pipelined microprocessor as described in claim 35, wherein the step of determining whether the result of the previous instruction is valid comprises: determining whether the result of the previous instruction is utilized A valid input operand is generated; and when the input operand is invalid, the result is invalid. 37. A method for generating a status flag in a pipelined microprocessor as described in claim 35, wherein the step of determining whether the result of the previous instruction is valid comprises: determining whether the previous instruction is An early execution logic of the pipelined microprocessor can execute one of the instructions; and when the previous instruction is not one of the instructions of the early execution logic, the result is invalid. 38. A method of generating a status flag early in a pipelined microprocessor as described in claim 37, wherein the early execution logic circuit generates the result before an execution unit of the pipelined microprocessor generates a valid request. . 39. The method for generating a status flag early in a pipelined microprocessor as described in claim 35, further comprising: determining whether the previous instruction corrects the status flag; and only correcting the status flag when the previous instruction The first request invalidates the first request. 40. The method of generating a status flag early in a pipelined microprocessor as described in claim 33, wherein the step of generating the first request does not need to be suspended, regardless of whether the input operand for the previous instruction is valid. The pipelined microprocessor pipeline. 41. The method of generating a status flag in a pipeline microprocessor as described in item 33 of the patent application, in the pipeline, the method further comprising: determining whether the pipeline type microprocessor pipeline is cleaned; and when the pipeline microprocessor system When cleaned, the structural state flag is copied to the first request of the status flag and the first request for the status flag is validated. 42. The method for generating a status flag early in a pipelined microprocessor as described in claim 33, further comprising: determining whether a phase corresponding to the pipelined microprocessor pipeline is generated after the stage of generating the first request All state flag correction instructions have updated the structural state flags of the pipelined microprocessor; and if the state flag correction instructions have updated the structural state flag of the pipelined microprocessor, then copy The structured status flag is flagged to the first request of the status flag and the first request of the status flag is marked as valid. 43. A computer data signal stored on a transmission medium, comprising: a computer readable code, which causes a computer to provide a device to generate the early status flags, thereby enabling activation of a structured An early execution of a conditional instruction in a pipelined microprocessor of a status flag, the readable readable code comprising: a first code that causes the computer to provide a storage component, the storage component being Accumulating at least one early status flag corresponding to the structural state flag 56 1273485; and a second code that causes the computer to provide a logic circuit that connects the storage element and instructs the previous condition based on the condition An early result of the instruction to update the early status flag in the storage element, wherein the logic circuit renders at least one of the early results of the instruction to correct the early status flag invalidated The early status flag is invalid, the logic circuit is enabled, and if the early status flag is valid, the execution of the conditional instruction is based on the early state. A flag, the early status flag is updated earlier than the pipelined microprocessor updates the structural status flag based on the final result produced by the previous instruction. 57