1272849 A7 __ B7 五、發明説明（彳) 【發明所屬之技術領域】 (請先閲讀背面之注意事項再填寫本頁) 本發明係關於解碼裝置及解碼方法、以及記錄媒體，特 別是關於可以實現對應以可以實現之電路規模能夠實際時 間動作之4 : 2 : 2P @ HL之視頻解碼器之解碼裝置及解碼方法 、以及記錄媒體。 【習知技術】 MPEG2(M〇ving Picture Coding Experts Group / Moving Picture Experts Group2)錄像器係由：IS〇/IEC(International Standards Organization/International Electrotechnical1272849 A7 __ B7 V. INSTRUCTION DESCRIPTION (彳) [Technical field to which the invention pertains] (Please read the note on the back side and then fill out this page.) The present invention relates to a decoding device, a decoding method, and a recording medium, and in particular, Corresponding to a decoding device, a decoding method, and a recording medium of a 4:2: 2P @HL video decoder capable of realizing time operation at a circuit scale that can be realized. [Prior Art] MPEG2 (M〇ving Picture Coding Experts Group / Moving Picture Experts Group 2) recorder is: IS〇/IEC (International Standards Organization/International Electrotechnical)
Commission) 13818-2 、 以 及 ITU-T(InternationalCommission) 13818-2, and ITU-T (International
Telecommunication Union-Telecommunication sector)勸告 H. 262所規定之視頻信號之高效率編碼方式。 經濟部智慧財產局員工消費合作社印製 MPEG2之編碼流（coding stream)係由藉由編碼手法而決 定之外形（profile)，以及由處理之像素數而決定之級數（level) 而被分級，可以對應廣範圍之應用。例如，MP@ML(主.外形. 主.級數）係該等級之1種，被廣泛實用化於DVB (Digital Video Groadc as t)或 DVD (Digital Versatile Disk)。外形以及級數係 被敘述在利用圖5之後敘述之seqence_extension。 又，在廣播局之視頻信號之製作上，以與習知之基頻同樣 之4:2:2方式處理視頻之色差信號，增加位元率之上限之 4··2··2Ρ(4:2··2外形）被規定著。進而，爲了對應次世代之高解 析度視頻信號，HL(高級數）被規定著。 圖1係顯示MPEG2之代表等級與個個等級之各種參數 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） / 1272849 A7 ___ B7 五、發明説明（2 ) (請先閲讀背面之注意事項再填寫本頁) 之上限値。圖1中係就：4:2:2P@ML(4:2:2外形.高級數）、 4:2:2P@ML(4:2:2外形·主級數）、MP @ HL(主.外形.主.級數） 、MP@HL-1440(主·外形·高.級數-1440)、MP@ML(主.外形. 主·級數）、MP@LL(主·外形·低·級數）、以及SP@ML(簡單.外 形·主.級數），分別顯不：位元率、每1行之取樣數、每一訊框 之行數、訊框頻率、以及樣本之處理時間之上限値。 由圖1，4:2:2P@HL之位元率之上限値爲300(Mbit/sec:百 萬位元/秒），處理之.像素數之上限値爲 62,668,800(821!^168/86(：:樣本/秒）。另一方面，]^?@]\/1?之位元 率之上限値爲15(Mbit/SeC)，處理之像素數之上限値爲 1 0,3 68,000(samples/sec)。SP，了解到：解碼 4:2:2P@HL 之視頻 解碼器與解碼MP@ML之視頻解碼器比較，需要位元率20倍 、處理像素數約6倍之處理能力。 經濟部智慧財產局員工消費合作社印製 圖2係顯示MPEG2視頻位元流之級數構造。 sequence_header被記述於最上位層之畫像層之最初。 sequence_header係定義MPEG位元流之順序之頭部資料者。 在順序最初之 sequence_header 沒有接續 sequence_extension 之情形，IS0/IEC1 1172-2之規定被適應於此位元流。在順序 之最初之 sequence_header 有接續 sequence — extension 之情开多， 在此後發生之全部的sequence_header之後都接續 sequence_extension 。即，於圖2所示之情形，在全部之 sequence_header 之後，都接續 sequence_extension。 sequence_extension係定義MPEG位元流之順序層之擴 張資料者。sequence_extension 只在 sequence_header 之後發 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 五、發明説明（3 ) 生，而且，爲了解碼後，以及訊框重整後，不要有訊框之損失，不 可以在位於位元流之最後之sequence_end_code之前。又，在 位元流中發生 seQuence_extension之情形，在個別之 picture一header 之後接續 picture — cording — sequence ° 複數之畫像（picture)被包含在G〇P(group_of _picture)。 G〇P_headei·係定義MPEG位元流之GOP層之頭部資料者，進 而，在此位元流中記述有藉由 picture_header與 picture_cording_extension所定義之資料元件。1張之畫像作 爲 picture_header 以及接續方令 picture_cording_extension 之 p i c t u r e _ d a t a被編碼。又，接續於G〇P _ h e a d e r之最初的編碼 訊框係被編碼之I訊框（即，G〇P_header之最初之畫像爲I畫 像）。在 ITU-T 勸告 H.262 在 sequence_extension 以及 picture_cording_extension之外，定義各種之擴張，此處，省略 圖示以及說明。 picture_header係定義MPEG位元流之畫像層之頭部資 料者，picture_cording_extension係定義MPEG位元流之畫像 層之擴張資料者。 picture_data係記述MPEG位元流之切片層以及大區塊 層之資料元件者。picture_data如圖2所示般地，係被分割爲 複數之slice(切片），切片被分割爲複 婁女之 macro — block(大區 塊）。 macro_block係以16x16之像素資料所構成。切片之最 初的大區塊以及最後之大區塊並非跳過大區塊（不含資訊之 大區塊）。大區塊係以16x16之像素資料構成。又，各區塊係 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 適 尺 張 -紙 本 一準 一標 I家 國 I國 ¾ -釐 公 1272849 A7 _— ___ B7 五、發明説明（4 ) (請先閲讀背面之注意事項再填寫本頁) 以8x8之像素資料構成。又，訊框DCT(Discrete Cosine 1]^1^£0]：111:離散餘弦轉換）編碼以及區域0(：丁編碼之使用爲 可能之訊框畫像中，在訊框編碼與區域編碼之情形，大區塊之 內部構成不同。 大區塊包含亮度成分以及色差成分之1區分。所謂大 區塊之用語係顯示資訊源以及解碼資料或對應之編碼資料 成分之其一。大區塊有：4:2:0、4:2:2以及4:4:4之3種色差 格式。大區塊之區塊的順序係依個別之色差格式而不同。 圖3(A)係顯示4:2:0方式之情形的大區塊。在4:2:0方 式之情形，大區塊係由4個之亮度（Y)區塊以及個別1個之色 差（Cb、C〇區塊構成。圖3(B)係顯示4:2:2方式之情形的大 區塊。在4:2:2方式之情形，大區塊係由4個之亮度（Y)區塊 以及個別2個之色差（Cb、Ci·)區塊構成。 經濟部智慧財產局員工消費合作社印製 各大區塊藉由幾種方法可以預測編碼處理。預測模式 被大別爲區域預測與訊框預測之2種。於區域預測中，使用 先被解碼之1個或複數之區域的資料，於各區域中，獨自進行 預測。訊框預測係使用先被解碼之1個或複數之訊框，進行 預測之預測。在區域畫像內，預測全部爲區域預測。另一方 面，在訊框畫像中，可以藉由區域預測或訊框預測之其一而進 行預測，該預測方法依每一大區塊而被選擇。又，大區塊之預 測編碼處理中，在區域預測以及訊框預測之外，也可以使用 16x8動作補償以及雙主要（dual pnme)之2種的特別預測模 式。 動作向量資訊以及其它之周邊資訊與各大區塊之預測 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一7 一 1272849 A7 B7 五、發明説明（5 ) (請先閲讀背面之注意事項再填寫本頁) 誤差信號一齊被編碼。關於動作向量之編碼，係將使用可變 長度編碼被編碼之最後的動作向量當成預測向量，編碼與預 測向量之差向量。可以表示之向量的最大長度可以每一畫 像進行編程（program)。又，適當之動作向量之計算係編碼器 所進行。 而且，在 picture — data 之後，配置：seqUence_header 與 sequence.extension 。 藉由此 sequence—header 與 sequence_extension被記述之資料元件與藉由被記述在視頻 流之順序之 Βϋί而的 sequence — header 與 sequence_extension 而 被記述之資料元件完全相同。如此在流（stream)中記述相同 資料之理由係爲了防止：在位元流接收裝置側，由資料流之中 途（例如，對應於畫像層之位元流部份）開始接收之情形，變成 無法接收順序層之資料，無法解碼流之故。 在藉由最後之 sequence_header 與 sequence_extension Μ 被定義之資料元件之後，即在資料流之最後，記述有顯示順序 之終了之 32 位元之 sequence__end_code 〇 接著，利用圖4至12,說明個別之資料元件之詳細。 經濟部智慧財產局員工消費合作社印製 圖4係顯示sequence_header之資料構成。被包含在 sequence_header 之資料元件係由：sequence_header — code 、 horizontal_size_value 、 vertical_size_value 、 aspect_ratio_information、 frame —rate —code 、 bit —rate_value 、 marker_bit 、 vbv —buffer_size_value 、 constrained_parameter_flag 、 load_intra_quantiser_matrix 、 in tr a —quantiser一matrix 、 load_non一intra 一 quantiser 一 matrix 、 本紙張尺度適用中國國家標準（CNS ) A4規格（21 OX 297公釐） 1272849 A7 ___^_ B7 _ 五、發明説明（6 ) 以及 non-intra — quantiser-matrix 等戶斤構成。 (請先閱讀背面之注意事項再填寫本頁) sequence_header_code係表示順序層之開始同步碼之資 料。honzontal_size_value係由畫像之水平方向之像素數之 下位12位元所形成之資料。vertical_size_value係由畫像之 縱的行數之下位 12 位元所形成之資料。 acpect —ratio_information係表示像素之長寬比（縱橫比）或顯 示畫面長寬比之資料。frame_rate_c〇de係表示畫像之顯示 週期之資料。bit_rate_value係對於發生位元量之限制用之 位元率之下位1 8位元之資料。 而且，marker_Mt係爲了防止開始碼模擬而被插入之位 元資料。vbv_buffer_size_value係決定發生編碼量控制用之 虛擬緩衝器VBV(Video Buffering VenfieO之大小値之下位 10位元資料。constrained_parameter_flag係顯示各參數在限 制以內之資料。load_non_intra_quantiser_matrix係顯示非內 部MB用量子化矩陣資料之存在之資料。 經濟部智慧財產局員工消費合作社印製 load_intra_quantiser_matrix係顯示內部MB用量子化矩 陣資料之存在之資料。intra_quantiser_matrix係顯不內部 MB用量子化矩陣之値之資料。non__intra_quantiser_matrix 係顯示非內部MB用量子化矩陣之値之資料。 圖 5 係顯示 sequence_extension 之資料構成。 sequence_extension 係由：extension_start_code、 extension_start_code_identifier、 profile_and_level_indication、 progressive — sequence、 chroma_format、 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ " 1272849 A7 ____ B7 _ 五、發明説明（7 ) horizontal —si ze_extension 、 vertical_size_extension 、 (請先閱讀背面之注意事項再填寫本頁) bit一rate_extension 、 marker—bit 、 vbv_buffer_size_extension 、low_delay、frame_rate__extension_n、以及 frame_rate_extension_d等資料元件所構成。 extension_start_code係表示擴張資料之開始同步碼之 資料。extension_start_code —identifier係表示哪個擴張資料 被傳送之資料。profile_and_level_indication係指定視頻資 料之外形與級數用之資料。progressive_sequence係表示視 頻資料爲依序掃描（漸進畫像）之資料。chromajormat係 指定視 頻 資料 之 色 差 格 式 用 之 資 料 〇 horizontal. _size_ 一extension 係 加 在 順 序 頭 部 之 horizontal. —size· _γ alue 之 上 位 2 位 元 之 資 料 〇 vertical_size_extension 係 加 在 順 序 頭 部 之 vertical_size_value之上位2位元之資料。 經濟部智慧財產局員工消費合作社印製 而且，b i t _ r a t e _ e X t e n s i ο η 係力□在順序頭部之 bit_rate_value之上位12位元之資料。marker_bit係防止開 始碼模擬而被插入之位元資料。vbv_buffer_size_extension 係加在順序頭部之vbv_buffer_size_value之上位8位元之資 料。l〇w_delay係顯示不包含B畫像之資料。 frame_rate_extension_n 係 與 順 序 頭 部 之 frame_rate_code 組合以獲得訊框率用之資料。 frame — rate_extension_d 係與順序頭部之 frame —rate_code 組 合以獲得訊框率用之資料。 圖6係顯示GOP-header之資料構成。表示GOP-header 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -10- 經濟部智慧財產局員工消費合作社印製 1272849 A7 _ B7 _ 五、發明説明（8 ) 之資料元件係由：group_start_code、time_code、closed_gop 、以及broken_link所構成。 group_start_code係顯示GOP層之開始同步碼之貧料。 time_code係表示G〇P之前端畫像之時間之時間碼。 closed_gop係表不GOP內之畫像可由其它之GOP獨1再生 之旗標資料。broken Jink係爲了編輯等用，表示GOP內之前 端的B畫像無法正確再生之旗標資料。 圖 7係顯示 picture_header之資料構成。關於 picture_header 之資料元件係由：picture_start_code 、 temporal_ref erence 、 picture —cording_type 、 vb v_delay 、 full_pel_forward_vector 、 forward_f_code 、 full_pel_backward_vector、以及 backward code 等所構成 . 〇 · picture_start_code係表示畫像層之開始同步碼之資料 。temporal_reference係表示畫像之顯示順序之資料，在G〇P 之前端被重置之資料。picture_cording_type係表示畫像形 式之資料。vbv_delay係表示隨機存取時之虛擬緩衝器之初 其月狀態之資料。 full_pel_forward_vector 、 forward_f_code 、 full_pel_backward_vector 、以及 backward_f_code 係在 MPEG2中未被使用之固定資料。 圖8係顯示picture_cording_extension之資料構成。 picture_cording_extension 係由 :extension_start_code 、 extension_start_code_identifier、f_code [0] [0]、f_code [0] [ 1 ] 、f_code[l][0] 、 f_code[1][1] 、 intra一dc_precision 、 i紙張尺度適财關家標準（CNS ) A4規格（21GX297公釐) ~ (請先閱讀背面之注意事項再填寫本頁) 1272849 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（9 ) picture — structure 、 top_field — first 、 frame 一 pred一frame_dct 、 concealment —motion一vectors 、 q —scale —type 、 intra_vlc_f ormat 、 alternate — scan 、 repeat —firt —field 、 chroma_420 —type、progressive_frame、 composite一display —flag 、 v — axis 、 field —sequence 、 sub_carrier、burst_amplitude、以及 sub_carrier_phase 等戶斤 構成。 extension_start_code係表示畫像層之擴張資料之開始 之開始碼。extension_start_code_identifier係顯示哪個之擴 張資料被傳送之碼。f_code[0][0]係表示前進方向之水平動 作向量探索範圍之資料。f_code[0][l]係表示前進方向之垂 直動作向量探索範圍之資料。f_c〇de[l][0]係表示往後方向 之水平動作向量探索範圍之資料。f_code[l][l]係表示往後 方向之垂直動作向量探索範圍之資料。 intra_dc_precision係表示DC係數之精度之資料。在表 示區塊內之各像素之亮度以及色差信號之行列f如施以 DCT,可以獲得8x8之DCT係數行列F。將此行列F之左上角 落之係數稱爲DC係數。DC係數係表示區塊內之平均亮度 、平均色差之信號。picture_structure係表示爲訊框結構或 區域結搆之資料。在區域結構之情形，也一倂顯示爲上位區 域或下位區域之資料。top_field_first係表示在訊框結構之 情形，最初之區域爲上位或下位之資料。 frame_predictive_frame_dct係表示在訊框結構之情形，訊框 模式 DCT 之預測只爲訊框模式之資料。 本^張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " I ^^ 着衣" """"訂 ί"丨L~~Φ (請先閲讀背面之注意事項再填寫本頁) 1272849 A7 B7 五、發明説明（10 ) concealment_motion_vectoi:s係表示隱蔽傳送錯誤用之動作 向量附於內部大區塊之資料。 (請先閲讀背面之注意事項再填寫本頁) q_scale_type係表示利用線性量子化尺度或利用非線性 重子化尺度之資料。intra_vlc_format係表示在內部大區塊 是否使用別的2次兀VLC(Variable Length Cording)之資料。 alternate」can係表示使用鋸齒掃描或交錯掃描之選擇。 repeat_firt_field係被使用於2:3下拉之際之資料。 chroma_420_type係表示在信號格式爲4:2:0之情形，與下一 progressive_frame爲相同之値，在非如此之情形，爲〇之資料 。progressive_frame係表示此畫像爲依序掃描或交錯區域 之資料。composhejisplayjlag係表示來源信號是否爲合 成信號之資料。 v_axi s 、 field_sequence 、 sub_carrier 、 burst —amplitude、以及 sub_carrier_phase 係被使用於來源信 號爲合成信號之情形的資料。 經濟部智慧財產局員工消費合作社印製 圖9係顯示picture_data之資料構成。由picture_data() 函數所定義之資料元件係由SUce()函數所定義之資料元件 。藉由此slice()函數所定義之資料元件在位元流中至少1個 被記述。 slice()函數如圖10所示般地，係藉由：slice_start_code、 quantiser_scale_code 、 intra_slice_flag 、 intra — slice 、 reserved_bits 、 extra_bit —slice 、 以及 extra_information_slice 等之資料元件以及 macroblockO函數 所定義。 slice_start_code係表示藉由slice()函數被定之資料兀 -13- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（11 ) 件之開始之開始碼。quantiser_scale_code係表示對於存在 於此切片層之大區塊而被設定之量子化部階大小之資料，在 每一大區塊被設定quantiser_scale_code之情形，對於各大區 塊被設定之macroblock_quantiser_scale_code之資料優先被 使用。 intra_slice_flag係表示在位元流中是否存在intra_slice 以及reserved_bits之旗標◦ intra_slice係表示在切片層中是 否存在非內部大區塊之資料。在切片層之大區塊之其一爲 非內部大區塊之情形，intra_slice成爲「0」，切片層之大區 塊之全部爲非內部大區塊之情形，intra_slice成爲「1」。 reserved_bits係 7位元之資料，取用「 0」之値。 extra_bit_slice係表示追加之資訊存在之旗標，在之後存在 extra__information_slice之情形，被設定爲「1」，在沒有追加 之資訊存在之情形，被設定爲「0」。 在這些資料元件之後，記述藉由macroblockO函數所定 義之資料元件。macroblock()函數係如圖11所示般地，記述 藉由：macroblock_escape 、 macroblock_address_increment 、 以及 quantiser_scale_code、以及 marker_bit 等之資料元件， 以及 macroblock_modes()函數、motion_vectors(s)函數、以 及〇〇(16(1_131〇〇1：_0 3价]：11()函數被定義之資料元件用之函婁女。 macroblock_escape係表示參考大區塊與前一大區塊之 水平方向之差是否在34以上之固定位元列。在參考大區塊 與前一大區塊之水平方向之差爲34以上之情形，33被加在 macroblock_address_increment ^ fit 〇 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 經濟部智慧財產局員工消費合作社印製 A7 ___ B7五、發明説明（12 ) macroblock_address_increment係表示參考大區塊與前 一大區塊之水平方向之差的資料。假如，在 macroblock_address —increment 之前 ， 存 在一個 macroblock_escape，在 It匕 macroblock_address_increment 之値 加上33之値變成顯示實際的參考大區塊與前一大區塊之水 平方向之差。 quantiser_scale_code係表示被設定在各區塊之量子化 部階大小之資料，只在macroblock__quant爲「1」時存在。 在各切片層係顯示切片層之量子化步階大小。 slice_quantiser_scale_c〇de雖被設定，但是對於參考大區 塊，scale_C〇de .被設定之情形，選擇此量子化步階大小。 在 macroblock_address一increment 之後，言己述藉由 macroblock_modes()函數所定義之資料元件。 macroblock_modes()函數係如圖 12所示般地，記述 :macroblock_type 、 frame — motion_type 、 field_motion_type 、dct_type等之資料元件用之函數。macroblock_type係表 示大區塊之編碼形式之資料。 macroblock_motion_forward 或 macroblock_moti〇n_backward爲「1」，畫像構造爲訊框，進而 ，在 frame_pred_frame_dct爲 「 0」之情形，在表示 macroblock_type之資料元件之後，記錄表示 frame>motion_type 之資料元件。又，此 frame_pred_frame_dct 係表示frame_motic)n__type是否存在於位元流中之旗標。 frame_motion_type係表示訊框之大區塊之預測形式之2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 仏 (請先閲讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（13 ) 一 ^ 位元之碼。如係預測向量爲2個，區域基礎之預測形式 ，frame-motion_type爲「〇〇」，如係預測向量爲}個，區域基 礎之預測形式，frame_motion_type爲「01」，如係預測向量 爲1個，訊框基礎之預測形式，f r a m e - m 〇 t i ο η _ t y p e爲「1 0」， 如係預測向量爲1個，雙主要之預測形式，frame_ _motion_type 爲「1 1」。 field_m〇tion_type係顯示區域之大區塊之動作預測之2 位元之碼。如係預測向量爲1個，區域基礎之預測形式，爲「 01」，如係預測向量爲2個，18x8大區塊基礎之預測，爲「1〇 」，如係預測向量爲1個，雙主要之預測形式，爲「1 1」。 畫像構造爲訊框，frame —pred_frame_dct 表示 frame_motion_type 存在於該位元流中，frame —pred_frame_dct 表示 dct_type存在於該位元流中之情形，在表示 macroblock_type之資料元件之後，記述表示dct_type之資料 元件。又，dct_type係表示DCT爲訊框DCT模式或區域DCT 模式之資料。 於MPEG2之流中，以上說明之個別之資料元件係以被稱 爲start code之特殊的位元形態而開始。這些之開始碼在別 的狀況爲不出現於視頻流中之特定的位元形態。各開始碼 係由：開始碼前綴以及接續於其之開始碼値所構成。開始碼 前綴爲位元列 '' 0000 0000 0000 0000 0000 0001 〃 。開始碼 値係辨識開始碼之形式之8位元之整數。 圖13係顯示MPEG2之各start code之値。很多之開始 碼係由1個之開始碼値所表示。但是，slice_start_code係藉 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _ (請先閲讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 A7 _________ B7五、發明説明（14 ) 由〇1至AF之複數的開始碼値所表示，此開始碼値表示對於 切片爲垂直位置。這些之開始碼全部爲字節（byte)單位之故， 開始碼前綴之最初之位元成爲字節之最初的位元般地，在開 始碼前綴之前，被插入複數之位元“ 0ό，開始碼被調整爲字 節單位。 _ 圖14係顯示對應習知之MP @ ML之MPEG視頻解碼器之 電路構成之方塊圖。 MPEG視頻解碼器係藉由：由流輸入電路11、緩衝器控 制電路12、時脈產生電路13、開始碼檢測電路14、解碼 器15、動作補償電路18、以及顯示輸出電路17所構成之 IC (i n t e g r a t e d c i r c u i t) 1;以及以流緩衝器2 1以及視頻緩衝器 22 所構成，例如由 DRAM(Dynamic Random Access Memory)所 形成之緩衝器2所構成。 IC1之流輸入電路11接收被高效率編碼之編碼流之輸 入，供給於緩衝器控制電路12。緩衝器控制電路12依循由 時脈產生電路1 3所供給之基本時脈，將被輸入之編碼流輸入 於緩衝器2之流緩衝器21 〇流緩衝器21具有MP@ ML之_1 碼所要求之VBV緩衝器大小之1,835,008位元之容量。被保 存在流緩衝器2 1之編碼流依循緩衝器控制電路1 2之控制， 由先被寫入之資料依序被讀出，被供給於開始碼檢測電路14 。開始碼檢測電路14由被輸入之流中，檢測出使用圖13說 明之開始碼，將檢測之開始碼以及被輸入之流輸出於解碼器 15。 解碼器15將被輸入之流依據MPEG語法（syntax)解碼° (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2!0X297公釐） -17- 1272849 A7 B7 五、發明説明（15 ) (請先閱讀背面之注意事項再填寫本頁) 解碼器依循被輸入之開始碼，首先，解碼畫像層之頭部參數， 以此爲基礎，將切片層分離爲大區塊，解碼大區塊，將其結果 所獲得之預測向量以及像素輸出於動作補償電路1 6。 在MPEG中，藉由利用畫像之時間冗餘性，獲得以接近之 畫像間做動作補償之差，善編碼效率。在MPEG視頻解碼 器中，對於利用動作補償之像素，藉由在現在解碼之像素加上 該動作向量顯示之參考畫像之像素資料而進行動作補償，解 碼爲編碼前之畫像資料。 在由解碼器15被輸出之大區塊沒有使用動作補償之情 形，動作補償電路16將該像素資料透過緩衝器控制電路12 寫入緩衝器2之視頻緩衝器22,準備爲顯示輸出之同時，也準 備爲此像素資料被當成其它之畫像之參考資料之情形。 經濟部智慧財產局員工消費合作社印製 在由解碼器1 5被輸出之大區塊使用動作補償之情形，動 作補償電路1 6依循由解碼器1 5被輸出之預測向量，透過緩 衝器控制電路1 2，由緩衝器2之視頻緩衝器2 2讀出參考像素 資料。而且，將讀出之參考像素資料加在由解碼器15所供給 之像素資料，進行動作補償。動作補償電路1 6將進行動作補 償之像素資料透過緩衝器控制電路1 2寫入緩衝器2之視頻 緩衝器22,準備爲顯示輸出之同時，也準備爲此像素資料被設 爲其它之像素的參考資料之情形。 輸出顯示電路1 7產生輸出解碼之畫像資料用之同步定 時信號，以此定時爲基礎，透過緩衝器控制電路1 2，由視頻緩 衝器22讀出像素資料，當成解碼視頻信號輸出。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 1272849 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（16 ) 【發明欲解決之課題】 如以上說明般地，MPEG2流具有階層構造。利用圖2說 明之畫像層之 sequence_header 至 picture_coding_extensi〇n 之資料在利用圖1說明之外形以及級數不同之情形，該資料 量不太被變更。另一方面，切片層以下之資料量依存於編碼 之像素數。 由圖1，於HL中，在1張之畫像必須處理之大區塊數對於 ML，約成爲6倍。進而，由圖3,於H2P中，在1個之大區塊 中處理之區塊數成爲MP之4/3倍。 即,以對應利用圖14說明之MP@ML之視頻解碼器要解 碼4:2:2P@HL之編碼流之情形，伴隨VBV緩衝器大小以及像 素數之增加，流緩衝器21之緩衝器大小不足。又，伴隨位元 率之增加，輸入流之對流緩衝器21之存取增加，伴隨像素數 之增加，對動作補償電路1 6之視頻緩衝器22之存取增加之 故，緩衝器控制電路12之控制變得來不及。進而，伴隨位元 率之增加、大區塊以及區塊數之增加，解碼器1 5之處理變得 來不及。 由於今日之半導體技術之進展，信號處理電路、記憶體( 緩衝器）電路之動作速度都顯著提升。但是，在現在之 ML@MP之解碼技術中，還未能到達解碼4:2:2P@HL 。一般， 在要進行此種高速之信號處理之情形，電路規模大幅增加，導 致構件點數增加以及消費電力之增加。 本發明係有鑑於此種狀況而完成者，利用今日之半導體 技術，作成以可以實現之電路規模能夠實現對應可以實際時 本紙張尺度適财關家鮮（CNS ) A4規格（210X297公釐) ~ 一 ' (請先閲讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 Μ Β7五、發明説明（彳7 ) 間動作之4__2:2P@HL之視頻解碼器者。 【解決課題用之手段】 本發明之第1解碼裝置係以具備：解碼編碼流之複數的 解碼手段;以及控制使複數之解碼手段並行動作之解碼控制 手段爲其特徵。 複數之解碼手段可以使顯示解碼處理之終了之信號輸 出於解碼控制手段，解碼控制手段可以對輸出顯示解碼處理 之終了之信號的解碼手段控制使之解碼編碼流。 可以進而具備：緩衝編碼流之第1緩衝器手段；以及由編 碼流讀出顯示被包含在編碼流之指定的資訊單位之開始之 開始碼之同時，讀出關於開始碼被保持在第1緩衝器手段之 .位置的位置資訊之讀出手段；以及緩衝藉由讀出手段被讀出 之開始碼以及位置資訊之第2緩衝器手段；以及控制藉由第 1緩衝器手段之編碼流之緩衝、以及藉由第2緩衝器手段之 開始碼以及位置資訊之緩衝之緩衝控制手段。 編碼流可以爲由ISO/IEC13812-2以及ITU-T勸告H.262 所規定之MPEG2之編碼流。 進而可以使之具備：選擇藉由複數之解碼手段被解碼、 輸出之複數的畫像資料之中的指定者之選擇手段；以及接受 由選擇手段被選擇之畫像資料之輸入，因應需要，施以動作補 償之動作補償手段。 解碼手段可以使顯示解碼處理終了之終了信號輸出於 選擇手段，選擇手段具有記憶對應複數之解碼手段之個別之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -20- (請先聞讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 A7 ___ B7 _______五、發明説明（18 ) 處理狀態之値之記憶手段，記憶手段之値全部成爲第1値之 情形，使被記憶於對應輸出顯示解碼處理終了之終了信號之 解碼手段之記憶手段之値由第1値變更爲第2値，在藉由被 記憶於對應之記憶手段之値爲第2値之解碼手段被解碼之 畫像資料之中，使之選擇其一之畫像資料，可以使被記憶在對 應解碼被選擇之畫像資料之解碼手段之記憶手段的値變更 爲第1値。 進而可以使之具備：保持藉由選擇手段被選擇之畫像資 料、或藉由動作補償手段被施以動作補償之畫像資料之保 持手段；以及控制藉由由選擇手段被選擇之畫像資料、以及 由動作補償手段被施以動作補償之畫像資料之保持手段之 保持之保持控制手段。 可以使保持手段將畫像資料之亮度成分與色差成分個 別分開保持。 可以進而使之具備：變更被供給於解碼手段之編碼流之 訊框之順序之變更手段，可以使保持手段保持比合計畫像順 序內之內部編碼流以及前方向預測編碼訊框之訊框數至少 還多2個之訊框，變更手段可以使編碼流之訊框之順序變更 以成爲逆轉再生編碼流用之指定之順序。 進而可以使之具備：讀出藉由保持手段被保持之畫像資 料而輸出之輸出手段，所謂指定之順序係內部編碼訊框、前 方向預測編碼訊框、雙方向預測編碼訊框之順序，而且，在雙 方向預測編碼訊框內之順序可以使之與編碼之順序成爲相 反者，輸出手段可以使之：依序讀出藉由解碼手段被解碼、藉 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -21 - 1272849 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（19 ) 由保持手段被保持之雙方向預測編碼流而輸出之同時，以指 定之定時，讀出藉由保持手段被保持之內部編碼訊框、或前 方向預測編碼訊框，插入雙方向預測編碼訊框之間的指定之 位置而輸出。 所謂指定之順序可以爲：以藉由輸出手段內部編碼訊框 或前方向預測編碼訊框被輸出之定時，藉由解碼手段被解碼 之1個之前的畫像順序之內部編碼訊框或前方向預測編碼 訊框藉由保持手段被保持之順序者。 進而可以使之具備：記錄解碼編碼流所必要之資訊之記 錄手段；以及控制藉由記錄手段之資訊之記錄以及對資訊之 解碼手段之供給之控制手段，編碼流可以設爲包含資訊者，控 制手段可以使之爲選擇解碼手段之解碼處理所必要之資訊， 使之供給於解碼手段。 控制手段供給於解碼手段之資訊可以設爲對應藉由解 碼手段被解碼之訊框之上位層編碼參數。 可以進行使之具備：讀出藉由保持手段被保持之畫像資 料以輸出之輸出手段，解碼手段可以設爲以通常再生所必要 之處理速度之N倍速解碼編碼流者，輸出手段可以設爲在藉 由保持手段被保持之畫像資料中，輸出每N訊框之畫像資料 者。 又，可以進而使之具備：保持編碼流之第1保持手段；以 及由編碼流讀出表示被包含在編碼流之指定的資訊單位之 開始之開始碼之同時，讀出關於開始碼被保持在第1保持手 段之位置之位置資訊之讀出手段；以及保持藉由讀出手段被 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ29<7公釐) ~ ' (請先閲讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（20 ) 讀出之開始碼以及位置資訊之第2保持手段；以及控制藉由 第1保持手段之編碼流之保持、以及藉由第2保持手段之開 始碼以及位置資訊之保持之第1保持控制手段；以及選擇耢 由複數之解碼手段被解碼、被輸出之複數的畫像資料之中 的指定者之選擇手段；以及接受藉由選擇手段被選擇之畫像 資料之輸入，因應需要，施以動怍補償之動作補償手段.；以及 保持藉由選擇手段被選擇之畫像資料、或藉由動作補償手 段被施以動作補償之畫像資料之第3保持手段；以及將藉由 選擇手段被選擇之畫像資料、以及藉由動作補償手段被施 以動作補償之畫像資料之第3保持手段之保持與第1保持控 制手段獨立地控制之第2保持控制手段。 本發明之第1解碼方法係以包含：解碼編碼流之複數之 解碼步驟；以及控制使複數之解碼步驟之處理並行動作之解 碼控制步驟爲其特徵。 被記錄於本發明之第1記錄媒體之程式係以包含：解碼 編碼流之複數之解碼步驟；以及控制使複數之解碼步驟之處 理並行動作之解碼控制步驟爲其特徵。 本發明之第1程式係以包含：解碼編碼流之複數之解碼 步驟；以及控制使複數之解碼步驟之處理並行動作之解碼控 制步驟爲其特徵。 本發明之第2解碼裝置係以具備：解碼編碼流之複數之 分割解碼器；以及控制使複數之分割解碼器並行動作之分割 解碼器控制手·段爲其特徵。 本發明之第2解碼方法係以包含：控制藉由解碼編碼流 本^氏張尺度適用中國國家標準（CNS ) A4規格（210父297公釐1 ~ — (請先閲讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（21 ) 之複數之分割解碼器之解碼的解碼控制步驟；以及控制使複 數控制步驟並行動作之分割解碼器控制步驟爲其特徵。 被記錄於本發明之第2記錄媒體之程式係以包含：控制 藉由解碼編碼流之複數之分割解碼器之解.碼的解碼控制步 驟；以及控制使複數控制步驟並行動作之分割解碼器控制步 驟爲其特徵。 本發明之第2程式係以包含：控制藉由解碼編碼流之複 數之分割解碼器之解碼的解碼控制步驟；以及控制使複數控 制步驟並行動作之分割解碼器控制步驟爲其特徵。 於本發明之第1解碼裝置、解碼方法、以及程式中，編 碼流被解碼，使解碼處理並行動作地，控制解碼處理。 於本發明之第2解碼裝置、解碼方法、以及程式中，編 碼流藉由複數之分割解碼器被解碼，藉由複數之分割解碼器 之解碼處理被並行進行。 【發明之實施形態】 以下，參考圖面，說明本發明之實施形態。 圖1 5係顯示適應本發明之MPEG視頻解碼器之電路構 成方塊圖。 圖15之MPEG視頻解碼器係由：流輸入電路41、開始碼 檢測電路42、流緩衝器控制電路43、時脈產生電路44、 畫像解碼器45 、分割解碼器控制電路46、分割解碼器47 至49、動作補償電路50、亮度緩衝器控制電路51 、色差 緩衝器控制電路52、以及顯示輸出電路53所構成之IC3 1; (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -24- 1272849 A7 B7 五、發明説明（22 ) (請先閱讀背面之注意事項再填寫本頁} 以及由流緩衝器61以及開始碼緩衝器62所構成，例如由 DRAM形成之緩衝器32;以及由亮度緩衝器71以及色差緩衝 器72構成，例如，由DRAM形成之視頻緩衝器33;以及控制器 34;以及驅動器35所構成。 流輸入電路4 1係接受被高效率編碼之編碼流之輸入，供 給於開始碼檢測電路42。開始碼檢測電路42將被輸入之編 碼流供給於流緩衝器控制電路43之同時，檢測利用圖1 3說 明之開始碼，以此爲基礎，產生包含該開始碼之種類予顯示該 開始碼被寫入流緩衝器6 1之位置之寫入指向器之開始碼資 訊，供給於流緩衝器控制電路43。 時脈產生電路44產生利用圖14說明之時脈產生電路13 之2倍的基本時脈，供給於流緩衝器控制電路43。流緩衝器 控制電路43依循由時脈產生電路44所供給之基本時脈，將 被輸入之編碼流寫入緩衝器32之流緩衝器6 1，將被輸入之開 始碼資訊寫入緩衝器32之開始碼緩衝器62。 經濟部智慧財產局員工消費合作社印製 在MPEG視頻解碼器成爲可以順方向再生4:2:2P@HL之 MPEG編碼流之情形，流緩衝器61至少具有4:2:2P@HL之解 碼所要求之VBV緩衝器大小之47,1 85,920之容量。又，MPEG 視頻解碼器在成爲可以實行逆轉再生之情形，流緩衝器6 1至 少具有可以記錄2GOP份之資料之容量。 畫像解碼器45透過流緩衝器控制電路43由開始碼緩衝 器62讀出開始碼資訊。例如，解碼開始時，由利用圖2說明之 sequence_header被開始解碼之故，畫像解碼器45由開始碼緩 衝器 62讀出對應於利用圖 4說明開始碼之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經 濟 部 智 慧 財 產 局 消 費 合 作' 社 印 製 1272849 A7 ___ B7 五、發明説明（23 ) sequence_header_code之寫入指向器，以該寫入指向器爲基礎 ，由流緩衝器61讀出sequence_header，進行解碼。接著，畫像 解碼器45予sequence_header之讀出同樣地，由流緩衝器61 讀出 sequence_extension 、 GO P_ header 、 picture — coding_extension 等進行解碼。 畫像解碼器45在由開始碼緩衝器62讀出最初之 slice_start_code之時間點，成爲該畫像之解碼所必要之全部 的參數湊齊。畫像解碼器45將解碼之畫像層之參數輸出於 分割解碼器控制電路46。 分割解碼器控制電路46接受畫像層之參數的輸入，透過 流緩衝器控制電路43,由開始碼緩衝器62讀出對應之切片之 開始碼資訊。又，分割解碼器控制電路46具有顯示使分割解 碼器47至49之其一解碼之切片是否爲被包含在編碼流之第 幾號之切片之寄存器，一*面參考該寄存器，一*面將畫像層之篸 數與被包含在開始碼資訊之切片的寫入指向器供給分割解 碼器47至49之其一。關於分割解碼器控制電路46在分割 解碼器47至49之中，選擇使實行解碼之分割解碼器之處理， 利用圖1 6以及圖1 7之後敘述。 分割解碼器47係由大區塊檢測電路8 1、向量解碼電路 82、逆量子化電路83、以及逆DCT電路84所構成，以由分 §!j解碼器控制電路4 6被輸入之切片的寫入指向益爲基礎，將 對應之切片透過流緩衝器控制電路43由流緩衝器6 1讀出。 而且，依循由分割解碼器控制電路46被輸入之畫像層之參數 ，解碼讀出之切片，輸出於動作補償電路50。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -26- !丨Ί丨裝丨丨 (請先閲讀背面之注意事項再填寫本頁) 訂 1272849 A7 B7 五、發明説明（24 ) (請先閲讀背面之注意事項再填寫本頁) 大區塊檢測電路8 1分離切片層之大區塊，解碼各大區塊 之參數，將被可變長度編碼之各大區塊之預測模式以及預測 向量供給於向量解碼電路82,將被可變長度編碼之係數資料 供給於逆量子化電路83。向量解碼電路82解碼被可變長度 編碼之各大區塊的預測模式以及預測向量，復原預測向量。 逆量子化電路83解碼被可變長度編碼之係數資料，供給於逆 DCT電路84。逆DCT電路84對被解碼之係數資料施以逆 DCT，復原編碼前之像素資料。 分割解碼器47對動作補償電路50要求對於解碼之大區 塊之動作補償之實行（即，圖中，使以REQ所示之信號成.爲1)， 由動作補償電路50接受顯示對於動作補償之實行要求之接 受之信號（圖中以ACK顯示之信號），將被解碼之預測向量以 及被解碼之像素供給於動作補償電路50。分割解碼器47接 受ACK信號之輸入，將被解碼之預測向量以及被解碼之像素 供給於動作補償電路50後，將REQ信號由1變更爲0。而且， 在接著被輸入之大區塊之解碼終了之時間點，將REQ信號再 度由0變更爲1。 經濟部智慧財產局員工消費合作社印製 又，於分割解碼器48之大區塊檢測電路85至逆DCT電 路88以及分割解碼器49之大區塊檢測電路89至逆DCT電 路92中，也與分割解碼器47之大區塊檢測電路81至逆DCT 電路84進行同樣之處理之故，省略其說明。 動作補償電路50具有顯示由分割解碼器47至49被輸 入之資料的動作補償是否終了之Reg_REQ_A、Reg_REQ_B 以及Reg-REQ_C之3個寄存器，一面參考這些寄存器之値，一 尺度適财關家辟（CNS ) A4規格（21GX297公釐)~ " 1272849 A7 B7 五、發明説明（25 ) 面適當選擇分割解碼器47至49中之1個，接受動作補償實行 要求（即，對於REQ信號，輸出ACK信號，接受預測向量與像素 之輸入），實行動作補償處理。此時，動作補償電路50在分割 解碼器47至49之中，於指定之定時（timing),對於REQ信號爲 1之分割解碼器47至49之動作補償分別各1次終了後，接受 下一動作補償要求。例如，即使分割解碼器47連續提出動作 補償要求，至分割解碼器4 8以及分割解碼器4 9之動作補償 終了爲止，分割解碼器47之第2個之動作補償要求不被接受 。動作補償電路50對於分割解碼器47至49之其一之解碼 器的輸出，選擇是否實行動作補償之處理，係利用圖1 8以及 圖1 9之後敘述。 由分割解碼器47至49之其一被輸入之大區塊不使用動 作補償之情形，動作補償電路50在該像素資料如係亮度資料 ，透過亮度緩衝器控制電路5 1寫入視頻緩衝器33之亮度緩 衝器7 1，如該像素資料係色差資料，透過色差緩衝器控制電路 52寫入視頻緩衝器33之色差緩衝器72,準備於顯示輸出之 同時，此像素資料也準備爲被設爲其它畫像之參考資料之情 形。 在由分割解碼器4 7至4 9之其一被輸出之大區塊使用動 作補償之情形，動作補償電路5 0依循由分割解碼器4 7至4 9 之中對應之解碼器被輸入之預測向量，如該像素資料係亮度 資料，透過亮度緩衝器控制電路51，由亮度緩衝器71讀入參 考像素，如該像素資料係色差資料，透過色差緩衝器控制電路 5 2由色差緩衝器7 2讀入參考像素資料。而且，動作補償電路 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I ； .---裝 — 丨 (請先閲讀背面之注意事項再填寫本頁) -訂 s' 經濟部智慧財產局員工消費合作社印製 -28- 1272849 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（26 50將讀入之參考像素資料加於由分割解碼器47至49之其一 被供給之像素資料，進行動作補償。 動作補償電路5 0將進行動作補償之像素資料，如該像素 資料係亮度資料，透過亮度緩衝器控制電路5 1寫入亮度緩衝 器71，如該像素資料係色差資料，透過色差緩衝器控制電路 5 2易入色差緩衝器7 2，準備於顯示輸出之同時，該像素資料 也準備於被設爲其它之像素之參考資料之情形。 顯示輸出電路5 3產生輸出解碼之畫像資料用之同步定 時信號，依循此定時，透過亮度緩衝器控制電路5 1，由亮度緩 衝器71讀出亮度資料，透過色差緩衝器控制電路52,由色差 緩衝器72讀出色差資料，當成解碼視頻信號輸出。 驅動器35係被接續於控制器34,因應需要與被裝置之磁 碟101、光碟102、光磁碟103、以及半導體記憶體HM等 進行資料之授受。又，控制器34係控制以上說明之IC31 、 以及驅動器35之動作者。控制器34例如依循被記錄在被裝 置於驅動器之磁碟1〇1、光碟102、光磁碟103、以及半導 體記憶體1 04等之程式，可以使1C3 1實行處理。 接著，參考圖1 6之流程圖，說明分割解碼器控制電路4 6 之處理。 於步驟S 1中，分割解碼器控制電路46將表示處理之切 片是編碼流之第幾號之切片之寄存器之値設爲N = 1 °於步 驟S2中，分割解碼器控制電路46判定分割解碼器47是否爲 處理中。 於步驟S2中，在被判斷分割解碼器47並非處理中之情 ! I! ΊI -φ 裝 I — — I — I 訂！ — (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） -29 - 1272849 A 7 B7 五、發明説明（27 ) (請先閱讀背面之注意事項再填寫本頁) 形，於步驟S3中，分割解碼器控制電路46將畫像層之參數與 被包含在開始碼資訊之切片N之寫入指向器供給分割解碼 器47,使分割解碼器47解碼切片N，處理進入步驟S8。 於步驟S2中，在被判斷分割解碼器47爲處理中之情形， 於步驟S 4中，分割解碼器控制電路4 6判斷分割解碼器4 8是 否爲處理中。於步驟S4中，在被判斷分割解碼器48並非處 理中之情形，於步驟S5中，分割解碼器控制電路46將畫像層 之餐術語被包含在開始碼資訊之切片N之寫入指向器供給 分割解碼器48,使分割解碼器48解碼切片N，處理進入步驟 S8。 於步驟S4中，在被判斷分割解碼器48爲處理中之情形， 於步驟S6中，分割解碼器控制電路46判斷分割解碼器49是 否爲處理中。於步驟S6中，在被判斷分割解碼器49爲處理 中之情形，處理返回步驟S2,此以後之處理被重複。 經濟部智慧財產局員工消費合作社印製 於步驟S6中，在被判斷分割解碼器49並非處理中之情 形，於步驟S7中，分割解碼器控制電路46將畫像層之參數與 被包含在開始碼資訊之切片N之寫入指向器供給於分割解 碼器49,使分割解碼器49解碼切片N，處理進入步驟S8。 於步驟S8中，分割解碼器控制電路46將顯示處理之切 片爲編碼流之第幾號之切片之寄存器之値設爲N = N+1 。於 步驟S9中，分割解碼器控制電路46判斷全部切片之解碼是 否終了。於步驟S9中，在被判斷全部切片之解碼尙未終了之 情形，處理返回步驟S2,其以後之處理被重複。於步驟S9中， 在被判斷全部切片之解碼終了之情形，終了處理。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •30- 1272849 A7 _____ B7 五、發明説明（28 ) 圖1 7係顯示利用圖1 6說明之分割解碼器控制電路46 之處理的具體例圖。如上述般地，畫像層之資料被以畫像解 碼器45解碼，該參數被供給於分割解碼器控制電路46。此 處，於利用圖6說明之步驟S 1中，分割解碼器控制電路4 6設 寄存器之値爲N=1。於步驟S2中，分割解碼器47被判斷並 非處理中之故，於步驟S3中，分割解碼器控制電路46將畫像 層之參數與被包含在開始碼資訊之切片1之寫入指向器供 給於分割解碼器47,使分割解碼器47解碼切片N(N=1)，於步 驟S8中，設寄存器之値爲N = N+1。而且，於步驟S9中，在被判 斷全部切片之解碼尙未終了之故，處理返回步驟S2。 於步驟S2中，分割解碼器47被判斷爲處理中。而且，於 步驟S 4中，分割解碼器4 8被判斷爲並非處理中之故，於步驟 S5中，分割解碼器控制電路46將畫像層之參數與切片2之寫 入指向器供給於分割解碼器48,使分割解碼器48解碼切片 N(N = 2)，於步驟S8中，設N = N+1。而且，於步驟S9中，被判斷 全部切片之解碼尙未終了之故，處理返回步驟S2。 於步驟S2中，分割解碼器47被判斷爲處理中，於步驟S4 中，分割解碼器48被判斷爲處理中。而且，於步驟S6中，分割 解碼器49被判斷爲並非處理中之故，於步驟S7中，分割解碼 器處理電路將畫像層之參數與切片3之寫入指向器供給於 分割解碼器49,使分割解碼器49解碼切片n(N = 3)，於步驟S8 中，設N = 。而且，於步驟S9中，被判斷全部切片之解碼尙 未終了之故，處理返回步驟S2。 分割解碼器47至49實施被輸入之切片的解碼處理後 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —---A--.---^袭-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -31 - 1272849 經濟部智慧財產局員工消費合作社印製 A7 B7 _ 五、發明説明（29 ) 將顯示解碼處理之完了的信號輸出於分割解碼器控制電路 46。即，由分割解碼器47至49之其一至顯示切片2之解碼 之完了之信號被輸入爲止，分割解碼器47至49全部處理中 之故，步驟S 2、步驟S 4、以及步驟S 6之處理被重複。而且， 以圖1 7之圖中A所示之定時，將顯示分割解碼器4 8解碼處 理之完了的信號輸出於分割解碼器46,於步驟S4中，被判斷 分割解碼器4 8並非處理中之故，於步驟S 5中，分割解碼器控 制電路46將切片4之寫入指向器供給於分割解碼器48,使分 割解碼器4 8解碼切片N (N = 4)，於步驟S8中，叹N — N+1。而且 ，於步驟S9中，被判斷全部切片之解碼尙未終了之故，處理返 回步驟S 2。 而且，接著至接受由分割解碼器47至49之其一顯示解 碼處理之完了之信號的輸入爲止，分割解碼器控制電路4 6重 複步驟S2、步驟S4、以及步驟S6之處理。於圖17中/分割 解碼器控制電路46以圖中B所示之定時，由分割解碼器49 接受顯示切片3之解碼終了之信號的輸入之故，於步驟S 6中 ，分割解碼器49被判斷並非處理中。於步驟S7中，分割解碼 器控制電路46將切片5之寫入指向器供給於分割解碼器49, 使分割解碼器49解碼切片N(N = 5)，於步驟S8中，設N = N+1 ° 而且，於步驟S9中，被判斷全部切片之解碼尙未終了之故，處 理返回步驟S 2。以下，至最後的切片之解碼被終了爲止，同 樣之處理被重複。 如此，分割解碼器控制電路4 6 —面參考分割解碼器4 7 至49之處理狀況，一面分配切片之解碼處理之故，可以有效 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 32- 1272849 A7 B7 五、發明説明（30 ) 率地使用複數之解碼器。 (請先閱讀背面之注意事項再填寫本頁) 接著，參考圖18之流程圖，說明藉由動作補償電路50之 切片解碼器之調停處理。 於步驟S21中，動作補償電路50初期化內部之寄存器 Reg —REQ一A 、 Reg_REQ_B 以及 Reg_REQ_C 。即，設 Reg一REQ一A=0 、 Reg一REQ一B=0 、 Reg—REQ—C=0 。 於步驟S22中，動作補償電路50判斷寄存器之値是否全 部爲0。於步驟S22中，在被判斷寄存器之値並非全部爲0( 良P,即使有1個爲1)之情形，處理進入步驟S24。 於步驟S22中，在被判斷寄存器之値全部爲〇之情形，於 步驟S23中，動作補償電路50以由分割解碼器47至49被輸 入之REQ信號爲基礎，更新寄存器之値。即，在REQ信號由 分割解碼器47被輸出之情形，設Reg_REQ_A=l，在REQ信號 由分割解碼器48被輸出之情形，設Reg_REQ_B = l，在REQ信 號由分割解碼器49被輸出知情習，設Reg_REQ_C = 1。而且 ,處理進入步驟S24。 經濟部智慧財產局員工消費合作社印製 於步驟S24中，動作補償電路50判斷是否Reg_REQ_A=l 。於步驟S24中，在被判斷Reg_REQ_A=l之情形，於步驟S25 中，動作補償電路50對分割解碼器47傳送ACK信號，設 Reg_REQ_A = 0。分割解碼器47對動作補償電路50輸出以向 量解碼電路82被解碼之預測向量以及以逆DCT電路84被逆 DCT之像素。而且，處理進入步驟S30。 於步驟S24中，在被判斷Reg_REQ_A不爲1之情形，於步 驟S26中，動作補償電路50判斷是否Reg_REQ_B = 1。於步 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 -— --—-—--—^ " 1 >—. 五、發明説明（31 ) 驟S26中，在被判斷Reg_REQ_B = 1之情形，於步驟S27中，動 (請先閱讀背面之注意事項再填寫本頁} 作補償電路50對分割解碼器48傳送ACK信號，設 Reg_REQ_B = 0。分割解碼器48對動作補償電路50輸出以向 量解碼電路86被解碼之預測向量與以逆DCT電路88被逆 DCT之像素。而且，處理進入步驟S30。 於步驟S26中，在被判斷Reg_REQ_B不是1之情形，於步 驟S28中，動作補償電路50判斷Reg_REQ_C是否爲1。於步 驟S28中，在被判斷Reg —REQ — C並不是1之情形，處理返回步 驟S 2 2，其以後之處理被重複。 於步驟S28中，在被判斷Reg —REQ —C = 1之情形，於步驟 S 29中，動作補償電路50對分割解碼器49傳送ACK信號，設 Reg_REQ_C = 0。分割解碼器49對動作補償電路50輸出以向 量解碼電路90被解碼之預測向量，以及以逆DCT電路92被 逆DCT之像素。而且，處理進入步驟S30。 於步驟S30中，動作補償電路50判斷由分割解碼器47至 49之其一被輸入之大區塊是否使用動作補償。 經濟部智慧財產局員工消費合作社印製 於步驟S30中，在被判斷大區塊使用動作補償之情形，於 步驟S3 1中，動作補償電路50對被輸入之大區塊進行動作補 償。即，動作補償電路50依循由分割解碼器47至49之中，對 應之解碼器所被輸出之預測向量，如該像素資料爲亮度資料， 透過亮度緩衝器控制電路5 1，由亮度緩衝器7 1讀出參考像素 ，如該像素資料爲色差資料，透過色差緩衝器控制電路52,由 色差緩衝器7 2讀出參考像素資料。而且，動作補償電路5 〇 將讀出之參考像素資料加在由分割解碼器47至49之其一所 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -34- 1272849 A7 ____ B7 五、發明説明（32 ) 供給之像素資料，進行動作補償。 (請先閲讀背面之注意事項再填寫本頁) 動作補償電路50將進行動作補償之像素資料，如該像素 資料爲亮度資料，透過亮度緩衝器控制電路5 1寫入亮度緩衝 器71，如該像素資料爲色差資料，透過色差緩衝器控制電路 5 2寫入色差緩衝器7 2，準備於顯示輸出之同時，準備爲此像 素資料被設爲其它像素之參考資料之情形。而且，處理返回 步驟S22,其以後之處理被重複。 於步驟S 3 0中，在被判斷大區塊不使用動作補償之情形， 於步驟S32中，動作補償電路50如該像素資料爲亮度資料，透 過亮度緩衝器控制電路51寫入亮度緩衝器71，如該像素資料 爲色差資料，透過色差緩衝器控制電路5 2寫入色差緩衝器 72,準備於顯示輸出之同時，準備爲此像素資料被設爲其它像 .素之參考資料之情形。而且，處理返回步驟S22,其以後之處 理被重複。 圖1 9係顯示藉由利用圖1 8說明之動作補償電路50之 解碼器之調整處理之具體例圖。 經濟部智慧財產局員工消費合作社印製 於圖19所示定時C中，藉由圖18之步驟S22之處理，在 被判斷動作補償電路50之寄存器全部爲0之情形，分割解碼 器47至49全部輸出REQ信號之故，藉由步驟S23之處理，個 別之寄存器之値被更新爲Reg_REQ_A=l、Reg_REQ_B = l、 Reg_REQ_C = l 。而且，藉由步驟S24之處理，被判斷爲 Reg_REQ_A = l之故，於步驟S25中，動作補償電路50對分割 解碼器47輸出ACK信號，設Reg —REQ_A = 0,由分割解碼器47 接受預測向量與像素之輸入，進行動作補償1 ° 35- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 五、發明説明（33 動作補償1終了後，即，於圖1 9之D所示之定時中，處理 再度返回步驟S22。於圖中D所示定時中，REQ信號由分割 解碼器47被輸出。但是，寄存器之値爲Reg_REQ_A = 0 、Telecommunication Union-Telecommunication sector) The high efficiency coding method of the video signal specified in 262. The coding stream of the MPEG2 printed by the Intellectual Property Office of the Intellectual Property Office of the Ministry of Economic Affairs is graded by a coding method that determines the profile and the level determined by the number of pixels processed. Can be used for a wide range of applications. For example, MP@ML (main. shape. the Lord. The series is one of the grades and is widely used in DVB (Digital Video Groadc as) or DVD (Digital Versatile Disk). The shape and the number of stages are described in the seqence_extension described later using FIG. In addition, in the production of the video signal of the broadcasting station, the color difference signal of the video is processed in the same 4:2:2 manner as the conventional fundamental frequency, and the upper limit of the bit rate is increased by 4··2··2Ρ (4:2) ··2 shape) is regulated. Further, in order to correspond to the next-generation high-resolution video signal, HL (Advanced Number) is defined. Figure 1 shows the various parameters of the representative grade and individual grade of MPEG2. The paper scale applies to the Chinese National Standard (CNS) Α4 specification (210 X 297 mm) / 1272849 A7 ___ B7 V. Invention Description (2) (Read first Please note the upper limit of the page on the back. In Figure 1, the system is: 4:2:2P@ML (4:2:2 shape. Advanced number), 4:2:2P@ML (4:2:2 shape · main series), MP @ HL (main. shape. the Lord. Series), MP@HL-1440 (main · shape · high. Series -1440), MP@ML (main. shape. Main · series), MP@LL (main · shape · low · series), and SP@ML (simple. External shape · Lord. The number of levels), respectively: the bit rate, the number of samples per line, the number of lines per frame, the frame frequency, and the upper limit of the processing time of the sample. The upper limit of the bit rate of Figure 1, 4:2:2P@HL is 300 (Mbit/sec: one million bits/second), which is processed. The upper limit of the number of pixels is 62,668,800 (821!^168/86(::samples/sec). On the other hand, the upper limit of the bit rate of ]^?@]\/1? is 15 (Mbit/SeC). The upper limit of the number of pixels processed is 1 0,3 68,000 (samples/sec). SP, know that: decoding 4:2:2P@HL video decoder compared with decoding MP@ML video decoder requires bits The processing capacity of 20 times and the number of processed pixels is about 6 times. The Ministry of Economic Affairs, Intellectual Property Bureau, Staff Consumer Cooperative, Printed Figure 2 shows the structure of the MPEG2 video bit stream. The sequence_header is described in the initial layer of the uppermost layer. The sequence_header is the header data that defines the order of the MPEG bitstream. In the case where the sequence_header is not followed by the sequence_extension, the specification of IS0/IEC1 1172-2 is adapted to this bitstream. In the beginning of the sequence, the sequence_header has Continuation sequence — extension is more open, and all sequence_headers that occur after that are followed by sequence_extension. That is, in the case shown in Figure 2, after all sequence_headers, sequence_extension is continued. sequence_ Extension is the expansion data that defines the order layer of the MPEG bit stream. The sequence_extension is only used after the sequence_header. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1272849 A7 B7 V. Description of invention (3) Moreover, in order to decode, and after the frame is reorganized, there is no loss of the frame, and it is not possible to precede the sequence_end_code at the end of the bit stream. Also, the case of seQuence_extension occurs in the bit stream, in the individual picture one. Header followed by picture — cording — sequence ° The picture of the complex number is contained in G〇P(group_of _picture). G〇P_headei· defines the head of the GOP layer of the MPEG bit stream, and further, in this bit A data element defined by picture_header and picture_cording_extension is described in the elementary stream. One picture is encoded as picture_header and picture_cording_extension picture_data is transmitted. Further, the first code frame following G〇P _ h e a d e r is the I frame to be encoded (that is, the first picture of G〇P_header is an I picture). Advised in ITU-T H. 262 In addition to sequence_extension and picture_cording_extension, various expansions are defined, and the illustration and description are omitted here. The picture_header is the header of the picture layer of the MPEG bit stream, and the picture_cording_extension is the extension of the picture layer of the MPEG bit stream. The picture_data describes the slice layer of the MPEG bit stream and the data elements of the large block layer. The picture_data is divided into a plurality of slices as shown in Fig. 2, and the slice is divided into a macro-block of a complex female. Macro_block is composed of 16x16 pixel data. The first large block and the last large block of the slice are not skipped by large blocks (large blocks without information). The large block is composed of 16x16 pixel data. Also, each block (please read the note on the back and then fill out this page). The Ministry of Economic Affairs, Intellectual Property Bureau, Staff and Consumer Cooperatives, Printed Appropriate Sheets - Paper, One Standard, One Country, I Country, Country I, 3⁄4 - PCT, 1272849 A7 _— ___ B7 V. Inventive Note (4) (Please read the note on the back and fill out this page). It consists of 8x8 pixels. In addition, the frame DCT (Discrete Cosine 1) ^ 1 ^ £ 0]: 111: discrete cosine transform) encoding and region 0 (: the use of D-code is possible in the frame image, in the case of frame encoding and region encoding The internal structure of the large block is different. The large block contains a distinction between the luminance component and the color difference component. The so-called large block language system displays one of the information source and the decoded data or the corresponding coded data component. The large block has: 4:2:0, 4:2:2, and 4:4:4 three color difference formats. The order of the blocks in the large block varies according to the individual color difference format. Figure 3 (A) shows 4:2 Large block in the case of the 0 mode. In the case of the 4:2:0 mode, the large block is composed of four luminance (Y) blocks and one color difference (Cb, C〇 blocks). 3(B) shows a large block in the case of the 4:2:2 mode. In the case of the 4:2:2 mode, the large block is composed of 4 luminance (Y) blocks and 2 individual color differences ( Blocks of Cb and Ci·) Blocks of the Ministry of Economic Affairs, Intellectual Property Office, and Consumers' Cooperatives, which can be used to predict the coding process by several methods. The prediction mode is determined by the regional prediction and Two types of frame prediction. In the area prediction, the data of the first or multiple regions decoded first is used to predict in each region. The frame prediction uses one or multiple signals that are decoded first. Box, predictive prediction. In the regional image, the prediction is all regional prediction. On the other hand, in the frame image, prediction can be performed by one of regional prediction or frame prediction, and the prediction method is In the prediction coding process of large blocks, in addition to regional prediction and frame prediction, it is also possible to use 16x8 motion compensation and dual pnme special prediction modes. Vector information and other surrounding information and predictions of major blocks. The paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm). A 7-1272849 A7 B7 V. Invention description (5) (Please read the back Note: Please fill in this page again) The error signals are encoded together. Regarding the encoding of the motion vector, the last motion vector encoded by the variable length coding is used as the prediction vector. The difference vector from the prediction vector. The maximum length of the vector that can be represented can be programmed for each portrait. Also, the calculation of the appropriate motion vector is performed by the encoder. Moreover, after picture_data, the configuration: seqUence_header and Sequence. Extension. The data elements described by the sequence_header and the sequence_extension are identical to the data elements described by the sequence_header and the sequence_extension which are described in the order of the video stream. The reason for describing the same data in the stream is to prevent the situation from being started in the middle of the data stream (for example, corresponding to the bit stream portion of the image layer) on the bit stream receiving device side. Receiving the data of the sequence layer, the stream cannot be decoded. After the data element defined by the last sequence_header and sequence_extension ,, at the end of the data stream, the sequence__end_code of the 32-bit sequence at the end of the display sequence is described. Next, the individual data elements are illustrated using FIGS. 4 to 12. detailed. Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing Figure 4 shows the data structure of sequence_header. The data elements contained in the sequence_header are: sequence_header_code, horizontal_size_value, vertical_size_value, aspect_ratio_information, frame_rate_code, bit_rate_value, marker_bit, vbv_buffer_size_value, constrained_parameter_flag, load_intra_quantiser_matrix, in tr a -quantiser-matrix, load_non Intra-quantiser-matrix, this paper scale applies Chinese National Standard (CNS) A4 specification (21 OX 297 mm) 1272849 A7 ___^_ B7 _ V. Invention description (6) and non-intra — quantiser-matrix Composition. (Please read the notes on the back and fill out this page.) sequence_header_code is the data indicating the start sync code of the sequence layer. The honzontal_size_value is a data formed by the lower 12 bits of the number of pixels in the horizontal direction of the portrait. The vertical_size_value is a data formed by 12 bits below the vertical line number of the portrait. Acpect —ratio_information is data indicating the aspect ratio (aspect ratio) of the pixel or the aspect ratio of the display. Frame_rate_c〇de is the data indicating the display period of the portrait. Bit_rate_value is the data of the bit bit below the bit rate for the limitation of the bit amount. Moreover, marker_Mt is a bit material inserted to prevent start code emulation. Vbv_buffer_size_value determines the virtual buffer VBV for the encoding amount control (the size of the Video Buffering VenfieO is less than 10 bits. The constrained_parameter_flag is the data showing the parameters within the limit. The load_non_intra_quantiser_matrix shows the non-internal MB quantization matrix data. Information on the existence. The Ministry of Economic Affairs, the Intellectual Property Office, the employee consumption cooperative, printed load_intra_quantiser_matrix, which displays the existence of the internal MB quantization matrix data. The intra_quantiser_matrix system does not show the data of the internal MB quantization matrix. Non__intra_quantiser_matrix shows the non-internal MB The data of the quantized matrix is used. Figure 5 shows the data structure of sequence_extension. The sequence_extension is: extension_start_code, extension_start_code_identifier, profile_and_level_indication, progressive_sequence, chroma_format, this paper scale applies Chinese National Standard (CNS) A4 specification (210X297 mm) ) ~ " 1272849 A7 ____ B7 _ V. Invention description (7) horizontal —si ze_extension , verti Cal_size_extension, (please read the note on the back and then fill out this page) bit_rate_extension, marker_bit, vbv_buffer_size_extension, low_delay, frame_rate__extension_n, and frame_rate_extension_d, etc. extension_start_code is the data indicating the start sync code of the expansion data. extension_start_code —identifier is the data indicating which expansion data is transmitted. profile_and_level_indication is the data for specifying the shape and level of the video data. The progressive_sequence indicates that the video data is scanned sequentially (progressive image). The chromajormat is the color difference format of the specified video data. Information about 〇horizontal. _size_ An extension is added to the horizontal of the header. —size· _γ The upper 2-bit data of al alue 〇 vertical_size_extension is the data of 2 bits above the vertical_size_value of the sequential header. Printed by the Ministry of Economic Affairs, the Intellectual Property Office, and the Consumer Cooperatives. Moreover, b i t _ r a t e _ e X t e n s i ο η is the data of the 12-bit upper bit of the bit_rate_value of the sequence header. The marker_bit is a bit material that is inserted to prevent the start of the code simulation. Vbv_buffer_size_extension is a bit of 8 bits added to the vbv_buffer_size_value of the sequence header. L〇w_delay shows the data that does not contain the B portrait. The frame_rate_extension_n is combined with the frame_rate_code of the sequential header to obtain the frame rate data. Frame — rate_extension_d is a combination of the frame_rate_code of the sequence header to obtain the frame rate data. Figure 6 shows the data structure of the GOP-header. Indicates GOP-header This paper scale applies to China National Standard (CNS) A4 specification (210X 297 mm) -10- Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed 1272849 A7 _ B7 _ V. Invention Description (8) It consists of: group_start_code, time_code, closed_gop, and broken_link. The group_start_code is a poor material that displays the start sync code of the GOP layer. Time_code is the time code indicating the time of the previous portrait of G〇P. The closed_gop is a flag data that cannot be reproduced by other GOPs. The broken Jink is used for editing and the like, and indicates that the B image in the front end of the GOP cannot be correctly reproduced. Figure 7 shows the data structure of the picture_header. The data elements for picture_header are composed of: picture_start_code , temporal_ref erence , picture —cording_type , vb v_delay , full_pel_forward_vector , forward_f_code , full_pel_backward_vector , and backward code . 〇 · picture_start_code is the data indicating the start sync code of the portrait layer. The temporal_reference is information indicating the order in which the portraits are displayed, and the data is reset at the front of the G〇P. Picture_cording_type is information indicating the form of the portrait. Vbv_delay is the data indicating the month of the virtual buffer at the time of random access. Full_pel_forward_vector , forward_f_code , full_pel_backward_vector , and backward_f_code are fixed data that are not used in MPEG2. Fig. 8 shows the data structure of picture_cording_extension. Picture_cording_extension consists of: extension_start_code, extension_start_code_identifier, f_code [0] [0], f_code [0] [1 ], f_code[l][0], f_code[1][1], intra-dc_precision, i paper size Home Standard (CNS) A4 Specification (21GX297 mm) ~ (Please read the note on the back and fill out this page) 1272849 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 5, Invention Description (9) picture — structure , Top_field — first , frame a pred a frame_dct , concealment —motion a vectors , q —scale —type , intra_vlc_f ormat , alternate — scan , repeat —firt —field , chroma_420 —type, progressive_frame, composite one display —flag , v — axis , field_sequence, sub_carrier, burst_amplitude, and sub_carrier_phase. The extension_start_code is a start code indicating the start of the expansion data of the portrait layer. Extension_start_code_identifier is the code that displays which extended data is transmitted. F_code[0][0] is the data indicating the horizontal motion vector search range of the forward direction. F_code[0][l] is the data indicating the search range of the vertical motion vector in the forward direction. F_c〇de[l][0] is a data indicating the horizontal motion vector search range in the backward direction. F_code[l][l] is a data indicating the range of vertical motion vector exploration in the backward direction. Intra_dc_precision is a data indicating the accuracy of the DC coefficient. The DCT coefficient row F of 8x8 can be obtained by expressing the luminance of each pixel in the block and the rank f of the color difference signal as applied to the DCT. The coefficient of the upper left corner of this row F is called the DC coefficient. The DC coefficient is a signal indicating the average luminance and average color difference within the block. Picture_structure is expressed as a frame structure or a structure of a region structure. In the case of the regional structure, it is also displayed as data of the upper area or the lower area. Top_field_first indicates the case where the frame is in the upper or lower position. The frame_predictive_frame_dct indicates that in the frame structure, the prediction of the frame mode DCT is only the frame mode data. This standard applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " I ^^ Clothing"""""订̄"丨L~~Φ (please read the notes on the back first) Fill in this page again) 1272849 A7 B7 V. INSTRUCTIONS (10) concealment_motion_vectoi: s is the information that the motion vector used for covert transmission errors is attached to the internal large block. (Please read the note on the back and then fill out this page.) q_scale_type is a data that uses linear quantization scales or uses nonlinear re-quantization scales. The intra_vlc_format indicates whether or not another secondary VLC (Variable Length Cording) data is used in the internal large block. Alternate"can indicates the choice of using a sawtooth scan or an interlaced scan. The repeat_firt_field is used for data at 2:3 pulldown. The chroma_420_type is expressed in the case where the signal format is 4:2:0, which is the same as the next progressive_frame, and in the case where it is not the case, it is the data of 〇. Progressive_frame is a representation of the image as a sequential scan or interlaced area. Composhejisplayjlag is information indicating whether the source signal is a synthetic signal. V_axi s , field_sequence , sub_carrier , burst —amplitude, and sub_carrier_phase are used for the case where the source signal is a composite signal. Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing Figure 9 shows the data structure of picture_data. The data element defined by the picture_data() function is a data element defined by the SUce() function. At least one of the data elements defined by the slice() function is described in the bit stream. As shown in FIG. 10, the slice() function is defined by data elements such as slice_start_code, quantiser_scale_code, intra_slice_flag, intra_slice, reserved_bits, extra_bit_slice, and extra_information_slice, and a macroblockO function. Slice_start_code indicates the data to be determined by the slice() function 兀-13- This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1272849 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 5, invention description (11) The starting code of the beginning of the piece. The quantiser_scale_code indicates the size of the quantization step size set for the large block existing in the slice layer. In the case where the quantiser_scale_code is set for each large block, the data of the macroblock_quantiser_scale_code set for each large block is preferentially use. The intra_slice_flag indicates whether or not the intra_slice and the reserved_bits flag are present in the bit stream. The intra_slice indicates whether or not there is a non-internal large block in the slice layer. In the case where one of the large blocks of the slice layer is a non-internal large block, intra_slice becomes "0", and all of the large blocks of the slice layer are non-internal large blocks, and intra_slice becomes "1". Reserved_bits is a 7-bit data, which is taken after "0". The extra_bit_slice is a flag indicating that the added information exists, and is set to "1" when there is extra__information_slice, and is set to "0" when there is no additional information. After these data elements, the data elements defined by the macroblockO function are described. The macroblock() function is as shown in FIG. 11, and includes data elements such as macroblock_escape, macroblock_address_increment, and quantiser_scale_code, and marker_bit, and macroblock_modes() function, motion_vectors(s) function, and 〇〇(16(1_131). 〇〇1: _0 3 price]: 11() function is defined as the data element used by the prostitute. The macroblock_escape is a fixed bit indicating whether the difference between the horizontal block and the previous large block is greater than 34. In the case where the difference between the horizontal direction of the reference large block and the former large block is 34 or more, 33 is added to the macroblock_address_increment ^ fit 〇 (please read the note on the back and fill in the page first). This paper size applies to China. National Standard (CNS) A4 Specification (210X297 mm) 1272849 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed A7 ___ B7 V. Invention Description (12) macroblock_address_increment indicates the horizontal direction of the reference block and the former block. Poor data. If there is a macroblock_e before macroblock_address_increment The scape, after adding 33 after It匕macroblock_address_increment, shows the difference between the horizontal direction of the actual reference large block and the previous large block. The quantiser_scale_code indicates the size of the quantization step size set in each block. It exists only when macroblock__quant is "1". The quantization step size of the slice layer is displayed in each slice layer. slice_quantiser_scale_c〇de is set, but for the reference large block, scale_C〇de. In the case of setting, the quantization step size is selected. After the macroblock_address-increment, the data elements defined by the macroblock_modes() function are described. The macroblock_modes() function is a function for data elements such as macroblock_type, frame_motion_type, field_motion_type, and dct_type, as shown in FIG. The macroblock_type is a representation of the encoded form of a large block. The macroblock_motion_forward or macroblock_moti〇n_backward is "1", and the image structure is constructed as a frame. Further, when the frame_pred_frame_dct is "0", after the data element indicating the macroblock_type, the data element indicating frame>motion_type is recorded. Also, this frame_pred_frame_dct is a flag indicating whether frame_motic)n__type exists in the bit stream. Frame_motion_type is the predicted form of the large block of the frame. 2 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 仏 (please read the note on the back and fill out this page) 1272849 Ministry of Economics Intellectual Property Bureau staff consumption cooperatives printed A7 B7 five, invention description (13) one ^ bit code. If the prediction vector is two, the prediction form of the region basis, the frame-motion_type is "〇〇", if the prediction vector is }, the prediction form of the region basis, the frame_motion_type is "01", and the prediction vector is 1 The frame-based prediction form, frame - m 〇ti ο η _ type is "1 0", if the prediction vector is one, the two main prediction forms, frame_ _motion_type is "1 1". Field_m〇tion_type is the 2-bit code of the motion prediction of the large block of the display area. If the prediction vector is 1, the prediction form of the regional basis is "01", if the prediction vector is 2, and the prediction of the 18x8 large block basis is "1", if the prediction vector is 1, double The main form of forecast is "1 1". The image is constructed as a frame, frame —pred_frame_dct indicates that frame_motion_type exists in the bit stream, and frame —pred_frame_dct indicates that dct_type exists in the bit stream. After the data element representing macroblock_type, the data element representing dct_type is described. Moreover, dct_type indicates that the DCT is the data of the frame DCT mode or the regional DCT mode. In the MPEG2 stream, the individual data elements described above begin with a special bit pattern called start code. These start codes are in other situations that are not in the particular bit pattern of the video stream. Each start code consists of a start code prefix and a start code followed by it. The start code prefix is the bit column '' 0000 0000 0000 0000 0000 0001 〃 . Start Code The integer number of octets in the form of the identification start code. Figure 13 is a diagram showing the start codes of MPEG2. A lot of the starting code is represented by the starting code of one. However, slice_start_code is based on the Chinese National Standard (CNS) A4 specification (210X297 mm) by the paper scale _ (please read the note on the back and fill out this page) 1272849 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Print A7 _________ B7 V. INSTRUCTION DESCRIPTION (14) From the start code 〇 of the complex number of 〇1 to AF, this start code 値 indicates that the slice is a vertical position. The start codes of these are all in bytes. The first bit of the start code prefix becomes the first bit of the byte. Before the start code prefix, the bit of the complex number is inserted. The code is adjusted to a byte unit. _ Figure 14 is a block diagram showing the circuit configuration of the MPEG video decoder corresponding to the conventional MP @ ML. The MPEG video decoder is composed of: stream input circuit 11, buffer control circuit 12 The clock generation circuit 13, the start code detection circuit 14, the decoder 15, the operation compensation circuit 18, and the IC (integrated circuit) 1 formed by the display output circuit 17; and the stream buffer 2 1 and the video buffer 22 For example, it is constituted by a buffer 2 formed by a DRAM (Dynamic Random Access Memory). The stream input circuit 11 of IC1 receives an input of a code stream which is encoded with high efficiency, and supplies it to the buffer control circuit 12. The buffer control circuit 12 follows The basic clock supplied from the clock generating circuit 13 inputs the input encoded stream into the stream buffer 21 of the buffer 2. The choke buffer 21 has the MP code of MP@ML. The required capacity of the VBV buffer size is 1,835,008 bits. The encoded stream stored in the stream buffer 21 is controlled by the buffer control circuit 12, and the data to be written first is sequentially read and supplied to The start code detecting circuit 14. The start code detecting circuit 14 detects the start code described using Fig. 13 from the input stream, and outputs the detected start code and the input stream to the decoder 15. The decoder 15 is input. The stream is decoded according to MPEG syntax (please read the note on the back and fill out this page). The paper size applies to the Chinese National Standard (CNS) A4 specification (2!0X297 mm) -17- 1272849 A7 B7 V. (15) (Please read the note on the back and fill out this page.) The decoder follows the input start code. First, decode the header parameters of the image layer. Based on this, the slice layer is separated into large blocks. Decoding a large block, and outputting the prediction vector and the pixel obtained as a result to the motion compensation circuit 16. In MPEG, by using the temporal redundancy of the image, the difference between the motion compensations of the close portraits is obtained. Good coding efficiency. In the MPEG video decoder, for the pixels compensated by motion, the motion compensation is performed by adding the pixel data of the reference image displayed by the motion vector to the currently decoded pixel, and decoding is performed as the image data before encoding. In the case where the large block outputted by the decoder 15 does not use motion compensation, the motion compensation circuit 16 writes the pixel data through the buffer control circuit 12 to the video buffer 22 of the buffer 2 to prepare for display output. It is also prepared to use this pixel material as a reference for other portraits. In the case where the Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative prints a large block outputted by the decoder 15 using motion compensation, the motion compensation circuit 16 follows the prediction vector outputted by the decoder 15 and transmits the buffer control circuit. 1 2, the reference pixel data is read by the video buffer 2 2 of the buffer 2. Further, the read reference pixel data is added to the pixel data supplied from the decoder 15 to perform motion compensation. The motion compensation circuit 16 writes the pixel data for performing motion compensation into the video buffer 22 of the buffer 2 through the buffer control circuit 12, and prepares to display the output, and is also prepared to set the pixel data to be other pixels. References. The output display circuit 17 generates a synchronous timing signal for outputting the decoded image data, and based on the timing, the pixel data is read by the video buffer 22 through the buffer control circuit 12, and is output as a decoded video signal. This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1272849 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed A7 B7 V. Invention description (16) [The subject to be solved] As explained above The MPEG2 stream has a hierarchical structure. The data of sequence_header to picture_coding_extensi〇n of the portrait layer illustrated in Fig. 2 is not changed in the case where the outer shape and the number of stages are different by using Fig. 1 . On the other hand, the amount of data below the slice layer depends on the number of pixels encoded. In Fig. 1, in HL, the number of large blocks that must be processed in one portrait is about six times that of ML. Further, from Fig. 3, in H2P, the number of blocks processed in one large block is 4/3 times that of MP. That is, in the case where the video decoder corresponding to the MP@ML explained using FIG. 14 is to decode the encoded stream of 4:2:2P@HL, the buffer size of the stream buffer 21 increases with the VBV buffer size and the number of pixels. insufficient. Further, as the bit rate increases, the access of the input stream to the convection buffer 21 increases, and as the number of pixels increases, the access to the video buffer 22 of the motion compensation circuit 16 increases, and the buffer control circuit 12 increases. The control has become too late. Furthermore, with the increase in the bit rate, the large block, and the increase in the number of blocks, the processing of the decoder 15 becomes too late. Due to the advancement of semiconductor technology today, the speed of operation of signal processing circuits and memory (buffer) circuits has increased significantly. However, in the current ML@MP decoding technology, decoding 4:2:2P@HL has not yet been reached. In general, in the case of such high-speed signal processing, the circuit scale is greatly increased, resulting in an increase in the number of component points and an increase in power consumption. The present invention has been completed in view of such a situation, and the use of today's semiconductor technology can be achieved in a achievable circuit scale that can be achieved in accordance with the actual paper size (CNS) A4 specification (210X297 mm). 1' (Please read the note on the back and fill in this page) 1272849 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing Μ 五 7 5, invention description (彳7) 4__2 between the action: 2P@HL video decoder. [Means for Solving the Problem] The first decoding device of the present invention is characterized in that it includes a decoding means for decoding a complex number of encoded streams, and a decoding control means for controlling a plurality of decoding means to operate in parallel. The decoding means of the complex number can output the signal of the end of the display decoding process to the decoding control means, and the decoding control means can control the decoding means for outputting the signal of the end of the decoding process to decode the encoded stream. Further, the method further includes: a first buffer means for buffering the encoded stream; and reading and displaying the start code included in the start of the designated information unit of the encoded stream by the encoded stream, and reading the start code is held in the first buffer Means of means. a means for reading location information of a location; and a second buffer means for buffering a start code and location information read by the reading means; and buffering the encoded stream by the first buffer means, and by buffering The buffer control means for the start code of the second buffer means and the buffer of the position information. The encoded stream can be advised by ISO/IEC13812-2 and ITU-T. 262 specifies the encoded stream of MPEG2. Further, it is possible to provide a selection means for selecting a designated one of the plurality of image data decoded and output by a plurality of decoding means, and inputting the image data selected by the selection means, and applying the action as needed Compensation compensation action means. The decoding means can output the end of the display decoding process to the selection means, and the selection means has the memory of the corresponding complex number of the individual paper scales applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -20- (please 1272849 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed A7 ___ B7 _______ V. Invention description (18) The memory means of handling the state, all the means of memory become the first In the case of 1値, the memory means of the decoding means stored in the signal corresponding to the end of the output display decoding process is changed from the first to the second, and the memory is stored in the corresponding memory means. Among the image data decoded by the decoding means, one of the image data selected is selected, and the memory means stored in the decoding means corresponding to the image data for decoding the selected image data can be changed to the first frame. Further, it is possible to provide means for holding image data selected by selection means or image data subjected to motion compensation by motion compensation means; and controlling image data selected by selection means, and The motion compensation means is controlled by the means for maintaining the image data of the motion compensation. The holding means can hold the luminance component and the color difference component of the image data separately. Further, the means for changing the order of the frames of the encoded stream supplied to the decoding means may be provided, and the holding means may maintain at least the number of frames of the inner coded stream and the forward direction predictive coded frame in the total image sequence. There are also two more frames, and the means for changing can change the order of the frames of the encoded stream to be the order in which the regenerated encoded stream is reversed. Furthermore, it is possible to provide an output means for outputting the image data held by the holding means, and the order of designation is the order of the inner coded frame, the forward direction predictive coded frame, and the bidirectional predictive coded frame, and The order in the two-direction predictive coding frame can be made opposite to the order of encoding, and the output means can be made: the sequential reading is decoded and borrowed by the decoding means (please read the back note first and then fill in This page applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -21 - 1272849 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed A7 B7 V. Invention description (19) Maintained by maintenance means While predicting the encoded stream and outputting, the internal coded frame or the forward direction predictive coded frame held by the holding means is read at a specified timing, and the specified position between the two-way predictive coded frames is inserted. Output. The order of designation may be: an internal coding frame or a forward direction prediction of a previous image sequence decoded by a decoding means by a timing at which an internal coding frame or a forward direction prediction coded frame is outputted by an output means The coded frame is held by the order in which the means are maintained. Further, it can be provided with: a recording means for recording information necessary for decoding the encoded stream; and a control means for controlling the recording of information by the recording means and the supply of the decoding means of the information, the encoded stream can be set to include information, and control The means can be made to provide information necessary for the decoding process of the decoding means to be supplied to the decoding means. The information supplied by the control means to the decoding means may be set to correspond to the bit layer upper layer coding parameters decoded by the decoding means. It is possible to provide an output means for reading out the image data held by the holding means, and the decoding means can decode the encoded stream by N times the processing speed necessary for normal reproduction, and the output means can be set to The image data of each N frame is outputted by the image data held by the holding means. Furthermore, it is possible to further include: a first holding means for holding the encoded stream; and reading, by the encoded stream, a start code indicating the start of the information unit included in the designated encoded stream, and reading about the start code is held at The means for reading the position information of the position of the first holding means; and maintaining the Chinese National Standard (CNS) A4 specification by the reading means (21〇Χ29) <7 mm) ~ ' (Please read the note on the back and fill out this page) 1272849 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Print A7 B7 V. Invention Description (20) Read start code and location information a second holding means; and a first holding control means for controlling the holding of the encoded stream by the first holding means and the holding of the start code and the position information by the second holding means; and selecting the plurality of decoding means a means for selecting a designator among the plurality of image data decoded and outputted; and accepting the input of the image data selected by the selection means, and applying the action compensation means for the dynamic compensation as needed; Selecting the image data selected by the means or the third holding means for the image data to be compensated by the motion compensation means; and the image data selected by the selection means and the action by the motion compensation means The second holding control means for maintaining the third holding means of the compensated image data independently of the first holding control means. The first decoding method of the present invention is characterized by comprising: a decoding step of decoding a complex number of encoded streams; and a decoding control step of controlling the parallel processing of the processing of the complex decoding steps. The program recorded in the first recording medium of the present invention includes a decoding step of decoding a complex number of encoded streams, and a decoding control step for controlling parallel operations of the complex decoding steps. The first program of the present invention is characterized by comprising: a decoding step of decoding a complex number of encoded streams; and a decoding control step of controlling the parallel processing of the processing of the complex decoding steps. The second decoding apparatus of the present invention is characterized in that it includes a split decoder that decodes a complex number of encoded streams, and a split decoder control hand segment that controls a plurality of divided decoders to operate in parallel. The second decoding method of the present invention includes: controlling the Chinese National Standard (CNS) A4 specification by applying the decoding code stream to the scale of the Chinese standard (CNS) A4 specification (210 parent 297 mm 1 ~ - (please read the back note first and then fill in This page) 1272849 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperatives Print A7 B7 V. Invention Description (21) The decoding control step of the decoding of the split decoder; and the split decoder control step that controls the parallel operation of the complex control steps The program of the second recording medium of the present invention includes: a decoding control step of controlling a solution of a plurality of divided decoders by decoding a coded stream; and controlling to cause the complex control steps to operate in parallel The split decoder control step is characterized by the second decoder of the present invention comprising: a decoding control step of controlling decoding of a plurality of divided decoders by decoding a coded stream; and a split decoder for controlling parallel operation of the complex control step The control step is characterized in that the encoded stream is decoded in the first decoding device, the decoding method, and the program of the present invention. The decoding process is controlled in parallel, and the decoding process is controlled. In the second decoding device, the decoding method, and the program of the present invention, the encoded stream is decoded by a plurality of divided decoders, and the decoding process by the plurality of divided decoders is [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the circuit configuration of an MPEG video decoder adapted to the present invention. The MPEG video decoder of Fig. 15 is composed of : stream input circuit 41, start code detecting circuit 42, stream buffer control circuit 43, clock generating circuit 44, image decoder 45, split decoder control circuit 46, split decoders 47 to 49, motion compensation circuit 50, luminance The buffer control circuit 51, the color difference buffer control circuit 52, and the display output circuit 53 constitute IC3 1; (Please read the back note first and then fill in the page) This paper size applies to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) -24- 1272849 A7 B7 V. INSTRUCTIONS (22) (Please read the notes on the back and then fill out this page) and by stream buffering 61 and a start code buffer 62, such as a buffer 32 formed of a DRAM; and a luminance buffer 71 and a color difference buffer 72, for example, a video buffer 33 formed of a DRAM; and a controller 34; The stream input circuit 41 receives the input of the encoded stream which is encoded with high efficiency, and supplies it to the start code detecting circuit 42. The start code detecting circuit 42 supplies the input encoded stream to the stream buffer control circuit 43 while The detection uses the start code described with reference to FIG. 13 , and based on this, generates start code information including the type of the start code to display the position of the write pointer to be written to the stream buffer 61. Stream buffer control circuit 43. The clock generation circuit 44 generates a fundamental clock which is twice as large as the clock generation circuit 13 described with reference to Fig. 14, and supplies it to the stream buffer control circuit 43. The stream buffer control circuit 43 writes the input encoded stream into the stream buffer 61 of the buffer 32 in accordance with the basic clock supplied from the clock generating circuit 44, and writes the input start code information into the buffer 32. The start code buffer 62. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative printed in the MPEG video decoder becomes the MPEG encoded stream that can reproduce 4:2:2P@HL in the forward direction. The stream buffer 61 has at least 4:2:2P@HL decoding station. The required VBV buffer size is 47,1 85,920. Further, in the case where the MPEG video decoder is capable of performing reverse reproduction, the stream buffer 61 has at least a capacity capable of recording data of 2 GOP shares. The picture decoder 45 reads the start code information from the start code buffer 62 through the stream buffer control circuit 43. For example, when decoding is started, the sequence_header described with reference to FIG. 2 is started to be decoded, and the picture decoder 45 reads out from the start code buffer 62 the Chinese National Standard (CNS) corresponding to the paper size of the start code explained using FIG. A4 specification (210X297 mm) Ministry of Economic Affairs Intellectual Property Bureau Consumer Cooperation 'Social Printing 1272849 A7 ___ B7 V. Invention Description (23) The sequence_header_code write pointer is based on the write pointer, and is stream buffer 61. Read the sequence_header for decoding. Next, the image decoder 45 reads the sequence_header in the same manner, and the stream buffer 61 reads out the sequence_extension, GO P_ header, picture_coding_extension, and the like for decoding. The image decoder 45 obtains all the parameters necessary for decoding the image when the first slice_start_code is read by the start code buffer 62. The image decoder 45 outputs the parameters of the decoded image layer to the split decoder control circuit 46. The division decoder control circuit 46 receives the input of the parameters of the image layer, and passes through the stream buffer control circuit 43 to read the start code information of the corresponding slice from the start code buffer 62. Further, the split decoder control circuit 46 has a register for displaying whether or not the slice decoded by the split decoders 47 to 49 is a slice included in the number of the encoded stream, and the * face is referred to as a * face The number of turns of the portrait layer and the write pointer of the slice included in the start code information are supplied to one of the split decoders 47 to 49. The division decoder control circuit 46 selects, among the division decoders 47 to 49, a process of causing the division decoder to perform decoding, which will be described later with reference to Fig. 16 and Fig. 17. The split decoder 47 is composed of a large block detecting circuit 81, a vector decoding circuit 82, an inverse quantization circuit 83, and an inverse DCT circuit 84, to be sliced by the §!j decoder control circuit 46. Based on the write pointer, the corresponding slice is read by the stream buffer 61 through the stream buffer control circuit 43. Then, the read slice is decoded and output to the motion compensation circuit 50 in accordance with the parameters of the image layer input by the split decoder control circuit 46. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) -26- !丨Ί丨装丨丨 (Please read the notes on the back and fill out this page) Order 1272849 A7 B7 V. Invention description (24 (Please read the note on the back and fill out this page.) Large block detection circuit 8 1 separates the large blocks of the slice layer, decodes the parameters of each block, and predicts the blocks of variable length coding. The mode and prediction vector are supplied to the vector decoding circuit 82, and the variable length coded coefficient data is supplied to the inverse quantization circuit 83. The vector decoding circuit 82 decodes the prediction modes and prediction vectors of the respective blocks of the variable length coding, and restores the prediction vector. The inverse quantization circuit 83 decodes the coefficient data of the variable length coding and supplies it to the inverse DCT circuit 84. The inverse DCT circuit 84 applies an inverse DCT to the decoded coefficient data to restore the pixel data before encoding. The split decoder 47 requests the motion compensation circuit 50 to perform motion compensation for the decoded large block (i.e., the signal shown by REQ is set to 1), and the motion compensation circuit 50 accepts the display for motion compensation. The signal to be accepted (the signal shown by ACK in the figure) is implemented, and the decoded prediction vector and the decoded pixel are supplied to the motion compensation circuit 50. The division decoder 47 receives the input of the ACK signal, supplies the decoded prediction vector and the decoded pixel to the motion compensation circuit 50, and changes the REQ signal from 1 to 0. Further, the REQ signal is again changed from 0 to 1 at the time point when the decoding of the input large block is completed. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative prints the large block detection circuit 85 from the large block detection circuit 85 of the split decoder 48 to the inverse DCT circuit 88 and the large block detection circuit 89 to the inverse DCT circuit 92 of the split decoder 49, The large block detecting circuit 81 of the split decoder 47 performs the same processing as the inverse DCT circuit 84, and the description thereof is omitted. The motion compensation circuit 50 has three registers of Reg_REQ_A, Reg_REQ_B, and Reg-REQ_C, which indicate whether or not the motion compensation of the data input by the split decoders 47 to 49 is finished, and a reference to these registers, a scale suitable for wealth ( CNS ) A4 specification (21GX297 mm)~ " 1272849 A7 B7 V. Inventive Note (25) One of the split decoders 47 to 49 is appropriately selected to accept the motion compensation implementation requirement (ie, for the REQ signal, the output ACK) The signal, which accepts the prediction vector and the input of the pixel, performs motion compensation processing. At this time, the motion compensation circuit 50 accepts the next one of the division decoders 47 to 49 in the division decoders 47 to 49 at the designated timing, and the operation compensation for the division decoders 47 to 49 having the REQ signal of 1 is completed. Motion compensation requirements. For example, even if the split decoder 47 continuously requests the motion compensation, the second motion compensation request of the split decoder 47 is not accepted until the motion compensation of the split decoder 48 and the split decoder 49 is completed. The motion compensation circuit 50 selects whether or not to perform the motion compensation processing for the output of the decoder of one of the split decoders 47 to 49, which will be described later with reference to Fig. 18 and Fig. 19. The motion compensation circuit 50 writes the video buffer 33 through the luminance buffer control circuit 51 in the pixel data such as the luminance data by the fact that one of the division decoders 47 to 49 is input without using motion compensation. The luminance buffer 71, if the pixel data is color difference data, is written into the color difference buffer 72 of the video buffer 33 through the color difference buffer control circuit 52, and is ready to be displayed and output, and the pixel data is also prepared to be set. The case of reference materials for other portraits. In the case where motion compensation is used by a large block which is outputted by one of the split decoders 4 7 to 49, the motion compensation circuit 50 follows the prediction that the corresponding decoder among the split decoders 4 7 to 49 is input. The vector, such as the luminance data of the pixel data, is read into the reference pixel by the luminance buffer 71 through the luminance buffer control circuit 51, such as the pixel data color difference data, and the color difference buffer is controlled by the color difference buffer control circuit 52. Read in the reference pixel data. Moreover, the motion compensation circuit is based on the Chinese National Standard (CNS) A4 specification (210X297 mm) I; .---Installation - 丨 (please read the notes on the back and fill out this page) - Order s' Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing -28- 1272849 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 5, invention description (26 50 to add the reference pixel data to one of the segmentation decoders 47 to 49 The pixel data supplied is compensated for. The motion compensation circuit 50 writes the pixel data of the motion compensation, such as the luminance data of the pixel data, into the luminance buffer 71 through the luminance buffer control circuit 51, such as the pixel data. The color difference data is transmitted through the color difference buffer control circuit 52 to the color difference buffer 72, and is prepared for display output, and the pixel data is also prepared for the reference data set as other pixels. Display output circuit 5 3 A synchronization timing signal for outputting the decoded image data is generated, and the brightness is read by the luminance buffer 71 through the luminance buffer control circuit 51 in accordance with the timing. Through the color difference buffer control circuit 52, the color difference data is read by the color difference buffer 72, and is output as a decoded video signal. The driver 35 is connected to the controller 34, and the disk 101, the optical disk 102, and the light of the device are required. The disk 103, the semiconductor memory HM, etc. transmit and receive data. Further, the controller 34 controls the IC 31 described above and the actor of the driver 35. The controller 34 is recorded, for example, on the disk 1 to be mounted on the drive. The program of 〇1, CD 102, optical disk 103, and semiconductor memory 104 can be processed by 1C3 1. Next, the processing of the split decoder control circuit 46 will be described with reference to the flowchart of Fig. 16. In step S1, the split decoder control circuit 46 sets the value of the register indicating that the slice being processed is the slice of the number of the encoded stream to N = 1 °. In step S2, the split decoder control circuit 46 determines the split decoder. Whether or not it is in process. In step S2, it is judged that the split decoder 47 is not in the process of processing! I! ΊI - φ I - I I - I book! - (Please read the back note first) Fill in this page again. This paper size is applicable to China National Standard (CNS) A4 specification (210x297 mm) -29 - 1272849 A 7 B7 V. Invention description (27 ) (Please read the note on the back and fill in this page) In step S3, the split decoder control circuit 46 supplies the parameter of the picture layer to the write pointer of the slice N included in the start code information to the split decoder 47, causes the split decoder 47 to decode the slice N, and the process proceeds to the step. S8. In step S2, in the case where it is judged that the split decoder 47 is in the process, in step S4, the split decoder control circuit 46 judges whether or not the split decoder 48 is in process. In step S4, in the case where it is judged that the split decoder 48 is not in the process, in step S5, the split decoder control circuit 46 supplies the meal term of the portrait layer to the write pointer supply of the slice N of the start code information. The split decoder 48 causes the split decoder 48 to decode the slice N, and the processing proceeds to step S8. In step S4, when it is judged that the split decoder 48 is in the process, in step S6, the split decoder control circuit 46 determines whether or not the split decoder 49 is in progress. In the case where it is judged that the division decoder 49 is in the processing in the step S6, the processing returns to the step S2, and the processing thereafter is repeated. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative is printed in step S6, and in the case where it is judged that the split decoder 49 is not in the process, in step S7, the split decoder control circuit 46 sets the parameters of the image layer and the start code. The write pointer of the slice N of the information is supplied to the split decoder 49, and the split decoder 49 decodes the slice N, and the processing proceeds to step S8. In step S8, the division decoder control circuit 46 sets the slice of the display processing to the register of the slice of the number of the encoded stream as N = N+1. In step S9, the split decoder control circuit 46 determines whether or not the decoding of all the slices ends. In step S9, in the case where it is judged that the decoding of all the slices is not finished, the processing returns to step S2, and the subsequent processing is repeated. In step S9, when it is judged that the decoding of all the slices is finished, the processing is terminated. This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) • 30-1272849 A7 _____ B7 V. Inventive Note (28) Figure 1 shows the processing of the split decoder control circuit 46 illustrated by Figure 16. Specific example map. As described above, the material of the image layer is decoded by the image decoder 45, and this parameter is supplied to the division decoder control circuit 46. Here, in step S1 explained using Fig. 6, the division decoder control circuit 46 sets the register to N = 1. In step S2, the split decoder 47 is judged not to be in the process. In step S3, the split decoder control circuit 46 supplies the parameters of the picture layer to the write pointer of the slice 1 included in the start code information. The split decoder 47 causes the split decoder 47 to decode the slice N (N = 1), and in step S8, sets the value of the register to N = N + 1. Further, in step S9, if it is determined that the decoding of all the slices has not been completed, the processing returns to step S2. In step S2, the split decoder 47 is judged to be in progress. Further, in step S4, the division decoder 48 is judged not to be in the process, and in step S5, the division decoder control circuit 46 supplies the parameters of the picture layer and the write pointer of the slice 2 to the division decoding. The processor 48 causes the split decoder 48 to decode the slice N (N = 2), and in step S8, set N = N+1. Further, in step S9, it is judged that the decoding of all the slices has not been completed, and the processing returns to step S2. In step S2, the division decoder 47 is determined to be in the process, and in step S4, the division decoder 48 is determined to be in the process. Further, in step S6, the division decoder 49 is determined not to be in the process, and in step S7, the division decoder processing circuit supplies the parameters of the picture layer and the write pointer of the slice 3 to the division decoder 49, The segmentation decoder 49 is caused to decode the slice n (N = 3), and in step S8, N = is set. Further, in step S9, it is judged that the decoding of all the slices is not completed, and the processing returns to step S2. After the segmentation decoders 47 to 49 implement the decoding process of the input slice, the paper size is applied to the Chinese National Standard (CNS) A4 specification (210×297 mm) —---A--.---^-- (please first Read the notes on the back and fill out this page. Printed by the Ministry of Economic Affairs, Intellectual Property Bureau, Staff and Consumer Cooperatives -31 - 1272849 Ministry of Economic Affairs, Intellectual Property Office, Staff and Consumers Cooperative, Printed A7 B7 _ V. Invention Description (29) Decoding Processing The completed signal is output to the split decoder control circuit 46. That is, after the decoding of one of the division decoders 47 to 49 to the display slice 2 is input, the division decoders 47 to 49 are all processed, and the steps S2, S4, and S6 are performed. Processing is repeated. Further, the signal indicating that the decoding process of the division decoder 48 is completed is output to the division decoder 46 at the timing indicated by A in the diagram of Fig. 17. In step S4, it is judged that the division decoder 48 is not being processed. Therefore, in step S5, the split decoder control circuit 46 supplies the write pointer of the slice 4 to the split decoder 48, and causes the split decoder 48 to decode the slice N (N = 4), in step S8, Sigh N — N+1. Further, in step S9, it is judged that the decoding of all the slices is not completed, and the processing returns to step S2. Then, the division decoder control circuit 46 repeats the processing of steps S2, S4, and S6 until the input of the signal of the completion of the decoding processing by the division decoders 47 to 49 is accepted. In Fig. 17, the split decoder control circuit 46 receives the input of the decoded signal of the slice 3 by the split decoder 49 at the timing shown by B in the figure. In step S6, the split decoder 49 is Judgment is not in progress. In step S7, the split decoder control circuit 46 supplies the write pointer of the slice 5 to the split decoder 49, causes the split decoder 49 to decode the slice N (N = 5), and in step S8, sets N = N+ 1 ° Further, in step S9, it is judged that the decoding of all the slices is not finished, and the process returns to step S2. Hereinafter, the decoding of the last slice is ended, and the same processing is repeated. In this way, the split decoder control circuit 46 can refer to the processing status of the split decoders 47 to 49, and can allocate the slice decoding process, which can be effective (please read the back note first and then fill in the page). Applicable to China National Standard (CNS) A4 Specification (210X297 mm) 32- 1272849 A7 B7 V. Invention Description (30) The use of multiple decoders. (Please read the precautions on the back side and fill out this page.) Next, with reference to the flowchart of Fig. 18, the mediation processing by the slice decoder of the motion compensation circuit 50 will be described. In step S21, the action compensation circuit 50 initializes the internal registers Reg_REQ_A, Reg_REQ_B, and Reg_REQ_C. That is, let Reg - REQ - A = 0, Reg - REQ - B = 0, Reg - REQ - C = 0. In step S22, the motion compensation circuit 50 determines whether or not all of the registers are zero. In step S22, if all of the judged registers are not 0 (good P, even if one is 1), the processing proceeds to step S24. In step S22, in the case where all of the judged registers are 〇, in step S23, the action compensation circuit 50 updates the register based on the REQ signals input from the split decoders 47 to 49. That is, in the case where the REQ signal is output by the split decoder 47, Reg_REQ_A = 1, and when the REQ signal is output by the split decoder 48, Reg_REQ_B = 1 is set, and the REQ signal is outputted by the split decoder 49. Set Reg_REQ_C = 1. Moreover, the process proceeds to step S24. In the step S24, the action compensation circuit 50 determines whether or not Reg_REQ_A = l. In step S24, in the case where Reg_REQ_A = 1 is judged, in step S25, the action compensation circuit 50 transmits an ACK signal to the division decoder 47, and Reg_REQ_A = 0 is set. The split decoder 47 outputs the prediction vector decoded by the vector decoding circuit 82 to the motion compensation circuit 50 and the pixel which is inverse DCT by the inverse DCT circuit 84. Moreover, the process proceeds to step S30. In the case where it is judged that Reg_REQ_A is not 1 in step S24, in step S26, the motion compensation circuit 50 determines whether or not Reg_REQ_B = 1. The Chinese National Standard (CNS) A4 specification (210X297 mm) is applied to the paper size of the step paper. 1272849 A7 B7 -— -------^ " 1 >-. V. Invention description (31) Step S26 In the case where Reg_REQ_B = 1 is judged, in step S27, the action (please read the note on the back side and then fill in the page) is used as the compensation circuit 50 to transmit the ACK signal to the split decoder 48, and set Reg_REQ_B = 0. Split decoder The pair 48 motion compensation circuit 50 outputs the prediction vector decoded by the vector decoding circuit 86 and the pixel which is inverse DCT by the inverse DCT circuit 88. Further, the processing proceeds to step S30. In step S26, in the case where it is judged that Reg_REQ_B is not 1, In step S28, the motion compensation circuit 50 determines whether Reg_REQ_C is 1. In the case where it is judged that Reg_REQ_C is not 1 in step S28, the processing returns to step S2 2, and the subsequent processing is repeated. In S28, when Reg - REQ - C = 1 is judged, in step S29, the motion compensation circuit 50 transmits an ACK signal to the division decoder 49, and Reg_REQ_C = 0. The division decoder 49 outputs the motion compensation circuit 50. Vector solution The prediction vector of the circuit 90 is decoded, and the pixel of the inverse DCT circuit 92 is inverted DCT. Further, the processing proceeds to step S30. In step S30, the motion compensation circuit 50 determines that one of the division decoders 47 to 49 is input. Whether the large block uses motion compensation. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative is printed in step S30, and in the case where it is judged that the large block uses motion compensation, in step S31, the motion compensation circuit 50 is input large. The block performs motion compensation. That is, the motion compensation circuit 50 follows the prediction vector output by the corresponding decoder among the split decoders 47 to 49, such as the pixel data as luminance data, and transmits the luminance buffer control circuit 5 1 . The reference pixel is read by the luminance buffer 71, and if the pixel data is color difference data, the reference pixel data is read by the color difference buffer 72 through the color difference buffer control circuit 52. Moreover, the motion compensation circuit 5 will read out The reference pixel data is applied to one of the paper scales by the segmentation decoders 47 to 49. The Chinese National Standard (CNS) A4 specification (210X297 mm) -34- 127284 9 A7 ____ B7 V. Invention Description (32) Supply pixel data, perform motion compensation. (Please read the back note and then fill in this page.) The motion compensation circuit 50 will perform motion compensation pixel data, such as the pixel data. The brightness data is written into the brightness buffer 71 through the brightness buffer control circuit 51. If the pixel data is color difference data, the color difference buffer control circuit 52 writes the color difference buffer 72 to prepare for display output. For this reason, the pixel data is set as a reference material for other pixels. Moreover, the processing returns to step S22, and the subsequent processing is repeated. In the step S30, when it is determined that the large block does not use the motion compensation, in step S32, the motion compensation circuit 50 writes the luminance buffer 71 through the luminance buffer control circuit 51 if the pixel data is the luminance data. If the pixel data is color difference data, the color difference buffer 72 is written into the color difference buffer 72 by the color difference buffer control circuit 52, and is prepared for the display output, and is prepared for the case where the pixel data is set as the reference material of other pixels. Moreover, the processing returns to step S22, and the subsequent processing is repeated. Fig. 19 is a view showing a specific example of the adjustment processing of the decoder by the motion compensation circuit 50 explained using Fig. 18. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative is printed in the timing C shown in Fig. 19. By the processing of step S22 of Fig. 18, the decoders 47 to 49 are divided in the case where the registers of the determined action compensation circuit 50 are all zero. After all the REQ signals are output, by the processing of step S23, the individual registers are updated to Reg_REQ_A=l, Reg_REQ_B = l, Reg_REQ_C = l. Further, by the processing of step S24, it is judged that Reg_REQ_A = 1. In step S25, the motion compensation circuit 50 outputs an ACK signal to the division decoder 47, and Reg - REQ_A = 0, and the prediction is accepted by the division decoder 47. Vector and pixel input, motion compensation 1 ° 35- This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) 1272849 A7 B7 V. Invention description (33 After the action compensation 1 is finished, ie, Figure 1 In the timing indicated by D of 9, the processing returns to step S22 again. In the timing shown by D in the figure, the REQ signal is output by the division decoder 47. However, the register is RegReg_REQ_A = 0,
Reg —REQ—1、Reg —REQ_C = 1，於步驟S22中，寄存器之値被判 斷爲並非全部爲0之故，處理進入步驟S24,寄存器之値不被 更新。 於步驟S24中，被判斷爲Reg__REQ_A = 0,於步驟S26中，被 判斷爲Reg_REQ — B = l之故，動作補償電路50於步驟S27中， 對分割解碼器48輸出ACK信號，設Reg_REQ_B = 0,由分割解 碼器48接受預測向量與像素之輸入，進行動作補償2。 動作補償2終了後，即，於圖1 9之E所示之定時中，處理 再度返回步驟S22。於圖中E所示之定時中，REQ信號也由 分割解碼器47被輸出。但是，寄存器之値爲Reg_REQ_A = 0 、Reg一REQ_B = 0、Reg_REQ_C= 1 之故，於步驟 S22 中，寄存 器之値被判斷爲不全爲0之故，與圖中D所示之定時時相同， 寄存器之値不被更新。 而且，於步驟S24中，被判斷爲Reg_REQ„_A=：0,於步驟S26 中，被判斷爲Reg_REQ_B = 0,於步驟S28中，被判斷爲 Reg_REQ_C = l之故，動作補償電路50於步驟S29中，對分割解 碼器49輸出ACK信號，設Reg_REQ_C = 0,由分割解碼器49接 受預測向量與像素之輸入，進行動作補償3。 動作補償3終了後，即，於圖19之F所示之定時中，處理 再度返回步驟S22 。在以F所示之定時中，寄存器之値爲 Reg一REQ一A = 0、Reg_REQ —B = 0、Reg_REQ — C = 0 之故，於步驟 ·-丨J -#衣—丨 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -36- 1272849 A7 B7 五、發明説明（34 ) S23中，寄存器之値被更新，成爲 Reg__REQ_A=l 、 Reg—REQ一B=1 、 Reg_REQ_C=0 。 (請先聞讀背面之注意事項再填寫本頁) 而且，於步驟S24中，被判斷爲Reg_REQ_A=l，藉由同樣 之處理，實行動作補償4。 藉由重複此種處理，動作補償電路5 0 —面調停分割解碼 器47至49,一面進行動作補償。 如以上說明般地，於圖1 5之Μ P E G視頻解碼器中，藉由設 置開始碼緩衝器62,可以使畫像解碼器45至分割解碼器49 不等待相互之動作的終了，存取流緩衝器61 。又，分割解碼 器47至49藉由分割解碼器控制電路46之處理，可以使之同 時動作。進而，動作補償電路30可以適當選擇1個之分割解 碼器，存取分別被分離之亮度緩衝器71以及色差緩衝器72, 進行動作補償。因此，於圖15之MPEG視頻解碼器中，解碼處 理性能以及對緩衝器之存取性能被提升，對於2:4:4P@HL之 解碼處理變成可能。 接著，說明被輸入圖15之MPEG視頻解碼器之MPEG流 被解碼再生之情形的訊框之緩衝。 經濟部智慧財產局員工消費合作社印製 圖20係顯示具備圖15之MPEG視頻解碼器之再生裝置 之構成之方塊圖。又，對於與圖1 5之情形對應之部份賦予相 同標號，適當省略其說明。 MPEG編碼流被記錄在硬碟1 1 2。伺服電路1 1 1依據控 制器34之控制，驅動硬碟112,藉由未圖示出之資料讀取部被 讀出之MPEG流被輸入IC31之再生電路121。 再生電路1 2 1係包含利用圖1 5說明之流輸入電路4 1至 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 五、發明説明（35 ) (請先閲讀背面之注意事項再填寫本頁) 時脈產生電路44之電路，在順方向之再生時，以被輸入之順 序將MPEG流當成再生流輸出於MPEG視頻解碼器122。而 且，於反方向之再生（逆轉再生）時，利用流緩衝器61，將被輸 入之MPEG編碼流置換爲適合逆轉再生之順序後，當成再生 流輸出於MPEG視頻解碼器122。 MPEG視頻解碼器122係包含利用圖15說明之畫像解 碼器45至顯示輸出電路53之電路，藉由動作補償電路50之 處理，因應需要，將被儲存在視頻緩衝器33之被解碼的訊框 當成參考畫像讀出，實行動作補償，將被輸入之再生流之各畫 像（訊框）以上述方法解碼，儲存於視頻緩衝器33之同時，藉由 顯示輸出電路53之處理，依序讀出被儲存在視頻解碼器33 之訊框，輸出、顯示於未圖示出之顯示部或顯示裝置。 經濟部智慧財產局員工消費合作社印製 此處，雖以解碼、輸出被儲存在硬碟1 1 2之MPEG編碼 流而使之顯示之情形爲例做說明，但是具備圖1 5之MPEG視 頻解碼器之再生裝置、或錄影再生裝置即使與圖20所示構 成爲不同之構成（例如，使MPEG視頻解碼器122具備與流緩 衝器61同樣地，保持編碼流之機能、以及與再生電路121同 樣地，置換訊框之機能之構成），基本上藉由同樣之處理，被輸 入之MPEG編碼流被解碼、輸出。 又，儲存編碼流之儲存媒體在硬碟112以外，不用說也可 以利用光碟、磁碟、光磁碟、半導體記憶體、磁帶等各種 之記錄媒體。 利用圖21以及圖22說明MPEG預測編碼畫像之畫像構 成。 -38- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（36 ) 圖2 1係顯示被輸入於未圖示出之編碼器（編碼裝置）被 編碼之MPEG視頻信號之畫像構成圖。訊框12係內部編碼 訊框（I畫像），不參考其它之畫像，被進行編碼。此種訊框雖 然提供解碼之開始點之編碼順序之存取點，但是其壓縮率不 太高。 訊框P 5、訊框P 8、訊框P b以及訊框P e係前方向預測 編碼訊框（P畫像），藉由由過去之I畫像或P畫像之動作補償 預測，進行比I畫像更有效率之編碼。P畫像本身也被當成 預測之參考而使用。訊框B3、訊框B4…訊框Bd係雙方向 預測編碼訊框，與I畫像、P畫像比較，雖然可以更有效率進 行壓縮，但是在動作補償上，需要過去以及將來之雙方之參考 畫像。B畫像不被當成預測之參考而使用。 圖22係顯示爲了產生利用圖2 1說明之瀏覽程式1 1編 碼畫像，利用以未圖示出之編碼器所實行之訊框間預測之瀏 覽程式11視頻信號之編碼例。 被輸入之視頻信號例如每15訊框被分割爲G〇P(Group of Pictures),由各G〇P之開始至第3號被設爲I畫像，以下，每 3訊框出現之訊框被設爲P畫像，其以外之訊框被設爲B畫像 (M = 15、N = 3)。而且，在編碼需要後方預測之B畫像之訊框 B 1 0以及訊框B 1 1被暫時保存在緩衝器，I畫像之訊框Π 2被 最先編碼。 訊框112之編碼之終了後，被暫時保存於緩衝器之訊框 B 10以及訊框B11以訊框112爲參考畫像被編碼。B畫像雖 本來應該參考過去與將來之兩方之參考畫像而被編碼，但是 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -39- 1272849 經濟部智慧財產局員工消費合作社印製 -40- A7 B7 五、發明説明（37 ) 如訊框B 1 0以及訊框B 1 1般地，在前方向無可以參考之畫像 之情形，立起Closed GOP旗標，不做前方向預測，只以後方向 之預測進行編碼。 在訊框B 1 0以及訊框B 1 1之編碼被進行之間被輸入之 訊框B 1 3以及訊框B 1 4被儲存在視頻緩衝器，接著被輸入之 訊框P15將訊框Π2當成前方向預測畫像參考，被編碼。而 且，由視頻緩衝器被讀出之訊框B 1 3以及訊框B 1 4將訊框11 2 當成前方向預測畫像參考，將訊框P15當成後方向預測畫像 參考而被編碼。 接著，訊框B16以及訊框B17被儲存在視頻緩衝器，以下， 依序同樣爲之，P畫像將前次被編碼之I畫像，或P畫像當成 前方向預測畫像參考而被編碼，B畫像一旦被儲存在視頻緩 衝器後，將以前被編碼之I畫像、或P畫像當成前方向預測 畫像或後方向預測畫像參考而被編碼。 如此爲之，經過複數之GOP,畫像資料被編碼，產生編碼 流。以上述方法被編碼之MPEG編碼流被記錄在圖20之硬 碟 112。 編碼時，藉由DCT轉換所獲得之DCT係數行列在將通常 之畫像轉換爲DCT之情形，具有於低頻成分大、在高頻成分 小之特徵。利用此特徵，謀求資訊之壓縮爲量子化（對於各 DCT係數，以某量子化單位分割，化整小數點以下）。量子化 單位被設定爲8x8之量子化表，對於低頻成分被設定爲小的 値，對於高頻成分被設定爲大的値。量子化之結果，灯列之左 上以外之成分幾乎都成爲〇 ◦而且，對應量子化矩陣之量子 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） — 丨 — — 丨一φ裝！ IJ I丨訂！ — _ (請先閱讀背面之注意事項再填寫本頁) 1272849 A7 _ B7 五、發明説明（38 ) (請先閱讀背面之注意事項再填寫本頁) 化ID被附加於壓縮資料，被傳達於解碼側。即，圖20之 MPEG視頻解碼器122由量子化ID參考量子化矩陣，解碼 MPEG編碼流。 接著，利用圖23說明在由硬碟1 1 2以順方向再生視頻資 料之情形，GOP1至GOP3之編碼流被輸入再生電路121，藉由 MPEG視頻解碼器122之處理被解碼之處理。 爲了順方向再生，由硬碟1 1 2被輸入再生電路1 2 1之 MPEG視頻流藉由再生電路121之處理，當成與被輸入之順序 相同之畫像排列之再生流，被輸出於MPEG視頻解碼器122 。於MPEG視頻解碼器122中，再生流依循利用圖15至圖19 說明之順序被解碼，被儲存在視頻緩衝器33。 最初被輸入之訊框11 2爲I畫像之故，解碼時不需要參考 畫像。在MPEG視頻解碼器122中，被解碼之訊框112被儲存 之視頻緩衝器33內之緩衝器區域視爲緩衝器1。 經濟部智慧財產局員工消費合作社印製 接著，被輸入MPEG視頻解碼器122之訊框B10以及訊框 B 1 1雖係B畫像，但是Closed GOP旗標站立之故，將被儲存在 視頻緩衝器3 3之緩衝器1之訊框11 2當成後方向參考畫像 參考而被解碼，被儲存在視頻緩衝器3 3 。將被解碼之訊框 B 1 0被儲存之緩衝器區域當成緩衝器3。 而且，藉由顯示輸出電路5 3之處理，訊框B 1 0由視頻緩 衝器33之緩衝器3被讀出，被輸出、顯示於未圖示出之顯示 部。而且，接著被解碼之訊框B11被儲存（即，寫入緩衝器3) 於視頻緩衝器3 3之緩衝器3之後，被讀出，被輸出、顯示於未 圖示出之顯示部。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ ' -- 1272849 A7 B7 五、發明説明（39 ) (請先閲讀背面之注意事項再填寫本頁) 接著，訊框112由緩衝器1被讀出，被輸出、顯示於未圖 示出之顯示部，以該定時，接著之訊框P1 5將被儲存在視頻緩 衝器33之緩衝器1之訊框112當成參考畫像被解碼，被儲存 在視頻緩衝器3 3之緩衝器2。 在訊框B 10以及訊框B11沒有站立Closed GOP旗標之 情形，在前方向沒有可以參考之畫像之故，訊框B 10以及訊框 B11未被解碼。在該情習力訊框112在最初由顯示輸出電路 5 3被輸出、顯示。 經濟部智慧財產局員工消費合作社印製 接著被輸入之訊框B13以被儲存在視頻緩衝器33之緩 衝器1之訊框112爲前方向參考畫像，以被儲存在緩衝器2之 訊框P15爲後方向參考畫像參考之而被解碼，被儲存在緩衝 器3。而且，藉由顯示輸出電路53之處理。訊框B13由視頻 緩衝器33之緩衝器3被讀出，在輸出顯示處理被實行之間，接 著被輸入之訊框B 14以被儲存在視頻緩衝器33之緩衝器1 之訊框112爲前方向參考畫像，以被儲存在緩衝器2之訊框 P15爲後方向參考畫像參考之而被解碼，被儲存在緩衝器3 。而且，藉由顯示輸出電路53之處理，訊框B 14由視頻緩衝 器33之緩衝器3被讀出，被輸出、顯示。 接著被輸入之訊框P 1 8以被儲存在緩衝器2之訊框P 1 5 爲前方向參考畫像被解碼。訊框B14之解碼如終了，被儲存 在緩衝器1之訊框Π2之後不被參考之故，被解碼之訊框P1 8 被儲存在視頻緩衝器33之緩衝器1。而且，以訊框P 1 8被儲 存在緩衝器1之定時，訊框P15由緩衝器2被讀出、被輸出 、顯示。 -42- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 1272849 A7 ___B7 五、發明説明（4〇 ) 以下，同樣地，GOP1之訊框依序被解碼，被儲存在緩衝器 1至3,依序被讀出、顯示。 (請先閲讀背面之注意事項再填寫本頁) GOP2之前端的訊框122被輸入時，I畫像之訊框122解 碼時不需要參考畫像之故，原樣地被解碼，被儲存在緩衝器2 。以該定時，GOP1之訊框Pie被讀出、被輸出、顯示。 接著被輸入之GOP2之訊框B20以及訊框B21將緩衝器 1之訊框Pie當成前方向參考畫像、將緩衝器2之訊框122 當成後方向參考畫像被解碼，被依序儲存在緩衝器3 、被讀 出、顯示。如此，位於GOP前端之B畫像以之前的G〇P之P 畫像爲前方向參考畫像被解碼。 以下，同樣地GOP2之訊框依序被解碼，被儲存在緩衝器 1至3,依序被讀出、顯示。而且，同樣爲之，GOP3以下之個別 之訊框被依序解碼，被儲存在緩衝器1至3,依序被讀出、顯 不 ° 於以上之處理中，MPEG視頻解碼器122參考量子化ID， 實行解碼處理。 經濟部智慧財產局員工消費合作社印製 接著，說明於利用圖20說明之再生裝置中，實施逆轉再 生之情形。 於習知之逆轉再生中，只取出I畫像實行解碼之故，只有 15訊框.中之1訊框被顯示，只能獲得不自然之再生畫像。 相對於此，在圖20之再生電路1 2 1中，依據被記錄於開始 碼緩衝器62之開始碼，可以變更被輸入流緩衝器61之GOP 之訊框的順序以產生再生流，可以使MPEG視頻解碼器1 22 解碼15訊框之全部。 -43- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1272849 A7 B7 五 、發明説明（41 但是，再生電路121爲了進行逆轉再生，並非只是依據被 S己錄在開始碼緩衝器62之開始碼，單純使被輸入流緩衝器6 1 之GOP之訊框的順序逆轉，產生再生流即可。 例如，使利用圖22說明MPEG編碼流之G0P2以及G〇P1 逆轉再生之情形，最初被輸出、顯示之訊框雖然不得不爲訊 框P2e，但是爲了解碼訊框P2e，作爲前方向參考畫像，需要參 考訊框P 2 b，進而爲了解碼訊框P 2 b，作爲前方向參考畫像需 要訊框P28。爲了解碼訊框P28也需要前方向參考畫像之故 ，結果爲：爲了解碼訊框P2e、使之輸出顯示，G0P2之I畫像 以及P畫像全部需要被解碼。 逆轉再生時爲了解碼最初被顯示之訊框P2e，全部解碼 G0P2,使之儲存在視頻緩衝器33,由後面之訊框依序讀出之 方法雖也可考慮，但是在該情形，視頻緩衝器33需要1G〇P( 15 訊框）份之緩衝器區域。 又，在此方法中，雖然可由訊框P2e至訊框122爲止解碼 再生，但是爲了解碼G0P2之開始之2訊框，即逆轉再生時，應 在最後被顯示之訊框之訊框B21以及訊框B20,作爲前方向 參考畫像需要G0P1之訊框Pie 。爲了解碼G0P1之訊框 Ple，需要G0P1之全部的I畫像以及P畫像。 良卩，在此方法中，雖然於視頻緩衝器33需要15訊框份之 緩衝器區域，但是卻無法進行1 GOP份之全部的訊框之逆轉 再生。 如利用圖22說明般地，以M=15、N = 3進行編碼之情形， 在1G0P內包含合計5訊框之I畫像或P畫像。 丨. · τ---衣-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -44- 1272849 A7 ________B7 五、發明説明（42 ) 因此，使得流緩衝器6 1至少可以儲存2G〇P份之訊框，依 據MPEG視頻解碼器122之逆轉再生用之解碼順序決定於再 生電路121中被產生之再生流之訊框之順序，藉由於視頻緩 衝器33至少儲存以「被包含在1G0P之I畫像以及P畫像之 合計+2」所表示之數目的訊框（例如，在逆轉再生M = 15 、 N = 3之MPEG編碼流之情形，爲7訊框），跨過G〇P之部份也連 續、可以逆轉再生全部之訊框。 利用圖24說明由硬碟1 12，G〇P1至G0P3之畫像資料被 逆轉再生之情形的解碼處理。 控制器34控制伺服電路111，由硬碟112首先使G0P3,接 著，G0P2之MPEG編碼流輸出於再生電路121 。再生電路 121使G0P3,接著，G0P2之MPEG編碼流儲存在流緩衝器61 〇 再生電路121由流緩衝器61讀出G0P3之前端訊框13 2, 當成再生流之最初的訊框，輸出於MPEG視頻解碼器122。 訊框132爲I畫像之故，爲了解碼之故，不需要參考畫像之故， 於MPEG視頻解碼器122被解碼，被儲存在視頻緩衝器33。 於視頻緩衝器33中，將被解碼之訊框132被儲存之區域當成 緩衝器1。 此處，個別之訊框之資料以被記載於利用圖2說明之頭 部以及擴張資料之參數爲基礎被解碼。如上述般地，於 MPEG視頻解碼器122之畫像解碼器45中，個別之參數被解 碼，被供給於分割解碼器控制電路46,被使用於解碼處理。 G0P1被解碼之情形，利用被記載於G0P1之sequence_header 本紙張尺度適用中周國家標準（CNS ) A4規格（210X 297公釐） ^ Ϊ-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 1272849 A7 ____B7 五、發明説明（43 ) (請先閲讀背面之注意事項再填寫本頁) 、sequence_extension 、以及 G〇P_ header之上位層之參婁女（ 例如，上述之量子化矩陣），實施解碼，在G0P2被解碼之情形， 利用被記載於 G0P2 之 sequence_headei·、 sequence_extension、以及GOP_header之上位層之參數，實施 解碼，在G0P3被解碼之情形，利用被記載於G0P2之 sequence_header、 sequence_extension、以及 GOP header 之 上位層之參數，實施解碼。 但是，於逆轉再生時，並非每一 GOP被實施解碼之故 ，MPEG視頻解碼器122於個別之GOP中，於最初I畫像被解 碼時，將上位層參數供給於控制器3 4。控制器3 4於內部具 有之未圖示出之記憶體保持被供給之上位層參數。 控制器34監視於MPEG視頻解碼器122中被實行之解 碼處理，由內部之記憶體讀出對應解碼處理中之訊框之上位 層參數，供給於MPEG視頻解碼器122,以進行適當之解碼處 理。 經濟部智慧財產局員工消費合作社印製 圖24中被顯示於再生流之訊框號碼之上部的數字係量 子化ID，再生流之各訊框與利用圖23說明之順方向之解碼 相同地，以量子化ID爲基礎被解碼。 又，於本實施形態中，雖以控制器34於其內部具有記憶 體，作爲保持上位層編碼參數而說明，但是也可以設置被接續 於控制器34之記憶體，控制器34內部不保有記憶體，在外部 之記憶體保持上位層編碼參數，因應需要而讀出，供給於 MPEG視頻解碼器122。 又，也可以使MPEG視頻解碼器122具備保持G〇P之上 本紙張尺度適财國辭鮮（CNS ) A4規格（21GX297公釐) ~ 1272849 A7 _______ B7 五、發明説明（44 ) (請先閱讀背面之注意事項再填寫本頁) 位層編碼參數用之記憶體◦進而，在上位層編碼參數等之編 碼條件爲已知之情形，也可以預先在MPEG視頻解碼器1 22 設定編碼條件，在上位層編碼參數不因GOP而變化爲已知之 情形，不須藉由控制器34每一 G〇P地讀出上位層編碼參數， 每一訊框地設定於MPEG視頻解碼器122,在動作開始時只要 一次在MPEG視頻解碼器122設定編碼參數即可。 再生電路121由流緩衝器61讀出訊框P35,作爲再生流 之下一訊框輸出於MPEG視頻解碼器122。於MPEG視頻解 碼器122中，訊框P35將被記錄於緩衝器1之訊框132當成前 方向參考畫像而被解碼，被儲存在視頻緩衝器33。於視頻緩 衝器33中，將被解碼之訊框P35被儲存之區域設爲緩衝器2 〇 經濟部智慧財產局員工消費合作社印製 再生電路1 2 1由流緩衝器3 1依序讀出訊框P 3 8、訊框 P3b 、以及訊框P3e，當成再生流輸出。這些之P畫像於 MPEG視頻解碼器122中，以一個之前被解碼之P畫像爲前方 向參考畫像而被解碼，被儲存在視頻緩衝器33。於視頻緩衝 器33中，將被解碼之這些P畫像之訊框被儲存之區域設爲緩 衝器3至緩衝器5。 此時，G0P3之I畫像以及P畫像係全部被解碼，被儲存在 視頻緩衝器33之狀態。 接著，再生電路121由流緩衝器61讀出G0P2之訊框 122,當成再生流輸出。於MPEG視頻解碼器122中，I畫像之 訊框122不須參考畫像被解碼，被儲存在視頻緩衝器33。設 被解碼之訊框122被儲存之區域爲緩衝器6。又，以訊框122 本紙張尺度適用中周國家標準（CNS ) A4規格（210X 297公釐） -47- 1272849 A7 B7 五、發明説明（45 ) 被儲存在緩衝器6之定時，G Ο P 3之訊框p 3 e由緩衝器5被讀 出、被輸出，當成逆轉再生之最初的畫像被顯示。 再生電路121由流緩衝器61讀出G0P3之訊框B3d，即在 G0P3之B畫像中，最初應被逆轉再生之訊框，當成再生流輸 出。於MPEG視頻解碼器122中，訊框B3d以緩衝器4之訊框 P3b爲前方向參考畫像、以緩衝器5之訊框P3e爲後方向參 考畫像被解碼，被儲存在視頻緩衝器3 3 。以被解碼之訊框 B3d被儲存之區域爲緩衝器7。 被儲存在緩衝益7之$框B 3 d在進行訊框/區域轉換以 及對輸出視頻同步定時之定時調和後，被輸出、顯示。以與 訊框B 3 d之顯示相同之定時，再生電路1 2 1由流緩衝器6 1讀 出G〇P 3之訊框B 3 c，輸出於Μ P E G視頻解碼器1 2 2。於Μ P E G 視頻解碼器122中，訊框B3c與訊框B3d相同地，以緩衝器4 之訊框P3b爲前方向參考畫像、以緩衝器5之訊框P3e爲後 方向參考畫像被解碼。 先前被解碼、被輸出之訊框B 3 d爲B畫像之故，不被其 它訊框之解碼所參考。因此，被解碼之訊框P3c代替訊框 B 3 d被儲存在緩衝器7 (即，寫入緩衝器7 )，在進行訊框/區域轉 換以及對輸出視頻同步定時之定時調和後，被輸出、顯示。 再生電路121由流緩衝器61讀出〇〇？2之訊框？25,輸出 於MPEG視頻解碼器122。於MPEG視頻解碼器122,G〇P2之 訊框P25以緩衝器6之訊框122爲前方向參考畫像被解碼。 被儲存在緩衝器5之訊框P 3 e從此以後，不被當成參考畫像 利用之故，被解碼之訊框P25代替訊框P3e被儲存在緩衝器5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I. .--^--—衣— I (請先閲讀背面之注意事項再填寫本頁) 、11 經濟部智慧財產局員工消費合作社印製 -48- 1272849 A7 ^_ B7 五、發明説明（46 ) 。而且，於與訊框P25被儲存在緩衝器25相同之定時，緩衝器 4之訊框P3b被讀出、顯示。 (請先閲讀背面之注意事項再填寫本頁) 再生電路121由流緩衝器61讀出G0P3之訊框B3a，當成 再生流輸出。於MPEG視頻解碼器122中，訊框B3a以緩衝器 3之訊框P38爲前方向參考畫像、以緩衝器4之訊框P3b爲 後方向參考畫像被解碼，被儲存在視頻緩衝器33之緩衝器7 〇 被儲存在緩衝器7之訊框B3a在進行訊框/區域轉換以 及對輸出視頻同步定時之定時調和後，被輸出、顯示。以與 訊框B3a之顯示相同之定時，再生電路121由流緩衝器61讀 出G0P3之訊框B39,輸出於MPEG視頻解碼器122 。於 MPEG視頻解碼器122中，訊框B39與訊框B3a相同地，以緩 衝器3之訊框P38爲前方向參考畫像、以緩衝器4之訊框 P3b爲後方向參考畫像被解碼，代替訊框B3a被儲存在緩衝 器7，在進行訊框/區域轉換以及對輸出視頻同步定時之定時 調和後，被輸出、顯示。 經濟部智慧財產局員工消費合作社印製 再生電路121由流緩衝器61讀出G0P2之訊框P28,輸出 於MPEG視頻解碼器122 ◦於MPEG視頻解碼器122中，G0P2 之訊框P28以緩衝器5之訊框P25爲前方向參考畫像被解碼 。被儲存在緩衝器4之訊框P3b從此以後不被當成參考畫像 利甩之故，被解碼之訊框P28代替訊框P3b被儲存在緩衝器4 。而且，以與訊框P28被儲存在緩衝器4相同之定時，緩衝器 3之訊框P38被讀出、顯示。 如此，以G0P2之I畫像或P畫像被解碼，被儲存在緩衝 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -49- 1272849 A7 B7 五、發明説明（46 ) 。而且，於與訊框P 2 5被儲存在緩衝器2 5相同之定時，緩衝器 4之訊框P3b被讀出、顯示。 (請先閲讀背面之注意事項再填寫本頁) 再生電路121由流緩衝器61讀出G〇P3之訊框B3a，當成 再生流輸出。於MPEG視頻解碼器122中，訊框B3a以緩衝器 3之訊框P 3 8爲則方向篸考畫像、以緩衝器4之訊框p 3 b爲 後方向參考畫像被解碼，被儲存在視頻緩衝器33之緩衝器7 〇 被儲存在緩衝器7之訊框B 3 a在進行訊框/區域轉換以 及對輸出視頻同步定時之定時調和後，被輸出、顯示。以與 訊框B 3 a之顯示相同之定時，再生電路1 2 1由流緩衝器6 1讀 出G0P3之訊框B39,輸出於MPEG視頻解碼器122 。於 MPEG視頻解碼器122中，訊框B39與訊框B3a相同地，以緩 衝器3之訊框P3 8爲前方向參考畫像、以緩衝器4之訊框 P3b爲後方向參考畫像被解碼，代替訊框B3a被儲存在緩衝 器7，在進行訊框/區域轉換以及對輸出視頻同步定時之定時 調和後，被輸出、顯示。 經濟部智慧財產局員工消費合作社印製 再生電路121由流緩衝器61讀出G〇P2之訊框P28,輸出 於MPEG視頻解碼器122。於MPEG視頻解碼器122中，GOP2 之訊框P28以緩衝器5之訊框P25爲前方向參考畫像被解碼 。被儲存在緩衝器4之訊框P3b從此以後不被當成參考畫像 利甩之故，被解碼之訊框P28代替訊框P3b被儲存在緩衝器4 。而且，以與訊框P28被儲存在緩衝器4相同之定時，緩衝器 3之訊框P38被讀出、顯示。 如此，以G0P2之I畫像或P畫像被解碼，被儲存在緩衝 本紙張尺度適用中國國家標準（CNS ) A4規格（210父297公釐） -49- 1272849 經濟部智慧財產局員工消費合作社印製 -50- A7 ____ B7 _ 五、發明説明（47 ) 器3 3之定時，G〇P 3之I畫像或p畫像由緩衝器3 3被讀出、 顯示。 以下，同樣爲之，如圖24所示般地，G0P3之剩餘之B畫像 、以及G0P2之剩餘之p畫像以B37、B36、P2b、B34、 B 3 3、P2e之順序被解碼。被解碼之B畫像被儲存在緩衝器 7，依序被讀出、顯。被解碼之G Ο P 2之P畫像依序被儲存在 參考終了之訊框被儲存之緩衝器1至6之其一，已經被儲存 在緩衝器1至6之其一之G0P3之P畫像以該定時，適合於逆 轉再生.之順序地，被讀出於B畫像之間被輸出。 再生電路121由流緩衝器61讀出G0P3之訊框B31，接著 讀出訊框B30,輸出於MPEG視頻解碼器122。於MPEG視頻 解碼器122中，訊框B31以及訊框B30之解碼所必要之前方 向參考畫像之訊框P2e被儲存在緩衝器2、後方向參考畫像 之訊框132被儲存在緩衝器1之故，G〇P3之開始的2訊框，即 逆轉再生時應被最後顯示之訊框也變成可以解碼。 被解碼之訊框B31以及訊框B30依序被儲存在緩衝器7, 在進行訊框/區域轉換以及對輸出視頻同步定時之定時調和 後，被輸出、顯示。 GOP3之全部的訊框由流緩衝器61被讀出後，控制器34 控制伺服電路111，由硬碟112讀出GOP1，使之供給於再生電 路121。再生電路121實行指定之處理，抽出GOP1之開始碼 ，使之記錄於開始碼緩衝器62之同時，將GOP1之編碼流供給 於流緩衝器61而使之儲存之。 接著，再生電路121由流緩衝器61讀出GOP1之訊框 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I---.--^---^裝 I------1T-------0 (請先閱讀背面之注意事項再填寫本頁) 1272849 經濟部智慧財產局員工消費合作社印製 A7 ____ B7 五、發明説明（48 ) II 2,當成再生流，輸出於MPEG視頻解碼器122。訊框112係I 畫像之故，在MPEG視頻解碼器122中，不參考其它畫像被解 碼，代替在此後之處理不被篸考之緩衝器1之訊框13 2，被輸 出、儲存於緩衝器1。此時，訊框P2e由緩衝器2被讀出、被 輸出，G0P2之逆轉再生顯示被開始。 接著，再生電路121由流緩衝器61讀出GOP2之訊框 B2d，即，G0P2之B畫像中，應該最初被逆轉再生之訊框，當成 再生流輸出。於MPEG視頻解碼器122中，訊框B2d以緩衝器 3之訊框P2b爲前方向參考畫像、以緩衝器2之訊框P2e爲 後方向參考畫像被解碼，被儲存在視頻緩衝器33。被解碼之 曰只框B 2 d被儲存在緩衝器7，在進fr訊框/區域轉換以及對輸 出視頻同步定時之定時調和後，被輸出、顯示。 以下，同樣爲止，G0P2之剩餘之B畫像、以及G0P1之剩 餘之 P 畫像，以 B2c、P15、B2a、P18、B27、B26、Plb 、B24、B23、Pie、P21、P20之順序被解碼，依序被儲存 在參考終了之訊框被儲存之緩衝器1至7之其一，以逆轉再 生之順序被讀出、輸出。而且，雖然未圖示出，但是在最後 ，G〇P 1之剩餘之B畫像被解碼，依序被儲存在緩衝器7，以逆 轉再生之順序被讀出、輸出。 在利用圖24說明之處理中，雖然實行以與通常再生相同 速度之逆轉再生，但是再生電路121也可以將再生流以通常 再生時之3分之1之速度輸出於MPEG視頻解碼器 122,MPEG視頻解碼器122以通常之3訊框之處理時間實行 只有1訊框之解碼處理，對未圖示出之顯示部或顯示裝置以 i紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 7, -- .---^---衣--- (請先閲讀背面之注意事項再填寫本頁) 訂 1272849 Α7 Β7 五、發明説明（49 ) 通常之3訊框之顯示時間，顯示同一訊框，3分之1倍速之順 方向再生、以及逆轉再生藉由同樣之處理成爲可能。 (請先閲讀背面之注意事項再填寫本頁) 又，顯示輸出電路5 3藉由重複同一訊框輸出之，所謂之 靜止再生也成爲可能。又，藉由改變由再生裝置121對mpeg 視頻解碼器122之資料輸出速度，以及MPEG視頻解碼器122 之處理速度，可以以任意之n，n分之1倍速之順方向再生、以 及逆轉再生藉由同樣之處理變成可能。 即，於利用本發明之再生裝置中，在等倍速之逆轉再生、 η分之1倍速之逆轉再生、靜止再生、n分之1倍速之順方 向再生、等倍速之順方向再生之間之任意的速度，平滑之特 殊再生都成爲可能。 經濟部智慧財產局員工消費合作社印製 又，MPEG視頻解碼器122爲MPEG2 4:2:2P@HL對應之 解碼器之故，具有以6倍速解碼MPEG2 MP@ML之編碼流之 能力。因此，再生電路121如將由MP@ ML之編碼流所產生之 再生流以通常再生時之6倍的速度輸出於MPEG視頻解碼器 122，MPEG視頻解碼器122具有以6倍速解碼MP@ML之編碼 流之能力之故，藉皮於未圖示出之顯示部、或顯示裝置使顯 示每6訊框被抽出之訊框，6倍速之順方向再生、以及逆轉 再生藉由同樣之處理變成可能。 即，在利用本發明之再生裝置中，在使MP@ML之編碼流 以6倍速之逆轉再生、等倍速之逆轉再生、η分之1倍速之 逆轉再生、靜止再生、η分之1倍速之順方向再生、等倍速 之順方向再生、6倍速之順方向再生之間之任意的速度，平 滑之特殊再生變成可能。 -52 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 1272849 A7 p—______ B7 五、發明説明（50 ) (請先閲讀背面之注意事項再填寫本頁) 又，MPEG視頻解碼器122在具備N倍速之解碼能力之情 形，本發明之再生裝置藉由同樣之處理，在N倍速之順方向再 生、以及逆轉再生變成可能，在N倍速之逆轉再生、等倍速 之逆轉再生、η分之1倍速之逆轉再生、靜止再生、n分之 1倍速之順方向再生、等倍速之順方向再生、Ν倍速之順方 向再生之間的任意的速度，平滑之特殊再生變成可能。 藉由此，例如，在影像信號之查證時，可以容易查證影像 素材之內容，改善影像素材查證作業之效率，在影像信號之編 輯作業中，可以舒適檢索編輯點，能夠改善編輯作業之效率。 上述一連串之處理也可以藉由軟體實行。該軟體係構 成該軟體之程式由記錄媒體被安裝於被組裝在專用之硬體 之電腦、或藉由安裝各種之程式，可以實行各種之機能之例 如泛用之個人電腦等。 經濟部智慧財產局員工消費合作社印製 此記錄媒體如圖1 5或圖20所示般地，係藉由與電腦不 同另外對使用者提供程式而被散發之記錄程式之磁碟1 0 1 ( 包含軟碟）、光碟 1〇2(包含 CD-R〇M(Compact Disk Read Only Memory)、DVD(Digital Versatile Disk))、光磁碟 103(包含 MD(Mini Disk))、或半導體記憶體104等所形成之套件媒體 等而構成。 又，於本詳細說明書中，記述被記錄於記錄媒體之程式的 步驟，當然可以爲沿著被記載之順序時間序列地被進行之處 理，但是也包含不一定要時間序列地被處理，並列或個別地被 實行之處理者。 -53- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 1272849 Μ __ Β7 _ 五、發明説明（51 ) 【發明之效果】 (請先閲讀背面之注意事項再填寫本頁) 如依據本發明之第1解碼裝置、解碼方法、以及程式， 解碼編碼流，使解碼處理並行動作之故，可以實現對應以可以 實現之電路規模能夠實際時間動作之4:2:2P@HL之視頻解 碼器。 如依據本發明之第2解碼裝置、解碼方法、以及程式， 以複數之分割解碼器解碼編碼流，藉由複數之分割解碼器使 解碼處理並行動作之故，可以實現對應以可以實現之電路規 模能夠實際時間動作之4:2: 2P @ HL之視頻解碼器。 【圖面之簡單說明】 圖1係說明依據MPEG2之之外形與級數之各參數之上 限値用之圖。 圖2係說明MPEG2之位元流之階層構造用之圖。 圖3係說明大區塊層用之圖。 圖4係說明sequence_header之資料構造用之圖。 圖5係說明seqUence_extension之資料構造用之圖。 經濟部智慧財產局員工消費合作社印製 圖6係說明G〇P_header之資料構造用之圖。 圖7係說明picture_header之資料構造用之圖。 圖8係說明plcture_cording_extension之資料構造用之 圖。 圖9係說明picture_data之資料構造用之圖。 圖1〇係說明slice之資料構造用之圖。 圖11係說明macroblock之資料構造用之圖。 本紙張尺度適用中周國家標準（CNS ) A4規格（210X297公釐） -54 - 1272849 A7 B7 五、發明説明（52 ) 圖12係說明macroblock_modes之資料構造用之圖。 圖1 3係s兌明開始碼用之圖。 (請先閱讀背面之注意事項再填寫本頁) 圖1 4係顯示解碼習知之ML @ MP之編碼流之視頻解碼 器之構成之方塊圖。 圖1 5係顯示適應本發明之視頻解碼器之構成之方塊圖 〇 圖1 6係說明分割解碼器控制電路之處理用之流程圖。 圖1 7係說明分割解碼器控制電路之處理之具體例用之 圖。 圖1 8係說明藉由動作補償電路之分割解碼器之調停處 理用之流程圖。 圖1 9係說明藉由動作補償電路之分割解碼器之調停處 理之具體例用之圖。 圖20係顯不具備圖15之MPEG視頻解碼器之再生裝置 之構成方塊圖。 圖2 1係顯示被輸入解碼器之被編碼之MPEG視頻信號 之畫像構成圖。 經濟部智慧財產局員工消費合作社印製 圖22係顯示利用訊框間預測之MPEG之畫像編碼之例 圖。 圖23係說明MPEG編碼流於順方向被再生之情形的解 碼處理用之圖。 圖24係說明MPEG編碼流被逆轉再生之情形的解碼處 理用之圖。 -55- 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 29<7公釐） 1272849 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（53 ) 【標號之說明】 31 : 1C 32 :緩衝器 33 :視頻緩衝器 3 4 :控制器 42 :開始碼檢測電路 43 :流緩衝器控制電 45 :畫像解碼器 46 :分割解碼器控制電路 47至49 :分割解碼器 50 :動作補償電路 51 :亮度緩衝器控制電路 52 :色差緩衝器控制電路 61 :流緩衝器 62 :開始碼緩衝器 7 1 :亮度緩衝器 72 :色差緩衝器 111 :伺服電路 112 :硬碟 121 :再生電路 122 : MPEG視頻解碼器 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -56-Reg - REQ - 1, Reg - REQ_C = 1, in step S22, the register is judged to be not all 0, the processing proceeds to step S24, and the register is not updated. In step S24, it is determined that Reg__REQ_A = 0. In step S26, it is determined that Reg_REQ - B = 1. Therefore, in step S27, the motion compensation circuit 50 outputs an ACK signal to the split decoder 48, and sets Reg_REQ_B = 0. The division decoder 48 accepts the input of the prediction vector and the pixel, and performs motion compensation 2. After the motion compensation 2 is terminated, that is, at the timing shown by E in Fig. 19, the processing returns to step S22 again. In the timing shown by E in the figure, the REQ signal is also outputted by the division decoder 47. However, after the register is Reg_REQ_A = 0, Reg_REQ_B = 0, and Reg_REQ_C=1, in step S22, the register is determined to be not all 0, which is the same as the timing shown in D in the figure. The status of the registers is not updated. Further, in step S24, it is determined that Reg_REQ _A =: 0, and in step S26, it is determined that Reg_REQ_B = 0, and in step S28, it is determined that Reg_REQ_C = 1, and the operation compensation circuit 50 is at step S29. The split decoder 49 outputs an ACK signal, and Reg_REQ_C = 0, and the split decoder 49 receives the input of the prediction vector and the pixel, and performs motion compensation 3. After the motion compensation 3 is terminated, that is, as shown in FIG. In the timing, the processing returns to step S22 again. In the timing indicated by F, the register is RegReg_REQ-A = 0, Reg_REQ - B = 0, Reg_REQ - C = 0, in the step - 丨J -#衣-丨(Please read the notes on the back and fill out this page) Order the Ministry of Economic Affairs Intellectual Property Bureau Employees Consumption Cooperatives Print this paper size Applicable to China National Standard (CNS) A4 Specification (210X297 mm) -36- 1272849 A7 B7 V. Inventive Note (34) In S23, the register is updated to become Reg__REQ_A=l, Reg-REQ-B=1, Reg_REQ_C=0. (Please read the back note first and then fill in this page) In step S24, it is determined that Reg_REQ_A=l, By the same processing, the motion compensation 4 is performed. By repeating such processing, the motion compensation circuit 50 adjusts the motion compensation by performing the motion compensation while arranging the split decoders 47 to 49. As described above, the PEG is shown in Fig. 15. In the video decoder, by setting the start code buffer 62, the picture decoder 45 to the division decoder 49 can be made to access the stream buffer 61 without waiting for the mutual operation. Further, the division decoders 47 to 49 are used. The processing of the division decoder control circuit 46 can be simultaneously operated. Further, the motion compensation circuit 30 can appropriately select one of the division decoders, and access the separated luminance buffer 71 and the color difference buffer 72 to perform motion compensation. Therefore, in the MPEG video decoder of Fig. 15, the decoding processing performance and the access performance to the buffer are improved, and the decoding processing for 2:4:4P@HL becomes possible. Next, the MPEG input into Fig. 15 is explained. The buffer of the frame in the case where the MPEG stream of the video decoder is decoded and reproduced. The Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, Printed Figure 20 shows the MPEG video decoder with Figure 15 The same reference numerals are given to the parts corresponding to those in the case of Fig. 15. The description of the MPEG encoded stream is recorded on the hard disk 112. The servo circuit 1 1 1 is based on the controller 34. The control drives the hard disk 112, and the MPEG stream read by the data reading unit not shown is input to the reproduction circuit 121 of the IC 31. The regenerative circuit 1 2 1 includes the flow input circuit 4 1 described in FIG. 15 to the paper scale applicable to the Chinese National Standard (CNS) A4 specification (210×297 mm) 1272849 A7 B7 5. Inventive Note (35) (Read first Note on the back side. The circuit of the clock generation circuit 44 outputs the MPEG stream as a reproduction stream to the MPEG video decoder 122 in the order in which it is input in the forward direction. Further, in the reproduction in the reverse direction (reverse reproduction), the stream buffer 61 is used to replace the input MPEG encoded stream with a sequence suitable for reverse reproduction, and then the reproduced stream is output to the MPEG video decoder 122. The MPEG video decoder 122 includes a circuit of the picture decoder 45 to the display output circuit 53 described with reference to FIG. 15, and the processing of the motion compensation circuit 50, if necessary, the decoded frame to be stored in the video buffer 33. When the reference image is read, motion compensation is performed, and each image (frame) of the input reproduction stream is decoded by the above method, stored in the video buffer 33, and sequentially read by the display output circuit 53. The frame stored in the video decoder 33 is output and displayed on a display unit or display device not shown. Printed by the Ministry of Economic Affairs, the Intellectual Property Office, and the Consumer Cooperatives, although the case of decoding and outputting the MPEG encoded stream stored in the hard disk 112 is displayed as an example, but with the MPEG video decoding of FIG. The reproduction device or the video reproduction device of the device is configured differently from the configuration shown in FIG. 20 (for example, the MPEG video decoder 122 is provided with the same function as the stream buffer 61, and has the same function as the reproduction circuit 121. The configuration of the function of the replacement frame is basically the same processing, and the input MPEG encoded stream is decoded and output. Further, the storage medium storing the encoded stream is other than the hard disk 112, and it is needless to say that various recording media such as a compact disc, a magnetic disk, an optical disk, a semiconductor memory, and a magnetic tape can be used. The image configuration of the MPEG predictive coded image will be described with reference to Figs. 21 and 22 . -38- This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) 1272849 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 5, invention description (36) Figure 2 1 shows the input is not shown An image composition diagram of an MPEG video signal encoded by an encoder (encoding device) is shown. Frame 12 is an internal coded frame (I image) that is encoded without reference to other images. Although such a frame provides an access point for the encoding order of the starting point of decoding, the compression ratio is not too high. Frame P 5, frame P 8 , frame P b, and frame P e are forward-predictive coded frames (P-pictures), which are compared with I images by the prediction of the motion of the past I or P pictures. More efficient coding. The P portrait itself is also used as a reference for prediction. Frame B3, frame B4... Frame Bd is a bidirectional predictive coding frame. Compared with I and P pictures, although it can compress more efficiently, it requires reference images of both past and future in motion compensation. . The B portrait is not used as a reference for prediction. Fig. 22 is a diagram showing an example of encoding of a video signal of a browsing program 11 using an inter-frame prediction performed by an encoder (not shown) in order to generate a coded image of the browsing program 1 1 described with reference to Fig. 21. The input video signal is divided into G〇P (Group of Pictures) for every 15 frames, and the frame is set as an I picture from the beginning of each G〇P to the third frame. Set to P image, the frame other than this is set to B portrait (M = 15, N = 3). Further, the frame B 1 0 and the frame B 1 1 for encoding the B picture requiring rear prediction are temporarily stored in the buffer, and the frame Π 2 of the I picture is encoded first. After the end of the encoding of the frame 112, the frame B 10 and the frame B11 temporarily stored in the buffer are encoded with the frame 112 as a reference picture. The B portrait should have been coded with reference to the reference images of the past and the future, but (please read the notes on the back and fill out this page). This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). -39- 1272849 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed -40- A7 B7 V. INSTRUCTIONS (37) If frame B 1 0 and frame B 1 1 are similar, there is no portrait in the front direction. In the case, the Closed GOP flag is set up, and the forward direction prediction is not performed, and only the prediction of the future direction is encoded. The frame B 1 3 and the frame B 1 4 that are input between the frame B 1 0 and the code of the frame B 1 1 are stored in the video buffer, and then the frame P15 is input to the frame Π 2 When the foreground direction prediction image reference is referenced, it is encoded. Moreover, the frame B 1 3 and the frame B 1 4 read by the video buffer treat the frame 11 2 as a forward direction prediction portrait reference, and encode the frame P15 as a backward direction prediction image reference. Next, the frame B16 and the frame B17 are stored in the video buffer. Hereinafter, the P picture is encoded by the previously encoded I picture or the P picture as the front direction prediction picture reference. Once stored in the video buffer, the previously encoded I picture or P picture is encoded as a forward direction prediction picture or a backward direction prediction picture reference. In this way, after a plurality of GOPs, the image data is encoded to generate a coded stream. The MPEG encoded stream encoded in the above manner is recorded on the hard disk 112 of FIG. At the time of encoding, the DCT coefficient obtained by the DCT conversion is converted into a DCT in the case of converting a normal image into a DCT, and has a feature that the low frequency component is large and the high frequency component is small. With this feature, the compression of information is quantized (for each DCT coefficient, it is divided by a certain quantization unit, and the decimal point is rounded down). The quantization unit is set to an 8x8 quantization table, and the low frequency component is set to a small 値, and the high frequency component is set to a large 値. As a result of the quantization, the components other than the upper left of the lamp column are almost all 〇◦ and the scale of the quantum paper corresponding to the quantization matrix is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) — 丨— —一φ Pack! IJ I booked! — _ (Please read the note on the back and then fill out this page) 1272849 A7 _ B7 V. INSTRUCTIONS (38) (Please read the note on the back and fill out this page) The ID is attached to the compressed data and is communicated to Decoding side. That is, the MPEG video decoder 122 of Fig. 20 decodes the MPEG encoded stream by quantizing the ID reference quantization matrix. Next, a case where the video stream is reproduced in the forward direction by the hard disk 112 will be described with reference to Fig. 23, and the encoded stream of GOP1 to GOP3 is input to the reproduction circuit 121, and the processing by the MPEG video decoder 122 is decoded. In order to reproduce in the forward direction, the MPEG video stream input to the reproducing circuit 1 2 1 from the hard disk 112 is processed by the reproducing circuit 121, and the reproduced stream which is arranged in the same order as the input image is outputted to the MPEG video decoding. 122. In the MPEG video decoder 122, the reproduced stream is decoded in the order described with reference to Figs. 15 through 19, and stored in the video buffer 33. The frame 11 that was originally input is the I picture, and there is no need to refer to the picture when decoding. In the MPEG video decoder 122, the buffer area in the video buffer 33 in which the decoded frame 112 is stored is regarded as the buffer 1. Printed by the Ministry of Economic Affairs, the Intellectual Property Office, and the Consumer Cooperatives. The frame B10 and the frame B 1 1 that are input to the MPEG video decoder 122 are B portraits, but the Closed GOP flag is stored in the video buffer. The frame 11 of the buffer 1 of 3 3 is decoded in the backward direction reference picture reference and stored in the video buffer 3 3 . The buffer area to be decoded B 1 0 is stored as buffer 3. Further, by the processing of the display output circuit 53, the frame B 10 is read by the buffer 3 of the video buffer 33, and is outputted and displayed on a display portion (not shown). Further, the frame B11 to be decoded is stored (i.e., written to the buffer 3) after being buffered by the buffer 3 of the video buffer 33, and is output and displayed on a display unit (not shown). This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) ~ ' -- 1272849 A7 B7 V. Invention description (39 ) (Please read the note on the back and fill in this page) Next, frame 112 The buffer 1 is read, output, and displayed on a display unit (not shown). At this timing, the frame P1 5 is then stored in the buffer 112 of the buffer buffer 33 as a reference image. The decoding is stored in the buffer 2 of the video buffer 33. In the case where the frame B 10 and the frame B11 do not stand the Closed GOP flag, there is no image that can be referred to in the front direction, and the frame B 10 and the frame B11 are not decoded. The behavior signal frame 112 is initially output and displayed by the display output circuit 53. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative prints the frame B13 that is input, and the frame 112 stored in the buffer 1 of the video buffer 33 is the front direction reference image to be stored in the buffer P15 of the buffer 2. It is decoded for the back direction reference picture reference and stored in the buffer 3. Moreover, the processing by the output circuit 53 is displayed. The frame B13 is read by the buffer 3 of the video buffer 33, and between the output display processing is executed, the frame B 14 is then input to be stored in the buffer 112 of the buffer 1 of the video buffer 33. The front direction reference picture is decoded by the frame P15 stored in the buffer 2 as a back direction reference picture reference, and is stored in the buffer 3. Further, by the processing of the display output circuit 53, the frame B 14 is read by the buffer 3 of the video buffer 33, and is output and displayed. The input frame P 1 8 is then decoded with the frame P 1 5 stored in the buffer 2 as the front direction reference picture. If the decoding of the frame B14 is completed, it is stored in the buffer frame 2 of the buffer 1 and is not referred to. The decoded frame P1 8 is stored in the buffer 1 of the video buffer 33. Further, the frame P15 is read, output, and displayed by the buffer 2 at the timing when the frame P 18 is stored in the buffer 1. -42- This paper scale applies to Chinese National Standard (CNS) A4 specification (210X 297 mm) 1272849 A7 ___B7 V. Invention description (4〇) The following, similarly, the GOP1 frame is decoded sequentially and stored in the buffer. The devices 1 to 3 are sequentially read and displayed. (Please read the precautions on the back and fill in this page.) When the frame 122 at the front of the GOP2 is input, the frame 122 of the I picture is decoded without being referenced, and is decoded as it is and stored in the buffer 2. At this timing, the frame Pie of GOP1 is read, output, and displayed. Then, the frame B20 and the frame B21 of the input GOP2 treat the frame Pie of the buffer 1 as a front direction reference image, and the frame 122 of the buffer 2 as a backward direction reference image, and are sequentially stored in the buffer. 3, is read and displayed. Thus, the B picture at the front end of the GOP is decoded with the P picture of the previous G〇P as the front direction reference picture. In the following, the frames of the GOP2 are sequentially decoded, stored in the buffers 1 to 3, and sequentially read and displayed. Moreover, for the same reason, the individual frames below GOP3 are sequentially decoded, stored in buffers 1 to 3, sequentially read and displayed in the above processing, and MPEG video decoder 122 refers to quantization. ID, the decoding process is implemented. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumers' Cooperatives. Next, the case where the reproduction is described in the reproduction device described with reference to Fig. 20 is reversed. In the reversal of the rehearsal, only the I image was taken out for decoding, only 15 frames. The 1st frame is displayed and only the unnatural reproduction portrait can be obtained. On the other hand, in the reproduction circuit 1 2 1 of FIG. 20, the order of the frames of the GOP input to the stream buffer 61 can be changed in accordance with the start code recorded in the start code buffer 62 to generate a reproduction stream, which can make The MPEG video decoder 1 22 decodes all of the 15 frames. -43- This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) 1272849 A7 B7 V. Invention Description (41 However, in order to carry out reverse regeneration, the regenerative circuit 121 is not only based on the S code recorded in the start code buffer. The start code of the device 62 simply reverses the order of the frames of the GOP input to the stream buffer 61 to generate a reproduced stream. For example, the case where the GOP2 and G〇P1 of the MPEG encoded stream are reversely reproduced will be described using FIG. The frame that is initially output and displayed has to be the frame P2e. However, in order to decode the frame P2e, as the front direction reference image, the reference frame P 2 b is required, and in order to decode the frame P 2 b, as the front direction. The reference picture requires the frame P28. In order to decode the frame P28, the front direction reference picture is also required. As a result, in order to decode the frame P2e and output it, the I picture and the P picture of G0P2 need to be decoded. In order to decode the frame P2e that is initially displayed, all of the GOP2 is decoded and stored in the video buffer 33, and the method of sequentially reading out the subsequent frames may be considered, but in this case The video buffer 33 requires a buffer area of 1 G 〇 P (15 frames). Also, in this method, although the frame P2e can be decoded and reproduced from the frame 122, in order to decode the start of the GG2 frame 2 frame In the case of reversing the reproduction, the frame B21 and the frame B20 of the frame to be displayed at the end should be the frame Pie of the G0P1 as the front direction reference picture. In order to decode the frame Ple of the G0P1, all the I pictures of the G0P1 are required. And the P image. In this method, although the buffer area of the 15 frame is required in the video buffer 33, the reverse reproduction of all the frames of 1 GOP cannot be performed. In the case of encoding with M=15 and N=3, an I picture or a P picture of a total of 5 frames is included in 1G0P. · τ---衣-- (Please read the note on the back and fill out this page). The Ministry of Economic Affairs, Intellectual Property Bureau, Staff and Consumer Cooperatives, Printed Paper Size Applicable to China National Standard (CNS) A4 Specification (210X297 mm) - 44- 1272849 A7 ________B7 V. Inventive Description (42) Therefore, the stream buffer 61 can be configured to store at least 2G frames, and the decoding order for the reverse reproduction of the MPEG video decoder 122 is determined by the reproduction circuit 121. The sequence of the frame of the generated regenerated stream is obtained by the video buffer 33 storing at least the number of frames indicated by "the total image of the 1G0P and the P image +2" (for example, in reversing the reproduction M). = 15 , N = 3 MPEG encoded stream in the case of 7 frames), across the G 〇 P part of the continuous, can be reversed to regenerate all frames. The decoding process in the case where the portrait data of the hard disk 1 12, G〇P1 to GOPO3 is reversely reproduced will be described with reference to FIG. The controller 34 controls the servo circuit 111, and the hard disk 112 first causes GP3, followed by the MPEG encoded stream of GOP2 to be output to the reproduction circuit 121. The reproduction circuit 121 stores the GOP3, and then the MPEG encoded stream of the GOP2 in the stream buffer 61. The reproduction circuit 121 reads the front frame 13 of the GOP3 from the stream buffer 61, and outputs the original frame as the reproduction stream to the MPEG. Video decoder 122. The frame 132 is an I picture. For decoding purposes, the reference picture is not required, and is decoded by the MPEG video decoder 122 and stored in the video buffer 33. In the video buffer 33, the area in which the decoded frame 132 is stored is regarded as the buffer 1. Here, the data of the individual frames is decoded based on the parameters described in the header and the expanded data described with reference to Fig. 2 . As described above, in the picture decoder 45 of the MPEG video decoder 122, the individual parameters are decoded, supplied to the division decoder control circuit 46, and used for the decoding process. When G0P1 is decoded, use the sequence_header recorded in G0P1. This paper size applies to the National Standard (CNS) A4 specification (210X 297 mm) ^ Ϊ-- (Please read the note on the back and fill in this page) Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 1272849 A7 ____B7 V. Invention Description (43) (Please read the note on the back and fill out this page), sequence_extension, and the G〇P_ header above the ginseng (for example In the case where G0P2 is decoded, the decoding is performed using the parameters of the sequence layer of sequence_headei·, sequence_extension, and GOP_header described in G0P2, and the case is decoded when G0P3 is decoded. Decoding is performed on the parameters of the sequence layer above the sequence_header, sequence_extension, and GOP header of G0P2. However, in the case of reverse reproduction, not every GOP is decoded. The MPEG video decoder 122 supplies the upper layer parameters to the controller 34 in the individual GOPs when the first I picture is decoded. The memory of the controller 34, which is not shown, remains supplied to the upper layer parameters. The controller 34 monitors the decoding process performed in the MPEG video decoder 122, reads the bit layer parameters of the frame in the corresponding decoding process from the internal memory, and supplies it to the MPEG video decoder 122 for appropriate decoding processing. . The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative prints the digital quantized ID displayed on the upper part of the frame number of the regenerative stream in Fig. 24, and the frames of the regenerative stream are identical to the decoding in the forward direction described with reference to Fig. 23. It is decoded based on the quantized ID. Further, in the present embodiment, the controller 34 has a memory therein and is described as holding the upper layer encoding parameter. However, the memory connected to the controller 34 may be provided, and the controller 34 does not have a memory inside. The upper layer coding parameters are held in the external memory, and are read out as needed, and supplied to the MPEG video decoder 122. Further, the MPEG video decoder 122 may be provided with a paper size of the above-mentioned paper size (CNS) A4 specification (21GX297 mm) ~ 1272849 A7 _______ B7 5. Invention description (44) (Please first Read the notes on the back page and fill in this page.) The memory used for the bit layer coding parameters. In the case where the coding conditions of the upper layer coding parameters are known, the coding conditions can be set in advance in the MPEG video decoder 1 22 . The upper layer coding parameters are not changed to be known by the GOP. It is not necessary to read the upper layer coding parameters by the controller 34, and each frame is set to the MPEG video decoder 122, and the operation starts. It is only necessary to set the encoding parameters in the MPEG video decoder 122 once. The reproduction circuit 121 reads out the frame P35 from the stream buffer 61, and outputs it to the MPEG video decoder 122 as a frame below the reproduction stream. In the MPEG video decoder 122, the frame P35 is decoded by the frame 132 recorded in the buffer 1 as a front direction reference picture, and stored in the video buffer 33. In the video buffer 33, the area in which the decoded frame P35 is stored is set as the buffer 2. The Ministry of Economic Affairs, the Intellectual Property Office, the employee consumption cooperative, and the reproduction circuit 1 2 1 are sequentially read by the stream buffer 3 1 . The frame P 3 8 , the frame P3b , and the frame P3e are output as a regenerative stream. These P pictures are decoded by the MPEG video decoder 122 as a forward reference picture by a previously decoded P picture, and are stored in the video buffer 33. In the video buffer 33, the area in which the frames of the P pictures to be decoded are stored is set as the buffer 3 to the buffer 5. At this time, all of the I picture and the P picture of the GOP 3 are decoded and stored in the state of the video buffer 33. Next, the reproduction circuit 121 reads out the frame 122 of the GOP2 from the stream buffer 61, and outputs it as a reproduction stream. In the MPEG video decoder 122, the frame 12 of the I picture is stored in the video buffer 33 without being decoded by the reference picture. The area in which the decoded frame 122 is stored is the buffer 6. Also, the frame 122 is applied to the paper size of the Chinese National Standard (CNS) A4 specification (210X 297 mm) -47-1272849 A7 B7 5. The invention description (45) is stored at the timing of the buffer 6, G Ο P The frame p 3 e of the frame 3 is read and output by the buffer 5, and the first image which is reproduced as the reverse is displayed. The reproduction circuit 121 reads out the frame B3d of the GOP3 from the stream buffer 61, i.e., in the B picture of the G0P3, the frame which should be reversely reproduced first is output as a reproduction stream. In the MPEG video decoder 122, the frame B3d is decoded by using the frame P3b of the buffer 4 as the forward direction reference picture and the frame P3e of the buffer 5 as the backward direction reference picture, and is stored in the video buffer 33. The area in which the decoded frame B3d is stored is the buffer 7. The frame B 3 d stored in the buffer 7 is output and displayed after the frame/area conversion and the timing of the output video synchronization timing are adjusted. At the same timing as the display of the frame B 3 d , the reproduction circuit 1 1 1 reads the frame B 3 c of the G 〇 P 3 from the stream buffer 6 1 and outputs it to the E P E G video decoder 1 2 2 . In the P E G video decoder 122, the frame B3c is the same as the frame B3d, and the frame P3b of the buffer 4 is referred to as the front direction reference picture, and the frame P3e of the buffer 5 is decoded as the backward direction reference picture. The frame B 3 d that was previously decoded and output is a B picture and is not referenced by the decoding of other frames. Therefore, the decoded frame P3c is stored in the buffer 7 (i.e., the write buffer 7) instead of the frame B3d, and is output after the frame/area conversion and the timing of the output video synchronization timing are adjusted. ,display. The reproduction circuit 121 is read by the stream buffer 61? 2 frame? 25, output to MPEG video decoder 122. In the MPEG video decoder 122, the frame P25 of the frame P2 is decoded with the frame 122 of the buffer 6 as the front direction reference picture. The frame P 3 e stored in the buffer 5 is not used as a reference image, and the decoded frame P25 is stored in the buffer 5 instead of the frame P3e. The paper size applies to the Chinese National Standard (CNS). A4 size (210X297 mm) I. . --^---衣衣 I (Please read the notes on the back and fill out this page), 11 Printed by the Intellectual Property Office of the Ministry of Economic Affairs, Consumers' Cooperatives -48- 1272849 A7 ^_ B7 V. Inventions (46). Further, at the same timing as the frame P25 is stored in the buffer 25, the frame P3b of the buffer 4 is read and displayed. (Please read the precautions on the back side and fill in this page.) The reproduction circuit 121 reads the frame B3a of the GOP3 from the stream buffer 61, and outputs it as a reproduction stream. In the MPEG video decoder 122, the frame B3a is buffered with the frame P38 of the buffer 3 as the forward direction reference picture, and the frame P3b of the buffer 4 is decoded for the backward direction reference picture, and is stored in the buffer of the video buffer 33. The buffer 7 is stored in the buffer B, and the frame B3a is output and displayed after the frame/area conversion and timing of the output video synchronization timing are adjusted. At the same timing as the display of the frame B3a, the reproduction circuit 121 reads the frame B39 of the GOP3 from the stream buffer 61, and outputs it to the MPEG video decoder 122. In the MPEG video decoder 122, the frame B39 is the same as the frame B3a, and the frame P38 of the buffer 3 is used as the front reference image, and the frame P3b of the buffer 4 is decoded as the backward direction reference image. The block B3a is stored in the buffer 7, and is output and displayed after the timing of the frame/area conversion and the timing of the output video synchronization. The Ministry of Economic Affairs Intellectual Property Office staff consumption cooperative printing reproduction circuit 121 reads the frame P28 of the GOP2 from the stream buffer 61, and outputs it to the MPEG video decoder 122 in the MPEG video decoder 122, and the frame P28 of the G0P2 buffer. The frame P25 of 5 is decoded for the front direction reference picture. The frame P3b stored in the buffer 4 is not regarded as a reference image since then, and the decoded frame P28 is stored in the buffer 4 instead of the frame P3b. Further, the frame P38 of the buffer 3 is read and displayed at the same timing as the frame P28 is stored in the buffer 4. In this way, the I picture or P picture of G0P2 is decoded and stored in the buffer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -49-1272849 A7 B7 5. Inventive Note (46). Further, the frame P3b of the buffer 4 is read and displayed at the same timing as the frame P 2 5 is stored in the buffer 25. (Please read the precautions on the back side and fill in this page.) The reproduction circuit 121 reads the frame B3a of G〇P3 from the stream buffer 61, and outputs it as a reproduction stream. In the MPEG video decoder 122, the frame B3a is decoded by the frame P 3 8 of the buffer 3, and the frame of the buffer 4 is decoded by the frame p 3 b of the buffer 4, and is stored in the video buffer. The buffer 7 of the buffer 33 is stored and displayed in the frame B 3 a of the buffer 7 after being subjected to frame/area conversion and timing adjustment of the output video synchronization timing. At the same timing as the display of the frame B 3 a , the reproduction circuit 1 1 1 reads the frame B39 of the GOP 3 from the stream buffer 61 and outputs it to the MPEG video decoder 122. In the MPEG video decoder 122, the frame B39 is the same as the frame B3a, and the frame P3 8 of the buffer 3 is used as the front direction reference picture, and the frame P3b of the buffer 4 is decoded as the back direction reference picture, instead of The frame B3a is stored in the buffer 7, and is output and displayed after the frame/area conversion and the timing of the output video synchronization timing are adjusted. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative prints the reproduction circuit 121 to read the frame P28 of the G〇P2 from the stream buffer 61, and outputs it to the MPEG video decoder 122. In the MPEG video decoder 122, the frame P28 of the GOP 2 is decoded with the frame P25 of the buffer 5 as the forward direction reference picture. The frame P3b stored in the buffer 4 is not regarded as a reference image since then, and the decoded frame P28 is stored in the buffer 4 instead of the frame P3b. Further, the frame P38 of the buffer 3 is read and displayed at the same timing as the frame P28 is stored in the buffer 4. In this way, the I picture or P picture of G0P2 is decoded and stored in the buffer paper size. The Chinese National Standard (CNS) A4 specification (210 father 297 mm) -49-1272849 Printed by the Intellectual Property Office of the Ministry of Economic Affairs -50- A7 ____ B7 _ V. Inventive Note (47) At the timing of the device 3 3, the I picture or the p picture of G 〇 P 3 is read and displayed by the buffer 3 3 . Similarly, as shown in Fig. 24, the remaining B portrait of GOP3 and the remaining p portrait of GOP2 are decoded in the order of B37, B36, P2b, B34, B3 3, and P2e. The decoded B picture is stored in the buffer 7, and is sequentially read and displayed. The P picture of the decoded G Ο P 2 is sequentially stored in one of the buffers 1 to 6 in which the reference frame is stored, and the P picture of the G0P 3 which has been stored in the buffers 1 to 6 is This timing is suitable for reverse regeneration. The order is read out between the B portraits and output. The reproduction circuit 121 reads out the frame B31 of the GOP3 from the stream buffer 61, and then reads out the frame B30, and outputs it to the MPEG video decoder 122. In the MPEG video decoder 122, the frame P2e of the previous direction reference picture necessary for decoding the frame B31 and the frame B30 is stored in the buffer 2, and the frame 132 of the backward direction reference picture is stored in the buffer 1. The frame of the beginning of G〇P3, that is, the frame that should be displayed last when the reproduction is reversed becomes also decodable. The decoded frame B31 and the frame B30 are sequentially stored in the buffer 7, and are output and displayed after the frame/area conversion and the timing of the output video synchronization timing are adjusted. After all the frames of the GOP 3 are read by the stream buffer 61, the controller 34 controls the servo circuit 111 to read the GOP 1 from the hard disk 112 and supply it to the reproduction circuit 121. The reproduction circuit 121 performs the designated processing, extracts the start code of the GOP1, records it in the start code buffer 62, and supplies the encoded stream of the GOP1 to the stream buffer 61 for storage. Next, the reproduction circuit 121 reads the frame of the GOP1 from the stream buffer 61. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210×297 mm) I---. --^---^Install I------1T-------0 (Please read the note on the back and fill out this page) 1272849 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed A7 ____ B7 V. Inventive Description (48) II 2, which is a reproduced stream, is output to the MPEG video decoder 122. The frame 112 is an I picture, and is decoded in the MPEG video decoder 122 without referring to other pictures, instead of being processed and stored in the buffer, instead of the frame 13 2 of the buffer 1 which is not processed later. 1. At this time, the frame P2e is read and output by the buffer 2, and the reverse reproduction display of the GOP2 is started. Next, the reproduction circuit 121 reads out the frame B2d of the GOP 2 from the stream buffer 61, i.e., the frame of the B image of the GOP2, which should be initially reversed, is output as a reproduction stream. In the MPEG video decoder 122, the frame B2d is decoded with the frame P2b of the buffer 3 as the forward direction reference picture and the frame P2e of the buffer 2 as the backward direction reference picture, and is stored in the video buffer 33. The decoded frame B 2 d is stored in the buffer 7, and is output and displayed after the fr frame/area conversion and the timing of the output video synchronization timing are adjusted. Hereinafter, the remaining B image of G0P2 and the remaining P image of G0P1 are decoded in the order of B2c, P15, B2a, P18, B27, B26, Plb, B24, B23, Pie, P21, and P20. The sequence is stored in one of the buffers 1 to 7 in which the frame of the reference is stored, and is read and output in the order of reverse reproduction. Further, although not shown, at the end, the remaining B pictures of G 〇 P 1 are decoded, sequentially stored in the buffer 7, and read and output in the order of reverse reproduction. In the process described with reference to Fig. 24, the reproduction is performed at the same speed as the normal reproduction, but the reproduction circuit 121 can output the reproduction stream to the MPEG video decoder 122 at a speed of one-third of the normal reproduction speed, MPEG. The video decoder 122 performs the decoding process of only one frame in the processing time of the usual three frames, and applies the Chinese National Standard (CNS) A4 specification (210×297 mm) to the display unit or the display device not shown in the i-paper scale. ) -- -- . ---^---衣--- (Please read the notes on the back and fill out this page) Order 1272849 Α7 Β7 V. Invention description (49) Normal 3 frame display time, display the same frame, 3 It is possible to reproduce in the direction of 1x speed and reverse the regeneration by the same processing. (Please read the precautions on the back and fill out this page.) Also, the display output circuit 5 3 is also possible to repeat the same frame output by repeating the same frame output. Further, by changing the data output speed of the mpeg video decoder 122 by the reproducing device 121 and the processing speed of the MPEG video decoder 122, it is possible to reproduce and reverse the reproduction in the direction of any one of n, n times. It becomes possible by the same process. In other words, in the regenerative apparatus of the present invention, any of the reversal of the equal-speed reversing, the reversal of the η-speed, the regenerative regeneration, the reciprocal regeneration of the 1×-speed, and the regeneration of the equal-speed in the forward direction. The speed, smoothing of special regeneration is possible. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the MPEG Video Decoder 122 is the decoder for MPEG2 4:2:2P@HL, and has the ability to decode the encoded stream of MPEG2 MP@ML at 6x speed. Therefore, the reproduction circuit 121 outputs the reproduction stream generated by the encoded stream of MP@ML to the MPEG video decoder 122 at a speed six times that of the normal reproduction, and the MPEG video decoder 122 has the code for decoding the MP@ML at the 6-times speed. For the ability to flow, it is possible to reproduce the 6-speed forward direction and reverse the reproduction by the same processing by using a display unit (not shown) or a display device to display a frame that is extracted every 6 frames. In other words, in the reproducing apparatus of the present invention, the encoded stream of MP@ML is reversely regenerated at 6x speed, reversed regeneration at equal speed, reversed reproduction at 1x speed of η, static reproduction, and 1x of η. It is possible to reproduce in the forward direction, at any speed between the equal speed in the forward direction and in the forward direction at the 6x speed, and smooth special reproduction is possible. -52 This paper size is applicable to China National Standard (CNS) Α4 specification (210X297 mm) 1272849 A7 p-______ B7 V. Invention description (50) (Please read the note on the back and fill in this page) Also, MPEG video decoding In the case where the decoding capability of the N-speed is provided, the reproducing apparatus of the present invention can reproduce in the forward direction of the N-speed and reverse the regeneration by the same processing, and reversing the regeneration at the N-speed, reversing the regeneration at the double speed, It is possible to perform smooth special regeneration in any speed between reverse regenerative regeneration, static regeneration, reciprocating regeneration at 1x speed, reciprocating in the forward direction at the same speed, and in the forward direction at the double speed. Therefore, for example, when the image signal is verified, the content of the image material can be easily verified, and the efficiency of the image material verification operation can be improved. In the editing operation of the image signal, the editing point can be comfortably searched, and the efficiency of the editing operation can be improved. The above series of processes can also be implemented by software. The software system that constitutes the software is installed on a computer that is assembled on a dedicated hardware by a recording medium, or a personal computer that can perform various functions by installing various programs, such as a general-purpose personal computer. The Ministry of Economic Affairs, the Intellectual Property Office, and the Employees' Cooperatives Co., Ltd. printed this recording medium as shown in Fig. 15 or Fig. 20, which is a disk of a recording program that is distributed to the user by a program different from the computer. Included in floppy disk), CD 1〇2 (including CD-R〇M (Compact Disk Read Only Memory), DVD (Digital Versatile Disk)), optical disk 103 (including MD (Mini Disk)), or semiconductor memory 104 It is composed of a kit medium formed by the like. Further, in the detailed description, the procedure of recording the program recorded on the recording medium may of course be performed in time series along the stated order, but may also be processed in a time series, or in parallel or in parallel. Individually executed handlers. -53- This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 1272849 Μ __ Β7 _ V. Invention description (51) [Effect of invention] (Please read the notes on the back and fill out this page. According to the first decoding apparatus, the decoding method, and the program of the present invention, the encoded stream is decoded, and the decoding processing is operated in parallel, so that the actual time operation can be realized in accordance with the achievable circuit scale 4:2:2P@HL Video decoder. According to the second decoding apparatus, the decoding method, and the program of the present invention, the encoded stream is decoded by the plurality of divided decoders, and the decoding process is performed in parallel by the plurality of divided decoders, so that the circuit scale that can be realized can be realized. 4:2: 2P @ HL video decoder capable of real time action. [Simple description of the drawing] Fig. 1 is a diagram illustrating the upper limit of each parameter according to the shape and series of MPEG2. Fig. 2 is a diagram for explaining the hierarchical structure of the bit stream of MPEG2. Figure 3 is a diagram illustrating the use of a large block layer. Fig. 4 is a diagram for explaining the structure of the data of the sequence_header. Fig. 5 is a diagram for explaining the structure of the data of seqUence_extension. Printed by the Ministry of Economic Affairs, the Intellectual Property Bureau, and the Consumer Cooperatives. Figure 6 is a diagram showing the data structure of G〇P_header. Fig. 7 is a diagram for explaining the structure of the picture_header. Fig. 8 is a diagram for explaining the data construction of the plcture_cording_extension. Fig. 9 is a view for explaining the structure of the picture_data. Fig. 1 is a diagram for explaining the data structure of the slice. Figure 11 is a diagram for explaining the data structure of the macroblock. This paper scale applies to the National Standard of the Week (CNS) A4 specification (210X297 mm) -54 - 1272849 A7 B7 V. Description of the invention (52) Figure 12 is a diagram for explaining the data structure of the macroblock_modes. Figure 1 3 is a diagram of the starting code. (Please read the notes on the back and fill out this page.) Figure 1 shows a block diagram showing the composition of the video decoder for decoding the ML @MP encoded stream. Figure 15 is a block diagram showing the construction of a video decoder adapted to the present invention. Figure 16 is a flow chart showing the processing of the split decoder control circuit. Fig. 1 is a diagram showing a specific example of the processing of the split decoder control circuit. Figure 18 is a flow chart showing the process of mediation processing by the split decoder of the motion compensation circuit. Fig. 19 is a diagram showing a specific example of the mediation processing by the split decoder of the motion compensation circuit. Fig. 20 is a block diagram showing the construction of a reproducing apparatus which does not have the MPEG video decoder of Fig. 15. Fig. 2 is a view showing a configuration of an image of an encoded MPEG video signal input to a decoder. Printed by the Ministry of Economic Affairs, the Intellectual Property Office, and the Consumer Cooperatives. Figure 22 shows an example of the MPEG image encoding using inter-frame prediction. Figure 23 is a diagram for explaining the decoding process of the case where the MPEG encoded stream is reproduced in the forward direction. Figure 24 is a diagram for explaining the decoding process in the case where the MPEG encoded stream is reversely reproduced. -55- This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 29) <7 mm) 1272849 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 5, Invention Description (53) [Description of Label] 31 : 1C 32 : Buffer 33 : Video Buffer 3 4 : Controller 42 : Start code detecting circuit 43: stream buffer control circuit 45: picture decoder 46: division decoder control circuits 47 to 49: division decoder 50: action compensation circuit 51: brightness buffer control circuit 52: color difference buffer control circuit 61 : stream buffer 62: start code buffer 7 1 : luminance buffer 72 : color difference buffer 111 : servo circuit 112 : hard disk 121 : reproduction circuit 122 : MPEG video decoder (please read the back of the note first) Page) This paper scale applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -56-