12716傲 7 6twf1.doc/006 95-10-11 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種時脈產生器，且特別是有關於一 種可產生不同時脈訊號的時脈產生器。 【先前技術】 在一個筆記型電腦中，包括了許多例如VGA卡或是區 域網路(LAN)等等不同的裝置，並且每一個裝置都有其需要 的工作時脈。而爲了要使工作時脈能夠穩定，在筆記型電 腦中’通常會使用石央晶體先振靈出一^個預定的參考頻率 訊號，再將此預定的參考頻率訊號輸入時脈產生器。然後 由時脈產生器內部的鎖相迴路(Phase lock loop，簡稱PLL) 依據輸入之預定的參考頻率來輸出穩定的工作時脈訊號。 圖1A係鎖相迴路的方塊圖。請參照圖1A，鎖相迴路 係主要由相位比較器101、除頻器103、參考訊號產生器 105、壓控振盪器（Voltage Control Oscillator，簡稱 VCO)107、低通濾波器(Low-Pass Filter，簡稱 LPF)109、充 電幫浦(Charge Pump)lll、補償電路113和控制電路115 所組成。壓控振盪器107接收並依據低通濾波器109輸出 的訊號，振盪出時脈訊號CLK，並同時輸出至輸出端out 和除頻器103。除頻器103會依據時脈訊號CLK產生比較 訊號fa並送入相位比較器101，同時，參考訊號產生器105 產生參考訊號fr，並且也送入相位比較器101。相位筆記器 1〇1將比較訊號fa和參考訊號fr比較後，會得到差値訊號 V並將之送入充電幫浦111。而充電幫浦111再將差値訊號 V提高一個預定位準後，再輸出至低通濾波器109。 5 2276twf 1 .doc/006 95-10-11 圖IB係繪示習知的時脈產生器方塊圖。請參照第i 圖，時脈產生器100，係使用一對一的方式來產生工作時 脈。更詳細的說，就是一個預定頻率訊號對應產生一個輸 出時脈訊號。例如將預定頻率訊號、f2、f3，分別輸入至 時脈產生器100內的鎖相迴路102、104、106，並且鎖相迴 路102、104、106係依據預定頻率訊號f!、f2、f3，分別產 生時脈訊號CLK1、CLK2、CLK3。 請繼續參照圖1B，前面已經說過，產生預定頻率訊號 A、f2、f3的裝置通常係使用石英（Crystal)晶體作爲振盪源。 但是因爲石央晶體的體積非常大，因此無法設計在晶片 中，而需要設計在晶片外部，如此時脈產生電路的體積會 相對龐大。此外，石英晶體的價格也非常昂貴，例如圖1B 中之習知的時脈產生器係需要三個預定頻率訊號，則就需 要三個石英晶體。 綜合上述的原因我們可以知道，習知的時脈產生器100 若是需要產生的工作時脈愈多，則相對地，石英振盪器的 數目也就愈多，因此體積就愈大，價格也就愈昂貴。 另外在電腦系統中，係需要使用展頻控制器（Spread Spectrum Controller，簡稱SSC)來控制VGA卡的展頻功 能。習知的技術係使用一個鎖相迴路接收輸入時脈訊號， 然後再輸出至展頻控制器以使得展頻控制器運作。但是習 知技術的缺點在於當展頻控制器不動作時，鎖相迴路也隨 之閒置，相當於多浪費了一個鎖相迴路在習知的時脈產生 器內。 【發明內容】 I2716P2?76tWfl.d〇c/00612716 proud 7 6twf1.doc/006 95-10-11 IX. Description of the invention: [Technical field of the invention] The present invention relates to a clock generator, and more particularly to a time when different clock signals can be generated Pulse generator. [Prior Art] In a notebook computer, a plurality of different devices such as a VGA card or a local area network (LAN) are included, and each device has its required working clock. In order to stabilize the working clock, in the notebook computer, the Shiyang crystal is usually used to vibrate a predetermined reference frequency signal, and then the predetermined reference frequency signal is input to the clock generator. Then, a phase lock loop (PLL) inside the clock generator outputs a stable working clock signal according to the input reference frequency. Figure 1A is a block diagram of a phase locked loop. Referring to FIG. 1A, the phase-locked loop is mainly composed of a phase comparator 101, a frequency divider 103, a reference signal generator 105, a Voltage Control Oscillator (VCO) 107, and a low-pass filter (Low-Pass Filter). , abbreviated as LPF) 109, a charge pump (llge pump) 111, a compensation circuit 113 and a control circuit 115. The voltage controlled oscillator 107 receives and signals the clock signal CLK according to the signal output from the low pass filter 109, and simultaneously outputs it to the output terminal out and the frequency divider 103. The frequency divider 103 generates a comparison signal fa according to the clock signal CLK and sends it to the phase comparator 101. At the same time, the reference signal generator 105 generates the reference signal fr and is also supplied to the phase comparator 101. The phase note device 1〇1 compares the comparison signal fa with the reference signal fr, and then obtains the difference signal V and sends it to the charging pump 111. The charging pump 111 further increases the rate signal V by a predetermined level and outputs it to the low pass filter 109. 5 2276twf 1 .doc/006 95-10-11 Figure IB is a block diagram showing a conventional clock generator. Referring to the i-th diagram, the clock generator 100 uses a one-to-one method to generate a working clock. In more detail, a predetermined frequency signal corresponds to an output clock signal. For example, the predetermined frequency signals, f2, and f3 are input to the phase-locked loops 102, 104, and 106 in the clock generator 100, respectively, and the phase-locked loops 102, 104, and 106 are based on predetermined frequency signals f!, f2, and f3. Clock signals CLK1, CLK2, and CLK3 are generated, respectively. Continuing to refer to Fig. 1B, it has been said that the means for generating the predetermined frequency signals A, f2, and f3 typically uses a quartz crystal as the oscillation source. However, since the core crystal is so large that it cannot be designed in a wafer and needs to be designed outside the wafer, the volume of the clock generating circuit is relatively large. In addition, the price of quartz crystals is also very expensive. For example, the conventional clock generator of Fig. 1B requires three predetermined frequency signals, and three quartz crystals are required. For the above reasons, we can know that if the conventional clock generator 100 needs to generate more working clocks, the number of quartz oscillators is relatively larger, so the larger the volume, the higher the price. expensive. In addition, in the computer system, the Spread Spectrum Controller (SSC) is required to control the spread spectrum function of the VGA card. The conventional technique uses a phase-locked loop to receive the input clock signal and then output it to the spread spectrum controller to operate the spread spectrum controller. However, the disadvantage of the prior art is that when the spread spectrum controller is not operating, the phase locked loop is also idle, which is equivalent to wasting a phase locked loop in the conventional clock generator. SUMMARY OF THE INVENTION I2716P2?76tWfl.d〇c/006
95-10-11 因此，本發明的目的在提供一種時脈產生器，係利用 一個預定頻率訊號，就可以產生不同的時脈訊號。 本發明再一目的在提供一種時脈產生器，在展頻控制 器不動作時，與其耦接的鎖相迴路還可以作其他的用途， 不會造成浪費。 本發明又一目的在提供一種時脈產生器，不但可以利 用一個預定頻率訊號來產生不同頻率的時脈訊號，還可以 接收輸入時脈訊號來進行展頻的動作。 本發明另一目的在提供一種時脈產生器，可以利用一 個預定頻率訊號來產生不同頻率而常用的時脈訊號，還可 以依據輸入的預定頻率訊號，再產生特殊頻率的時脈訊號。 爲達以上和其他目的，本發明提供一種時脈產生器包 括了有頻率多工電路和多頻鎖相迴路。在頻率多工電路方 面，其包括了展頻控制器、內部鎖相迴路和多工器。其中 展頻控制器用來使頻率多工電路將所接收的輸入時脈訊號 進行展頻處理，來獲得第一時脈訊號。另外，內部鎖相迴 路係用來使頻率多工電路接收固定的預定頻率訊號，以獲 得第二時脈訊號。而第二時脈訊號的頻率係等於預定頻率 訊號之頻率乘以N再除以M，而N及Μ爲正整數。前述的 第一時脈和第二時脈係同時輸入至多工器的輸入端，且多 工器會選擇第一時脈訊號或是第二時脈訊號，來輸出第三 時脈訊號。另外，在多頻鎖相迴路方面，會接收前述的預 定頻率訊號，以輸出第四時脈訊號和第五時脈訊號。其中， 第四時脈訊號之頻率係等於前述的預定頻率訊號之頻率乘 以Τ再除以U。而第五時脈訊號之頻率係等於前述的預定 12716股95-10-11 Accordingly, it is an object of the present invention to provide a clock generator that utilizes a predetermined frequency signal to generate different clock signals. Still another object of the present invention is to provide a clock generator which can be used for other purposes without causing waste when the spread spectrum controller is not operating. It is still another object of the present invention to provide a clock generator that can generate a clock signal of a different frequency using a predetermined frequency signal, and can also receive an input clock signal to perform a spreading operation. Another object of the present invention is to provide a clock generator that can generate a clock signal that is commonly used at different frequencies by using a predetermined frequency signal, and can also generate a clock signal of a special frequency according to the input predetermined frequency signal. To achieve the above and other objects, the present invention provides a clock generator comprising a frequency multiplex circuit and a multi-frequency phase lock loop. In the frequency multiplex circuit, it includes a spread spectrum controller, an internal phase locked loop, and a multiplexer. The spread spectrum controller is configured to cause the frequency multiplexing circuit to perform the spread spectrum processing on the received input clock signal to obtain the first clock signal. In addition, the internal phase-locked loop is used to cause the frequency multiplex circuit to receive a fixed predetermined frequency signal to obtain a second clock signal. The frequency of the second clock signal is equal to the frequency of the predetermined frequency. The frequency of the signal is multiplied by N and divided by M, and N and Μ are positive integers. The first clock and the second clock are simultaneously input to the input end of the multiplexer, and the multiplexer selects the first clock signal or the second clock signal to output the third clock signal. In addition, in the multi-frequency phase-locked loop, the predetermined frequency signal is received to output the fourth clock signal and the fifth clock signal. The frequency of the fourth clock signal is equal to the frequency of the aforementioned predetermined frequency signal multiplied by Τ and then divided by U. The frequency of the fifth clock signal is equal to the aforementioned predetermined 12,716 shares.
276twf 1 .doc/OOQ276twf 1 .doc/OOQ
95-10-11 頻率訊號之頻率乘以T再除以V。其中T、U及V需要有 一定的關聯性，才能提高多頻鎖相迴路之輸出時脈訊號的 精準度。因此，本發明係將T、U及V設定爲爲2X、3Y與 5Ζ三者之任二者的乘積之倍數，且X、Υ及Ζ皆爲正整數。 在較佳的情況下來說，多頻鎖相迴路更包括接收上述 所提及的預定頻率訊號，以輸出第六時脈訊號。此第六時 脈訊號之頻率係預定頻率訊號之頻率乘以Τ再除以W，而 W同樣設定爲2Χ、3Υ與52三者之任二者的乘積之倍數， 且X、Υ及Ζ皆爲正整數。 上述中，T、U、V以及W係皆設定爲2Χ、3Υ與52三 者之任二者的乘積之倍數，是因爲在筆記型電腦中，大多 數裝置所需之工作頻率，係某一頻率乘以2Χ、3¥與5Ζ三者 中任二者的乘積之倍數，因此本發明係採取上述之設計。 在本發明其中一個實施例中，時脈產生器更包括第一 開關模組和第二開關模組。其中，第一開關模組係耦接第 三時脈訊號和輸出致能訊號，並且第一開關模組會依據輸 出致能訊號來決定是否將第三時脈訊號輸出。此外，第二 開關模組則是接收第四時脈訊號和輸出致能訊號，並且第 二開關模組同樣也是依據輸出致能訊號來決定是否將第四 時脈訊號輸出。 在較佳的情況下，第一開關模組和第二開關模組包括 多工器。 從另一觀點來看，本發明提供~種時脈產生器，主要 由頻率多工電路、多頻鎖相迴路和特定頻率鎖相迴路所組 成。同樣地，頻率多工電路還是包括展頻控制器和內部鎖 95-10-11 127·一，正替換頁丨 相迴路和多工器。其中頻率多工電路係利用展頻控制器進 行展頻處理，並會獲得第一時脈訊號，另外頻率多工電路 係經由內部鎖相迴路接收固定的預定頻率訊號，而獲得第 二時脈訊號。接著，多工器會選擇第一時脈訊號或是第二 時脈訊號來輸出第三時脈訊號。而多頻鎖相迴路也會接收 前述之預定頻率來輸出第四時脈訊號與第五時脈訊號。而 在特定頻率鎖相迴路方面，同樣也接收前述的預定頻率訊 號以獲得特定頻率訊號，而輸出第六時脈訊號。此外，第 六時脈訊號之頻率等於特定頻率訊號之頻率乘以Q再除以 P，且Q及P皆爲正整數。 在本發明其中一個實施例中，時脈產生器更包括第一 開關模組、第二開關模組和第三開關模組。其中，第一開 關模組係接第三時脈訊號和輸出致能訊號，並且第一開關 模組會依據輸出致能訊號來決定是否將第三時脈訊號輸 出。此外，第二開關模組則是接收第四時脈訊號和輸出致 能訊號，並且第二開關模組同樣也是依據輸出致能訊號來 決定是否將第四時脈訊號輸出。另外，第三開關模組係接 收第六時脈訊號和輸出致能訊號，並且第三開關模組也是 依據輸出致能訊號來決定是否將第六時脈訊號輸出。 在較佳的情況下，第一、第二和第三開關模組包括多 工器。 從本另一觀點來看，本發明提供一種時脈產生器之頻 率多工電路，其包括了展頻控制器、內部鎖相迴路和多工 器。其中展頻控制器係用來使鎖相迴路將所接收到的輸入 時脈訊號進行展頻處理，以獲得第一時脈訊號。另外，內 12716股 7 6twf 1 .doc/006 95-10-11 部鎖相迴路係用來使頻率多工電路接收固定的預定頻率訊 號，以獲得第二時脈訊號。另外，上述之第二時脈訊號的 頻率等於預定頻率訊號之頻率乘以N再除以M，而N及Μ 爲正整數。多工器係接收第一時脈訊號和第二時脈訊號， 以選擇第一時脈訊號或是第二時脈訊號來輸出第三時脈訊 號。 在本發明其中一個實施例中，本發明之時脈產生器更 包括有特定頻率鎖相迴路，係用來接收前述的預定頻率訊 號，而獲得特定頻率訊號以輸出第四時脈訊號，其中，第 四時脈訊號的頻率係等於特定頻率訊號之頻率乘以Q再除 以Ρ，且Q及Ρ皆爲正整數。 從另一觀點來看，本發明提供一種時脈產生器包括有 多頻鎖相迴路，其特徵在於此多頻鎖相迴路接收固定的預 定頻率訊號來輸出第一時脈訊號和第二時脈訊號。其中， 第一時脈訊號之頻率係等於預定頻率訊號之頻率乘以Τ再 除以U，而第二時脈訊號之頻率係等於預定頻率訊號之頻 率乘以Τ再除以V。前述之Τ、U及V皆爲2Χ、3¥與5Ζ 三者之任二者的乘積之倍數，且X、Υ及Ζ皆爲正整數。 在較佳的情況下來說，上述的多頻鎖相迴路更包括接 收預定頻率，以輸出第三時脈訊號。此第三時脈訊號之頻 率係預定頻率訊號之頻率乘以Τ再除以w，而W係2Χ、3Υ 與5Ζ三者之任二者的乘積之倍數，且χ、γ及ζ皆爲正整 數。 在本發明其中一個實施例中，本發明之時脈產生器， 更包括特定頻率鎖相迴路，用來接收前述之預定頻率訊號 1271609 八 12276twfl .doc/006 7 95-10-1 1 -.,.. .., r 以獲得一特定頻率訊號而輸出第四時脈訊號。其中，第四 時脈訊號之頻率係等於特定頻率訊號之頻率乘以Q再除以 P，且Q及P皆爲正整數。 綜上所述，本發明因爲將所需要的時脈訊號，整理出 一個最小公倍數的規則，因此只需要使用一個固定的預定 頻率訊號，就可以產生不同的時脈訊號。也因爲本發明只 需要使用一個固定的預定頻率訊號，相對地，所要用到的 石英晶體也只需一個，因此使得本發明之時脈產生器的體 積和價格都大幅度的降低。 另外，本發明之時脈產生器內的頻率多工電路，在展 頻控制器閒置的時候還可以輸出時脈訊號，而不會隨之閒 置造成浪費。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉幾個實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 第一實施例 圖2A係繪示依照本發明第一實施例之時脈產生器方 塊圖。請參照圖2A，在本實施例中，時脈產生器係包括了 頻率多工電路200，係接收輸入時脈訊號T!和預定頻率訊 號6來產生第三時脈訊號CLK3。而在本實施例中，預定頻 率訊號6爲14.318MHz。 詳細地來看頻率多工電路200的內部結構，請繼續參 照圖2A，多工器21係接收係接收輸入時脈訊號T!和預定 頻率訊號A，而其輸出耦接內部鎖相迴路204。而內部鎖相95-10-11 The frequency of the frequency signal is multiplied by T and divided by V. Among them, T, U and V need to have a certain correlation, in order to improve the accuracy of the output clock signal of the multi-frequency phase-locked loop. Therefore, in the present invention, T, U, and V are set to be a multiple of the product of any of 2X, 3Y, and 5Ζ, and X, Υ, and Ζ are all positive integers. In a preferred case, the multi-frequency phase-locked loop further includes receiving the predetermined frequency signal mentioned above to output a sixth clock signal. The frequency of the sixth clock signal is the frequency of the predetermined frequency signal multiplied by Τ and then divided by W, and W is also set to a multiple of the product of any two of 2Χ, 3Υ and 52, and X, Υ and Ζ are both Is a positive integer. In the above, the T, U, V, and W systems are all set to a multiple of the product of 2, 3, and 52, because in the notebook computer, the operating frequency required by most devices is a certain The frequency is multiplied by a multiple of the product of either 2, 3, and 5, and thus the present invention adopts the above design. In one embodiment of the invention, the clock generator further includes a first switch module and a second switch module. The first switch module is coupled to the third clock signal and the output enable signal, and the first switch module determines whether to output the third clock signal according to the output enable signal. In addition, the second switch module receives the fourth clock signal and the output enable signal, and the second switch module also determines whether to output the fourth clock signal according to the output enable signal. In a preferred case, the first switch module and the second switch module comprise a multiplexer. From another point of view, the present invention provides a clock generator that is mainly composed of a frequency multiplex circuit, a multi-frequency phase locked loop, and a specific frequency phase locked loop. Similarly, the frequency multiplex circuit also includes the spread spectrum controller and the internal lock 95-10-11 127·, which is replacing the page 丨 phase loop and the multiplexer. The frequency multiplexing circuit uses the spread spectrum controller for the spread spectrum processing, and obtains the first clock signal, and the frequency multiplexing circuit receives the fixed predetermined frequency signal through the internal phase locked loop to obtain the second clock signal. . Then, the multiplexer selects the first clock signal or the second clock signal to output the third clock signal. The multi-frequency phase-locked loop also receives the predetermined frequency to output the fourth clock signal and the fifth clock signal. In the specific frequency phase-locked loop, the predetermined frequency signal is also received to obtain a specific frequency signal, and the sixth clock signal is output. In addition, the frequency of the sixth clock signal is equal to the frequency of the specific frequency signal multiplied by Q and then divided by P, and both Q and P are positive integers. In one embodiment of the present invention, the clock generator further includes a first switch module, a second switch module, and a third switch module. The first switch module is connected to the third clock signal and the output enable signal, and the first switch module determines whether to output the third clock signal according to the output enable signal. In addition, the second switch module receives the fourth clock signal and the output enable signal, and the second switch module also determines whether to output the fourth clock signal according to the output enable signal. In addition, the third switch module receives the sixth clock signal and the output enable signal, and the third switch module also determines whether to output the sixth clock signal according to the output enable signal. In the preferred case, the first, second and third switch modules comprise a multiplexer. Viewed from another point of view, the present invention provides a frequency multiplexer circuit for a clock generator that includes a spread spectrum controller, an internal phase locked loop, and a multiplexer. The spread spectrum controller is used to cause the phase locked loop to perform the spread spectrum processing on the received input clock signal to obtain the first clock signal. In addition, the internal 12716 shares 7 6twf 1 .doc/006 95-10-11 phase-locked loops are used to cause the frequency multiplex circuit to receive a fixed predetermined frequency signal to obtain a second clock signal. In addition, the frequency of the second clock signal is equal to the frequency of the predetermined frequency signal multiplied by N and then divided by M, and N and Μ are positive integers. The multiplexer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal to output the third clock signal. In one embodiment of the present invention, the clock generator of the present invention further includes a specific frequency phase-locked loop for receiving the predetermined frequency signal to obtain a specific frequency signal to output a fourth clock signal, wherein The frequency of the fourth clock signal is equal to the frequency of the specific frequency signal multiplied by Q and then divided by Ρ, and both Q and Ρ are positive integers. From another point of view, the present invention provides a clock generator comprising a multi-frequency phase locked loop, wherein the multi-frequency phase locked loop receives a fixed predetermined frequency signal to output a first clock signal and a second clock. Signal. The frequency of the first clock signal is equal to the frequency of the predetermined frequency signal multiplied by Τ and then divided by U, and the frequency of the second clock signal is equal to the frequency of the predetermined frequency signal multiplied by Τ and then divided by V. The above Τ, U and V are all multiples of the product of 2Χ, 3¥ and 5Ζ, and X, Υ and Ζ are all positive integers. In a preferred case, the multi-frequency phase-locked loop further includes receiving a predetermined frequency to output a third clock signal. The frequency of the third clock signal is the frequency of the predetermined frequency signal multiplied by Τ and then divided by w, and the W is a multiple of the product of the two of 2Χ, 3Υ and 5Ζ, and χ, γ and ζ are positive Integer. In one embodiment of the present invention, the clock generator of the present invention further includes a specific frequency phase-locked loop for receiving the aforementioned predetermined frequency signal 1271609 八12276 twfl.doc/006 7 95-10-1 1 -. .. .., r to obtain a specific frequency signal and output the fourth clock signal. The frequency of the fourth clock signal is equal to the frequency of the specific frequency signal multiplied by Q and then divided by P, and both Q and P are positive integers. In summary, the present invention organizes a minimum common multiple of the required clock signals, so that only a fixed predetermined frequency signal is used to generate different clock signals. Also, since the present invention only requires the use of a fixed predetermined frequency signal, relatively only one quartz crystal is required, so that the volume and price of the clock generator of the present invention are greatly reduced. In addition, the frequency multiplex circuit in the clock generator of the present invention can also output a clock signal when the spread spectrum controller is idle, without being wasted by idle. The above and other objects, features, and advantages of the present invention will become more apparent from [Embodiment] FIG. 2A is a block diagram of a clock generator according to a first embodiment of the present invention. Referring to FIG. 2A, in the embodiment, the clock generator includes a frequency multiplexing circuit 200 for receiving an input clock signal T! and a predetermined frequency signal 6 to generate a third clock signal CLK3. In the present embodiment, the predetermined frequency signal 6 is 14.318 MHz. Referring in detail to the internal structure of the frequency multiplex circuit 200, please continue to refer to FIG. 2A. The multiplexer 21 receives the input clock signal T! and the predetermined frequency signal A, and its output is coupled to the internal phase locked loop 204. Internal phase lock
95-10-11 迴路204則將其輸出耦接至展頻控制器202和多工器206。 多工器206係分別接收接收內部鎖相迴路204和展頻控制 器202的輸出。 在本實施例中，安置展頻控制器202的目的係爲了針 對例如視頻圖形陣列(video graphics array，以下簡稱VGA) 等的裝置進行展頻的動作。設計者可以使用展頻控制致能 訊號SSC-EN來控制多工器206切換輸出。當本發明之時 脈產生器要對VGA進行展頻時，展頻控制致能訊號SSC-EN 可以控制多工器206導通輸入端206a和輸出端206c，以選 擇展頻控制器202的輸出來產生時脈訊號CLK3。而若是頻 率多工電路200不用進行展頻時，則展頻控制致能訊號 SSC_EN使多工器導通輸入端206b和輸出端206c，以選擇 內部鎖相迴路204的輸出來產生時脈訊號CLK3。 請繼續參照圖2B，多工器21係依據選擇訊號SEL來 選擇輸入時脈訊號乃或是預定頻率訊號^做爲輸出。當本 發明之時脈產生器需要對VGA進行展頻的動作時，則選擇 訊號SEL會使得多工器21選擇輸入時脈訊號乃送至內部 鎖相迴路204。內部鎖相迴路204係將輸入時脈訊號乃乘 以N再除以Μ之後產生時脈訊號CLK1，其中Μ和N都是 正整數，並且Μ和Ν的數値，可以由熟習此技藝者依據實 際情況自行設計。接著，展頻控制器202會依據時脈訊號 CLK1來產生時脈訊號CLK2。若是本發明之時脈產生器不 需要進行展頻的動作時，選擇訊號SEL則使得多工器21 選擇預定頻率訊號6送至內部鎖相迴路204而產生時脈訊 號 CLK1。 12716股 7 6twf 1. doc/006 年月 換頁 曰修(f)正替 95-10-11 而另一選擇實施例，請參照圖2B，其繪示另一種頻率 多工電路的內部方塊圖。在圖2B中，頻率多工電路200只 需要一個預定頻率訊號作輸入即可，因此可以節省圖2B中 之多工器21，使得頻率多工電路200的內部架構更爲簡 潔。而在本圖中，頻率多工電路200輸入的預定頻率訊號 可以選擇27MHz。 第二實施例 圖3A係繪示依照本發明之第二實施例之時脈產生器 方塊圖。請參照圖3A，在本實施例中，本發明之時脈產生 器包括了有多頻鎖相迴路300。多頻鎖相迴路300係接收與 第一實施例相同的預定頻率訊號fi，來同時產生時脈CLK1 和時脈CLK2。一般來說，如果輸入頻率訊號和輸出的時脈 訊號係一對一的關係時，也就是說，當鎖相迴路如果是接 收一個預定頻率訊號來產生一個時脈訊號的時候，其時脈 訊號的精準度非常高。但若是如本發明之時脈產生器係接 收一個頻率訊號而產生多個時脈訊號的時候’則每一個輸 出的時脈訊號間就需要有一些關聯性來提高輸出訊號之頻 率的精準度。 請繼續參照圖3A，多頻鎖相迴路300具有頻率設定電 路302、304、306。在本實施例中，多頻鎖相迴路300係接 收預定頻率訊號A，並使得頻率設定電路302將頻率訊號 A之頻率乘以T後，分別送入頻率設定電路304和頻率設 定電路306。其中，頻率設定電路304係將預定頻率訊號 A乘以T以後再除以U，然後由多頻鎖相迴路3〇〇產生時 脈訊號CLK1。而頻率設定電路306係將預定頻率訊號fi 13 12716傲 76twf 1 .doc/006 95-10-11 乘以T後再除以V，且由多頻鎖相迴路300產生時脈訊號 CLK2。在本實施例中，Τ、U及V都是正整數，並且也都 是2Χ、3¥與5Ζ三者中，任二者的乘積之倍數，同樣地，X、 Υ及Ζ也都是正整數。 在本實施例中，將Τ、U及V設定爲2Χ、3Υ與5Ζ三者 中任二者的乘積之倍數的原因，是因爲在筆記型電腦中， 很多裝置的工作頻率係2^3¥與52三者中任二者的乘積之 倍數，例如VGA的工作頻率係27ΜΗζ。因此，本發明將筆 記型電腦中所常用到的工作頻率取最小公倍數，就得到時 脈訊號CLK1和CLK2之間的關係’也因此可以提高精確 度。 雖然本實施例中，多頻鎖相迴路300係接收頻率訊號 心來產生時脈訊號CLK1和CLK2，但是並不以此來限定本 發明。圖3Β係繪示依照本發明第二實施例之另一種時脈產 生器方塊圖。請參照圖3Β，多頻鎖相迴路300除了產生時 脈訊號CLK1和CLK2以外，還可以例如圖3Β中產生 CLK3。與圖3Α同樣的原理，多頻鎖相迴路300係接收預 定頻率訊號^後，使得頻率設定電路302和308將預定頻 率訊號Α乘以Τ再除以W，再由多頻鎖相迴路300產生時 脈訊號CLK3，其中T和W係2X、3Y與5Z三者中，任二 者的乘積之倍數，同樣地，X、Y及Z也都是正整數。 圖3C係繪示多頻鎖相迴路的部分內部方塊示意圖。請 參照圖3C，壓控振盪器31係耦接除頻器33、頻率設定電 路304、306和308,而除頻器33的輸出則耦接至相位比較 器35。當壓控振盪器31開始振盪時，會產生輸出時脈訊號 14 127161 wf 1 .doc/006 95-10-11 CLKOUT至除頻器33 〇除頻器33會將輸出時脈訊號 CLKOUT的頻率除以T以後而產生時脈訊號CLKA，在此 T爲2X、3Y與5Z三者中，任二者的乘積之倍數。另外，相 位比較器35係接時脈訊號CLKA和預定頻率訊號A，並且 相位比較器35會依據二者比較的結果產生比較時脈訊號 CLKCOM。然後比較時脈訊號CLKCOM會經過後續電壓提 昇和低通濾波等程序之後(詳細原理請參照圖1A)，再回授 至壓控振盪電路31。 請繼續參照圖3C，頻率設定電路304、306和308同 樣也會接收輸出時脈訊號CLKOUT。其中，頻率設定電路 304會將輸出時脈訊號CLKOUT的頻率除以U，以產生時 脈訊號CLK1 ;頻率設定電路306會將輸出時脈訊號 CLKOUT的頻率除以V，以產生時脈訊號CLK2 ;而頻率設 定電路308會將輸出時脈訊號CLKOUT的頻率除以W，以 產生時脈訊號CLK3。其中，U、V及W係2X、3Y與52三 者中，任二者的乘積之倍數。而當整個多頻鎖相迴路300 趨於穩定後，時脈訊號CLKA的頻率，就會等於預定頻率 訊號Α之頻率。也就是說，輸出時脈訊號CLKOUT的頻率， 會等於頻率訊號^之頻率的T倍。而一般來說，頻率設定 電路304、306和308，可以用除頻器電路來實現。 第三實施例 圖4係繪示依照本發明第三實施例之時脈產生器方塊 圖。請參照圖4，在第二實施例中有提到，筆記型電腦內大 部分的裝置其工作頻率係預定頻率訊號^乘上2X、3¥與5Z 三者中任二者的乘積之倍數，但是也不是所有的裝置其工 12716敗 9^：ia L') Μ 頁; 76twfl .doc/006 95-10-11 作頻率都是如此。有些裝置的工作頻率無法使用第二實施 例中多頻鎖相迴路300的方式產生出來，因此必須另外產 生特定的時脈訊號。因此，在本實施例中，特別設計了特 定頻率鎖相迴路400來產生特定的時脈訊號。在本實施例 中，特定頻率鎖相迴路400可以與其他的電路來組合成本 發明之時脈產生器。如本實施例中，係將頻率多工電路200 與特定頻率鎖相迴路400作結合而組合成本發明之時脈產 生器。其中頻率多工電路200在第一實施例中已經介紹過， 在此不再贅述。此外，特定頻率鎖相迴路400係接收上述 的預定頻率訊號A來產生時脈訊號CLK4和時脈訊號 CLK5。 請繼續參照圖4,特定頻率鎖相迴路400包括了頻率設 定電路402和頻率設定電路404。特定頻率鎖相迴路400 同樣也是接收預定頻率訊號A，再經過頻率設定電路402 後，會使得特定頻率鎖相迴路400輸出特定頻率的時脈訊 號CLK5，在本實施例中，時脈訊號CLK5的頻率例如爲 24.567MHz，這個頻率是無法用第二實施例中的頻率設定電 路產生出來的。接下來，使得頻率設定電路404將頻率設 定電路402送來的訊號再乘以Q除以P後，使得特定頻率 鎖相迴路400會產生時脈訊號CLK4，而Q和P都爲正整 數。 第四實施例 圖5係繪示依照本發明第四實施例之時脈產生器方塊 圖。請參照圖5，在本實施例中，本發明之時脈產生器包括 了多頻鎖相迴路300和特定頻率鎖相迴路400。其中多頻鎖 127 wf 1. doc/006 95,10.11 II / 月日修(欠)正替換頁 95-10-11 相迴路300和特定頻率鎖相迴路400係同時接收預定頻率 訊號fi而產生時脈訊號CLK1、CLK2、CLK3、CLK4和 CLK5，其個別的工作原理在以上實施例已經說明過，在此 不再贅述。 第五實施例 圖6係繪示依照本發明第五實施例之時脈產生器方塊 圖。請參照圖6,在本實施例中，係將第一實施例中的頻率 多工電路200和第二實施例中的多頻鎖相迴路300,組合成 本發明之時脈產生器。其個別的工作原理請參照第一實施 例和第二實施例，在此不再贅述。 第六實施例 圖7係繪示依照本發明第六實施例之時脈產生器方塊 圖。請參照圖7，在本實施例中，本發明之時脈產生器係包 括了頻率多工電路200、多頻鎖相迴路300和特定頻率鎖相 迴路400，係接收輸入時脈訊號几和預定頻率訊號^，以 產生時脈訊號 CLK3、CLK4、CLK5、CLK6、CLK7、CLK8 和CLK9。其中，CLK9的頻率就是預定頻率訊號6的頻率， 在本實施例中，預定頻率訊號fi的頻率例如爲14.318MHz。 另外在本實施例中，頻率設定電路302係將多頻鎖相迴路 300所接收的預定頻率訊號A之頻乘以5乘以8乘以27以 後，分別送入頻率設定電路304、306和308。 其中，頻率設定電路304係將頻率設定電路302送來 的時脈訊號之頻率除以2X1除以3Y1除以5Z1。此外，頻率 設定電路306係將頻率設定電路302送來的時脈訊號之頻 率除以2X2除以3Y2除以5Z2，而頻率設定電路308則是將 12716游 76twfl.doc/006 95-10-11 頻率設定電路302送來的時脈訊號之頻率除以2X3除以3Y3 除以 5Ζ3。前述的 XI、Χ2、Χ3、Yl、Υ2、Υ3、Zl、Ζ2、 Ζ3皆爲正整數。而頻率多工電路200、多頻鎖相迴路300 和特定頻率鎖相迴路400個別詳細的工作原理，上述實施 例都已經提過，因此本發明在此不再贅述。 在以上六個實施例中，提出了本發明可以變化的方 式，但是並不以此限定本發明非要如此設計。只要時脈產 生器係用鎖相迴路組成，並且可以用一個固定的預定頻率 訊號，來產生多個時脈訊號的輸出，即符合本發明之精神。 因此熟習此技藝者，可以依照實際需要來做變化。例如圖 8，其繪示依照本發明之一較佳實施例之較省電的時脈產生 器方塊圖。在圖8中，每一個輸出的時脈訊號都輸入至例 如多工器81的開關電路，並且每一個開關電路都例如多工 器81所示，接收輸出致能訊號0-ΕΝ來決定是否將時脈訊 號 CLK3、CLK4、CLK5、CLK6、CLK7、CLK8 和 CLK9 輸出。當時脈產生電路在省電模式時，輸出致能訊號0-ΕΝ 可控制將所有的開關電路之輸出關閉，以節省電力的損耗。 綜上所述，本發明之時脈產生器有以下幾個優點： 1.本發明之時脈產生器因爲將所需要的時脈訊號，整理 出一個最小公倍數的規則，故只需要一個輸入頻率訊號就 可以產生多個不同的時脈訊號。因此所需要的石英晶體的 數目只要一個，而有效地使本發明之時脈產生器在電路上 所佔的體積減少。同時也因爲石英晶體的數目少，因此本 發明之時脈產生器整體的價格也可以下降。 2·本發明之時脈產生器內的鎖相迴路在展頻控制器閒The 95-10-11 loop 204 couples its output to the spread spectrum controller 202 and the multiplexer 206. The multiplexer 206 receives and receives the outputs of the internal phase locked loop 204 and the spread spectrum controller 202, respectively. In the present embodiment, the purpose of the spread spectrum controller 202 is to perform a spreading operation for a device such as a video graphics array (VGA). The designer can use the spread spectrum control enable signal SSC-EN to control the multiplexer 206 to switch the output. When the clock generator of the present invention is to spread the VGA, the spread spectrum control enable signal SSC-EN can control the multiplexer 206 to turn on the input terminal 206a and the output terminal 206c to select the output of the spread spectrum controller 202. The clock signal CLK3 is generated. If the frequency multiplexing circuit 200 does not need to spread the frequency, the spread spectrum control enable signal SSC_EN causes the multiplexer to turn on the input terminal 206b and the output terminal 206c to select the output of the internal phase locked loop 204 to generate the clock signal CLK3. Referring to FIG. 2B, the multiplexer 21 selects the input clock signal or the predetermined frequency signal ^ as the output according to the selection signal SEL. When the clock generator of the present invention needs to perform a spreading operation on the VGA, selecting the signal SEL causes the multiplier 21 to select the input clock signal to be sent to the internal phase locked loop 204. The internal phase-locked loop 204 generates the clock signal CLK1 by multiplying the input clock signal by N and dividing by ,, where Μ and N are both positive integers, and the number of Μ and Ν can be determined by the skilled person. The situation is designed by itself. Then, the spread spectrum controller 202 generates the clock signal CLK2 according to the clock signal CLK1. If the clock generator of the present invention does not need to perform the spreading operation, the selection signal SEL causes the multiplexer 21 to select the predetermined frequency signal 6 to be sent to the internal phase locked loop 204 to generate the clock signal CLK1. 12716 shares 7 6twf 1. doc/006 year page change page repair (f) replacement 95-10-11 and another alternative embodiment, please refer to FIG. 2B, which shows an internal block diagram of another frequency multiplex circuit. In Fig. 2B, the frequency multiplex circuit 200 only needs a predetermined frequency signal for input, so that the multiplexer 21 of Fig. 2B can be saved, so that the internal structure of the frequency multiplex circuit 200 is simpler. In the figure, the predetermined frequency signal input by the frequency multiplexing circuit 200 can be selected to be 27 MHz. SECOND EMBODIMENT Fig. 3A is a block diagram showing a clock generator in accordance with a second embodiment of the present invention. Referring to Figure 3A, in the present embodiment, the clock generator of the present invention includes a multi-frequency phase locked loop 300. The multi-frequency phase locked loop 300 receives the same predetermined frequency signal fi as in the first embodiment to simultaneously generate the clock CLK1 and the clock CLK2. Generally, if the input frequency signal and the output clock signal are in a one-to-one relationship, that is, when the phase-locked loop receives a predetermined frequency signal to generate a clock signal, its clock signal The accuracy is very high. However, if the clock generator of the present invention receives a frequency signal and generates a plurality of clock signals, then each of the output clock signals needs to have some correlation to improve the accuracy of the frequency of the output signal. Referring to Figure 3A, the multi-frequency phase locked loop 300 has frequency setting circuits 302, 304, 306. In the present embodiment, the multi-frequency phase-locked loop 300 receives the predetermined frequency signal A, and causes the frequency setting circuit 302 to multiply the frequency of the frequency signal A by T, and then sends it to the frequency setting circuit 304 and the frequency setting circuit 306, respectively. The frequency setting circuit 304 multiplies the predetermined frequency signal A by T and then divides by U, and then generates the clock signal CLK1 by the multi-frequency phase locked loop 3〇〇. The frequency setting circuit 306 multiplies the predetermined frequency signal fi 13 12716 proud 76twf 1 .doc/006 95-10-11 by T and then divides by V, and generates the clock signal CLK2 by the multi-frequency phase locked loop 300. In the present embodiment, Τ, U, and V are both positive integers, and are also multiples of the product of any two of 2Χ, 3¥, and 5Ζ. Similarly, X, Υ, and Ζ are also positive integers. In the present embodiment, the reason why Τ, U, and V are set to a multiple of the product of any two of 2Χ, 3Υ, and 5Ζ is because in the notebook computer, the operating frequency of many devices is 2^3¥ A multiple of the product of any of the 52, for example, the operating frequency of the VGA is 27ΜΗζ. Therefore, the present invention takes the least common multiple of the operating frequency commonly used in the notebook computer, and the relationship between the clock signals CLK1 and CLK2 is also obtained, thereby improving the accuracy. In the present embodiment, the multi-frequency phase-locked loop 300 receives the frequency signal to generate the clock signals CLK1 and CLK2, but does not limit the present invention. Figure 3 is a block diagram showing another clock generator in accordance with a second embodiment of the present invention. Referring to FIG. 3A, in addition to generating the clock signals CLK1 and CLK2, the multi-frequency phase-locked loop 300 can also generate CLK3, for example, in FIG. In the same principle as FIG. 3A, the multi-frequency phase-locked loop 300 receives the predetermined frequency signal ^, so that the frequency setting circuits 302 and 308 multiply the predetermined frequency signal Τ by Τ and then divide by W, and then generate the multi-frequency phase-locked loop 300. The clock signal CLK3, in which T and W are multiples of the product of 2X, 3Y, and 5Z, and X, Y, and Z are also positive integers. FIG. 3C is a partial internal block diagram of the multi-frequency phase locked loop. Referring to FIG. 3C, the voltage controlled oscillator 31 is coupled to the frequency divider 33, the frequency setting circuits 304, 306, and 308, and the output of the frequency divider 33 is coupled to the phase comparator 35. When the voltage controlled oscillator 31 starts to oscillate, an output clock signal is generated. 14 127161 wf 1 .doc/006 95-10-11 CLKOUT to the frequency divider 33 〇 The frequency divider 33 divides the frequency of the output clock signal CLKOUT The clock signal CLKA is generated after T, where T is a multiple of the product of any of 2X, 3Y, and 5Z. In addition, the phase comparator 35 is connected to the clock signal CLKA and the predetermined frequency signal A, and the phase comparator 35 generates a comparison clock signal CLKCOM according to the result of the comparison. Then, the comparison clock signal CLKCOM is subjected to a subsequent voltage boosting and low-pass filtering process (refer to FIG. 1A for the detailed principle), and then fed back to the voltage controlled oscillation circuit 31. Continuing to refer to Figure 3C, frequency setting circuits 304, 306, and 308 also receive the output clock signal CLKOUT. The frequency setting circuit 304 divides the frequency of the output clock signal CLKOUT by U to generate the clock signal CLK1; the frequency setting circuit 306 divides the frequency of the output clock signal CLKOUT by V to generate the clock signal CLK2; The frequency setting circuit 308 divides the frequency of the output clock signal CLKOUT by W to generate the clock signal CLK3. Among them, U, V, and W are multiples of the product of any of 2X, 3Y, and 52. When the entire multi-frequency phase-locked loop 300 is stabilized, the frequency of the clock signal CLKA is equal to the frequency of the predetermined frequency signal Α. In other words, the frequency of the output clock signal CLKOUT will be equal to T times the frequency of the frequency signal ^. In general, frequency setting circuits 304, 306, and 308 can be implemented with a frequency divider circuit. THIRD EMBODIMENT Fig. 4 is a block diagram showing a clock generator in accordance with a third embodiment of the present invention. Referring to FIG. 4, it is mentioned in the second embodiment that most of the devices in the notebook computer have a working frequency of a predetermined frequency signal multiplied by a multiple of the product of 2X, 3¥, and 5Z. But not all devices have their work 12716 defeated 9^: ia L') Μ page; 76twfl .doc/006 95-10-11 The frequency is the same. The operating frequency of some devices cannot be generated using the multi-frequency phase-locked loop 300 of the second embodiment, so a specific clock signal must be additionally generated. Therefore, in the present embodiment, a specific frequency phase locked loop 400 is specifically designed to generate a specific clock signal. In this embodiment, the specific frequency phase locked loop 400 can be combined with other circuits to cost the inventive clock generator. In the present embodiment, the frequency multiplex circuit 200 is combined with a specific frequency phase locked loop 400 to be combined with the clock generator of the present invention. The frequency multiplexing circuit 200 has been introduced in the first embodiment, and details are not described herein again. In addition, the specific frequency phase-locked loop 400 receives the predetermined frequency signal A to generate the clock signal CLK4 and the clock signal CLK5. With continued reference to FIG. 4, the particular frequency phase locked loop 400 includes a frequency setting circuit 402 and a frequency setting circuit 404. The specific frequency phase-locked loop 400 also receives the predetermined frequency signal A, and then passes through the frequency setting circuit 402, which causes the specific frequency phase-locked loop 400 to output the clock signal CLK5 of a specific frequency. In this embodiment, the clock signal CLK5 is The frequency is, for example, 24.567 MHz, and this frequency cannot be produced by the frequency setting circuit in the second embodiment. Next, the frequency setting circuit 404 multiplies the signal sent from the frequency setting circuit 402 by Q and divides P, so that the specific frequency phase-locked loop 400 generates the clock signal CLK4, and both Q and P are positive integers. Fourth Embodiment Fig. 5 is a block diagram showing a clock generator in accordance with a fourth embodiment of the present invention. Referring to Figure 5, in the present embodiment, the clock generator of the present invention includes a multi-frequency phase locked loop 300 and a specific frequency phase locked loop 400. Among them, multi-frequency lock 127 wf 1. doc/006 95, 10.11 II / month repair (under) positive replacement page 95-10-11 phase loop 300 and specific frequency phase-locked loop 400 are simultaneously received when receiving the predetermined frequency signal fi The individual operating principles of the pulse signals CLK1, CLK2, CLK3, CLK4, and CLK5 have been described in the above embodiments, and are not described herein again. [Fifth Embodiment] Fig. 6 is a block diagram showing a clock generator in accordance with a fifth embodiment of the present invention. Referring to Fig. 6, in the present embodiment, the frequency multiplexing circuit 200 of the first embodiment and the multi-frequency phase locked circuit 300 of the second embodiment are combined into a clock generator of the present invention. Please refer to the first embodiment and the second embodiment for their respective working principles, and details are not described herein again. Sixth Embodiment Fig. 7 is a block diagram showing a clock generator in accordance with a sixth embodiment of the present invention. Referring to FIG. 7, in the embodiment, the clock generator of the present invention includes a frequency multiplexing circuit 200, a multi-frequency phase-locked loop 300, and a specific frequency phase-locked loop 400 for receiving input clock signals and predetermined numbers. The frequency signal ^ is generated to generate clock signals CLK3, CLK4, CLK5, CLK6, CLK7, CLK8 and CLK9. The frequency of the CLK9 is the frequency of the predetermined frequency signal 6. In the embodiment, the frequency of the predetermined frequency signal fi is, for example, 14.318 MHz. In addition, in the present embodiment, the frequency setting circuit 302 multiplies the frequency of the predetermined frequency signal A received by the multi-frequency phase-locked loop 300 by 5 times 8 times 27 and sends them to the frequency setting circuits 304, 306, and 308, respectively. . The frequency setting circuit 304 divides the frequency of the clock signal sent from the frequency setting circuit 302 by 2X1 divided by 3Y1 by 5Z1. In addition, the frequency setting circuit 306 divides the frequency of the clock signal sent by the frequency setting circuit 302 by 2X2 divided by 3Y2 and divided by 5Z2, and the frequency setting circuit 308 is 12716. 76wfl.doc/006 95-10-11 The frequency of the clock signal sent by the frequency setting circuit 302 is divided by 2X3 divided by 3Y3 divided by 5Ζ3. The aforementioned XI, Χ2, Χ3, Yl, Υ2, Υ3, Zl, Ζ2, Ζ3 are all positive integers. The detailed operation of the frequency multiplexing circuit 200, the multi-frequency phase-locked circuit 300, and the specific frequency phase-locked circuit 400 have been described above, and thus the present invention will not be described herein. In the above six embodiments, the present invention can be modified, but the invention is not so limited. It is in accordance with the spirit of the present invention that the clock generator is comprised of a phase-locked loop and that a fixed predetermined frequency signal can be used to generate the output of a plurality of clock signals. Therefore, those skilled in the art can make changes according to actual needs. For example, Figure 8 is a block diagram of a more power efficient clock generator in accordance with a preferred embodiment of the present invention. In FIG. 8, each output clock signal is input to a switching circuit such as multiplexer 81, and each switching circuit is shown, for example, as shown in multiplexer 81, and receives an output enable signal 0-ΕΝ to determine whether or not Clock signals CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, and CLK9 are output. When the current generation circuit is in the power saving mode, the output enable signal 0-ΕΝ can control the output of all the switching circuits to be turned off to save power loss. In summary, the clock generator of the present invention has the following advantages: 1. The clock generator of the present invention only needs one input frequency because it arranges the required clock signal to a rule of the least common multiple. The signal can generate multiple different clock signals. Therefore, the number of quartz crystals required is only one, and the volume occupied by the clock generator of the present invention on the circuit is effectively reduced. Also, since the number of quartz crystals is small, the price of the entire clock generator of the present invention can be lowered. 2. The phase-locked loop in the clock generator of the present invention is idle in the spread spectrum controller
12716股 76twfl .doc/006 95-10-H 置的時候，不會隨之閒置而是轉而輸出時脈訊號，因此不 會造成浪費。 3. 本發明之時脈產生器也因爲結合了不同的鎖相迴 路，故不但可以使用一個輸入頻率訊號來產生多個不同的 時脈訊號，還可以同時進行展頻的動作。 4. 承上所述，因爲結合了不同的鎖相迴路，故不但可以 產生常用頻率的時脈訊號，還可以另外產生特定頻率的時 脈訊號。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 圖1A係習知鎖相迴路的方塊圖。 圖1B係繪示習知的時脈產生器方塊圖。 圖2A係本發明第一實施例之頻率多工電路方塊圖之 --- 〇 圖2B係本發明頻率多工電路方塊圖之二。 圖3A係本發明第二實施例之時脈產生器方塊圖之一。 圖3B係本發明第二實施例時脈產生器方塊圖之二。 H 3C係多頻鎖相迴路的部分內部方塊示意圖。 圖4係本發明第三實施例之時脈產生器方塊圖。 Η 5係本發明第四實施例之時脈產生器方塊圖。 Η 6係本發明第五實施例之時脈產生器方塊圖。 Η 7係本發明第六實施例之時脈產生器方塊圖。 12716路 76twfl .doc/00612,716 shares 76twfl .doc/006 95-10-H When set, it will not idle, but will output the clock signal, so it will not cause waste. 3. Since the clock generator of the present invention combines different phase-locked loops, not only one input frequency signal can be used to generate a plurality of different clock signals, but also the spread spectrum action can be performed at the same time. 4. As mentioned above, because different phase-locked loops are combined, not only can the clock signals of common frequencies be generated, but also the clock signals of specific frequencies can be generated. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a block diagram of a conventional phase-locked loop. FIG. 1B is a block diagram showing a conventional clock generator. 2A is a block diagram of a frequency multiplex circuit according to a first embodiment of the present invention. FIG. 2B is a block diagram of a frequency multiplex circuit of the present invention. Figure 3A is a block diagram of a clock generator of a second embodiment of the present invention. Figure 3B is a block diagram of the clock generator of the second embodiment of the present invention. A partial internal block diagram of the H 3C multi-frequency phase-locked loop. Figure 4 is a block diagram of a clock generator of a third embodiment of the present invention. Η 5 is a block diagram of a clock generator of a fourth embodiment of the present invention. Η 6 is a block diagram of a clock generator of a fifth embodiment of the present invention. Η 7 is a block diagram of a clock generator of a sixth embodiment of the present invention. 12716 Road 76twfl .doc/006
95-10-11 圖8係本發明之一較佳實施例之較省電的時脈產生器 方塊圖。 【圖式標示說明】 21、81、206 :多工器 35、101 :相位比較器 33、103 :除頻器 105 :參考訊號產生器 31、107 :壓控振盪器 109 :低通濾波器 111 :充電幫浦 113 :補償電路 115 :控制電路 100 :時脈產生器 102、104、106 :鎖相迴路 200 :頻率多工電路 202 :展頻控制器 204 :內部鎖相迴路 206a、206b :輸入端 206c :輸出端 300 :多頻鎖相迴路 302、304、306、308、402、404 :頻率設定電路 400 :特定頻率鎖相迴路95-10-11 Figure 8 is a block diagram of a more power efficient clock generator in accordance with a preferred embodiment of the present invention. [Illustration description] 21, 81, 206: multiplexer 35, 101: phase comparator 33, 103: frequency divider 105: reference signal generator 31, 107: voltage controlled oscillator 109: low pass filter 111 : Charging pump 113 : compensation circuit 115 : control circuit 100 : clock generator 102 , 104 , 106 : phase locked loop 200 : frequency multiplex circuit 202 : spread spectrum controller 204 : internal phase locked loop 206 a , 206 b : input Terminal 206c: output terminal 300: multi-frequency phase locked loop 302, 304, 306, 308, 402, 404: frequency setting circuit 400: specific frequency phase locked loop