TWI270839B - Liquid crystal display system with lamp feedback and method for controlling power to cold cathode fluorescent lamp - Google Patents

Abstract

A liquid crystal display system and CCFL power converter circuit is provided using a high-efficiency zero-voltage-switching technique that eliminates switching losses associated with the power MOSFETs. An optimal sweeping-frequency technique is used in the CCFL ignition by accounting for the parasitic capacitance in the resonant tank circuit. Additionally, the circuit is self-learning and is adapted to determine the optimum operating frequency for the circuit with a given load. An over-voltage protection circuit can also be provided to ensure that the circuit components are protected in the case of open-lamp condition.

Description

1,270839 ▼ IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a DC to AC power converter circuit. More specifically, the present invention provides a highly efficient controller circuit that uses zero-switching techniques to adjust the power to the load. The present invention is generally applicable to circuits that drive one or more cold cathode fluorescent lamps (CCFLs), but those skilled in the art will appreciate that the present invention can be applied to any load that requires high efficiency and precise power control. [Prior Art] Fig. 1 depicts a conventional cold cathode fluorescent lamp (CCFL) power supply system. The system generally includes a power source 12, a cold cathode fluorescent lamp ((:: 10 drive circuit 16 controller 14, a feedback loop 18, and one or more cold cathode fluorescent lights associated with LCD panel 20) Lamp (CCFL) The power supply 12 provides a DC voltage to the drive circuit 16 and is controlled by the controller 14 through the transistor M1. The drive circuit is a self-resonant circuit, which is a known Roy circuit circuit. Essentially, The drive circuit 16 is a self-oscillating DC to AC converter whose resonant frequency is determined by the inductor L1 and the capacitor (^, which specifies the number of turns of the transformer winding and winding. In operation, the transistor () 1 and (^2 alternately turns on and switches the input voltages on windings N1 and N2 respectively. If the body Q1 is turned on, the input voltage is applied to the winding N1. The voltage with the corresponding polarity will be placed on the other winding. The induced voltage of winding N4 makes the base of transistor Q2 extremely positive, and transistor φ is turned on by a small voltage drop between the collector and emitter terminals. The induced voltage of winding N4 also keeps transistor q2 94102201-0011C3CIP1 tw SPEC (amended) (02 950623) .doc 1270839 is in the off state. The transistor Q1 is turned on until the magnetic flux in the core of the transformer TX1 is saturated. When saturated, the voltage at the collector terminal of the transistor Q1 rises rapidly (to the value determined by the base circuit), and The induced voltage in the transformer drops rapidly. The transistor Q1 is pulled away from saturation and the VCE rises, causing the voltage on the winding N1 to drop further. The loss of the base drive will cause the transistor Q1 to turn off, which in turn causes the core to be in the core. The magnetic flux drops slightly and a current is generated in winding N4 to turn on transistor Q2. The induced voltage of N4 keeps transistor Q1 in a saturated conduction state until the core is saturated in the opposite direction, and a similar reverse operation occurs to complete Switching Cycles Although the cold cathode fluorescent lamp driving circuit 16 is composed of relatively few components, its proper operation depends on the nonlinear and complex interaction between the transistor and the transformer. In addition, the capacitance C1, the transistors Q1 and Q2 vary. (typical error is 35%) The drive circuit 16 is not allowed to be used in a parallel transformer arrangement because any copy of the drive circuit 16 is An additional, undesired operating frequency will be generated that may resonate at certain harmonics. When applied to a cold cathode glory (CCFL) load, the circuit is generated in a cold cathode fluorescent lamp (CCFL) Obvious, undesirable, beat effect. Even if the error is almost consistent, because the drive circuit 16 operates in self-resonant mode, its "Beat" effect cannot be removed' because of any The reproduction of the circuit will have its own unique operating frequency. Some other drive systems can be found in U.S. Patent Nos. 5,430,641, 5,619,402, 5,615,93, 5,8, 18,172. These references are all inefficient, two-stage power conversion, variable frequency operation, and /bit 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc 1270839 Disadvantages associated with load. In addition, when the load contains a cold cathode fluorescent lamp (CCFL) and components, an intrinsic capacitance is introduced, which affects the impedance of the cold cathode fluorescent lamp (CCFL) itself. In order to efficiently design a properly operated circuit, the circuit design must take into account the intrinsic impedance used to drive the cold cathode fluorescent lamp (CcFL) load. This type of approach is not only time consuming, expensive, but also difficult to produce an optimal converter design when handling different loads. Therefore, there is a need to overcome these shortcomings and provide a circuit solution that is characterized by high efficiency, reliable lighting of cold cathode fluorescent lamps (CCFLs), load independent power regulation, and single frequency power conversion. SUMMARY OF THE INVENTION The present invention provides a liquid crystal display system comprising: a liquid crystal display panel; a cold cathode fluorescent lamp for illuminating the liquid crystal display panel; and a secondary to the cold cathode fluorescent lamp a transformer winding that supplies current to the cold cathode fluorescent lamp; a primary transformer winding coupled to the secondary transformer winding that provides magnetic flux to the secondary transformer winding; a switch that engages the primary transformer winding, The current is allowed to flow through the primary transformer winding; a feedback control loop circuit coupled to the cold cathode fluorescent lamp receives a feedback signal indicative of the power supplied to the cold cathode fluorescent lamp, and only if When the signal is greater than a predetermined threshold, the power delivered to the cold cathode fluorescent lamp is controlled. In another embodiment, the liquid crystal display system includes: a liquid crystal display panel 'a cold cathode fluorescent lamp for illuminating the liquid crystal display panel; a secondary transformer winding coupled to the cold cathode fluorescent lamp, which is provided The current is given to the cold 94102201-00UC3CIP1 tw SPEC (amended) (02 950623).doc · Ί · .1270839 cathode fluorescent lamp, a primary transformer winding coupled to the secondary transformer winding 'which provides magnetic flux to the secondary transformer winding a switch coupled to the primary transformer winding that allows current to flow through the primary transformer winding; a feedback control loop circuit coupled to the cold cathode fluorescent lamp that receives a feedback from the cold cathode fluorescent lamp No., when the feedback signal is expressed as an open_lamp state, reducing the power supplied to the cold cathode fluorescent lamp. In still another embodiment, the liquid crystal display system comprises a liquid crystal display panel; a cold cathode fluorescent lamp for illuminating a liquid crystal display panel; a secondary transformer winding coupled to the cold cathode fluorescent lamp, which supplies current to the cold cathode fluorescent lamp, one side a primary transformer winding coupled to the secondary transformer winding, which provides magnetic flux to the secondary transformer winding; a first switch coupled to the primary transformer winding that allows current to flow through the primary transformer winding in a first direction; a second switch coupled to the primary transformer winding, the current is allowed to flow through the primary transformer winding in a second direction; a coupling Φ to the primary transformer winding and a third switch of the first switch, when the third switch And when there is an overlap state with the first switch, the first switch provides current, the primary transformer winding; and a feedback control loop circuit coupled to the cold cathode fluorescent lamp, receiving a cold cathode fluorescent The feedback signal ' of the light lamp' maintains the cold cathode fluorescent lamp at a predetermined minimum power by maintaining a minimum overlap between the third switch and the first switch. The present invention also provides a method of controlling the power supplied to a cold cathode fluorescent lamp in a liquid crystal display system, the method comprising the steps of: providing a pulse signal, '. The electric 曰 a body acts as a conduction path of a primary transformer winding; generates a 011C3CIP1 ^ SPEC (four) n butterfly 〇 2 9 inspection 1270839 a feedback signal from a cold cathode fluorescent lamp coupled to the primary transformer winding, the signal represents An electrical state of the cold cathode fluorescent lamp; receiving a feedback signal from the cold cathode fluorescent lamp; and adjusting to provide the cold only when the feedback signal indicates that the cold cathode fluorescent lamp is lit The power of the cathode fluorescent lamp. It will be apparent to those skilled in the art that the following description of the preferred embodiments and methods of use are not intended to limit the invention. The invention is to be construed as being limited by the scope of the appended claims. Other features and advantages of the present invention will be described in the following detailed description with reference to the accompanying drawings. [Embodiment] Although it is not intended to be limited by the examples, the following detailed description will be referred to as a load of the circuit of the present invention with reference to a display screen having a cold cathode fluorescent lamp (CCFL). However, it will be apparent that the invention is not limited to driving only one or more cold cathode fluorescent lamps (CCFLs), and the invention should be broadly understood to be a power converter circuit and method that is independent of the particular application load. In summary, the present invention provides a circuit that uses a feedback signal and a pulse signal to adjust the on-time of two pairs of switches to controllably transfer power to the load. When a pair of switches are controllably turned on, their on-times overlap and power is transferred to the load through a transformer along the conduction path defined by the pair of switches. Similarly, when another pair of switches is controllably turned on,

94102201-0011C3CEP1 tw SPEC (amended) (02 950623).doc Q .1270839 'When the on-time overlaps, the power is routed through the transformer to the load along the conduction path defined by the other pair of switches. Therefore, the present invention can accurately control the power delivered to the fixed load by selectively turning on the overlap between the control switches. Further, the present invention includes overcurrent and overvoltage protection; the circuit It circuit suspends power to the load in the event of a short circuit or an open circuit. Moreover, the controllable switch topology described herein allows the circuit to operate under load independent and with a single-chip frequency that is independent of the spectral response of the transformer configuration. These characteristics will be discussed below with reference to the drawings. The circuit diagram shown in Figure 2 shows a preferred embodiment of the phase shifted, full bridge, zero voltage switching power converter of the present invention. In essence, the circuit shown in FIG. 2 includes a power supply 12; a plurality of switches 8A arranged to define an alternate conduction path for the diagonally arranged switch pairs; driving the drive circuit 5 of each switch; A sweeper 22 is generated which generates a square wave pulse to the drive circuit 5, a transformer TX1 (having an associated harmonic 10-slot circuit defined by the secondary side of the transformer TX1 and the capacitor (1) jin) and a load. Preferably, the present invention also includes an overlay feedback control loop 40 that controls the conduction time of at least one of each pair of switches, thereby allowing controllable power to be delivered to the load. A power source 12 is applied to the system. Initially, the power supply generates a bias/reference signal 30 for use by the control circuitry (in the feedback control loop 4). Preferably, a frequency sweeper 22 generates a pulse signal having a duty cycle of 5〇%, which starts at a higher frequency and sweeps down at a predetermined rate and a predetermined step (ie, a square that can be changed in pulse width). Wave signal). Sweeper 22 is preferably a programmable frequency generator known in the art. (from the frequency sweeper 22) The pulse signal 9〇 is transmitted to the drive •10- 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc 1270839 Dynamic circuit (B-Drive) (which drives switch B, ie control switch b The gate is transmitted to the A" drive circuit (A-Drive) which produces a complementary pulse signal 92 and a ramp signal 26. The complementary pulse signal 92 differs from the pulse signal 90 by approximately 180 degrees, and the ramp signal 26 is approximately 90 degrees out of phase with the pulse signal, as described below. Ramp signal 26 is preferably a sawtooth signal as shown. Ramp signal 26 will be compared by comparator 28 to output signal 24 (referred to herein as a CMP signal) of error amplifier 32, thereby producing signal 94. The output signal 94 of the comparator 28 is likewise a pulse signal transmitted to the c-drive circuit (C-Drive) with a duty cycle of 50% for triggering the conduction of the switch C (Switch-C), which then The signal again determines the amount of overlap between switch B and switch C, and between switch A and switch D. Its complementary signal (approximately 180 degrees out of phase) is applied to switch d through a D-drive circuit (D-Drive). Those skilled in the art will appreciate that the circuits of drive circuit_A to drive circuit D respectively consume control lines (e.g., gates) from switch A to switch D, as described herein, allowing each switch to be controllably Turn on. Lamp current regulation is accomplished by adjusting the amount of overlap between switches B, C and A, D. In other words, the amount of overlap in the on-state of the switch determines the amount of power processed in the converter. Thus, switch B and switch C, and switch A and switch D are referred to herein as overlapping switches. Although not wishing to be limited by the examples in this embodiment, the B drive circuit is preferably constructed of a totem pole circuit, a conventional low impedance operational amplifier circuit or an emitter follower circuit. The C-drive circuit has a similar construction. Since the A-drive circuit and the D-drive circuit are not directly grounded (ie, floated), these drive circuits are preferably implemented by a buck circuit (b〇〇t_strap circuit) 94102201-0011C3CIP1 tw SPEC (amended) (02 950623). Doc 1270839 or other high-side drive circuits known in the art are constructed. Further, as described above, the A-drive circuit and the 1)-drive circuit include an inverter for inverting signals (i.e., phases) from the B-drive circuit and the C-drive circuit, respectively. High efficiency operation is achieved through a zero voltage switching technique. Four metal oxide half V bodies (MOSFETs) (switch A to switch D) 80 are turned on after their intrinsic diodes (D1 to D4) are turned on, which is provided in the transformer/capacitor (TX1/C14& The current flow path of the energy, thereby ensuring that when these switches are turned on, the voltage across them is zero. Due to such controlled operation, the switching losses can be minimized and high efficiency is maintained. Figures 2a through 2f show overlap The preferred switching operation timing diagram of the switch 80. The switch C is turned off during a certain period in which the switches B and C are simultaneously turned on (Fig. 2f). When the switch C is turned off, the current in the slot (refer to Fig. 2) flows first. The intrinsic diode D4 in switch D (Fig. 2e), the primary side of the transformer, the capacitor C1, and the switch B, thus causing the capacitor C1 to resonate with the voltage and current in the transformer as a result of energy transfer when the switch C is turned on. (Figure 2f) Note that this condition must occur because a sudden change in the direction of the current on the primary side of the transformer will violate Faraday's law. Therefore, the current must flow through the intrinsic diode D4 when the switch c is open. The essential diode D4 is turned on. After the switch D is closed Similarly, switch B is turned off (Fig. 2a), and current is transferred to the intrinsic diode D1 associated with switch a (Fig. 2e) before switch A is turned on. Similarly, switch D is turned off (Fig. 2) Now the current flows from switch A, through the capacitor, the primary side of the transformer, and the intrinsic diode D3. Switch C turns on after the intrinsic diode D3 turns on (Figure 2e). Switch B turns on after switch A is turned off, which allows the essence Diode D2 is turned on by 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -12- •1270839 before switch B is turned on. Note that the on-time switches B, C, and A, D are on time. The overlap determines the energy delivered to the transformer, as shown in Figure 2f. In this embodiment, Figure 2b shows that the ramp signal 26 is generated only when the switch A is turned on. Thus, the drive circuit a that produces the ramp signal 26 is preferred. A constant current generator circuit (not shown) is included, the circuit including a capacitor having an appropriate time constant for generating a ramp signal. For this purpose, a reference current (not shown) is used to charge the capacitor, and the capacitor is grounded (by example _ such as a battery The body switch) such that the discharge rate exceeds the charge rate, thus producing a sawtooth ramp L No. 26. Of course, as described above, this can be achieved by integrating the pulse signal 90, so an integrator circuit (eg, an operational amplifier and Capacitor) to form the ramp signal 26. During the lighting process, a predetermined minimum overlap is produced between the two diagonal switches (ie between switches A, D and B, C). This produces an input. The minimum energy to the tank circuit including the capacitor ci, transformer, capacitor C2, capacitor 〇, and cold cathode fluorescent lamp (CCFL) load. Note that the load can be resistive φ and / or capacitive. The drive frequency starts at a predetermined higher frequency until the resonant frequency of the equivalent circuit reflected by the tank circuit and the secondary side of the transformer is approached, and a large amount of energy is transferred to the load connected to the cold cathode fluorescent lamp (CCFL). . Due to the high impedance characteristics of the cesium before lighting, the cold cathode fluorescent lamp (ccfl) is affected by the high voltage supplied to the primary side energy. This voltage is sufficient to illuminate the cold cathode fluorescent lamp (CCFL). When the cold cathode fluorescent lamp (CCFL) impedance drops to its normal operating value (eg 1 〇〇 ohm to 13 〇 ohms), the energy supplied to the primary side based on the minimum overlap operation will no longer be sufficient to maintain cold cathode fluorescence Steady state operation of the lamp (CCFL). The output of comparator 28 begins to adjust its 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -13- 1270839 function to increase the overlap. Therefore, the size of the output of comparator 28 determines the amount of overlap. For example: Referring to Figures 2b, 2c and feedback control loop 40 of Figure 2, it is important to note that when comparator 28 determines ramp signal 26 (generated by drive circuit_A) and CMP signal 24 (generated by error amplifier 32) When the values are equal, the switch C is turned on. This is shown as intersection 36 in Figure 2b. In order to prevent short circuit, switches A, B and C, D must not be turned on at the same time. The energy delivered to the transformer is adjusted by controlling the level of overlap of the switches A, D and B, C by controlling the level of the CMP signal. In order to adjust the energy delivered to the transformer (and thus the energy delivered to the cold cathode fluorescent lamp (CCFL) load), switches C and D are time shifted with respect to switches A and B by controlling the CMP signal 24 of the error amplifier ( Time-shifted). As can be seen from the timing diagram, if the drive pulse from the output of the comparator 28 into the switches C and D is shifted to the right by increasing the level of the CMP signal, an increase in overlap between the switches A and D, B and C is achieved. Thus, the energy delivered to the transformer is increased. In fact, this corresponds to a higher-lamp current operation. Conversely, shifting the drive pulses of switches C and D to the left (reducing the CMP signal) will reduce the amount of energy transferred.

For this purpose, the error amplifier 32 compares the feedback signal FB with a reference voltage REF. The feedback signal FB is a measure of the current value through the sense resistor Rs, which represents the total current through the load 20. The reference voltage REF is a signal representative of the ideal load condition, such as the desired current through the load. In normal operation, REF=FB However, if the load state is intentionally offset, such as from a dimmer switch associated with an LCD panel display, the value of the reference voltage REF will increase accordingly. /cut back. This comparison value accordingly produces a CMP 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -14- 1270839 signal. The value of the CMP signal reflects the load state and/or an internal bias voltage and is implemented by the difference between REF and FB (i.e., REF-FB). In order to protect the load and the circuit from being in an open state of the load at the load end (for example, 'Cold cathode fluorescent lamp (CCFL) open state under normal operation), the feedback signal FB is preferably a reference value (not shown and compared with the above reference voltage) The ref signal is different) compared to the current sense comparator 42 whose output defines the state of the switch 38 as described below. The reference value can be programmable, and/or user definable, and preferably reflects the minimum or maximum current allowed by the system (eg, can be rated for individual components, particularly for cold cathode fluorescent light). Light (CCFL) load). If the value of the feedback signal FB and the reference signal is within the allowable range (normal operation), the output of the current sense comparator is 1 (or high potential). This allows the CMP signal to flow through switch 38, which operates as described above to transfer power to the load. However, if the values of the feedback signal FB and the reference signal are outside the predetermined range (open or shorted state), the output of the current detecting comparator is 〇 (or low), and the CMP signal is prohibited from flowing through the switch 38. (Of course, the inverse process can be implemented where the switch is triggered in a low state). The minimum voltage Vmin is supplied by switch 38 (not shown) to the comparator 28 until the current sense comparator indicates that the allowable current flows through the sense resistor RS. Therefore, the switch 38 is included for appropriately selecting the programmable voltage vmin when the detected current is zero. Referring again to Figure 2b, the effect of this operation is that the DC value of the CMP signal drops to the nominal or minimum value (i.e., CMP = Vmin) so that the transformer TX1 does not experience a high voltage state. Therefore, the intersection 36 is shifted to the left, thereby reducing the amount of overlap between the complementary switches (the switch C is turned on at the intersection 36). Similarly, when the detected value is 〇 (or other preset value indicating an open state), the current detecting comparator 42 is connected to 94102201-00HC3CIP1 tw SPEC (amended) (02 950623).doc 1270839 to the frequency generator 22' The frequency generator 22 is turned off. The cmp signal is fed back to the protection circuit 60. If the cold cathode fluorescent lamp (CCFL) is removed during operation (open state), the frequency sweeper 22 is turned off. In order to protect the circuit from an overvoltage condition, the present embodiment preferably includes a protection circuit 60' which operates as follows (described above for overcurrent protection by current sense comparator 42). The protection circuit 6A includes a protection comparator 62 that compares the CMP signal with a voltage signal 66 derived from the load 2〇. Preferably, the voltage signal is derived from voltage divider capacitors C2 and C3 (i.e., in parallel with load 20) as shown in FIG. In the open-lamp condition, the sweeper continues to sweep until the 〇vp signal 66 reaches a critical value. 〇vp k#66 is taken from the output voltage divider capacitor C2&C3 to detect the output voltage of the transformer τχι. To simplify the analysis, these capacitors also represent the total capacitance of the equivalent load capacitor. The threshold is a reference value and the circuit is designed such that the voltage on the secondary side of the transformer is greater than the minimum lighting voltage (e.g., the voltage required by the Lcd panel) and less than the rated voltage of the transformer. When the 〇VP signal φ exceeds the critical value, the sweeper stops sweeping. At the same time, the current detecting comparator 42 does not detect a signal on the sense resistor. Therefore, by setting the signal at the output signal 24 of the switch 38 to the minimum value, the overlap between the switches A and D, B and C is minimized. Preferably, once the OVP signal exceeds the threshold, timer 64 begins to operate, thereby initiating a time-out sequence initialization. The pause period is preferably designed according to load requirements (such as the cold cathode fluorescent lamp (CCFL) of the LCD display panel), but can also be set to some programmable value. Once the pause is reached, the drive pulse is inactive, thus providing a safe working output of the converter circuit. That is, the protection circuit 60 provides a sufficient voltage to make 94102201.0011C3CIP1 tw SPEC (amended) (02 950623).doc . 16 . 1270839 The lamp lights 'right' is not connected to 辕w 俊 褥,, It is turned off after a certain period of time, so it is possible to avoid the wrong high voltage at the turn of the ruling. Since the unlit lamp is similar to the open circuit of the lamp, this p-spot θ and 4 # are time-necessary. Figures 3 and 3a-3f depict another preferred embodiment of the present invention, a / / a lean-month machine / parent flow circuit. In this embodiment, the circuit type is similar to that provided in Figures 2 and 2a_2f.

However, the present embodiment also includes a phase-locked loop (PLL) 70' for controlling the frequency sweeper and a flip-flop circuit 72 for timing the input of the signal of the c-drive circuit. It can be understood from the timing diagram that if the pulse of the switches C and D is shifted to the right by 5〇% by increasing the size of the (10) signal, the increase of the overlap between the switches VIII and D, Β and C can be realized, thereby increasing the delivery to The energy of the transformer. In effect, this corresponds to the operation of the higher lamp current (if necessary, the REF voltage can be manually increased as described above). Conversely, the left shift of the drive pulse of switch C*D (by reducing the CMP signal) reduces the amount of energy being delivered. Phase-locked loop 7〇 Maintains the phase relationship between the feedback current (via sense resistor Rs) and the tank current (transformed |§ TX1 / valley C1) under normal operation, as shown in Figure 3. The phase locked loop (PLL) 70 preferably includes input signals from the tank circuit (capacitor (^ and transformer τχ primary side), signal 98, and sense resistor RS (the FB signal described above). Once the cold cathode fluorescent lamp (CCFL) is clicked The lamp, and the current in the cold cathode fluorescent lamp (CCFL) is detected by the sense resistor RS, and a phase-locked loop (PLL) 70 is activated which locks between the lamp current and the primary resonant tank (capacitor C1 and transformer primary side) current. Phase. That is, the phase-locked loop (PLL) regulates the frequency of the sweeper 22 due to any fundamental changes in temperature, mechanical configuration, such as the wiring between the converter and the LCD panel, and the effects. The distance between the lamp of the capacitance value and the inductance value and the metal chassis of the LCD panel. The system is better to protect the current of the resonant tank circuit and the voltage flowing through the detecting resistor Rs. 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc 1270839 The phase difference between the (load currents) is 180 degrees. Therefore, the system can find an optimum operating point regardless of the specific load state and/or the operating frequency of the tank circuit. Figure 3 The feedback loop works similarly. The above description of Fig. 2. However, as shown in Fig. 3b, this embodiment is timed by the flip-flop circuit 72 (the start # of a drive circuit output is counted. For example, in normal operation, the error amplification boundary 32 The output will be fed through control switch 38 (described above), which results in output signal 24. A certain amount of overlap between switch a and 〇, B and C is obtained by comparator 28 and flip-flop circuit 72, positive and negative. The circuit 72 drives the switches c and d (the D-drive circuit produces a complementary signal to the C-drive circuit). This provides steady-state operation for the cold cathode fluorescent lamp CCFL (display panel) load, taking into account the cold during normal operation. Cathode Fluorescent Lamp CCFL (Display Panel), the CMp signal is increased to the boundary value of the error amplifier output (rail 〇f 〇utput), and the protection circuit is triggered immediately. This function is disabled when lighting. Refer briefly to Figure 3a- 3f, in this embodiment, the switch D is alternately triggered by the c-drive circuit and the D-drive circuit as the result of the operation of the flip-flop circuit 72. As shown in FIG. 3b, the flip-flop is triggered each time, thereby initializing the drive circuit (and Initialize D relatively The drive circuit). The other timings operate in the same manner as described above with reference to Figures 2a-2f. Referring now to Figures 4a-4f, the output current of Figure 2 or 3 is simulated. For example, Figure 乜 shows the frequency sweep at 21V input. When the device is close to 75.7 KHz (0.5 us overlap), the output reaches 1.67 KVp_p. If the cold cathode fluorescent lamp (CCFL) requires 33〇〇Vp-p lighting, this voltage is not enough to give the cold cathode fluorescent lamp (CcFL) point. When the frequency drops to 68 KHz, the minimum overlap produces about 3.9 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc .1270839 KVp-p at the output, which is enough to light the cold cathode fluorescent lamp (CCFL). ). As shown in Figure 4b. At this frequency, the overlap is increased to 1.5 us, which causes the output ι·9 KVp-p to operate the lamp impedance of 130 K ohms. This has been shown in Figure 4C. As another example, Figure 4d shows the operation at an input voltage of 7 v. At 71β4 KHz, the output is 750 Vp-p before lighting. When the frequency is reduced, the output voltage increases until it lights up. Figure 4e shows an output of 3500 Vp-p at 68.5 KHz. The regulation of the cold cathode fluorescent lamp (CCFL) current is accomplished by adjusting the weight and supporting an impedance of 130 K ohms after lighting. The voltage of the cold cathode fluorescent lamp (CCFL) is now ι·9 KVp_p for the 660 Vrms lamp. This is also shown in Figure 4f. Although not shown, the circuit simulation of Figure 3 proceeds in a similar manner. It should be noted that the difference between the first and second embodiments (i.e., the addition of a flip-flop and a phase-locked loop (PLL) in Figure 3) will not affect the overall operating parameters set forth in Figures 4a-4f. However, the decision to add a phase-locked loop (PLL) is to consider the non-ideal impedance generated in the circuit and can be added as an alternative to the circuit shown in Figure 2. At the same time, the addition of the flip-flop allows the removal of the constant current circuit described above. Therefore, it is apparent that a highly efficient and adaptable DC/AC converter circuit is provided, which satisfies the objectives set forth herein. It will be apparent to those skilled in the art to which the invention pertains that modifications may be made. For example, although the present invention has been described as using a MOSFET as a switch, it is known in the art to which the entire circuit can be constructed using a BJT transistor, or a combination of any type of transistor, including a MOSFET and a BJT. Other modifications are also possible. For example, the driving training example associated with the driving circuit B and the driving circuit - D (10) tw s SPEC (Cai nded) (〇 2 95 〇 623) such as • 1270839 circuit can be composed of a common collector circuit because of the associated transistor Grounded, so there is no floating state. The phase-locked loop (PLL) described herein is preferably a conventional phase-locked loop (PLL) 7〇 known in the art to which the present invention pertains, suitably modified to receive input signals and generate control signals, as described above. Pulse generator 22 is preferably a pulse width modulation circuit (pWM) or a bandwidth modulation circuit (FWM), both of which are well known in the art to which the present invention pertains. Similarly, the 'keeping circuit 60' and the timer are constructed of known circuits and modified as appropriate, and operate as described. Figure 5 depicts an embodiment of a liquid crystal display system of the present invention. The liquid crystal display system 500 includes a thin film transistor display screen 5〇1. The thin film transistor display screen 5〇1 is coupled to the row driver 502. Row driver 502 controls the rows on thin film transistor display 501. The thin film transistor display screen 〇1 is also coupled to the column driver 503. The column driver 503 controls the columns on the thin film transistor display screen 5〇1. Row driver 502 and column driver 503 are coupled to timing controller 5〇4. The timing controller 504 controls the timing of the row driver 502 and the column driver 503. Timing controller 504 is coupled to video signal processor 505. The video signal processor 5〇5 processes the video signal. In another embodiment, video signal processor 5〇5 may be a director device. The thin film transistor display screen 501 is illuminated by a display illumination system 599. Display illumination system 599 includes a cold cathode fluorescent lamp 562. Cold cathode fluorescent lamp 562 is coupled to secondary transformer winding 560. The secondary transformer winding 56 is a cold cathode fluorescent lamp 5 62 for current supply. The secondary transformer winding 5 60 is fused to the primary transformer winding 5 18 . The primary transformer winding 5 18 provides magnetic flux to the secondary transformer winding 56 〇. Primary transformer winding 5 18 is coupled to switch 532. Switch 532 allows current 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -20- 1270839 to flow through primary transformer winding 518. Primary transformer winding 518 is also lightly coupled to switch 512. Switch 512 allows current to pass through primary transformer winding 518. Switch 532 and switch 512 are coupled to controller 550. Controller 550 provides a pulse signal for controlling the switching of switch 532 and switch 512. It is worth noting that any of the controllers described herein can function as controller 550. It is also worth noting that any of the display illumination systems described herein can be substituted for display illumination system 599. Figure 6 depicts a liquid crystal display system in accordance with one embodiment of the present invention. The liquid crystal display system 600 includes a thin film transistor display screen 601. A thin film transistor display is coupled to row driver 602. Row driver 602 controls the rows on thin film transistor display 601. Thin film transistor display screen 601 is also coupled to column driver 603. The column driver 603 controls the columns on the thin film transistor display screen 601. Row driver 602 and column driver 603 are coupled to timing controller 6〇4. The timing controller 604 controls the timing of the row driver 602 and the column driver 603. Timing controller 604 is coupled to video signal processor 605. The video signal processor 6〇5 processes the video signal. Video signal processor 605 is coupled to a video demodulator 606. Video demodulator 606 demodulates the video signal. The video demodulator 606 is coupled to a tuner (tunei 〇 607. The tuner 6 7 provides a video signal to the video demodulator 606. The tuner 607 adjusts the liquid crystal display system 6 to a particular frequency. Video demodulation The 606 is also coupled to the microcontroller 6. 8 The tuner 607 is also coupled to an audio demodulator 611. The audio demodulator 611 demodulates the audio signal from the tuner 607. The audio demodulator 611 is coupled to an audio signal processor. 610. The audio horn processor 610 processes the audio 来自 from the audio demodulator 611. The audio horn processor 610 is coupled to the audio amplifier 6-1. The audio amplifier 609 amplifies the audio signal from the audio signal processor 61 94. -0011C3CIP1 tw SPEC (amended) (〇2 950623) d〇 (-21 - 1270839) The thin film transistor display screen 601 is illuminated by the display illumination system 699. The display illumination system 699 includes a cold cathode fluorescent lamp 662. The cold cathode fluorescent lamp 662 Coupled to secondary transformer winding 660. Secondary transformer winding 66A provides current to cold cathode fluorescent lamp 662. Secondary transformer winding 66 is coupled to primary transformer winding 618. Primary transformer winding 61 8 is secondary The transformer winding 66 is provided with a magnetic flux. The primary transformer winding 618 is coupled to a switch 632. The switch 632 allows current to flow through the primary transformer winding 618. The primary transformer winding 6丨8 is also coupled to the switch 612. The switch 612 allows current to pass through the primary transformer winding 618. Switch 632 is coupled to switch 612 to controller 650. Controller 650 provides a pulse signal for controlling the switching of switch 632 and switch 612. It is noted that any of the controllers described herein can function as controller 650. It should be noted that any of the display illumination systems described herein may be substituted for display illumination system 699. Figure 7 depicts a liquid crystal display system in accordance with an embodiment of the present invention. Liquid crystal display system 700 includes a graphics adapter (Graphics Adaptor) 790. Liquid crystal display system The 700 may also include the components of the liquid crystal display system 5 shown above and shown in Figure 5, or the components of the liquid crystal display system 600 described above and shown in Figure 6. The Graphics Adaptor 790 is coupled to a video signal processing. The video signal processor 505 can be the video signal as described above and shown in FIG. The 505, or the video signal processor 605 described above and illustrated in Figure 6. A Graphics Adaptor 790 is coupled to the Chipset Core Logic 791. The Chipset Core Logic 791 transfers data between devices connected thereto. Core logic 791 is also coupled to microprocessor 792. Microprocessor 792 processes the data, including video material. The chipset core logic 791 also meets 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -22- J270839 to memory 793. Memory 793 can be a random access memory and provides short term storage of information. Chipset core logic 791 is also coupled to hard disk drive 794. Hard disk drive 794 provides long term storage of data. Chipset core logic 791 is also incorporated into optical disk drive 795. The optical disk drive 795 extracts data from a CD-ROM or a DVD-ROM. Referring to Figure 8, an embodiment of a switch mode cold cathode fluorescent lamp (CcFL) power supply circuit 100 of the present invention is depicted. The present invention is a switch mode power supply that provides energy to a cold cathode fluorescent lamp (CCFL). This power supply converts a constant current (DC) low voltage into an alternating current (AC) high voltage and supplies it to a cold cathode fluorescent lamp (CcFL). The switch mode power supply circuit includes a first switch having a source, a drain and a gate. The drain of the first switch is connected to the primary winding of the step-up transformer. The secondary winding of the step-up transformer has a number of turns of at least 20 times the number of primary windings, preferably 50 to 150 times. The source of the first switch is connected to a power source. A second switch also contains a source, a drain and a gate. The drain of the second switch is simultaneously connected to the drain of the first switch and one end of the primary winding of the transformer. The source of the second switch is connected to the ground reference of a power supply. The primary winding has a second end that is coupled to the midpoint of a two-capacitor voltage divider. Thus, the two switches are connected in series to approximately equalize the input voltage of the power supply. These two capacitors are connected in series and connected to both ends of the power supply. A control circuit transmits a control signal to the first and second switches to alternately turn the switches on at 18 degrees. When the first switch is turned on, a current flows through the first switch and the primary winding of the transformer in a forward direction. When the second switch is turned on, this current flows in the reverse direction through the primary winding of the transformer and through the second open 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -23. .1270839. The transformer is driven in both directions such that the magnetic flux swept to the core is used in two quadrants in the hysteresis curve associated with the transformer. This reduces the size of the transformer core, which saves the cost of the transformer.

The two capacitors form a capacitive divider that is connected to the - terminal of the primary winding of the transformer. When each switch is turned on, the two capacitors are charged or discharged by the current flowing through the primary winding of the transformer. When the #第_ switch is turned on, the current is charged for the second capacitor while the first capacitor is discharged, and the current is reset when the first switch is turned off and the essential diode connected to the second switch is turned on. When the second switch is turned on, the current flowing through the primary winding of the transformer is reversed. As this current flows, the first capacitor is charged and the second capacitor is discharged. After the second switch is turned off, current is recovered via the intrinsic diode of the first switch. If the switches are turned on when their essential diodes are turned on, then the switches are essentially turned on at zero voltage. This zero voltage switching technique minimizes the switching losses of the switch. Therefore, the efficiency of the power converter is improved. The power circuit 100 includes a controller 150, a first switch 112, a second switch 132, and a transformer 120, and is coupled to the power source 274 for use as a load (eg, a cold cathode fluorescent lamp (CCFL) in a flat panel display). 162, the tablet can not provide power for &quot;liquid crystal display. The first switch 112 can be an N-channel metal oxide semiconductor field effect transistor (MOSFET) gating switch and includes a drain 丨 14 connected to one end of the primary winding 187 of the step-up transformer 120. The first end 125 of the primary winding 11 $ is coupled to the junction of the first capacitor 124 and the second capacitor 126. The source 128 of the first switch 112 is coupled to the ground reference of the power source 274. The second switch 132 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -24- 1270839 can be a P-channel MOSFET gate switch. The drain of the p-channel switch 132 is also coupled to the drain 114 of the first switch 112. The first switch U2 and the second switch 132 both include the intrinsic diodes 134 and 136, respectively. Gate 138 and gate 152 of switches 132 and 112 are coupled to the output of controller 150. The secondary winding 160 of the step-up transformer 120 is coupled to a cold cathode fluorescent lamp (CCFL) 162. Compared with the nonlinear magnetic permeability of the saturation core used in the transformer in the R〇yer circuit, a magnetic core with linear magnetic permeability is formed in the step-up transformer 12〇. The core is not saturated when the power circuit 1 is operating. The step-up transformer 120 has a turns ratio of at least 20:1 and is typically in the range of 50:1 to 150:1. The secondary winding 16A of the step-up transformer 120 is connected in parallel with the two capacitors 163, 164 in series. Capacitors 163, 164 form a voltage divider for detecting the voltage of secondary winding 160 of step-up transformer 120 and converting the rectangular wave of primary winding 丨丨8 into an approximately sinusoidal wave for supply to a cold cathode fluorescent lamp (CCFL). Load 162. Under normal operation, voltage detection 1 86 is always reset by switch 1 70, which is controlled by the current flowing through the cold cathode fluorescent lamp (CCFL) 162. The function of switch 17〇 will be detailed below. The controller 150 can be a pulse width modulation controller that provides a first gate drive signal 152 to the gate 152 of the first switch 112 and a second gate drive signal 138 to the gate 138 of the switch 132. In addition to providing the drive ## for the switches 112, 132, the controller 150 provides other functions, such as two distinct frequencies for cold cathode fluorescent lamp (CCFL) lighting and normal operation. A lamp-on identification circuit 250 in control 150 is used to determine if the cold cathode fluorescent lamp (CCFL) 16 2 is clicked to 'determine which of the two frequencies is -25- 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc 1270839 Output. When the cold cathode fluorescent lamp (CCFL) 162 is turned on, the light-on signal 252 is de-asserted and indicates that the cold cathode fluorescent lamp (CCFL) 162, which is not illuminated, is open on the circuit. Based on the turn-on signal 252, a first frequency is obtained at the oscillator 254. The current of the first-class cold cathode fluorescent lamp (CCFL) 162 was detected after lighting. Therefore, the light-on signal 252 is asserted, indicating that the cold cathode fluorescent lamp (CCFL) is lit. A second frequency is obtained at the output of the oscillator 254. It should be noted that the light-on signal 252 also determines the output signal 256 of the low frequency pulse width modulation (PWM) circuit 258. During the lighting process, the output signal 256 does not interfere with the waveform supplied to the cold cathode fluorescent lamp (CCFL) 162 and a smooth lighting voltage is obtained. In other words, the output signal 256 does not affect the output control logic 286 until the turn signal 252 is set. Controller 150 also includes lamp current and voltage detection and control functions. The lamp current is detected by the sense resistor 182. The detected value 184 is compared to the reference signal 212 by a comparator (e.g., an error amplifier 230 that controls the on-time of switches 112 and 132). The capacitive voltage divider senses the lamp voltage value by capacitors 163 and 164. The voltage detection signal 186 is compared by a comparator 232 and a reference signal 214. The output signal 234 of the comparator 232 determines the activation of the digital clock timing circuit 236. After a period of time (e.g., one to two seconds) after the clock timing circuit 236 is activated, if the output signal 234 is still not set, the output signal 238 of the clock timing circuit 236 will cause the protection circuit 240 to be set to stop the operation of the switches 112 and 132. . This period is used to provide a little lamp time (e.g., one to two seconds) for the cold cathode fluorescent lamp (CCFL) 162. Oscillator 254 provides two frequencies for the operation of power supply circuit 100, a higher frequency for lighting and a lower frequency for normal operation. Higher frequencies can be 20% to 30% higher than lower frequencies. The lower frequency 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -26- 1270839 rate can be 68 KHz as shown in Figure 4b, or 65.8 KHz as shown in Figure 4e, or lower than these two frequencies Any frequency value. The low frequency pulse width modulation circuit 258 is operative to generate an output signal 256 to modulate the energy delivered to the lamp to effect brightness control. The output signal 256 has a frequency preferably in the range of 150 Hz to 400 Hz. The turn-on identification circuit 250 receives a lamp current detection signal 184 whose output turn-on signal 252 is set to identify the presence of a cold cathode fluorescent lamp (CCFL) load 162 or the completion of lighting. The protection circuit 240 receives a turn-on signal 252 indicating the presence of a cold cathode fluorescent lamp (CCFL) 162, the output signal 260' indicating the presence of a current in the cold cathode fluorescent lamp (CCFL) 162 and a pause indicating the open state of the lamp. Output signal 238. Therefore, when the cold cathode fluorescent lamp (CCFL·) 162 has an open lamp, an overcurrent, an overvoltage condition, or an undervoltage occurs at the voltage input pin 130, the output signal 262 of the protection circuit 240 is set to stop the switch 112. And 132 work. The controller 150 includes a ground pin 272 that is electrically connected to the circuit (circuit gr〇un(j), and a voltage input pin _130 that is connected to the DC voltage source. In the controller 150, the voltage input is connected. The pin 130 is coupled to a reference/bias (Ref/Bias) circuit 210 which produces different reference signals 212, 214, etc. for internal use. The voltage input pin 130 is also coupled to an undervoltage lockout circuit (under-voltage). The lock-out circuit 220 and the output driver 222. When the voltage supplied to the voltage input pin 130 exceeds a threshold, the output signal 224 of the undervoltage lockout circuit 220 enables the rest operation of the controller 150. On the other hand, if the voltage at the voltage input pin 130 is less than the threshold, the output signal 224 will stop the rest of the controller 150. When the cold cathode fluorescent lamp (CCFL) is working, the cold cathode fluorescent lamp (ccFL) is bright. 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -27- -1270839 degree control function and function of lamp open circuit It is complementary. Advantageously, the two signals 168 and 186 can be multiplexed such that signals 168 and 186 are simultaneously received at an input pin 284 of the controller 15A. This implementation reduces the cost of the controller 150. The clock pin 276 of the controller 150 is coupled to an oscillator 254 that connects a valley 278 to the ground of the circuit, or a resistor 280 to the voltage input pin 130 to provide a clock signal at the clock pin 276. (preferably a ramp signal). Advantageously, in the present invention, the power supply circuit 1 实现 utilizes the least number of connections to the controller 15 to achieve the most functions to drive the cold cathode fluorescent lamp (CCFL) load. The operation of this power supply is as follows. A direct current (DC) voltage VIN is applied to the power supply circuit 1〇〇. Once the voltage input at voltage input pin 130 exceeds the critical value set by undervoltage lockout circuit 22, controller 150 begins operation. The reference/bias circuit 21A generates a reference voltage for the other circuits in the controller 150. Since the cold cathode fluorescent lamp (CCFL) 162 is not lit and there is no current feedback signal 184 from the cold cathode fluorescent lamp (CCFL) load 162, the oscillator 254 produces a higher frequency pulse signal. Output driver 222 outputs pulse width modulation drive signals 152 and 138 to switches 112 and 132, respectively. Capacitor 216 is gradually charged such that the voltage of output signal 260 gradually increases over time. Since the voltage at the output signal 260 gradually increases with time, the pulse widths of the drive signals 138 and 152 gradually increase. Therefore, the power transmitted to the step-up transformer 120 and the load 162 is also gradually increased. Capacitors 124 and 126 are designed such that the voltage across each capacitor is approximately one-half of the input voltage. In the first half cycle, open 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc • 28- , 1270839 ‘Off 132 is turned on, a current flows from the power supply, through switch 132 to primary winding 118. This current then flows into capacitor 12 6 and contains the magnetizing current and the reflected load current. When capacitor 126 is charged, capacitor 124 is discharged. When switch 132 is open, the current of primary winding 118 continues to flow in the same direction. The intrinsic diode 134 allows the current to continue to circulate. After the switch 132 is turned on, the switch 112 is turned on at about 180 degrees. The power supply provides current through capacitor 124 to primary winding 118 and in the opposite direction through first switch U2 to reference circuit ground pin 272. This current (including magnetizing current and load reflected current) flows in the opposite direction of _. At the same time, when capacitor 126 is discharged, capacitor 124 is charged. When the first switch 112 is open, the intrinsic diode 136 supports continued flow of current in the primary winding 118. After the first switch Π2 is turned on, the switch 132 is turned on at about 180 degrees. The switch continues to work periodically. Therefore, the voltage of the primary winding 11 8 is substantially a rectangular wave. Figure 9 depicts the waveforms at the different endpoints. Figure 9(a) shows the drive waveform at output pin 152. Figure 9(b) shows the corresponding drive waveform at output pin 138. Note that the switch-on time difference between switches 112 and 132 is 180 degrees. Of course, switch 132 can be replaced with an N-channel device. In this case, the logic of the drive signal 138 is inverted to indicate an on/off (ΟΝ/OFF) drive signal. Figure 9(c) shows the voltage waveform at the second end 125. A small chopped wave superimposed on the DC voltage (half of the input voltage VIN) represents the charging and discharging of the capacitor 126. The input voltage VIN minus the voltage at the second terminal 125 results in a similar waveform that represents the voltage of the valley 124. The voltage also has a small ripple superimposed on one-half of the input voltage. Figure 9(d) shows the voltage at the first switching drain 114 and Figure 9(f) shows the current flowing through the primary winding 丨丨8. Note that when -29- 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -1270839 switch 132 is turned on at tl, the voltage at 114 is close to vin. The current of primary winding 118 flows in a forward direction to charge capacitor 126 while discharging capacitor 124. Therefore, the voltage at capacitor 126 increases (positive slope). At time t2, switch 132 is open. The current at the primary winding 118 continues to flow in the same direction, but tends to decrease. The intrinsic diode 134 continues to circulate this current until the current decreases to zero at t3. During the period from t2 to ^, it is apparent that the voltage at 114 is close to zero. Since the current flows in the same direction, the voltage at capacitor 126 still increases. Immediately after t3, due to the reverse magnetomotive force of the primary winding 118, a small current flows in the opposite direction, the intrinsic diode 丨36 conducts, and the voltage of 114 reaches VIN plus the forward voltage drop of the intrinsic diode 136. At time t4, the first switch 112 is turned on. The voltage drops to near zero and the current in primary winding 118 increases 'but the direction is reversed. When capacitor 124 is charged, capacitor 126 is discharged. Therefore, the voltage of the capacitor 126 is reduced (negative slope). The switch 112 is turned off at time t5, the intrinsic diode 13 6 is turned on, and the current continues to flow. When the current of the primary winding 118 reaches zero, the intrinsic diode ι 36 stops conducting. At the same time, a small current flows in the forward direction. In other words, since the intrinsic diode 134 is turned on, the voltage at II4 is close to zero. The operation continues until the next cycle begins at time t7, where switch 132 is again turned "on". The step-up transformer 120 is driven in two directions, thus maximizing the use of magnetic flux swipe to provide power to the cold cathode fluorescent lamp (CCFL) load. The step-up transformer 120, the output capacitors 163, 164, and all of the intrinsic reactive components associated with the transformer 12's primary side circuit form a slot circuit. The slot circuit selects a higher harmonic component associated with the rectangular wave appearing at the primary winding 118 and produces a shaped, approximately positive - 30 - 10102201.00 UC3 CIP1 tw SPEC (amended) at the cold cathode fluorescent lamp (CCFL) 162. (02 950623).doc 1270839 The waveform of the string. As shown in Figure 9(e). Note that based on the intrinsic components of the secondary winding 160 and the load 162, the waveform 172 may have different phase shifts for the waveforms shown in Figures 9(a)-9(d) and 9(f). The voltage at waveform 172 is divided by capacitors 163 and 164. Therefore, capacitors 163 and 164 serve two purposes. One purpose is for voltage detection 186 and another is for waveform shaping. When the cold cathode fluorescent lamp (CCFL) 162 is connected, the amount of current passing through the cold cathode fluorescent lamp (CCFL) 162 is detected by the sense resistor 182. The detected signal 184 is fed to a current amplifier 230 which is coupled with a compensation capacitor 216 at its output signal 260 _ . Output signal 260 is compared to a signal from oscillator 254 and produces an output to output control logic 286 to determine the on time of switches 112 and 132. One method of adjusting the power delivered to the load is to provide a command signal 168 to the input pin 284 of the controller 150. The signal at input pin 284 is converted to a low frequency pulse signal by low frequency pulse width modulation circuit 258 and passed to output control logic 286, whereby output driver 222 output pins 138 and 152 are modulated by the low frequency pulse signal. Thus, 10 effectively controls the energy delivered to the cold cathode fluorescent lamp (CCFL) 162. During lighting, a cold cathode fluorescent lamp (CCFL) 162 is connected to the power supply circuit 100 as an element of infinite impedance. Also, during this time, the cold cathode fluorescent lamp (CCFL) 162 typically requires a predetermined turn-on voltage. A power supply circuit 100 including capacitors 163 and 丨 64 detects the voltage of the cold cathode fluorescent lamp (CCFL) 162. Thus, the predetermined turn-on voltage is scaled at voltage detection signal i 86 and passed to input pin 284 of controller 150 for voltage regulation. The light-on identification circuit 250 generates an on-light signal 252 indicating that the cold cathode fluorescent lamp (CCFL) 162 is not conducting. The output signal 234 is set to start the digit -31 - 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc , 1270839 • Clock timing circuit 236. Similarly, the light-on signal 252 commands the oscillator 254 to produce a higher frequency suitable for cold cathode fluorescent lamp (CCFL) 162 lighting. During this time, the voltage at the cold cathode fluorescent lamp (CCFL) 162 is adjusted to a predetermined value. Approximately one or two seconds after the output signal 234 is set, the digital clock timing circuit 236 produces an output signal 238. If the cold cathode fluorescent lamp (CCFL) 162 is turned on before the output signal 238 is set, the cold cathode fluorescent lamp (CCFL) 162 continues to operate as described in the previous paragraph. If the cold cathode fluorescent lamp (CCFL) 162 is not lit (damaged, unconnected or loosely connected), the output signal 238 is set to activate the protection circuit Φ 240. The output signal 262 of the protection circuit 240 is used to stop the operation of the output driver 222, so the switches 112 and 132 are turned off. Since the cold cathode fluorescent lamp (CCFL) 162 is not lit during this time and no power is being delivered to the cold cathode fluorescent lamp (CCFL) 162, the power control command signal 168 naturally does not contribute to the operation of the power supply. In other words, when the power supply circuit 100 implements the cold cathode fluorescent lamp (CCFL) 162 lighting function, the brightness control of the power adjusted to the cold cathode fluorescent lamp (CCFL) 162 is stopped. Similarly, in normal operation, switch 170 resets voltage detection signal 186, so this signal does not affect the brightness control of the Cold Cathode Fluorescent Lamp (CCFL). Therefore, the multiplex function reduces the number of pins, thus saving the cost of the controller 150 and the power supply circuit. Oscillator 254 is coupled to the ground of the reference circuit via capacitor 278 or to the input voltage via resistor 280 to generate a pulse signal. When capacitor 278 is coupled to circuit ground, oscillator 254 sources current to capacitor 278 and also sinks current from capacitor 278. When resistor 280 is coupled to the input voltage, oscillator 254 sinks current from voltage input and resistor 280. -32- 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc 1270839 Features that make it possible to distinguish between regulation and delivery to cold cathode fluorescence Lamp (CCFL) 162 power control modes. For the linear mode, in order to distinguish the low frequency pulse width modulation mode as previously described, the power control command signal 168 commands and regulates the power delivered to the cold cathode fluorescent lamp (CCFL) 162 so that the transmission of the power does not have to pass the low frequency pulse width. Modulation circuit 25 8. When the oscillator 25 is coupled to the resistor 280 to the voltage input, the command signal 168 flows through the input pin 284 and then through the low frequency pulse width modulation circuit 258 to generate/rewrite a reference signal 212 to the amplifier 230. The command signal 168 thus directly controls the magnitude of the current feedback signal 184 to regulate the current through the cold cathode fluorescent lamp (CCFL) 162. In this mode of operation, the signal at 282 cuts off the low frequency pulse width modulation circuit 258 and allows the signal feed of the input pin 284 to conduct. Therefore, connecting resistor 280 or capacitor 278 to oscillator 254 not only produces a pulse signal, but also determines the control mode of the cold cathode fluorescent lamp (CCFL) load 162 power regulation (either in linear control mode or at low frequency pulse width modulation). In the variable mode). Such a design reduces the number of components used around the controller 150, but greatly increases the flexibility of the designer. As described above, the first switch U2 and the second switch 132 corresponding to the power supply circuit 100 of the present invention are controlled by the controller 150 and alternately turned on, so that the current alternately flows through the cold cathode fire in the first direction and the second direction. A light (CCFL) 162, and the power circuit 1 converts the DC power to AC power to provide power to the Cold Cathode Fluorescent Lamp (CCFL) 162. Therefore, various modifications and/or alternatives of the inventions will be apparent to those skilled in the <RTIgt; Therefore, the following application 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -33 - 1270839 n The patent scope is intended to be interpreted as encompassing all modifications or alternatives within the spirit and scope of the invention. Other circuits that will be discovered by those skilled in the art, and all modifications may be limited by the spirit and scope of the invention, and only by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a conventional DC/AC converter circuit; FIG. 2 shows a preferred embodiment of the DC/AC converter circuit of the present invention; FIG. 2a-2f shows FIG. A typical timing diagram of a circuit; Figure 3 shows another preferred embodiment of the DC/AC converter circuit of the present invention; Figures 3a-3f show a typical timing diagram of the circuit of Figure 3; Figures 4a-4f show a diagram 2 and a schematic diagram of the circuit shown in FIG. 3; FIG. 5 is a view showing an embodiment of the liquid crystal display system of the present invention; FIG. 6 is a view showing an embodiment of the liquid crystal display system of the present invention; An embodiment of a display system; Fig. 8 shows an embodiment of a display illumination system of a liquid crystal display system of the present invention; and Fig. 9 shows a waveform of an embodiment of the liquid crystal display system of the present invention. [Graphic main component symbol description] A/B/C/D switch C1/C2/C3 capacitor 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -34- 1270839

FB feedback signal N1/N2/N3/N4 feedback winding Q1/Q2 transistor REF reference voltage Rs detection resistance TXl transformer 10 CCFL power system 12 power supply 14 controller 16 drive circuit 18 feedback circuit 20 LCD panel / load 22 sweep Frequency/Frequency Generator/Pulse Generator 24 Output Signal/CMP Signal 26 Ramp Signal 28 Comparator 30 Bias/Reference Signal 32 Error Amplifier 36 Intersection 38 Switch 40 Feedback Control Loop 42 Current Sense Comparator 50 Drive Circuit 60 Protection circuit 62 protection comparator 64 timer 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -35- 1270839 66 OVP signal 70 phase-locked loop (PLL) 72 flip-flop circuit 80 switch 90 pulse signal 92 complementary pulse Signal 94 Signal 98 Signal 100 Power Circuit 112 Switch 114 Datum 118 Primary Winding 120 Transformer 124 Capacitor 125 Second End 126 Second Capacitor 128 Source 130 Voltage Input Pin 132 Switch 134/136 Intrinsic Diode 138/152 Output Foot / Gate / 150 Controller 160 Secondary winding 162 Cold Cathode Fluorescent Lamp (( 163/164 Capacitor 16 8 signal 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -36 1270839

170 Switch 172 Waveform 182 Sense Resistor 184 Detected Value / Lamp Current Detect Signal / Current Feedback Signal 186 Voltage Detect / Voltage Detect Signal 210 Reference / Bias Circuit 212 / 214 Reference Signal 216 Capacitor 220 Undervoltage Lockout Circuit 222 Output Driver 224/234/238 Output signal 230 Amplifier 232 Comparator 236 Clock timing circuit 240 Protection circuit 250 Light-on identification circuit 252 Light-on signal 254 Oscillator 256 Output signal 258 Low-frequency pulse width modulation circuit 260 Output signal 262 Output signal 272 Ground Pin 274 Power Supply 276 Clock Pin 94102201-0011C3CIP1 tw SPEC (amended) (02 950629).doc -37- 1270839

278 Capacitor 280 Resistor 284 Input Pin 286 Output Control Logic 500/600/700 LCD Display System 501/601 Thin Film Transistor 502/602 Line Driver 503/603 Column Driver 504/604 Timing Controller 505/605 Video Signal Processor 512/612 Switch 518/618 Primary Transformer Winding 532/632 Switch 550/650 Controller 560/660 Secondary Transformer Winding 562/662 Cold Cathode Fluorescent Lamp (CCFL) 599/699 Display Lighting System 605 Video Signal Processing 606 Video Demodulator 607 Tuner 608 Microcontroller 609 Audio Amplifier 611 Audio Signal Processor 610 611 Audio Demodulator 790 Graphics Adaptor 791 Chipset Core Logic 94102201-0011C3CIP1 tw SPEC (amended) (02 950623 ).doc -38- 1270839 792 Microprocessor 793 Memory 794 Hard Disk Drive 795 Optical Disk Player 94102201-0011C3CIP1 tw SPEC (amended) (02 950623).doc -39-

Claims (1)

.1270839 X. Patent application scope: 1 · A liquid crystal display system comprising: a liquid crystal display panel; a cold cathode fluorescent lamp for illuminating the liquid crystal display panel; a secondary transformer winding coupled to the cold cathode fluorescent light a light lamp for supplying current to the cold cathode fluorescent lamp; a primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding; _ a first switch 'faced to the primary transformer winding Allowing a current to flow through the primary transformer winding; and a feedback control loop coupled to the cold cathode fluorescent lamp, the feedback control loop receiving a feedback signal indicative of the power delivered to the cold cathode fluorescent lamp, The power supplied to the cold cathode fluorescent lamp is controlled if and only if the feedback signal is above a predetermined threshold. 2 • The liquid crystal display system of claim 1, further comprising: an input voltage source coupled to the switch to provide current to the switch. The liquid crystal display system of claim 2, wherein the input voltage source is a power supply device. The liquid crystal display system of claim 2, further comprising: a first capacitor consuming the primary transformer winding and the ground potential; and a second capacitor coupled to the primary transformer winding and the input voltage source . The liquid crystal display system of claim 1, wherein the feedback control loop maintains the cold cathode fluorescent lamp at a predetermined minimum power if the feedback signal No. 1270839 is not higher than a predetermined threshold. 6. The liquid crystal display system of claim 5, further comprising: a second switch coupled to the primary transformer winding to allow current to flow in the reverse direction through the primary transformer winding; and a second switch And coupled to the primary transformer winding and the first switch to provide current to the primary transformer winding when there is an overlap between the third switch and the first switch. 7. The liquid crystal display system of claim 6, wherein the feedback control loop maintains the cold cathode fluorescent lamp at the predetermined minimum by maintaining a minimum overlap between the third switch and the first switch power. 8. The liquid crystal display system of claim 1, further comprising: a voltage detector coupled to the cold cathode fluorescent lamp to detect the voltage of the cold cathode fluorescent lamp. 9. The liquid crystal display system of claim 8, further comprising: a voltage protection circuit coupled to the voltage detector, when the voltage of the cold cathode fluorescent lamp exceeds a predetermined threshold The power delivered to the cold cathode fluorescent lamp is reduced. 10. The liquid crystal display system of claim 9, further comprising: a timing device coupled to the voltage protection circuit to provide a pause period. A liquid crystal display system comprising: a liquid crystal display panel; a cold cathode fluorescent lamp that illuminates the liquid crystal display panel; .1270839 a secondary transformer winding coupled to the cold cathode fluorescent lamp, the cold cathode fluorescent lamp a light lamp provides current; a primary transformer winding 'slightly coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding; a first switch coupled to the primary transformer winding to allow current to flow through the primary transformer Winding; and Lightly coupled to a feedback control loop of the cold cathode fluorescent lamp, the feedback control loop receiving a feedback signal from the cold cathode fluorescent lamp, when the feedback signal indicates an open lamp state , reducing the power supplied to the cold cathode fluorescent lamp. 12. The liquid crystal display system of claim U, wherein the feedback signal indicates a voltage of the cold cathode fluorescent lamp, and when the voltage exceeds a predetermined threshold, indicates that the lamp is in an open state. 13. The liquid crystal display system of claim 12, wherein the feedback control loop maintains the cold cathode illuminating lamp at a predetermined minimum power when the voltage exceeds a predetermined threshold. 14. The liquid crystal display system of claim 13, further comprising: a second switch coupled to the primary transformer winding to allow flow to flow in the reverse direction through the primary transformer winding; and a third opening 'It is lightly coupled to the primary transformer winding and the first switch 'when there is an overlap between the third switch and the first switch' to supply current to the primary transformer winding. 15. The liquid crystal display system of claim 14, wherein the feedback loop maintains the cold cathode fluorescent lamp by maintaining a maximum of 1270839 overlap between the third switch and the first switch Minimum power. 16. The liquid crystal display system of claim U, wherein the feedback signal indicates a voltage of the cold cathode fluorescent lamp, and when the voltage exceeds a predetermined threshold for a predetermined period of time, indicating that the lamp is in an open state. 17. The liquid crystal display system of claim 5, further comprising: a first capacitor coupled to the primary transformer winding and a ground potential; and a second capacitor coupled to the primary transformer winding and a voltage input . 18. The liquid crystal display system of claim n, further comprising: an input voltage source coupled to the switch to provide current to the switch. The liquid crystal display system of claim 2, wherein the input voltage source is a power supply device. 20. The liquid crystal display system of claim 3, wherein the feedback signal represents a current flowing through the cold cathode fluorescent lamp, and when the current is below a predetermined threshold, indicating the light-on state. A liquid crystal display system comprising: a liquid crystal display panel; a cold cathode fluorescent lamp that illuminates the liquid crystal display panel; a secondary transformer winding coupled to the cold cathode fluorescent lamp, the cold cathode fluorescent lamp Providing a current; a primary transformer winding coupled to the secondary transformer winding to provide magnetic flux to the secondary transformer winding; a first switch coupled to the primary transformer winding, allowing current -1270839 to flow in a first direction a primary transformer winding; a second switch coupled to the primary transformer winding to allow current to flow through the primary transformer winding in a second direction; a second switch coupled to the primary transformer winding and the first switch, Providing a current to the primary transformer winding when there is an overlapping state between the third switch and the first switch; and a feedback control loop coupled to the cold cathode fluorescent lamp, the feedback control loop Receiving a feedback signal from the cold cathode fluorescent lamp, and by maintaining a minimum weight between the second switch and the first switch Stacked to maintain a predetermined minimum power of the cold cathode fluorescent lamp. 22. The liquid crystal display system of claim 21, further comprising: an input voltage source coupled to the first switch and the second switch to provide current to the first switch and the second switch. 23. The liquid crystal display system of claim 22, wherein the input voltage source is a power supply device. Φ 24· A method for controlling the power of a cold cathode fluorescent lamp of a liquid crystal display system, the method comprising the steps of: providing a pulse signal to a transistor as a first conduction path of a primary transformer winding; generating a coupling from a feedback signal to the cold cathode fluorescent lamp of the primary transformer winding, the signal indicating an electrical state of the cold cathode fluorescent lamp; receiving the feedback signal from the cold cathode fluorescent lamp; and only when The feedback signal indicates that the power supplied to the cold cathode fluorescent lamp is adjusted by the 1270839 when the cold cathode fluorescent lamp is turned on. 25. 26. The method of claim 24, wherein the feedback signal indicates a voltage across the cold cathode fluorescent lamp, and when the voltage is below a predetermined threshold, indicating the cold The lighting of the cathode fluorescent lamp. The method of claim 24, wherein the feedback signal indicates a current through the cold cathode fluorescent lamp, and when the current is above a predetermined threshold, indicates that the cold cathode fluorescent lamp is lit. The method of claim 24, wherein the method further comprises the step of: maintaining a predetermined minimum value of the power to the cold cathode fluorescent lamp when the feedback signal indicates non-lighting. The method of claim 27, further comprising the steps of: providing a second pulse signal to a second transistor as a second conduction path of the primary transformer winding; providing a third pulse signal to the first a tri-electrode as the first conduction path of the primary transformer winding; maintaining a minimum amount of overlap between the first transistor and the third transistor. The method of claim 24, further comprising the step of: cutting off the power to the cold cathode fluorescent lamp when the feedback signal indicates non-lighting for a predetermined time interval. 29.