1268070 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種頻率補償系統，詳言之，係關於一種 用於最小鍵移調變訊號之頻率補償系統。 【先前技術】 無線通訊系統中’因為有頻率偏移效應會降低系統效 能，故需要一頻率補償系統來補償頻率偏移。習知之頻率1268070 IX. Description of the Invention: [Technical Field] The present invention relates to a frequency compensation system, and more particularly to a frequency compensation system for a minimum key shift modulation signal. [Prior Art] In a wireless communication system, since a frequency offset effect reduces system efficiency, a frequency compensation system is required to compensate for frequency offset. Frequency of knowledge
補 <員方法，第一類是在高頻部份使用鎖相迴路來實現，第 二類在基頻利用訊號處理的方式來實現（如中華民國專，The method of supplementing the staff is implemented in the high frequency part using a phase-locked loop, and the second type is implemented in the fundamental frequency by means of signal processing (such as the Republic of China,
公告第252249號及第263644號），這類方式是將基頻訊號和J 延遲的訊號取共軛做相乘，然後取其結果的相位部分做運 算以計算得頻率偏移量，為了增加準確度一般會將多次、 運算結果取平均。 人、 利用以下之公式來說明習知利用數位訊號處理方 頻率補償的方式，假設接收基頻訊號為…），則估測的方式 為 Λ是估測出來的頻率偏移量，乃是延遲取樣點，『是位元 時間，一般Z)會選擇和Rxos一樣大，R 疋70 、 Rxos4 一個位元時間 被過取樣的次數。由於在開始估測的 了抶 並不能知道這 個初始點是不是數位訊號的取樣峰值，所以同樣的估、則方 式’必須要做Rx〇S次’取樣率越高估測次數也會越多:欠。 習知基頻訊號處理的方式運算詈鲂 热、, 季大’因為數位訊號需 要過取樣，在不知道位元波形峰值的 1月❿下，要重複運算， 102806.doc 1268070 ㈣重複的次數與過取樣的值㈣，然後由這幾個估測值 選出較為合適的估測值來補償，這樣的方式會耗費較多運 算時間與硬體成本。 、 另外，習知的方法重複估麻細次，㈣斷估測出來汉則 次^>·((,,)的絕對值大小，纟決定哪—次的估測最接 ' 近是最高取樣點，由此可知估測一次便要利用很大的運算 成本’而且必須估測多次。如此習知之架構，必須要很大 • $記，體來暫存這些尚未利用的資料，或是重複利用記憶 體計算，以及耗費等待運算的時間。 因此，有必要提供一種創新且具進步性的頻率補償系 統，以解決上述問題。 【發明内容】 本發明之目的在於提供—種用於最小鍵移調變訊號之頻 率補償系統，《包括：一類比至數位轉換器、一時間延遲 器、一相位偵測器及一頻率偏移計算裝置。該類比至數位 ·#換器用以將一類比接收訊號’轉換為一數位接收訊號。 〜 该時間延遲器用以將數位接收訊號延遲一設定時間，為一 延遲數位接收訊號。該相位偵測器用以計算該數位接收訊 號與該延遲數位接收訊號間之一相位差值。該頻率偏移計 异裝置用以依據該相位差值，計算一頻率偏移值。 因此，利用本發明用於最小鍵移調變訊號之頻率補償系 統，可以計算得該頻率偏移值。並且，本發明用於最小鍵 移調變訊號之頻率補償系統不需要知道位元波形最高的取 樣點，而是利用最小鍵移調變的連續相位特性。同時，本 102806.doc 1268070 舍月用於最小鐽移調變tfl號之頻率補償李轉 訊妒的flM 貝手Ή貝糸統所比較的基頻 儿、s不疋傳統上的一個位元時間差，而是一個笔 pi ΘΒ ^ ,,, 皮個取樣 …。本發明用於最小鍵移調變㈣之 可以大幅地降低訊號暫存之量，在整體架構上較為： 並可節省硬體成本。 【實施方式】Bulletin Nos. 252249 and 263644), in which the fundamental frequency signal and the J-delayed signal are multiplied by a conjugate, and then the phase portion of the result is calculated to calculate the frequency offset, in order to increase the accuracy. The degree will generally be averaged multiple times and the results of the operation. The following formula is used to illustrate the conventional method of using the digital signal processing side frequency compensation. If the receiving fundamental frequency signal is ...), the estimation method is Λ is the estimated frequency offset, which is the delayed sampling. Point, "is the bit time, generally Z) will choose the same as Rxos, R 疋70, Rxos4 the number of times a bit time has been oversampled. Since it is not known at the beginning of the estimation that this initial point is the sampling peak of the digital signal, the same estimation, the method 'must do Rx〇S times', the higher the sampling rate, the more the number of estimations will be: owe. The method of calculating the fundamental frequency signal processing is hot, and the season is large. Because the digital signal needs to be oversampled, the operation is repeated without knowing the peak value of the bit waveform. 102806.doc 1268070 (4) Repeat times and oversampling The value (4) is then compensated by selecting the more appropriate estimates from these estimates. This method will consume more computing time and hardware costs. In addition, the conventional method repeats the estimation of the number of times, (4) the estimated value of the Han Dynasty is less than the absolute value of ((,,), which determines which one is the most accurate. Point, it can be known that the estimation will take a lot of computational cost once and must be estimated multiple times. Such a well-known architecture must be very large. $Note, to temporarily store these unused data, or to repeat The use of memory calculations and the time spent waiting for calculations. Therefore, it is necessary to provide an innovative and progressive frequency compensation system to solve the above problems. SUMMARY OF THE INVENTION The object of the present invention is to provide a minimum key shift Frequency compensation system for variable signals, including: a analog-to-digital converter, a time delay, a phase detector, and a frequency offset computing device. The analog-to-digital converter is used to receive an analog signal. Converted to a digital receive signal. ~ The time delay is used to delay the digital receive signal by a set time and receive a signal for a delay. The phase detector is used to calculate the digital receive. And a phase difference value between the number and the delayed digital receiving signal. The frequency offset counting device is configured to calculate a frequency offset value according to the phase difference value. Therefore, the frequency of the minimum key shifting signal is used by the present invention. The compensation system can calculate the frequency offset value. Moreover, the frequency compensation system for the minimum key shift modulation signal of the present invention does not need to know the sampling point with the highest bit waveform, but uses the minimum key shift to change the continuous phase characteristic. At the same time, this 102806.doc 1268070 is used for the minimum frequency shifting tfl number of the frequency compensation Li transfer 妒 flM 贝 Ή 所 所 所 所 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较 比较Instead, a pen pi ΘΒ ^ , , , a sample of the skin .... The invention for the minimum key shift modulation (4) can greatly reduce the amount of signal temporary storage, in the overall architecture: and can save hardware costs. the way】
々參考圖1，係顯示本發明用於最小鍵移調變訊號之頻率補 償系=之方塊示意圖。本發明用於最小鍵移調變訊號之頻 率補償系統10包括：一類比至數位轉換器〗丨、—時間延遲 器12、一相位偵測器13及一頻率偏移計算裝置14。該類比 至數位轉換器11用以將一類比接收訊號，轉換為一數位接 收訊號。該類比接收訊號係為複數基頻訊號。該類比至數 位轉換器11將該複數基頻訊號，轉換成數位接收訊號（A)， 並里化成固定的值。 該時間延遲器12用以將數位接收訊號（A)延遲一設定時 間’為一延遲數位接收訊號（B)。該設定時間為一取樣時 間。因此，延遲數位接收訊號（B)則為該數位接收訊號（A) 前一個取樣時間的值。 參考圖2，係顯示本發明之相位偵測器I3之方塊示意圖。 該相位偵測器13用以計算該數位接收訊號（A)與該延遲數 位接收訊號（B)間之一相位差值（D)。該相位偵測器丨3包 括··一第一相位計算器131、一第二相位計算器132、一算 術運算器133及一相位差值判斷器134。該第一相位計算器 131用以計算該數位接收訊號（A)之相位P(A)。該第二相位 102806.doc 1268070 計算器132用以計算該延遲數位接收訊號（B)之相位p(B)。 該异術運算器133用以依據該數位接收訊號之相位p(A) 與該延遲數位接收訊號（B)之相位P(B)，計算得一原始相位 差值（C)。該算術運算器133可為一加法器。 該相位差值判斷器134用以依據該原始相位差值，計 算得該相位差值（D)。由於在計算相位圖示中，使用到正切 反函數（tan·1)，正切反函數會在角度變化時有相位含糊 (phase ambiguity)，亦即是會出現不同的角度有相同的正切 反函數值。因此，利用相位差值判斷器134修正其相位含糊 現象。 參考圖3，係顯示本發明之該相位差值判斷器134之流程 及方塊示意圖。該相位差值判斷器134包括：一第一比較器 135、一第二比較器136、一第一運算器137、一第二運算器 13 8及一第三運算器139。該第一比較器135用以比較該原始 相位差值（C)之絕對值（亦即為| c | )是否小於一第一數 值，其中該第一數值為7Γ。當該原始相位差值之絕對值小 於該第一數值時，該第一運算器137計算該相位差值等於該 原始相位差值（D=C)。 該第二比較器136用以比較該原始相位差值（c)是否小於 一第二數值，該第二數值為0。當該原始相位差值小於該第 -數值時’弟一運鼻裔138用以计鼻該相位差值等於該原始 相位差值加上一第三數值（D=C + 27Γ)，該第三數值為27Γ。 當該原始相位差值大於該第二數值時，該第三運算器139 用以計算該相位差值等於該原始相位差值減該第三數值 102806.doc -9- 1268070 (D=C — 2 7Γ ) 〇 在最小鍵移調變中一個位元時間變化中的相位值會變化 〇·5π，在此設定一個位元時間被過取樣的次數為Rx〇s，所 以一個取樣時間中相位的變化會是O 5;c/Rx〇s。如上述，已 — 經計算出一個取樣時間差中的相位差值（D)，然而，已知在 • 最小鍵移調變中相位變化在一個取樣時間的大小不是 0.5tc/Rx〇s就是負的〇.5tc/Rxos，所以該頻率偏移計算裝置 _ 是利用已知的相位差值（O.k/Rx〇s或負〇.5tc/RxOS)和計算出 的相位差值（D)來計算。 參考圖4 ’係顯示本發明之該頻率偏移計算裝置14之流程 及方塊示意圖。該頻率偏移計算裝置14用以依據該相位差 值（D) ’計算一頻率偏移值⑺。該頻率偏移計算裝置μ包 括：一第三比較器141、一第四運算器142及一第五運算器 143。該第三比較器141用以比較該相位差值（d)是否小於二 第四數值，其中該第四數值為Ge #該相位差值小於該第四 • 錢亦即該相位差值⑼為負，代表相位在減少，該第 四運算器142用以計算該頻率偏移值⑴等於該相位差值加 上一第五數值（f=D+0.57t/Rx〇s)。該第五數值為一取樣時間 之相位變化值’亦即為上述之〇.減細。當該相位差值大 於該第四數值時，亦即該相位差值（D)為正時，該第五運算 器143用以計算該頻率偏移值（f)等於該相位差值減該第五 數值（f=D+0.57t/Rx〇s)。 因此矛J用本毛明用於最小鍵移調變訊號之頻率補償系 Λ 1 〇可以计异侍该頻率偏移值。並且，本發明用於最小 102806.doc 1268070 鍵移調變訊號之頻率補償系統10不需要知道位元波形最高 的取樣點，而是利用最小鍵移調變的連續相位特性。同時， 本發明用於最小鍵移調變訊號之頻率補償系統10所比較的 基頻訊號的間距不是傳統上的一個位元時間差，而是一個 ， 取樣時間差。故本發明用於最小鍵移調變訊號之頻率補償 ‘ 系統10可以大大的降低訊號暫存的量，在整體架構上較為 簡易’並可節省硬體成本。 馨 准上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不違背本發 月之精神對上述貫施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1係顯示本發明用於最小鍵移調變訊號之頻率補償系 統之方塊示意圖； 圖2係顯示本發明之相位偵測器之方塊示意圖； _ 圖3係顯示本發明之該相位差值判斷器之流程及方塊示 意圖；及 _圖4係顯示本發明之該頻率偏移計算裝置之流程及方塊 示意圖。 【主要元件符號說明】 10 本發明之頻率補償系統 11 類比至數位轉換器 12 時間延遲器 13 相位偵測器 102806.doc 1268070 131 第一相位計算器 132 第二相位計算器 133 算術運算器 134 相位差值判斷器 135 第一比較器 136 第二比較器 137 第一運算器 138 第二運算器 139 第三運算器 14 頻率偏移計算裝置 141 第三比較器 142 第四運算器 143 第五運算器 102806.doc -12-Referring to Fig. 1, there is shown a block diagram of the frequency compensation system for the minimum key shift modulation signal of the present invention. The frequency compensation system 10 for the minimum key shifting signal of the present invention comprises: an analog to digital converter, a time delay 12, a phase detector 13 and a frequency offset calculating means 14. The analog to digital converter 11 is used to convert an analog reception signal into a digital reception signal. The analog signal is a complex fundamental frequency signal. The analog-to-digital converter 11 converts the complex fundamental frequency signal into a digital received signal (A) and converts it into a fixed value. The time delay unit 12 is configured to delay the digital received signal (A) by a set time ‘ as a delayed digital received signal (B). This set time is a sampling time. Therefore, the delayed digital reception signal (B) is the value of the previous sampling time of the digital reception signal (A). Referring to Figure 2, there is shown a block diagram of a phase detector I3 of the present invention. The phase detector 13 is configured to calculate a phase difference (D) between the digital received signal (A) and the delayed digital received signal (B). The phase detector 丨3 includes a first phase calculator 131, a second phase calculator 132, an arithmetic operator 133, and a phase difference determiner 134. The first phase calculator 131 is configured to calculate the phase P(A) of the digital received signal (A). The second phase 102806.doc 1268070 calculator 132 is used to calculate the phase p(B) of the delayed digital received signal (B). The operative operator 133 is configured to calculate a raw phase difference (C) according to the phase p(A) of the digital received signal and the phase P(B) of the delayed digital received signal (B). The arithmetic operator 133 can be an adder. The phase difference value determiner 134 is configured to calculate the phase difference value (D) based on the original phase difference value. Since the tangent inverse function (tan·1) is used in the calculation of the phase diagram, the tangent inverse function has phase ambiguity when the angle changes, that is, different angles have the same tangent inverse function value. . Therefore, the phase difference determinator 134 is used to correct the phase ambiguity. Referring to Fig. 3, there is shown a flow chart and block diagram of the phase difference value determiner 134 of the present invention. The phase difference determiner 134 includes a first comparator 135, a second comparator 136, a first operator 137, a second operator 138, and a third operator 139. The first comparator 135 is configured to compare whether the absolute value (ie, |c|) of the original phase difference value (C) is less than a first value, wherein the first value is 7Γ. When the absolute value of the original phase difference value is less than the first value, the first operator 137 calculates that the phase difference value is equal to the original phase difference value (D = C). The second comparator 136 is configured to compare whether the original phase difference value (c) is smaller than a second value, and the second value is zero. When the original phase difference value is smaller than the first value, the second phase value is equal to the original phase difference plus a third value (D=C + 27Γ), the third The value is 27Γ. When the original phase difference value is greater than the second value, the third operator 139 is configured to calculate the phase difference value equal to the original phase difference value minus the third value 102806.doc -9-1268070 (D=C-2 7Γ) 相位 The phase value in one bit time change in the minimum key shift modulation changes 〇·5π, where the number of oversampling times is set to Rx〇s, so the phase change in one sampling time will Is O 5; c/Rx〇s. As described above, the phase difference (D) in a sampling time difference has been calculated, however, it is known that the phase change in the minimum key shift modulation is not 0.5tc/Rx〇s or negative in a sampling time. .5tc/Rxos, so the frequency offset calculation means _ is calculated using the known phase difference value (Ok/Rx〇s or negative 〇.5tc/RxOS) and the calculated phase difference value (D). Referring to Fig. 4', there is shown a flow chart and block diagram of the frequency offset calculating means 14 of the present invention. The frequency offset calculating means 14 is operative to calculate a frequency offset value (7) based on the phase difference value (D)'. The frequency offset calculating means μ includes a third comparator 141, a fourth operator 142 and a fifth operator 143. The third comparator 141 is configured to compare whether the phase difference value (d) is smaller than two fourth values, wherein the fourth value is Ge #, and the phase difference value is smaller than the fourth money, that is, the phase difference value (9) is negative. , the representative phase is decreasing, and the fourth operator 142 is configured to calculate the frequency offset value (1) equal to the phase difference value plus a fifth value (f=D+0.57t/Rx〇s). The fifth value is a phase change value of a sampling time, which is the above-mentioned 〇. When the phase difference value is greater than the fourth value, that is, when the phase difference value (D) is positive, the fifth operator 143 is configured to calculate the frequency offset value (f) equal to the phase difference value minus the first Five values (f = D + 0.57t / Rx 〇 s). Therefore, the spear J uses the local frequency compensation system for the minimum key shift modulation signal Λ 1 〇 can calculate the frequency offset value. Moreover, the frequency compensation system 10 of the present invention for the minimum 102806.doc 1268070 key shifting signal does not need to know the sampling point with the highest bit waveform, but uses the minimum key shifting continuous phase characteristic. At the same time, the spacing of the fundamental frequency signals compared by the frequency compensation system 10 for the minimum key shifting signal of the present invention is not a conventional one-bit time difference, but a sampling time difference. Therefore, the present invention is used for frequency compensation of the minimum key shift modulation signal. ‘System 10 can greatly reduce the amount of signal temporary storage, and is simple in overall architecture' and can save hardware cost. The above examples are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of this month. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a frequency compensation system for a minimum key shifting signal according to the present invention; FIG. 2 is a block diagram showing a phase detector of the present invention; FIG. 3 is a block diagram showing the present invention. The flow and block diagram of the phase difference value determiner; and FIG. 4 is a flow chart and block diagram showing the frequency offset calculation device of the present invention. [Main component symbol description] 10 Frequency compensation system of the present invention 11 Analog to digital converter 12 Time delay 13 Phase detector 102806.doc 1268070 131 First phase calculator 132 Second phase calculator 133 Arithmetic operator 134 Phase Difference determiner 135 First comparator 136 Second comparator 137 First operator 138 Second operator 139 Third operator 14 Frequency offset calculation means 141 Third comparator 142 Fourth operator 143 Fifth operator 102806.doc -12-