TWI267987B - Method for forming thin film transistor in an LCD device - Google Patents

Abstract

In a method for forming TFT in an LCD device, a buffer layer and a polysilicon layer are sequentially formed on a transparent substrate first. Then, a gate dielectric layer is formed on surface of the polysilicon layer by using plasma treatment, wherein the plasma contains oxygen, nitrogen, or both, and the treatment temperature is between about 300 to 600 DEG C. Next, a gate electrode layer is formed on the gate dielectric layer, and a source and a drain regions are formed on the opposite direction of the gate electrode layer.

Description

1267987 - V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) [Technical Field of the Invention] The present invention relates to a method for forming a cry in the right, 曰 in / night crystal display, and particularly relates to a pen γ thousand. . Fangshan life of the yf-bound scented crystal is called k. In Tao & crystal liquid crystal display, the method of the smashing voltage barrier gate insulation is formed in the high-previous [current technology] in the liquid crystal display Drive, one ~, ,.day >: The day has a fast response feature that makes the display. And better. Z, the structure of the bonded transistor has a bottom gate and a top dipole. In the first figure, a schematic diagram of the formation of the top gate is shown in the step: In the first A picture, a buffer layer i 〇 2 and an amorphous austenite layer 104 are deposited on a glass substrate i ,, wherein the material of the buffer layer i 〇 2 is selectively oxidized. Shi Xi or i fossil eve. Then, as shown in Figure B, Execmer Laser Annealing (ELA), or Continuous Grain Silicon (CGS), Sequential Lateral Solidification ; SLS), Metal Induced Crystallization (MIC), the formation of amorphous germanium layer 104 by means of Mean 1: a 1 I nduced L atera 1 Crystallization; MILC The polycrystalline layer is 1 0 6 . Thereafter, in the first C picture, a gate oxide layer 108 is deposited on the polysilicon layer 106 using a plasma gain chemical vapor deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method. The way of deposition is to use Shi Xijia

Page 6 1267987___ V. INSTRUCTIONS (2) The alkane reacts with Ν 2 0 or Ο 2 to form cerium oxide or is decomposed into cerium oxide using tetraethyl hydrazine (TEOS). Next, as shown in Fig. D, a gate metal layer 110 is formed on the gate oxide layer 108. The manner of formation involves depositing a metal layer on the gate oxide layer and then transferring the pattern of the gate to the metal layer using optical lithography and a residual pattern. In the first diagram, a lightly doped bungee region 1 1 2 is formed in the polysilicon layer 1 〇6 by means of an ion implanter or an ion shower. Layer] 1 0 on both sides. Thereafter, as shown in the first F diagram, a spacer 1 1 4 is formed on the sidewall of the gate layer 110. Then, in the first G picture, the source and drain regions 1 1 6 are formed on both sides of the gate metal layer by ion implantation of the germanium layer 10.6. Because of the traditional use of chemical vapor deposition, whether it is plasma gain chemical vapor deposition or low pressure chemical vapor deposition, the deposited ga te oxide layer, its breakdown voltage is usually compared, small Moreover, the interface defects of the polycrystalline stone and the oxide layer will be more, and leakage current is likely to occur. Such gate oxide quality cannot meet the needs of future component shrinkage and integration. Therefore, in order to increase the quality of the gate oxide layer, it is necessary to solve the problem of low breakdown voltage and leakage current; that is, increase the breakdown voltage and reduce the interface defects between the gate oxide layer and the germanium oxide layer. SUMMARY OF THE INVENTION A gate formed by a chemical vapor deposition method in view of the above-described background of the invention

Page 7 1267987 V. DESCRIPTION OF THE INVENTION (3) A number of problems and disadvantages of the electrode layer are provided. The main object of the present invention is to provide a gate insulating layer by means of plasma processing. It is mainly formed by using the already formed intrinsic crystal enthalpy (intrinsic ρ ο 1 ysi 1 ic ο η) and a plasma containing oxygen or nitrogen to form cerium oxide and cerium nitride at a temperature of 300 to 600 ° C. Or a dielectric material such as ruthenium oxynitride as a gate insulating layer. Another object of the present invention is to provide a high breakdown voltage for the gate insulating layer formed by plasma treatment. A further object of the invention is that the gate insulating layer formed by the plasma treatment has lower interface defects and thus has a lower leakage current. A further object of the present invention is to use different reactive gases to select the material of the gate insulating layer that needs to be grown during the plasma processing. In accordance with the above objects, the present invention provides a method of forming a thin film transistor in a liquid crystal display, the method comprising the steps of sequentially forming a buffer layer and a polysilicon layer on a transparent substrate. Thereafter, the surface of the polysilicon layer is plasma-treated to treat the polysilicon layer to form a gate insulating layer. Then, a gate layer is formed on the gate insulating layer. Next, a source and a gate region are formed on both sides of the gate layer in the above-mentioned polysilicon layer. The invention also provides a high collapse in a thin film transistor liquid crystal display

Page 8 1267987 V. DESCRIPTION OF THE INVENTION (4) A method of breaking a voltage gate insulating layer, the method comprising forming a polysilicon layer on a transparent substrate. Thereafter, the above-mentioned polysilicon layer is plasma-treated between 300 and 60 (TC) to form a gate insulating layer, wherein the reaction gas forming the plasma may contain oxygen or nitrogen, and the gate is insulated. The layer may be tantalum oxide, tantalum nitride, or hafnium oxynitride. [Embodiment] Some embodiments of the present invention will be described in detail below. However, the present invention may be broadly applied to other embodiments except for the detailed description. The scope of the present invention is not limited by the scope of the following claims. Further, in order to provide a clearer description and a better understanding of the present invention, the various parts of the drawings are not drawn according to their relative sizes. Some dimensions have been exaggerated compared to other related scales; the unrelated details have not been fully drawn, and the succinct illustrations are simple. The present invention utilizes the essence of the polycrystalline stone and the electricity containing gases such as oxygen or nitrogen. The poly' reacts at a temperature of 300 to 600 ° C, and then forms a gate insulating layer. If the anti-gas is mainly oxygen, the gate insulating layer is cerium oxide. If the reaction gas is mainly nitrogen The gate insulating layer is tantalum nitride. If the reaction gas contains oxygen and nitrogen, the gate insulating layer may be nitrogen oxynitride. Because the gate insulating layer formed by the intrinsic polysilicon is processed after high temperature treatment It becomes denser, so you can get a higher breakdown voltage.

Page 9 1267987 V. INSTRUCTIONS (5) The interface between the edge layer and the polycrystalline stone is also better, and the leakage current can be reduced. Furthermore, placing the transparent substrate on a rotatable table can increase the uniformity of the thickness of the gate insulating film film. The invention provides a method for forming a thin film transistor in a liquid crystal display, the step of which comprises sequentially forming a buffer layer and a polycrystalline layer on a transparent substrate, wherein the transparent substrate can be a glass substrate or the like. High molecular polymer. The above-mentioned polycrystalline fracture layer may be formed by depositing an amorphous germanium layer on the buffer layer and then annealing the amorphous germanium layer into a complex layer. The above annealing method may be Eximmer Laser Annealing (ELA). However, there are other ways to directly form a polycrystalline stone layer, such as continuous crystalline stone (C ο n t i n u o u s

Grain Silicon; CGS), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), Metal Induced Lateral Crystallization (MILC), or Solid Phase Crystallization Solid Phase Crystallization (SPC). Thereafter, the polysilicon layer is treated by plasma on the surface of the polysilicon layer to form a gate insulating layer. Then, a gate layer is formed on the above-mentioned gate insulating layer. A lightly doped drain region is formed on both sides of the gate layer in the polysilicon layer, and a spacer is formed on the sidewall of the gate layer. Next, a source and a NMOS region are formed on both sides of the gate layer in the above-mentioned single crystal layer. Wherein the plasma treatment step is between 30 and 60 ° C, and the above

Page 10 1267987 V. INSTRUCTIONS (6) The reactive gas of the plasma may contain oxygen or nitrogen, such as 02, N2, H20, NH3, N20. When the reaction gas is mainly oxygen, such as 02, N20 or Η20, the above-mentioned gate insulating layer is yttrium oxide. When the reaction gas is mainly nitrogen, such as ruthenium 20, ruthenium 2 or ruthenium 3, the above-mentioned gate insulating layer is ruthenium nitride. When the reaction gas contains oxygen and nitrogen, such as 0 2, Ν 2, Ή 2 0, Ν 2 0, and Ν Η 3, the above-mentioned gate insulating layer may be yttrium oxynitride. The present invention also provides a method of forming a high breakdown voltage gate insulating layer in a thin film transistor liquid crystal display, the method comprising forming a g-polysilicon layer on a transparent substrate. Thereafter, the above-mentioned polysilicon layer is plasma-treated between 300 and 600 ° C to form a gate insulating layer, wherein the reaction gas forming the plasma may contain oxygen or nitrogen or both Contains, for example, hydrogen peroxide, oxygen, or nitrogen oxides. The gate insulating layer may be tantalum oxide, tantalum nitride, nitrogen, or hafnium oxynitride. The preferred temperature in the above plasma treatment step is between 4 50 - 5 50 ° C. The transparent substrate described above rotates during the plasma processing step. An inert gas may be introduced to clean and remove the twin oxide layer on the surface of the polysilicon layer prior to the plasma treatment step. A preferred embodiment of the present invention will be described in detail with reference to the structural diagrams of the steps shown in the second figure. As shown in FIG. 2A, a buffer layer 220 is formed on a transparent substrate 200.

Page 11 1267987 V. INSTRUCTIONS (7) The material of the transparent substrate 200 can be a high molecular polymer such as a glass substrate, acrylic, or transparent plastic. As the buffer layer 220, ruthenium oxide or tantalum nitride can be used. The material selection of the buffer layer 2 0 2 is mainly based on the material matching the lattice constant of the germanium lattice, and the transparency of the light needs to be considered, and the process is simple and good. In general, oxidized stone is a good material because the deposition of existing cerium oxide, such as plasma gain chemical vapor deposition or low pressure chemical vapor deposition, is a very mature process. Further, the buffer layer 202 can also prevent metal ions of the transparent substrate 200 from running into the amorphous layer, causing leakage current of the element. In one embodiment, the buffer g 2 0 2 has a thickness of about 1 0 0 0 - 4 0 0 angstroms. The manner in which the present embodiment is formed for forming a germanium is described by forming an amorphous germanium first and then forming a germanium by annealing. However, it is also possible to form a polycrystalline germanium layer directly in the form of continuous crystalline germanium, continuous side solidification, metal induced crystallization, metal induced side crystallization, or solid phase crystallization. Next, an amorphous germanium layer 220 is formed on the buffer layer. The amorphous germanium layer 204 can be formed by using the currently mature plasma gain chemical vapor deposition method or the _ pressure chemical vapor deposition method. One way is to use hydrogen to decompose methane as a precursor to helium, or helium. Taking the plasma gain chemical vapor deposition method as an example, the process temperature is about 200-600 ° C, the pressure in the reaction chamber is about 0.1-2000 mtorr, and the flow rate of hydrogen is about 20-1000 SCCM. The traffic of 曱炫 is about 50 - 1 0 0 0 SCCM. The thickness of the deposited amorphous germanium layer 104 is about

Page 12 1267987__ V. The invention description (8) is 5 0 - 500 angstroms. ^ As shown in the second B-graph, the amorphous germanium layer 104 is annealed to form a polycrystalline germanium layer 106. The semiconductor characteristics of the polycrystalline germanium layer 106 are better than those of the amorphous germanium, so it is necessary to convert the amorphous germanium into a germanium germanium. The simplest way to convert is to directly heat up the anneal, but the temperature at which the transparent substrate 2000 can withstand must be considered. In the present invention, the preferred annealing method may be an excimer laser annealing method. Next, as shown in the second C diagram, the table of the polysilicon layer 206 is treated with the plasma 2 2 0 «between 300-600 ° C to form the gate insulating layer 208. The selection of the plasma 2 2 0 is mainly determined by the material of the gate insulating layer 208. The plasma 2 2 0 used herein may use a plasma containing oxygen to form a gate insulating layer of ruthenium oxide 2 0 8. A plasma containing nitrogen may also be used to form a gate insulating layer of tantalum nitride. . Further, it is also possible to simultaneously use a plasma containing oxygen and nitrogen to form a gate insulating layer 208 of ruthenium oxynitride. If the gate insulating layer 20 8 is yttrium oxide, the input gas of the plasma 2 2 0 may be 02, H20, or N20, and the flow rate of the input gas is about 2 0 - 5 0 0 0 SCCM, and the reaction chamber pressure is about For 1 - 1 0 0 0 mt rr, the preferred temperature is about 4 50 - 5 5 0 _. Under the above conditions, the thickness of the yttrium oxide formed is about 1 0 0 - 1 0 0 angstrom. If the gate insulating layer is tantalum nitride, the input gas of the plasma 220 may be N2, N3H, N20, the flow rate of the input gas is about 2 0 - 5 0 0 SCCM, and the reaction chamber pressure is about 1-1. 0 0 0 mt 〇rr, the preferred temperature is about 4 5 0 - 5 5 0 °C. Under the above conditions, the thickness of the tantalum nitride formed is about 1 〇 〇 - 1 〇 〇 〇

Page 13 1267987__ V. Description of invention (9) Egypt. If the gate insulating layer is arsenic oxide, the input gas of the plasma 2 2 0 may be 02, H20, N20, N3H, NO, and the flow rate of the input gas is about 2 0 - 5 0 0 0 SCCM, the reaction chamber pressure It is about 1 - 1 0 0 mtorr, and the preferred temperature is about 4 50 - 5 50 °C. Under the above conditions, the thickness of yttrium oxynitride formed is about 1 0 0 - 1 0 0 angstrom. Thereafter, as shown in the second D diagram, a gate layer '2 1 0 is formed on the gate insulating layer 208. The formation method comprises several steps: depositing a metal layer on the gate insulating layer 202, forming a photoresist layer on the metal layer, and transferring the pattern of the gate to the photoresist layer by optical lithography to The photoresist layer is a mask etch metal _ and the photoresist layer is removed. In the above process, the material of the metal may be Ming, chrome, town, braid, or the alloy described above. The metal layer can be deposited by chemical vapor deposition or physical vapor deposition. The photoresist layer can use either positive or negative photoresist, and the material used depends on the frequency of the light being exposed. The way of engraving money can be an isotropic remnant or an anisotropic I insect. As shown in the second E diagram, the next steps may be optional. Because of the lightly twisted and polar regions 212, the transistors have better component characteristics. The dopants are implanted into the polycrystalline germanium layer 206 by means of an ion implanter or an ion cloud. The 10 doped particles are mainly elements which can provide electrons as a conductive carrier, and are generally pentavalent elements such as phosphorus or arsenic. The meaning of light doping means that the doping concentration is lower than the source and is extremely low, about 1 3 3 per square centimeter.

Page 14 1267987 V. INSTRUCTION DESCRIPTION (10) As shown in the second F diagram, the step from the *^ θθ watt is to form the spacer 214 on the sidewall of the gate metal layer 2 10 . The formed person, conformal) dielectric layer, the human-type 10,000-type inclusion, first deposits a layer of conformal and then anisotropic etching. This step has a few _ complex α " we k points, after the ion implantation to form the source S / and the polar region to cover the lightly doped bungee region 2 1 2, and provide the gate and source / Better electrical isolation between the immersion zones. The source and drain regions 2 1 6 are formed by implanting dopants into the polycrystalline layer 2 〇 6 as an ion implanter or as an ion cloud, as in the first G diagram. Here, the doped particles may or may not be the same as the dopants implanted in the previously lightly doped bungee region 2丨2. The doping concentration is higher than the lightly doped bungee region 2 1 2 . The third figure shows a schematic structural view of the reaction chamber of the plasma treatment step. The conduit 3 0 2 introduces the reaction gas 340 and the carrier gas into the reaction chamber 3 〇 , and the substrate 200 is placed on the tray table 320 . A frequency power supply 3 0 6 is provided in the reaction chamber 300 to allow the reaction gas 3 0 4 to form a plasma. The reaction chamber 300 is close to the carrier platform 3 2 0 and has a heater 3 0 8 to heat the substrate 200 to a suitable temperature, and the reaction gas can react with the polysilicon on the substrate 200 to become a gate insulating layer. . The carriage platform 200 can be rotated so that the surface of the polysilicon can be uniformly reacted with the reaction gas, so that the thickness of the grown gate insulating layer is uniform. In addition, a valve 310 charges the gas in the reaction chamber 300. In this step, the inert gas, such as argon, is first introduced into the reaction chamber 300 at the beginning to perform the cleaning action, and can go

Page 15 1267987____ V. INSTRUCTIONS (11) In addition to the layer of neo-oxidation (na t i ve ox i de) on the surface of the ceramsite. The gas input flow is approximately 1 0 0 -8 0 0 0 SC CM and lasts approximately 1 Ο -6 seconds. The inert gas is then turned off, the reaction gas is input, and the power of the radio frequency is adjusted to adjust the plasma concentration produced. The reaction chamber 300 was heated to an appropriate temperature. The reaction platform is rotated at a frequency of approximately 1-10 0# per minute. The pressure in the reaction chamber is approximately 1 - 1 0 0 m t 〇 r r. The gate insulating layer formed by the plasma treatment method, whether it is a cerium oxide, a nitride or an oxynitride, is produced by a combination of a smectite layer and a plasma. The gate insulating layer formed in this manner has better quality than the prior chemical vapor deposition method, and the material has high compactness, so that a high breakdown voltage can be obtained. In addition, the defect between the gate insulating layer and the polycrystalline silicon produced by the reaction of the double crystal layer and the electric beam is less than that of the previous chemical vapor deposition method, so that the leakage current can be reduced. The present invention has been described above by way of a preferred example, and is not intended to limit the scope of the invention. Modifications and similar arrangements made within the spirit and scope of the invention are intended to be included within the scope of the appended claims. Therefore, a preferred embodiment of the invention as set forth above may be used to identify various modifications within the spirit and scope of the invention.

III

Page 16 1267987___ Schematic description of the drawing [Simple description of the drawing] * The first figure shows the structure of a thin film transistor forming a top gate in a conventional manner, and the second figure shows a method according to the present invention. A schematic view of the structure of the thin film transistor forming the top gate at each step; and the third diagram showing the structure of the device for forming the gate insulating layer by plasma treatment. , the main component symbol description] 100 glass substrate 1 02 \ 202 buffer layer 104, 204 amorphous germanium layer 106 > 206 polysilicon layer 108 gate oxide layer 1 1 0 ~ 210 gate metal layer 112, 212 lightly doped Polar region 114, 214 gap wall 16 6 216 source and drain region 200 transparent substrate 208 gate insulating layer 220 plasma 300 reaction chamber

Page 17 1267987 Schematic description 3 0 2 Conduit 3 0 4 Reactive gas 3 0 6 RF power supply 3 0 8 Heater 3 10 Valve 3 2 0 Bracket platform

Page 18

Claims (1)

1267987__ VI. Patent Application Range 1. A method for forming a thin film transistor in a liquid crystal display' includes: sequentially depositing a buffer layer and a polysilicon layer on a transparent substrate; treating the polysilicon layer by plasma Forming a gate insulating layer; forming a gate layer on the gate insulating layer; and forming a source and a drain region in the polysilicon layer on both sides of the gate layer. The method for forming a thin film transistor according to the first aspect of the patent, wherein the plasma processing step is a temperature between 300 and 60 °C. 3. The method of forming a thin film transistor according to claim 2, wherein the electropolymerization comprises oxygen. 4. The method of forming a thin film transistor according to claim 3, wherein the slurry of the earth contains nitrogen. 5. The method of forming a thin film transistor according to claim 3, wherein the gate insulating layer is yttrium oxide. 6. The method of forming a thin film transistor according to the fourth aspect of the patent application, wherein the gate insulating layer is yttrium oxide. 7. The method of forming a thin film transistor according to the second aspect of the patent application, wherein: 1267987___, the patent scope of the invention comprises nitrogen. 8V/ A method of forming a thin film transistor according to claim 7, wherein the gate insulating layer is tantalum nitride. The method of forming a thin film transistor according to claim 4, wherein the gate insulating layer comprises ruthenium oxide and tantalum nitride. 10. The method of forming a thin film transistor according to claim 1, wherein the buffer layer is oxidized or oxidized. 1 1. The method of forming a thin film transistor according to claim 1, wherein the method for forming the polysilicon layer comprises: depositing an amorphous germanium layer on the buffer layer; and quantifying the amorphous germanium layer The molecular laser annealing method is converted into the polycrystalline germanium layer. 1 2. The method for forming a thin film transistor according to claim 1, wherein the method for forming the polycrystalline germanium layer is continuous crystallization, continuous side solidification, metal induced crystallization, metal induced side crystallization, or One of solid phase crystallization φ. 1 . The method of forming a thin film transistor according to claim 1 , before the step of forming the source drain region further comprises: forming a lightly doped drain region in the gate layer in the polysilicon layer Both sides; to 1267987, the patent application scope and the formation of a spacer on the sidewall of the gate layer. A method of forming a thin film transistor according to the first aspect of the invention, wherein the transparent substrate is a glass substrate. 1 5. A method for forming a high breakdown voltage gate insulating layer in a thin film transistor liquid crystal display, comprising: providing a transparent substrate; ▲ the tube 3 (forming a polycrystalline layer on the substrate; 0 0 - 60) The polysilicon layer is treated by plasma treatment between 0 ° C to form a gate insulating layer, wherein the plasma comprises oxygen or contains nitrogen, and the gate insulating layer is tantalum oxide, tantalum nitride, or Is a bismuth oxynitride. 1 6. A method of forming a high breakdown voltage gate insulating layer according to claim 15 of the patent application, wherein the temperature of the step of treating the plasma is at 455 - 550 °C 1. The method of forming a high-crash voltage gate insulating layer according to claim 16 of the patent application, wherein the above-mentioned plasma contains oxygen and nitrogen. 1 8. The high breakdown occurs in the case of claim 17 A method of voltage gate insulating layer, wherein the transparent substrate is rotated in the plasma processing step. 1267987 6. Patent application scope 1. 9. Method for forming high breakdown voltage gate insulating layer according to claim 18 Where the above is introduced by the step of plasma treatment The gas is hydrogen oxide, oxygen, nitrogen, or nitrogen oxide. The layered pole-extinguishing gate is broken, the high-oxygen is formed into the edge of the layer, and the 9th pole is the first step. , such as the law • Fang ο 2 layer and the edge of the cleansing of the body brake pressure ιέί! Electric 隋 入 山 山 朋 弓 弓 弓 高 高 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 成 氧 氧 氧 氧 氧 氧 氧At the table, the plasma layer of the special electric dream, please be in the crystal Shen, the same as the method of the party except the TX 2