1266412 九、發明說明： 【發明所屬之技術領域】 本發明係概括關於一種電阻結構及其製作方法，尤指一 種具有低側端阻抗（low end_resistance)之電阻結構及其製 作方法。 【先前技術】 半導體晶片製程中，常利用多晶矽材料來形成高阻抗電 阻’這種電阻可以取代作為負載(load)的電晶體 (transistor)。例如在靜態隨機存取記憶體(staticrand〇m access memory，SRAM)内的電晶體可由多晶矽所形成的負 載電阻取代，使SRAM内電晶體數量減少，而達到節省成 本、提高積集度(integration)的目的。 常見之負載電阻可概分為多晶矽電阻(p〇lysmc〇n resistor)以及擴散電阻(diffusi〇n resist〇r)兩種。多晶石夕電阻 包含有-摻雜多晶⑪層’且其阻抗可以利❹晶砍層内之 摻質濃度予以調整控制。至於擴散電_是先利用離子佈 植在-半導體基底内形成-摻雜層，然後再利用熱擴散的 方式來活化摻雜層内之離子，以調整其阻抗。—般而言， 無論是多晶砍電阻或擴散電阻，大多具有—類似三明治結 構，其兩侧結構定義為-低阻抗區域，用來製作内連線之 1266412 接觸插塞，以使電阻與其他導線產生電連接，至於被夹於 兩侧低阻抗區域間之南阻抗區域則為電阻之主要結構，用 來提供電子元件或電路設計中需求之高阻抗。 隨著電子產品之多樣化’應用貞載電阻之t路設計亦日 趨複雜，舉例而言，在類比/數位混合模式(mixedm〇de)或 採線電頻率(radiofreqUency，RF)等積體電路中，其對於負 載電阻所提供之高阻抗需求亦愈來愈趨嚴苛。然而由於習 $之電阻結構在高阻抗區域與低阻抗_之接面處具有較 同的側端阻抗’導致電阻結構之阻抗、溫度係數以及電壓 係數等與電阻結構本身之長度、線寬間之線性關係受到衝 擊，因此使得阻抗準確度之估算更為困難，進而無法提供 穩定的高阻抗，影響產品良率。 【發明内容】 因此，本發明之目的即在提供一種電阻結構及其製作方 法，以提供穩定的高阻抗。 、在本發明之較佳實闕巾，該電阻結構包含有一基底， 以及-半導體層設於基底表面。半導體層表面定義有至少 一高阻抗區域以及-低阻抗區域。此外，半導體層包含有 一預定區域與低阻抗區域，低阻抗區域、高阻抗區域接面， 以及鄰近低阻抗區域、高阻抗區域接面之部分高阻抗 1266412 相重疊 區域。 且半導體層於預定區域内之穆雜濃度係大於其他 ^本發明之触實_巾，財法係紐供一基底，並 =，表面形成—半導體層’以及於半導體層表面定義 ^间叫區域以及—低阻抗區域。接著於半導體層表 =全面進行-第—離子佈植製程，以及於半導體層之一預 =域中進行—第二離子佈植製程，以使半導體層於預定 内之H辰度大於其他區域。其中預定區域係與低阻 二區域餘抗區域、高阻抗區域接面，以及鄰近低阻抗 區域、高阻抗區域接面之部分高阻抗區域相重疊。 由於本發明於高阻抗區域以及低阻抗區域接面附近增 =了離子之摻雜濃度，因此可以有效降低電阻結構之側端 改善自知電阻結構中高阻抗區域以及低阻抗區域因 t /辰度洛差導致其接面附近阻抗不穩定的問題，進而可 以綠供一穩定高阻抗來提昇產品的良率。 【實施方式】 明芩考第1圖，第1圖為本發明一電阻結構之剖面示清 圖。如第1圖所示，本發明電阻結構包含有一基底10，一 半導贐層12設於基底1〇表面，且半導體層12表面定義肩 门科抗區域A，以及一低阻抗區域b設於高阻抗區域/ 1266412 之兩側。由於為了改善鄰近高阻抗區域 接面之阻抗不穩定的問題，半導體層12包“=區域B 域仏設於高阻抗區域A中，以及二重換 ㈣參雜區 與低阻抗區域B，低阻抗區域B、高阻抗區域設於 及鄰近低阻抗區域B、高阻抗區域A.接面: 以 域A相重疊之處。半導體層I2a和其兩側之二= 係由具有不同摻質濃度之同一型式形例如： 質形成，以提供一高阻抗成二= ⑶則係由"+摻質形成，以提供-較·抗，用== 作内連線之接觸插塞，使電阻 衣 外，半導體層12a亦可以由P-C生電連接。此 則由P+摻質开M。 、屯成’而半導體層m 在本發明之其他實施例中，為丄 A、低阻抗區域B接面之阻抗不近高:抗區域 可以進-步具有-漸層式的摻質濃声八布通半¥體層,12b 内連線接觸插塞之側端 =°列如於欲製作 其阻抗，至於鄰近低阻抗區域域，以降低 形成一較輕摻雜區域，此較輕摻雜===接面處則 區域B、高阻抗_ 鄰近低阻抗 高阻抗區域A相重疊，# “域及部分 於高阻抗半導體^輕朗之摻質濃度應大 牛泠體層l2a，摻質濃度。 1266412 在本發明之較佳實施例中，半導體層12可以應用於多 晶矽電阻或擴散電阻。若應用於多晶矽電阻，則半導體層 12係由多晶矽形成，且半導體層12下方另包含有一介電 層（未顯示）設於基底10表面，以使半導體層12可以利用 設於介電層中的接觸插塞向下連接至其他元件。若應用於 擴散電阻，半導體層12則由植入基底10表面之一摻雜層 形成，且半導體層12下方可能為設於基底10内之一離子 換雜井5視產品電性要求而定。 在本發明之較佳實施例中，高阻抗區域A内另包含有一 金屬石夕化物阻擋層（salicide block, SAB) 14設於半導體層 12a表面以及鄰近高阻抗區域A、低阻抗區域B接面之部 分半導體層12b表面。低阻抗區域B内另包含有一金屬石夕 化物層（salicide layer)16設於半導體層12b表面。此外，基 底10表面另包含有一層間介電層（inter-layer dielectric, ILD)18用來隔離金屬矽化物層16與其他導電層，至少一 連接至金屬矽化物層16之接觸洞20設於層間介電層18 J-* .-%» η ύζ r^L o’ ->-rL j^k 日日人 /iii» 辑 1 Ο xVr? 主1266412 IX. Description of the Invention: [Technical Field] The present invention relates generally to a resistor structure and a method of fabricating the same, and more particularly to a resistor structure having a low end resistance (low end_resistance) and a method of fabricating the same. [Prior Art] In a semiconductor wafer process, a polysilicon material is often used to form a high-impedance resistor. This resistor can replace a transistor as a load. For example, a transistor in a static random access memory (SRAM) can be replaced by a load resistor formed by polysilicon, so that the number of transistors in the SRAM is reduced, thereby achieving cost saving and integration. the goal of. Common load resistors can be broadly classified into polysilicon resistors (p〇lysmc〇n resistors) and diffusion resistors (diffusi〇n resist〇r). The polycrystalline shi resistance contains a layer of doped polycrystalline 11 and its impedance can be adjusted to control the concentration of dopants in the tantalum layer. As for the diffusion electricity, ions are implanted in the semiconductor substrate to form a doped layer, and then the ions in the doped layer are activated by thermal diffusion to adjust the impedance. In general, whether it is a polysilicon-cutting resistor or a diffusion resistor, most of them have a sandwich-like structure, and the two sides are defined as a low-impedance region, which is used to make the 1266412 contact plug of the interconnect to make the resistor and other The wires are electrically connected, and the south impedance region sandwiched between the low-impedance regions on both sides is the main structure of the resistors to provide the high impedance required in electronic components or circuit design. With the diversification of electronic products, the design of the application of the load-carrying resistor is becoming more and more complicated. For example, in an integrated circuit such as an analog/digital mixing mode or a radio frequency (radifreqUency, RF). The high impedance requirements provided by the load resistors are becoming more and more stringent. However, since the resistor structure has a similar side-end impedance at the junction of the high-impedance region and the low-impedance _, the impedance of the resistor structure, the temperature coefficient, the voltage coefficient, and the like, the length of the resistor structure itself, and the line width. The linear relationship is impacted, making the estimation of impedance accuracy more difficult, which in turn does not provide stable high impedance and affects product yield. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a resistor structure and a method of fabricating the same to provide a stable high impedance. In the preferred embodiment of the present invention, the resistor structure includes a substrate, and the semiconductor layer is disposed on the surface of the substrate. The surface of the semiconductor layer is defined with at least one high impedance region and a low impedance region. In addition, the semiconductor layer includes a predetermined region and a low-impedance region, a low-impedance region, a high-impedance region junction, and a portion of the high-impedance 1266412 overlap region adjacent to the low-impedance region and the high-impedance region junction. And the impurity concentration of the semiconductor layer in the predetermined region is greater than that of the other inventions, the financial system is for a substrate, and the surface formation-semiconductor layer and the surface of the semiconductor layer are defined. And - low impedance area. Then, in the semiconductor layer table = comprehensive - the first ion implantation process, and in the pre- = domain of the semiconductor layer - the second ion implantation process, so that the semiconductor layer within a predetermined degree of H is greater than other regions. The predetermined area overlaps with the low resistance two-region residual area, the high-impedance area junction, and a part of the high-impedance area adjacent to the low-impedance area and the high-impedance area junction. Since the present invention increases the doping concentration of ions in the vicinity of the junction between the high-impedance region and the low-impedance region, the side end of the resistor structure can be effectively reduced to improve the high-impedance region and the low-impedance region of the self-known resistor structure due to t/Chen Luo The difference leads to the problem of unstable impedance near the junction, which in turn can provide a stable high impedance to improve the yield of the product. [Embodiment] FIG. 1 is a cross-sectional view showing a resistor structure of the present invention. As shown in FIG. 1, the resistor structure of the present invention comprises a substrate 10, a semi-conducting layer 12 is disposed on the surface of the substrate, and a surface of the semiconductor layer 12 defines a shoulder-resistant region A, and a low-impedance region b is disposed at a high level. Impedance area / sides of 1266412. In order to improve the impedance instability of the junction adjacent to the high-impedance region, the semiconductor layer 12 includes "= region B region is set in the high-impedance region A, and the double-replacement (four) impurity region and the low-impedance region B, low impedance The region B, the high-impedance region is located at and adjacent to the low-impedance region B, and the high-impedance region A. junction: where the domain A overlaps. The semiconductor layer I2a and the two sides thereof are equal to each other having different dopant concentrations The shape is, for example, formed to provide a high impedance to two = (3) is formed by "+ dopant to provide - comparison resistance, with == as the contact plug of the interconnect, so that the resistance is outside, The semiconductor layer 12a may also be electrically connected by a PC. This is made by P+ doping M. , and the semiconductor layer m is in other embodiments of the invention, the impedance of the junction of the 丄A, low-impedance region B is not Near height: the anti-region can be step-in-step with the gradation of the dense octagonal octagonal half-body layer, the side end of the 12b interconnecting contact plug = ° column if the impedance is to be made, as for the adjacent low impedance Region to reduce the formation of a lighter doped region, this lighter doping === junction at region B _ A low impedance high impedance high impedance adjacent the overlap region A, # "field and a high impedance portion of the semiconductor light Langevin ^ dopant concentration should be large cattle Ling L2a layer, doping concentration. 1266412 In a preferred embodiment of the invention, the semiconductor layer 12 can be applied to a polysilicon resistor or a diffusion resistor. If applied to the polysilicon resistor, the semiconductor layer 12 is formed of polysilicon, and a dielectric layer (not shown) is further disposed under the semiconductor layer 12 on the surface of the substrate 10, so that the semiconductor layer 12 can be disposed in the dielectric layer. The contact plug is connected down to other components. If applied to a diffusion resistor, the semiconductor layer 12 is formed by one of the doped layers on the surface of the implant substrate 10, and the underlying semiconductor layer 12 may be an ion-exchanged well 5 disposed in the substrate 10 depending on the electrical requirements of the product. In a preferred embodiment of the present invention, the high-impedance region A further includes a metallization block (SAB) 14 disposed on the surface of the semiconductor layer 12a and adjacent to the high-impedance region A and the low-impedance region B. Part of the surface of the semiconductor layer 12b. The low-resistance region B further includes a sacrificial layer 16 disposed on the surface of the semiconductor layer 12b. In addition, the surface of the substrate 10 further includes an inter-layer dielectric (ILD) 18 for isolating the metal telluride layer 16 from the other conductive layers, and at least one contact hole 20 connected to the metal telluride layer 16 is disposed between the layers. Dielectric layer 18 J-* .-%» η ύζ r^L o' ->-rL j^k Japanese/iii» Series 1 Ο xVr? Main
T ， 从汉王一守电/W么么汉々;^ I曰J ”「电"冒 1 〇 <石卩，刀取W 以及接觸洞20内，以使電阻結構得以藉由接觸洞20内之 導電層22電連接至後續形成在層間介電層18上方的導線 和元件。 請參考第2圖至第4圖，第2圖至第4圖為本發明製作 1266412 私阻之方法示思圖。如第2圖所示，本發明方法先於基 底1〇表面形成半導體層12，並且於半導體層12表面定義 一向阻抗區域A以及二低阻抗區域B設於高阻抗區域a之 兩側。接著進行一第一離子佈植製程，利用n型或p型摻 貝來對半導體層12表面全面進行摻雜。然後，如第3圖所 示，進行一微影製程，以於半導體層12表面形成一由光阻 形成的遮罩24覆盍於高阻抗區域a之部分表面。隨後再進 行一第二離子佈植製程，利用與第一離子佈植製程同一型 式之摻質植入半導體層12中。經過熱處理活化半導體層 12後，半導體層12内可形成輕摻雜區域12a設於高阻抗 區域A中，以及二重摻雜區域設於與低阻抗區域B， 低阻抗區域B、尚阻抗區域a接面，以及鄰近低阻抗區域 B、高阻抗區域A接面之部分高阻抗區域A相重疊之處。 如第4圖所示、，去除遮罩24後，隨後於高阻抗區域A 内之半導體層12a以及部分半導體層12b表面形成金屬矽 化物阻擋層14,並且利用金屬矽化物阻擋層I#作為遮罩， 於低阻抗區域B内之半導體層12b表面形成金屬石夕化物層 16，以降低兩側半導體層12b之阻抗。接下來再於基底1〇 表面形成層間’ I %層18 ’例如^ 一乳化妙層或石朋填破玻璃 (borophosphosilicate glass，BPSG)，用來隔離金屬矽化物層 16與其他導電層。然後利用微影以及飿刻製程，在層間介 電層18中形成至少一連接至金屬矽化物層μ之接觸洞 1266412 20，並且於層間介電層18之部分表面以及接觸洞20内形 成導電層22，以使電阻得以藉由接觸洞20内之導電層22 電連接至後續形成在層間介電層18上方的導線和元件，完 成如第1圖所示之電阻結構製作。 相較於習知之電阻結構，本發明於高阻抗區域以及低阻 抗區域接面附近增加了離子之摻雜濃度，因此可以有效降 低電阻結構之側端電阻約一至兩個數量級，改善習知電阻 結構中南阻抗區域以及低阻抗區域因換質濃度落差導致其 接面附近阻抗不穩定的問題，進而可以提供穩定而均勻之 高阻抗來滿足SRAM、類比電路、類比/數位混合模式以及 無線電頻率等積體電路中對於大量負載電阻之需求，並且 提昇產品的良率。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋 範圍。 【圖式簡單說明】 第1圖為本發明一電阻結構之剖面示意圖。 第2圖至第4圖為本發明製作一電阻之方法示意圖。 1266412 【主要元件符號說明】 10 基底 12、 12a、12b半導體層 14 金屬石夕化物阻搶層 16 金屬石夕化物層 18 層間介電層 20 接觸洞 22 導電層 24 遮罩 A 南阻抗區域 B 低阻抗區域 12T, from Hanwang one defensive / W 么 々 々; ^ I 曰 J ” “Electric” quot; 1 〇 < stone 卩, knife W and contact hole 20, so that the resistance structure can be contacted by the hole 20 The conductive layer 22 is electrically connected to the wires and components formed subsequently over the interlayer dielectric layer 18. Please refer to Figures 2 to 4, and Figures 2 to 4 show the method for making the 1266412 private resistance of the present invention. As shown in FIG. 2, the method of the present invention forms a semiconductor layer 12 on the surface of the substrate 1 and defines a direct impedance region A and two low-impedance regions B on both sides of the high-impedance region a on the surface of the semiconductor layer 12. Then, a first ion implantation process is performed, and the surface of the semiconductor layer 12 is fully doped by using n-type or p-type doping. Then, as shown in FIG. 3, a lithography process is performed to surface the semiconductor layer 12. A mask 24 formed of a photoresist is formed to cover a portion of the surface of the high-impedance region a. Subsequently, a second ion implantation process is performed to implant the semiconductor layer 12 with a dopant of the same type as the first ion implantation process. After the semiconductor layer 12 is activated by heat treatment, the semiconductor layer 12 is The lightly doped region 12a can be formed in the high impedance region A, and the double doped region is disposed in the low impedance region B, the low impedance region B, the still impedance region a, and the adjacent low impedance region B, high impedance. A portion of the high-impedance region A where the junction of the region A overlaps. As shown in Fig. 4, after the mask 24 is removed, a metal telluride is subsequently formed on the surface of the semiconductor layer 12a and the portion of the semiconductor layer 12b in the high-impedance region A. The barrier layer 14 is formed with a metal telluride barrier layer I# as a mask to form a metallization layer 16 on the surface of the semiconductor layer 12b in the low-resistance region B to reduce the impedance of the semiconductor layers 12b on both sides. The surface of the substrate 1 is formed with an interlayer 'I% layer 18' such as a emulsified layer or a borophosphosilicate glass (BPSG) for isolating the metal telluride layer 16 from other conductive layers. In the encapsulation process, at least one contact hole 1266412 20 connected to the metal telluride layer μ is formed in the interlayer dielectric layer 18, and a conductive layer 22 is formed on a part of the surface of the interlayer dielectric layer 18 and the contact hole 20 so that The resistor is electrically connected to the wires and components formed subsequently over the interlayer dielectric layer 18 by the conductive layer 22 in the contact hole 20, and the resistor structure as shown in FIG. 1 is completed. Compared with the conventional resistor structure, The invention increases the doping concentration of ions in the vicinity of the high-impedance region and the low-impedance region junction, so that the side-end resistance of the resistor structure can be effectively reduced by about one to two orders of magnitude, and the south impedance region and the low-impedance region in the conventional resistor structure are improved. The drop in mass concentration results in an unstable impedance near the junction, which in turn provides a stable and uniform high impedance to meet the demand for a large number of load resistors in integrated circuits such as SRAM, analog circuits, analog/digital mixing modes, and radio frequencies. And improve the yield of the product. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patentable scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a resistor structure of the present invention. 2 to 4 are schematic views showing a method of fabricating a resistor according to the present invention. 1266412 [Description of main components] 10 Substrate 12, 12a, 12b Semiconductor layer 14 Metallurgical barrier layer 16 Metallurgical layer 18 Interlayer dielectric layer 20 Contact hole 22 Conductive layer 24 Mask A South impedance region B Low Impedance area 12