TWI265685B - Slicer apparatus and method for generating slicer output values - Google Patents

Slicer apparatus and method for generating slicer output values

Info

Publication number
TWI265685B
TWI265685B TW093132506A TW93132506A TWI265685B TW I265685 B TWI265685 B TW I265685B TW 093132506 A TW093132506 A TW 093132506A TW 93132506 A TW93132506 A TW 93132506A TW I265685 B TWI265685 B TW I265685B
Authority
TW
Taiwan
Prior art keywords
slicer
generating
output values
viterbi
circuits
Prior art date
Application number
TW093132506A
Other languages
English (en)
Other versions
TW200614723A (en
Inventor
Tsu-Chun Liu
Ming-Lu Wu
Original Assignee
Ic Plus Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ic Plus Corp filed Critical Ic Plus Corp
Priority to TW093132506A priority Critical patent/TWI265685B/zh
Priority to US10/906,580 priority patent/US20060088131A1/en
Publication of TW200614723A publication Critical patent/TW200614723A/zh
Application granted granted Critical
Publication of TWI265685B publication Critical patent/TWI265685B/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/062—Setting decision thresholds using feedforward techniques only

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Dc Digital Transmission (AREA)
TW093132506A 2004-10-27 2004-10-27 Slicer apparatus and method for generating slicer output values TWI265685B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093132506A TWI265685B (en) 2004-10-27 2004-10-27 Slicer apparatus and method for generating slicer output values
US10/906,580 US20060088131A1 (en) 2004-10-27 2005-02-25 Slicer apparatus and method for generating slicer output values

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093132506A TWI265685B (en) 2004-10-27 2004-10-27 Slicer apparatus and method for generating slicer output values

Publications (2)

Publication Number Publication Date
TW200614723A TW200614723A (en) 2006-05-01
TWI265685B true TWI265685B (en) 2006-11-01

Family

ID=36206175

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093132506A TWI265685B (en) 2004-10-27 2004-10-27 Slicer apparatus and method for generating slicer output values

Country Status (2)

Country Link
US (1) US20060088131A1 (zh)
TW (1) TWI265685B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2447080B8 (en) * 2007-03-01 2011-08-03 Artimi Inc Signal decoding systems
CN108111442B (zh) * 2016-11-25 2020-09-01 北京紫光展锐通信技术有限公司 维特比均衡方法、维特比均衡器及接收机

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5099500A (en) * 1988-10-14 1992-03-24 Concord Communications, Inc. Symbol detection and error correction coding in a local area network
US6252904B1 (en) * 1998-11-13 2001-06-26 Broadcom Corporation High-speed decoder for a multi-pair gigabit transceiver

Also Published As

Publication number Publication date
TW200614723A (en) 2006-05-01
US20060088131A1 (en) 2006-04-27

Similar Documents

Publication Publication Date Title
Roshan-Zamir et al. A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR-and IIR-tap adaptation in 65-nm CMOS
US7822113B2 (en) Integrated decision feedback equalizer and clock and data recovery
WO2005060655A3 (en) Deterministic jitter equalizer
US8934527B2 (en) Architecture for very high-speed decision feedback sequence estimation
WO2006081044A3 (en) Power sourcing equipment having auto-zero circuit for determining and controlling output current
US10263759B2 (en) Signal presence detection circuit and method
US9973356B1 (en) Slicer and decision feedback equalization circuitry
KR101802791B1 (ko) 판정 궤환 등화기
US10523472B1 (en) Interface circuitry
TW200629726A (en) A common-mode shifting circuit for CML buffers
TW200703014A (en) System and method of adjusting output voltage of a transmitter based on error rate
WO2013081572A3 (en) Methods and circuits for reducing clock jitter
US8634500B2 (en) Direct feedback equalization with dynamic referencing
US20100117688A1 (en) Differential pre-emphasis driver
TWI265685B (en) Slicer apparatus and method for generating slicer output values
Wu et al. A 2$\,\times\, $25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet
EP2465203A4 (en) INTEGRATED CIRCUIT AND ELECTRONIC DEVICE HAVING A THRESHOLD GENERATION CIRCUITRY, AND ASSOCIATED METHOD
TW200711396A (en) Pilot-directed and pilot/data-directed equalizers
TW200520378A (en) Impedance matching circuit and method
CN205490150U (zh) 一种低功耗的电源供电系统
Song et al. A maximum-likelihood sequence detection powered ADC-based serial link
WO2008126207A1 (ja) 半導体集積回路の設計方法
US20150207648A1 (en) Modular Low Power Serializer-Deserializer
Lee et al. 0.37-pJ/b/dB PAM-4 transmitter and adaptive receiver with fixed data and threshold levels for 12-m automotive camera link
Vamvakos et al. A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications