1265604 14372-1 twf.doc/g 九、發明說明： 【發明所屬之技術領域】 . 本發明是有關於—種半導體記憶體元件，且特別是有 . 關於一種非揮發性記憶體及其製造方法與操作方法。 【先前技術】 在各，非揮發性記憶體產品中，具有可進行多次資料 之存入、讀取、抹除等動作，且存入之資料在斷電後也不 • 會消失之優點的可電抹除且可程式唯讀記憶體 (EEPR0M)，已成為個人電腦和電子設備所廣泛採用的一 種記憶體元件。 典型的可電抹除且可程式唯讀記憶體係以摻雜的多晶 石夕(polysilicon)製作浮置閘極(floating gate)與控制閘極 (control gate)。而且，為了避免典型的可電抹除且可程式唯 谓s己憶體在抹除時，因過度抹除現象太過嚴重，而導致資 料之疾判的問題。而在控制閘極與浮置閘極側壁、基底上 方另設一選擇閘極(select gate)，而形成分離閘極(Split-gate) _ 結構。 此外，在習知技術中，亦有採用一電荷陷入層(charge trapping layer)取代多晶矽浮置閘極，此電荷陷入層之材質 例如是氮化石夕。這種氮化;B夕電荷陷入層上下通常各有一層 氧化矽，而形成氧化矽/氮化矽/氧化石夕 (oxide-nitride-oxide，簡稱0N0)複合層。此種元件通稱為 矽/氧化矽/氮化矽/氧化矽/碎(SONOS)元件，具有分離閘極 結構的SONOS元件也已經被揭露出來，如美國專利 1265604 14372-ltwf.doc/g US5930631 號案。 然而，上述具有分離閘極結構的s〇N〇s元件， e又置分離驗結構需要較大的分離_區柄具有的 記憶胞尺寸，因此其記憶胞尺寸較具有堆疊之可電技 除且可程式唯讀記憶體之記憶献寸大，喊生所謂 增加元件集積度之問題。 ·、、“ 【發明内容】1265604 14372-1 twf.doc/g IX. Description of the invention: [Technical field of the invention] The present invention relates to a semiconductor memory element, and in particular to a non-volatile memory and a method of manufacturing the same And method of operation. [Prior Art] In each non-volatile memory product, there are many operations in which data can be stored, read, erased, etc., and the stored data does not disappear after power-off. Erasable and programmable read-only memory (EEPR0M) has become a memory component widely used in personal computers and electronic devices. A typical electrically erasable and programmable read-only memory system fabricates a floating gate and a control gate with doped polysilicon. Moreover, in order to avoid the typical electric erasable and programmable only when the suffix is erased, the over-erasing phenomenon is too serious, which leads to the problem of material discrimination. A select gate is formed on the sidewalls of the control gate and the floating gate and above the substrate to form a split gate (Split-gate) structure. In addition, in the prior art, a charge trapping layer is used instead of the polysilicon floating gate, and the material of the charge trapping layer is, for example, nitride nitride. This nitriding; usually has a layer of yttrium oxide on the upper and lower sides of the charge trapping layer, and forms a composite layer of oxide-nitride-oxide (0N0). Such elements are commonly referred to as yttrium/yttria/tantalum nitride/yttria/smear (SONOS) components, and SONOS components having a separate gate structure have also been disclosed, such as U.S. Patent 1,265,604, 14372-ltwf.doc/g US5930631 case. However, the above-mentioned s〇N〇s element having a separate gate structure, e and the separation structure require a larger separation memory cell size, so that the memory cell size is more than the stackable electrical technology. The memory of the programmable read-only memory is large, and the so-called increase in the accumulation of components is called. ·,," [Summary of the Invention]
有鑑於此，本發明之一目的為提供一種非揮發性記 體及其製造方法與操作方法，可以提高記憶縣積度及^ 件效能。 、本發明之再一目的為提供一種非揮發性記憶體及其製 造方法與操作方法，此_揮發性記顏可關用源極側 注入效，(s〇urce_Side Injection，SSI)進行程式化操作而 能夠提高程式化速度，並提高記憶體效能。 、本發，之再一目的為提供一種非揮發性記憶體及其製 造方法與操財法，可以提高記紐齡容量，且製程簡 單，可以降低成本。 + 3本^明提出一種非揮發性記憶體單元，此記憶單元至 〈疋，第一圮憶胞、第一絕緣間隙壁與第二記憶胞所構 成第一圯彳思胞設置於基底上。第一絕緣間隙壁設置於第 一記憶胞之側壁上。第二記憶胞設置於基底上，並透過第 、、、邑、、彖間隙壁與第-記憶胞相鄰。第_記憶胞包括：設置 ^基底上的第-閘極、設置於第_閘極與基底之間的第一 複合介電層。其中，第—複合介電層包括第_底介電層、 1265604 14372-ltwf.doc/g 第二記憶胞包括:設置 =與第-記憶胞之間: ^電層包如二齡電層、第二電荷陷人層與第 二電=====中’第-電荷陷入層與第 介電層、第二麻Λ為乳化石夕。第—底介電層、第一頂 在上述之轉^介1層讀f可為氧化矽。 質可為氧切或 第-閘極表面沈積2、、、巴、、彖間隙壁疋猎由在 刻形成的。緣層後，利用自行對準非等向性姓 上^之轉發性記鮮元巾，第二複合介電#更包 5又置於第二閘極與第一絕緣間隙壁之間。曰 區盥汲極區職Γ ^縣卿:壁、源極 己憶胞行由多數個上述之記憶單元所 一 -乂些圮憶單元串聯連接在一起，並由多數個第 離選擇單元設置於記憶胞行之一侧。選 弟一閘極與第三複合介電層。其中，第三 極口又置於^底上。第三複合介電層設置於第三閘極與基底 之!b?二複合介電層包括第三底介電層、第三電荷陷 入曰與第三頂介電層。第三絕緣間隙壁設置於選擇單元之 側壁上’其巾第三絕緣_壁設置於選擇單元與記憶胞行 1265604 14372-1 twf.doc/g 之源極區設置於記憶胞行另一側之基底中。沒極區設置於 選擇單元外側之基底中。 在上述之非揮發性記憶體中’弟二電荷陷入層之材質 可為氮化石夕。第三底介電層與第三頂介電層之材質可為氧 化石夕。第二絕緣間隙壁及第三絕緣間隙壁之材質可為氧化 石夕或氮化石夕。 在本發明之非揮發性記憶體中，記憶胞行是由多數個 第一 ό己丨思胞及第二記憶胞交錯排列而成。由於在第一記慎 胞與第二記憶胞之間並沒有間隙，且選擇單元與第二記情 胞之間也沒有間隙，因此可以提升記憶胞陣列之積集度。 而且，在記憶胞行中的各個第一記憶胞及第二記憶胞都可 以儲存電荷，因此也可以提升儲存容量。 此外，由於第一記憶胞及第二記憶胞是使用電荷陷入 層作為電荷儲存單元，因此不需要考慮閘極耦合率的概 念，而能以較低的工作電壓，達到相同的操作速度。 本發明又提出一種非揮發性記憶體，此非揮發性記憶 體至少是由記憶胞陣列、多數個選擇單元、多數個第一摻 ，區、多數個第二掺雜區、多數條字元線、多數條位元線、 多數條選擇線、多數條共用線所構成。記憶胞陣列的每一 讀、胞行包括錄個第—記憶胞與多數個第二記憶胞。多 數個選擇單元分職置在記憶胞陣㈣各記憶胞行的一 側，其中在各記憶胞行中的選擇單元與多數個第一記憶胞 之間具有多數個_，各_二記憶胞分職人不同的各 固間隙中’數個第一摻雜區分別設置於記憶胞陣列的各 1265604 14372-ltwf.doc/g 二= 亍，二之基底中。多數個第二摻雜區分別設置 =選擇::外侧之基底中。多數條字元線與多數條位元 ====::記憶胞或第二記憶胞的 元。多數條共用線分別連===，選擇單 .,列之多數個第一摻雜區。 閘極232性則意體中，各第—記憶胞是由第一 一複合介電層設置於第方％緣_壁所構成。第 —人 1極下方’且複合介雷声舍括第 -底”電層、第-電荷陷人層與第—頂 二 ;緣間隙壁設置於第-閘極之側壁上。各第:球:二 於第二閉極下方，此第1^構；1^複=電層設置 層、-第二電荷陷入層與—第」頂1層^括—第二底介電 由選擇閘極i 一對第一_=頂㈣層。各選擇單元是 間隙壁設置於選擇閘極之側壁上。獨成冑弟一絶緣 在上述之非揮發性記憶 —— 電荷陷入層之材質可為氮化石夕。第—底入f與第二 電層、第二底介電層與第 底"電層、弟一頂介 第-絕緣間隙壁與第二絕緣間;辟^^質可為氧化矽。 化石夕。 材質可為氧化石夕或氮 在上述之非揮發性記憔一 合介電層。此第三複人八: 、擇早兀具有第三複 三複人介静勺ζΐ 口層設置於選擇閘極下方，此第 頂介電層。其中，第三電;3爲弟二電荷陷入層與第三 電何入層之材質可為氮化矽。第 1265604 14372-ltwf.doc/g 二底介電層與第三頂介電層之材質可為氧化矽。 口在上述之非揮發性記憶體中，第一摻雜區為卜型源極 區第一摻雜區為η-型汲極區。而且，各汲極區分別連接 至不同的位元線的其中之一。 在亡述之非揮發性記憶體中，各第一記億胞的第一閘 極/、各第一δ己憶胞的第二閘極分別連接至不同的字元線的 其中之一。 在上述之非揮發性記憶體中，第二記憶胞的第二複合 介電層在_巾形成呈U_字形，且由各第二記憶胞的第二 閘極填滿。 ^在本發明之非揮發性記憶體中，記憶胞行是由多數個 第一，憶胞及第二記憶胞交錯排列而成。由於在第一記憶 胞與第一記憶胞之間並沒有間隙，且選擇單元與第二記憶 胞之間也沒有_，因此可以提升記憶胞陣狀積集度二 而且’在鋪胞行中的各個第—記憶胞及第二記憶胞都可 以儲存電荷，因此也可以提升儲存容量。 此外’由於第一記憶胞及第二記憶胞是使用電荷陷入 層作為電荷儲存單元’因此*需要考慮陳躺合率的概 念，而能夠以較低工作電壓，達到相同的操作速度。 立抑本發明再提供一種非揮發性記憶單元，此非揮發性記 憶單元至少是由第-記憶胞、選擇單元、第二記憶胞、第 一絕緣間隙壁、第二絕緣間隙壁所構成。第—記憶胞，設 置於基底上。選擇單元設置在基底上，且選擇單元與第一 3己k胞以一間隙相隔離。第二記憶胞填入此間隙中。第一 1265604 14372-ltwf.doc/g 離與第二記憶胞。第二絕緣間隙 =;擇::與第二，其中第-記憶胞包括第- 二用以門：二'月t包括弟—閘極’第三記憶胞包括第三閘 - 極用以開啟/關閉其下方的通道區。 u字述1非揮發性記憶單元中，第二忠隱胞更包括- 二字形層支擇間隙中的第二閉極。此U-字 形層可為電荷陷入層。而且 癱，此外，U·字形層可為複合介：；形層之材質可為氮化 •穿随介電層、電荷陷入層斑頂;j，此複合介電層包括 之材質可為氧切，電其中，穿隨介電層 電層之材質可為氧切。可為氮化梦，頂介 在上述之非揮發性記憶單元中， 4 -穿隨介電層、第一電荷陷 弟更包括第 随介電層設置於基底上。第介電層。第一穿 介電層上。第-頂介電層設置又置於第一穿隨 第一穿隨介電層之材質可為氧切上。其中’ 在上述之非揮發性記憶單元中， 電荷陷入層。虛擬電荷陷人層設 擬 陷入層與第一頂介電層。第一穿隨=认弟-電荷 第:電荷陷入層設置於第-穿_::== 設置於第一電荷陷入層上。 弟頂介電層 在上述之非揮發性記鮮元巾，轉單4包括第二 1265604 14372-ltwf.doc/g 穿，介電層與第二頂介電層。第二穿隨介電層設置於虛擬 電荷陷入層與基底之間。第二頂介電層設置於虛擬電荷陷 - 入層與第三閘極之間。 …在上狀轉發性記鮮元+，第二記憶胞更包括u_ 子形層。此u-字形層可為一複合介電層，此複合介電層至 少包括第二電荷陷入層。其中，第二電荷陷入層之材士可 為氮化石夕。而且，u-字形層更包括第三穿隨介電層盘第三 • 頂介電層。第三穿隧介電層設置於第二電荷陷入層與基底 =間。第二頂介電層設置於第二電荷陷人層與第二閉極之 本發明提出-種非揮發性記憶體之操作方法，適用於 2之非揮發性記㈣，此方法在騎程式化操作時，於 ^疋之位讀施加0伏特賴，於非敎之位元線施加一 -電壓’於與選定之記憶胞所祕之字元線相鄰、且靠 定之字元線上施加—第二電壓，於其他非選 Μ ΐί線及選擇線上施加一第三電壓，於源極線施加― 四电壓’以祕側注人效應程式化選定之記懷胞。 3 3^1 述之轉發性記㈣之操作方法中，第一電麗為 匕伏特左右，第二賴h5伏特左右，第三電壓為9伏 荷左右，苐四電壓為4.5伏特左右。 在上狀鱗發性記賴讀作方法巾，騎讀取操 於^之位猶施加G伏特雜，於非敎之位元 ^：=五霞，於敎之記憶胞_接之字元線施加 心、輕，於其他非敎之字元線及選擇線上施加一第 1265604 14372-1 twf.doc/g 七電壓，於源極線施加一第八電壓，以讀取選定之記憶胞。 在上述之非揮發性記憶體之操作方法中，第五電壓為 1·5伏特左右，第六電壓為15伏特左右，第七電壓為6 ^ 特左右，第八電壓為1.5伏特左右。 在上述之非揮發性記憶體之操作方法中，在進行抹除 操作時，於選定之位元線施加一第九電壓，於非選定之位 加0伏特輕’於選定之記憶胞職接之字元線施 十輕，於選定之記憶胞輪接之字元線與汲極區 =間的所有麵定之字元線、選擇線上施加—第十一電 二ΐ選ΐ之記憶胞所输之字元線與源極區之間的所有 ------ 伏特左右。 3 _左右’斜-電壓為9 在上述之非揮發性記憶體之操作方 抹除操作之方式是於字元線上施〗= ，一第十三電壓，以_ 基底 陣列之抹除。 牙隧放應進仃整個記憶胞 為^作樹，第十二電壓 伏特左右，且第十三電壓—為伏特。第十二電壓為〇 特左右，且第十三電壓為6伏特。寺。第十二電壓為_6伏 在本發明之鱗贿記憶體之操作方法巾，其係利用 1265604 14372-ltwf.doc/g 源極側注入效應(S〇urce-Side Injection，SSI)以單一記憶胞 之單一位元為單位進行程式化，並利用熱電洞注入效應或 F-N穿隧效應進行記憶胞之抹除。因此，其電子注入效率 幸父鬲’故可以降低操作時之記憶胞電流，並同時能提高操 作速度。因此，電流消耗小，可有效降低整個晶片之功率 損耗。 本發明又提出一種非揮發性記憶體的製造方法，此方 法係先提供一基底，並於此基底上形成多數個堆疊閘極結 構。其中堆疊閘極結構各自包括第一複合介電層、第一閘 極與頂蓋層，且相鄰兩該些堆疊閘極結構之間具有間隙。 然後，於堆疊閘極結構之側壁分別形成絕緣間隙壁，並於 基底上形成第二複合介電層。接著，基底上形成導體層， 並移除邛分此導體層，以形成填滿堆疊閘極結構之間的間 ^的f數個第二閘極，且第二閘極與堆疊閘極結構構成記 憶胞行。之後，於記憶胞行兩側之基底巾形成祕區與汲 入在上，之非揮發性記憶體的製造方法中，於第一複合 複合介電層各自包括底介電層、電荷陷入層 法。於^广I。/移除部分導體層之方法包括化學機械研磨 ;土&中形成源極區與汲極區之方法包括離子植入法。 於堆非揮發性記憶體的製造方法中，由於採用 要微;間填入第二複合介電層及導體層，不需 極姓構。因ί ί即可於堆疊閘極結構之間製作出另一種閘 匕衣程較為簡單，且可以減少成本。此外，本 1265604 143 72-1 twf.doc/g 發明之非揮發性記憶體，使用電荷陷入層作為電荷儲存單 元’因此^需要考慮間極_馬合率的概念，T降低操作所需 " 之工作電壓，而且提升記憶胞的操作效率。此外，本發明 死^成非揮叙性§己憶體之步驟與習知的製程相比較為簡單， 因此可以減少製造成本。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 I 明如下。 【實施方式】 圖1A為緣示本發明之非揮發性記憶體之一較佳實施 例之上視圖。圖1B為繪示圖ία中沿α·Α，線之結構剖面 圖。圖1C為繪示本發明之記憶單元及選擇單元之結構剖 面圖。 请同時參照圖1Α、圖1Β及圖1C，本發明之非揮發 性記憶體結構至少是由基底100、元件隔離結構1〇2、主動 區104、多數個記憶單元…〜如、選擇單元1〇6、汲極區 # 應(摻雜區）、源極區110(摻雜區)所構成。 基底100例如是矽基底，此基底100可為ρ型基底或 Ν型基底。元件隔離結構1〇2設置於基底1〇〇中，用以定 義出主動區104。 多數個記憶單元Q1〜Qn設置於基底100上。各個記憶 單元Q1〜Qn是由記憶胞H2及記憶胞ι14所構成。 記憶胞112設置於基底1〇〇上，其例如是由複合介電 層116、閘極118、頂蓋層120所構成。閘極118設置於基 15 1265604 14372-ltwf.doc/g 底H)〇 h複合介電層116設置於 間。此複合介電層116狁其麻1λλ>+ 丞低i⑻之 電荷陷入層⑽與頂介電%^ 6依序為底介電層116a、 n 11Q u b 丨電層116c。頂蓋層120設置於閘 L之^辟_ 122 ^置於_18與複合介電層 :\之材_如是氮化發；頂介電層116c之 閘極118之材質例如是摻雜多晶石夕。 貝皿層120之材貝例如是氧化石夕。絕緣間隙壁122之材質 匕括絕緣材料，例如是氮化矽或氧化矽。In view of the above, it is an object of the present invention to provide a non-volatile record, a method of manufacturing the same, and a method of operating the same, which can improve the memory level and the efficiency of the memory. A further object of the present invention is to provide a non-volatile memory, a method for fabricating the same, and a method for operating the same, which can be programmed with a source side injection effect (s〇urce_Side Injection, SSI). It can improve stylization speed and improve memory performance. A further object of the present invention is to provide a non-volatile memory, a manufacturing method thereof and a financial method, which can improve the capacity of the New Age, and the process is simple, and the cost can be reduced. +3 本明 proposes a non-volatile memory unit, wherein the memory unit is disposed on the substrate by the first memory cell, the first insulating spacer and the second memory cell. The first insulating spacer is disposed on a sidewall of the first memory cell. The second memory cell is disposed on the substrate and is adjacent to the first memory cell through the first, the, the 邑, and the 彖 spacer. The first memory cell includes: a first gate electrode disposed on the substrate, and a first composite dielectric layer disposed between the first gate and the substrate. Wherein, the first composite dielectric layer comprises a first dielectric layer, 1265604 14372-ltwf.doc/g, and the second memory cell comprises: between the setting = and the first memory cell: ^ an electrical layer package, such as a second-generation electrical layer, The second charge trapping layer and the second electric===== 'the first charge trapping layer and the first dielectric layer, and the second paralysis is an emulsified stone. The first-bottom dielectric layer and the first top can be yttrium oxide in the above-mentioned layer 1 of the transfer layer. The quality can be formed by oxygen cutting or the first-gate surface deposition, 2,, bar, and 彖 gaps. After the edge layer, the second composite dielectric is further disposed between the second gate and the first insulating spacer by self-aligning the non-isotropic first name.盥汲区盥汲极区职Γ ^县卿: The wall and the source have been recalled by a plurality of the above-mentioned memory units - these memory units are connected in series, and are set by a plurality of first selection units One side of the memory cell line. Choose a gate and a third composite dielectric layer. Among them, the third pole is placed on the bottom. The third composite dielectric layer is disposed on the third gate and the substrate. The bb-di composite dielectric layer includes a third bottom dielectric layer, a third charge trapping layer, and a third top dielectric layer. The third insulating spacer is disposed on the sidewall of the selection unit. The third insulating wall of the device is disposed on the other side of the memory cell. The source region of the selected cell and the memory cell row 1265604 14372-1 twf.doc/g is disposed on the other side of the memory cell row. In the substrate. The non-polar region is disposed in the substrate outside the selection unit. In the non-volatile memory described above, the material of the second charge trapping layer may be nitrided. The material of the third bottom dielectric layer and the third top dielectric layer may be oxidized stone. The material of the second insulating spacer and the third insulating spacer may be oxidized or nitrided. In the non-volatile memory of the present invention, the memory cell line is formed by staggering a plurality of first ό 丨 cells and a second memory cell. Since there is no gap between the first cell and the second cell, and there is no gap between the selection unit and the second cell, the integration of the memory cell array can be improved. Moreover, each of the first memory cells and the second memory cells in the memory cell row can store charges, and thus can also increase the storage capacity. In addition, since the first memory cell and the second memory cell use the charge trapping layer as the charge storage unit, it is not necessary to consider the concept of the gate coupling ratio, and the same operating speed can be achieved with a lower operating voltage. The invention further provides a non-volatile memory, the non-volatile memory is at least a memory cell array, a plurality of selection units, a plurality of first doping regions, a plurality of second doping regions, and a plurality of word lines. , a plurality of strip lines, a plurality of strips, and a plurality of strips. Each read and cell line of the memory cell array includes a first memory cell and a plurality of second memory cells. A plurality of selection units are placed on one side of the memory cell array (4), wherein a plurality of selection units and a plurality of first memory cells in each memory cell row have a plurality of _, each _ two memory cells The plurality of first doped regions in the different gaps of the employee are respectively disposed in the base of each of the 1265604 14372-ltwf.doc/g two=亍, two of the memory cell array. A plurality of second doped regions are respectively set = select:: in the outer substrate. Most of the word lines and the majority of the bits ====:: the memory cell or the second memory cell. Most of the common lines are connected to ===, and the singles are selected. The gate 232 is in the form of a body, and each of the first memory cells is composed of a first composite dielectric layer disposed on the first side edge wall. The first one is below the first pole of the human and the composite dielectric thunder is surrounded by the first-bottom electrical layer, the first-charge trapping layer and the first-top two; the edge spacer is disposed on the sidewall of the first gate. : 2 below the second closed pole, the first 1 structure; 1 ^ complex = electrical layer setting layer, - second charge trapping layer and - "top" layer ^ - second bottom dielectric by the selection gate i A pair of first _= top (four) layers. Each of the selection units is a spacer disposed on a sidewall of the selection gate. Independence of a single brother in the above non-volatile memory - the material of the charge trapping layer can be nitrided. The first bottom is connected to the second electric layer, the second bottom dielectric layer and the first bottom, the electric layer, the second layer, and the second insulating interlayer; and the second insulating layer; Fossil eve. The material may be oxidized stone or nitrogen in a non-volatile recording dielectric layer as described above. This third resurrection eight:, choose early 兀 has a third complex, three complexes, and the sputum layer is placed under the selective gate, the first dielectric layer. Wherein, the third electricity; 3 is the material of the second electric charge trapping layer and the third electric input layer may be tantalum nitride. No. 1265604 14372-ltwf.doc/g The material of the two bottom dielectric layers and the third top dielectric layer may be yttrium oxide. In the above non-volatile memory, the first doped region is a di-type drain region, and the first doped region is an n-type drain region. Moreover, each of the drain regions is connected to one of the different bit lines. In the non-volatile memory of the description, the first gate of each of the first cells and the second gate of each of the first δ cells are respectively connected to one of different word lines. In the non-volatile memory described above, the second composite dielectric layer of the second memory cell is U-shaped in the smear and filled by the second gate of each of the second memory cells. In the non-volatile memory of the present invention, the memory cell row is formed by staggering a plurality of first, memory cells and second memory cells. Since there is no gap between the first memory cell and the first memory cell, and there is no _ between the selection unit and the second memory cell, the memory cell array degree 2 can be improved and the 'in the cell line Each of the first memory cells and the second memory cell can store charge, and thus can also increase the storage capacity. Further, since the first memory cell and the second memory cell use the charge trapping layer as the charge storage unit, the concept of the recoil ratio needs to be considered, and the same operating speed can be achieved with a lower operating voltage. The present invention further provides a non-volatile memory unit comprising at least a first memory cell, a selection cell, a second memory cell, a first insulating spacer, and a second insulating spacer. The first memory cell is placed on the substrate. The selection unit is disposed on the substrate, and the selection unit is isolated from the first three cells by a gap. The second memory cell is filled in this gap. The first 1265604 14372-ltwf.doc/g is separated from the second memory cell. The second insulation gap =; select: and the second, wherein the first memory cell includes the first - second gate: the second month t includes the brother - the gate - the third memory cell includes the third gate - the pole is used to turn on / Close the channel area below it. In the non-volatile memory unit, the second loyalty cell further includes a second closed pole in the zigzag layer. This U-shaped layer can be a charge trapping layer. Moreover, in addition, the U-shaped layer may be a composite medium; the material of the shaped layer may be a nitrided-through dielectric layer, a charge-trapped layer top; j, the composite dielectric layer may comprise a material that is oxygen-cut In the electric, the material of the dielectric layer that is worn with the dielectric layer may be oxygen cut. In the non-volatile memory unit described above, the 4-via dielectric layer and the first charge trap further comprise a first dielectric layer disposed on the substrate. Dielectric layer. The first layer is on the dielectric layer. The material of the first-top dielectric layer disposed on the first pass-through dielectric layer may be oxygen cut. Wherein in the above non-volatile memory cell, the charge is trapped in the layer. The virtual charge trapping layer is designed to be trapped in the layer and the first top dielectric layer. First wear = confession - charge: The charge trapping layer is disposed on the first pass-through _::== on the first charge trapping layer. The top dielectric layer of the above non-volatile fresh-keeping towel, the transfer order 4 includes a second 1265604 14372-ltwf.doc/g wear, a dielectric layer and a second top dielectric layer. The second pass-through dielectric layer is disposed between the dummy charge trapping layer and the substrate. The second top dielectric layer is disposed between the dummy charge sinking layer and the third gate. ...in the upper-like forwarding character +, the second memory cell further includes the u_sub-layer. The u-shaped layer can be a composite dielectric layer that includes at least a second charge trapping layer. Among them, the material of the second charge trapping layer may be nitride rock. Moreover, the u-shaped layer further includes a third top dielectric layer of the third dielectric interlayer. The third tunneling dielectric layer is disposed between the second charge trapping layer and the substrate. The second top dielectric layer is disposed on the second charge trapping layer and the second closed pole. The method for operating a non-volatile memory is applicable to the non-volatile memory (4) of the method. In operation, 0 volts is applied to the bit of the 疋, and a voltage is applied to the bit line of the non-敎 cell adjacent to the word line of the selected memory cell and applied to the word line. For the second voltage, a third voltage is applied to the other non-selective lines and the selection line, and the "four voltages" are applied to the source line to program the selected cells with the secret side effect. 3 3^1 In the method of forwarding (4), the first galvanic is about volts, the second ray is about 5 volts, the third voltage is about 9 volts, and the fourth voltage is about 4.5 volts. In the upper scaly, the reading method is used as a method towel, and the riding operation is applied to the position of the ^, and the G volt is applied to the position of the non-敎 ^ ^:=五霞, the memory of the 胞 敎 接 施加 施加 施加 施加Heart, light, apply a voltage of 1265604 14372-1 twf.doc/g to other non-敎 character lines and selection lines, and apply an eighth voltage to the source line to read the selected memory cells. In the above non-volatile memory operation method, the fifth voltage is about 1.5 volts, the sixth voltage is about 15 volts, the seventh voltage is about 6 volts, and the eighth voltage is about 1.5 volts. In the above non-volatile memory operation method, when performing the erase operation, a ninth voltage is applied to the selected bit line, and 0 volts is added to the unselected bit to 'select the memory cell. The character line is ten light, and is applied to all the fixed word lines between the character cell line and the bungee area of the selected memory cell, and the selection line is the eleventh electric two. All ------ volts between the word line and the source area. 3 _ left and right slant - voltage is 9 In the above non-volatile memory operation, the erase operation is performed on the word line, and a thirteenth voltage is erased by the _ substrate array. The tunnel should be inserted into the entire memory cell as the tree, the twelfth voltage volt is around, and the thirteenth voltage is volt. The twelfth voltage is about 〇, and the thirteenth voltage is 6 volts. Temple. The twelfth voltage is _6 volts in the operation method towel of the present invention, which uses a 1265604 14372-ltwf.doc/g source side injection effect (S〇urce-Side Injection, SSI) as a single memory. The single cell of the cell is programmed in units, and the memory cell is erased by the thermoelectric hole injection effect or the FN tunneling effect. Therefore, the electron injection efficiency is so good that it can reduce the memory current during operation and at the same time improve the operation speed. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire wafer. The present invention further provides a method of fabricating a non-volatile memory by first providing a substrate and forming a plurality of stacked gate structures on the substrate. The stacked gate structures each include a first composite dielectric layer, a first gate and a cap layer, and a gap between adjacent stacked gate structures. Then, insulating spacers are respectively formed on the sidewalls of the stacked gate structure, and a second composite dielectric layer is formed on the substrate. Then, a conductor layer is formed on the substrate, and the conductor layer is removed to form a plurality of second gates filling the gap between the stacked gate structures, and the second gate and the stacked gate structure are formed Memory cell line. Thereafter, in the manufacturing method of the non-volatile memory in which the base tissue on both sides of the memory cell line forms a secret region and is infiltrated, the first composite composite dielectric layer includes a bottom dielectric layer and a charge trapping layer method. . In ^ Guang I. The method of removing a portion of the conductor layer includes chemical mechanical polishing; the method of forming the source region and the drain region in the soil & includes ion implantation. In the manufacturing method of the non-volatile memory in the stack, since the second composite dielectric layer and the conductor layer are filled in between, the polar structure is not required. Because of the ί ί, it is easier to make another gate between the stacked gate structures and reduce the cost. In addition, the non-volatile memory of the invention of 1265604 143 72-1 twf.doc/g uses the charge trapping layer as the charge storage unit. Therefore, it is necessary to consider the concept of the interpole madness ratio, and the T reduction operation is required. The working voltage, and improve the operating efficiency of the memory cell. In addition, the steps of the present invention are simpler than the conventional processes, and thus the manufacturing cost can be reduced. The above and other objects, features, and advantages of the present invention will become more apparent from the understanding of the appended claims. [Embodiment] Fig. 1A is a top view showing a preferred embodiment of a nonvolatile memory of the present invention. Fig. 1B is a cross-sectional view showing the structure of the line along the line α·Α in Fig. ία. Fig. 1C is a cross-sectional view showing the structure of a memory unit and a selection unit of the present invention. Referring to FIG. 1A, FIG. 1A and FIG. 1C simultaneously, the non-volatile memory structure of the present invention is at least composed of a substrate 100, an element isolation structure 1, an active area 104, a plurality of memory units, and a selection unit. 6. The drain region # should be composed of (doped region) and source region 110 (doped region). The substrate 100 is, for example, a ruthenium substrate, and the substrate 100 may be a p-type substrate or a ruthenium-type substrate. The element isolation structure 1 〇 2 is disposed in the substrate 1 , to define the active region 104. A plurality of memory cells Q1 to Qn are disposed on the substrate 100. Each of the memory cells Q1 to Qn is composed of a memory cell H2 and a memory cell ι14. The memory cell 112 is disposed on the substrate 1B, which is composed of, for example, a composite dielectric layer 116, a gate 118, and a cap layer 120. The gate 118 is disposed on the base 15 1265604 14372-ltwf.doc/g. The bottom H) 〇 h composite dielectric layer 116 is disposed between. The composite dielectric layer 116 has a charge-trapping layer (10) and a top dielectric layer 116a, which are sequentially the bottom dielectric layer 116a, n 11Q u b and the dielectric layer 116c. The top cover layer 120 is disposed on the gate L _122 ^ placed on the _18 and the composite dielectric layer: \ material _ such as nitrided hair; the top dielectric layer 116c of the gate 118 material is, for example, doped polycrystalline Shi Xi. The material of the shell layer 120 is, for example, an oxidized stone. The material of the insulating spacer 122 includes an insulating material such as tantalum nitride or tantalum oxide.
記憶胞114設置於記憶胞112 一側之侧壁與基底⑽ 上，其例如是由複合介電層124與閘極126所構成。問極 126設置於基底100上。複合介電層m設置於間極以 與基底100之間及閘極126與記憶胞112之間。複合介電 層124從基底1〇〇與記憶胞112 一侧之侧壁起依序:底^ 電層124a、電荷陷入層i24b與頂介電層124C。其中，底 介電層124a之材質例如是氧化矽；電荷陷入層12牝之材 質例如是氮化矽；頂介電層124c之材質例如是氧化矽；閘 極126之材質例如是摻雜多晶矽。記憶胞114係透過絕緣 間隙壁122與記憶胞112相間隔。 、 記憶單元Q1〜Qn例如是在主動區1〇4上串聯成一記情 胞行128，且記憶胞112與記憶胞114交錯排列，彼此^ 無間隙。記憶胞行128中之記憶胞112與記憶胞U4彼此 以絕緣間隙壁122相隔離。在記憶胞行128之間彼此以元 件隔離結構102相隔離。 1265604 14372-1 twf.doc/g 選擇單元106與記憶胞行128中最外侧之記憶胞114 相連接’其例如是由複合介電層130、閘極132、頂蓋層 —I34 ^絕緣間隙壁136所構成。閘極132設置於基底1〇〇 ^。複合介電層130設置於閘極132與基底1〇〇之間。此 1合介電層130從基底100起依序為底介電層13〇a、電荷 P曰入層130b與頂介電層13〇c。頂蓋層134設置於閘極132 上。絕緣間隙壁136設置於閘極132與複合介電層13〇之 # 側土其中，底介電層130a之材質例如是氧化石夕；電荷陷 入層130b之材質例如是氮化矽；頂介電層^㈦之材質例 如是氧化矽；閘極132之材質例如是摻雜多晶矽。頂蓋層 ^4之材質例如是氧化矽。絕緣間隙壁136之材質例如是 氮化f或氧化矽。選擇單元1〇6與記憶胞行128中最外侧 之胞114係透過絕緣間隙壁136相間隔。選擇單元1〇6 中的電荷陷入層1通，並不作為儲存電荷之用，因此電荷 1¾入層130b係為虛擬的電荷陷入層。 此外’各圮憶單元Q1〜Qn中的各個記憶胞114例如是 零分別設置於相鄰兩記憶胞112之間的間隙以及選擇單元 _與記憶單元φ之記憶胞112之間的間隙。而且，記憶 胞114分別填入不同的各間隙中。記憶胞ιΐ4的的複合介 電層例如為u-字形層，此u-字形層支擇間隙中的閘極1；26。 “汲極區108(摻雜區)例如是設置於選擇單元106不與 把憶胞行128相鄰-侧之基底_中。源極區11〇(摻雜區) 例如是設置於歧髓1G8相對應之另__基底謂 中，亦即記憶胞行128最外側之記憶胞112 一侧之基底1〇〇 17 1265604 14372-ltwfdoc/g 中。其中，汲極區1G8與源極區UG例如^型摻雜區。 此外，汲極區108藉由插塞138連接至位元線140。 源極區110則電性連接至源極線142。The memory cell 114 is disposed on the sidewall of the memory cell 112 side and the substrate (10), which is composed of, for example, a composite dielectric layer 124 and a gate 126. The question electrode 126 is disposed on the substrate 100. A composite dielectric layer m is disposed between the interpoles and the substrate 100 and between the gates 126 and the memory cells 112. The composite dielectric layer 124 is sequentially from the side walls of the substrate 1 and the memory cell 112 side: the bottom layer 124a, the charge trapping layer i24b, and the top dielectric layer 124C. The material of the bottom dielectric layer 124a is, for example, tantalum oxide; the material of the charge trap layer 12 is, for example, tantalum nitride; the material of the top dielectric layer 124c is, for example, tantalum oxide; and the material of the gate 126 is, for example, doped polysilicon. The memory cell 114 is spaced apart from the memory cell 112 by an insulating spacer 122. For example, the memory cells Q1 QQn are connected in series to the cell row 128 in the active region 1〇4, and the memory cells 112 and the memory cells 114 are staggered, and there is no gap between them. The memory cell 112 and the memory cell U4 in the memory cell row 128 are isolated from each other by an insulating spacer 122. The memory cell rows 128 are isolated from each other by the element isolation structure 102. 1265604 14372-1 twf.doc/g The selection unit 106 is connected to the outermost memory cell 114 of the memory cell row 128. It is, for example, composed of a composite dielectric layer 130, a gate 132, a cap layer, and an I34^ insulating spacer. 136 constitutes. The gate 132 is disposed on the substrate 1〇〇. The composite dielectric layer 130 is disposed between the gate 132 and the substrate 1〇〇. The 1-dielectric layer 130 is sequentially provided from the substrate 100 as a bottom dielectric layer 13A, a charge P-into layer 130b and a top dielectric layer 13A. The cap layer 134 is disposed on the gate 132. The insulating spacer 136 is disposed on the side of the gate 132 and the composite dielectric layer 13 , wherein the material of the bottom dielectric layer 130 a is, for example, oxidized oxide; the material of the charge trapping layer 130 b is, for example, tantalum nitride; The material of the layer (7) is, for example, ruthenium oxide; the material of the gate 132 is, for example, doped polysilicon. The material of the top cover layer ^4 is, for example, yttrium oxide. The material of the insulating spacer 136 is, for example, nitrided f or yttrium oxide. The selection unit 1〇6 is spaced apart from the outermost cell 114 of the memory cell row 128 by an insulating spacer 136. The charge trapping layer 1 in the selection cell 1〇6 is not used as a storage charge, so the charge layer 130b is a virtual charge trapping layer. Further, each of the memory cells 114 in the respective memory cells Q1 to Qn is, for example, a gap which is set between the adjacent two memory cells 112 and a gap between the selection cell _ and the memory cell 112 of the memory cell φ. Moreover, the memory cells 114 are filled into different gaps, respectively. The composite dielectric layer of the memory cell ΐ4 is, for example, a u-shaped layer which supports the gate 1; 26 in the gap. The "drain region 108 (doped region) is, for example, disposed in the substrate _ which is not adjacent to the side of the cell 128. The source region 11 掺杂 (doped region) is, for example, disposed on the nucleus 1G8 Corresponding to the other __base, that is, the memory cell 112 on the outermost side of the memory cell 112 side of the substrate 1 〇〇 17 1265604 14372-ltwfdoc / g. Among them, the bungee region 1G8 and the source region UG, for example In addition, the drain region 108 is connected to the bit line 140 by a plug 138. The source region 110 is electrically connected to the source line 142.
在上述非揮發性記憶體中，主動區104上之記憶胞行 128疋由多數個記憶胞112及記憶胞114《錯排列而成。 由於在記憶胞112與記錄114之間並沒有_，且選擇 單元106與記憶胞114之間也沒有間隙，因此可以提升記 憶胞陣狀積集度。而且，在記憶胞行128巾的各個記憶 胞112及記憶胞114都可以儲存電荷，因此也可以提升儲 存容量。 此外，由於記憶胞112及記憶胞114是使用電荷陷入 層110作為電荷儲存單元，因此不需要考慮間極輕合率的 概念’而降低操作所需之王作電壓，而提升記憶胞的操作 效率。In the above non-volatile memory, the memory cell line 128 on the active area 104 is "arranged by a plurality of memory cells 112 and memory cells 114". Since there is no _ between the memory cell 112 and the record 114, and there is no gap between the selection unit 106 and the memory cell 114, the memory cell-like accumulation can be improved. Moreover, each of the memory cells 112 and the memory cells 114 of the memory cell 128 can store charges, so that the memory capacity can also be improved. In addition, since the memory cell 112 and the memory cell 114 use the charge trapping layer 110 as a charge storage unit, there is no need to consider the concept of the inter-polarity ratio, and the operating voltage required for operation is lowered, thereby improving the operational efficiency of the memory cell. .
另外，本發明中串接的記憶胞結構的數目，可以視實 際需要而串接適當的數目，舉例來說，同-記憶胞行^ 可以串接32至64個記憶胞結構。 圖2所纷示為本發明之非揮發性記憶體之一較佳實施 例的電路簡圖，以說明本發明之非揮發性記憶體的操作模 式。圖3A為本發明之程式化操作之一實例的示意圖。圖 3B為本發明之讀取操作之一實例的示意圖。圖3c為用以 說明讀取記憶胞時所產生之一現象的示意圖。圖3D為本 發明之抹除操作之一實例的示意圖。圖3E為本發明之抹 除操作之再一實例的示意圖。圖3F為本發明之抹除操作 1265604 14372-ltwf.doc/g 之另一實例的示意圖。圖3G為本發明之抹除操作之又一 實例的示意圖。 請參照圖2,非揮發性記憶體包括多數個記憶胞 Mil〜M3n、多數個選擇單元ST1〜ST3、選擇線SG、字元 線WL1〜WLn、位元線BL1〜BL3、源極線SL(共用線）。 多數個記憶胞Mil〜M3n設置於基底上，排列成一行/ 列陣列，同一行之記憶胞彼此無間隙的串聯連接成一記憶 胞行。舉例來說，記憶胞Mil、M12、M13…Min構成一 個記憶胞行；記憶胞M21、M22、M23…M2n構成一個記 憶胞行；記憶胞M31、M32、M33…M3n構成一個記憶胞 行。 多數個選擇單元ST1〜ST3分別與各記憶胞行的一側 之最外侧的記憶胞相連接。舉例來說，選擇單元ST1連接 έ己板、胞Mil，選擇單元ST2連接記憶胞M21 ;選擇單元 ST3連接記憶胞M31。選擇線SG連接同一列之選擇單元 ST1〜ST3之閘極。 多數條子元線WL1〜WLn在列方向平行排列，連接 同一列之記憶胞之閘極。舉例來說，字元線WL1連接記 fe胞Mil、M21、M31之閘極；WL2連接記憶胞M12、 M22、M32之閘極：以此類推，WLn連接記憶胞Mln、 M2n、M3n之閘極。 多數條位元線BL1〜BL3在行方向平行排列，連接同 一行之汲極區，汲極區設置於各個選擇單元ST1〜ST3 一侧 之基底中。字元線WL1〜WLn與位元線BL1〜BL3的每 1265604 14372-ltwf.doc/g 一交錯點對應至不同的記憶胞Mil〜M3n。 源極線SL連接同一列之源極區，源極區設置於各記 憶胞行的另一側之基底中。在記憶胞行中，以相鄰之兩個 記憶胞為記憶單元Q，舉例來說，記憶胞Mil、M12構成 一記憶單元；記憶胞M13、M14構成一記憶單元；依此類 推，記憶胞M3(n-1)、M3n構成一記憶單元。 請同時參照圖2及圖3A，在進行程式化操作時，以記In addition, the number of memory cell structures connected in series in the present invention may be connected in series according to actual needs. For example, the same-memory cell line may be connected in series to 32 to 64 memory cell structures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 2 is a schematic circuit diagram of a preferred embodiment of a non-volatile memory of the present invention to illustrate the mode of operation of the non-volatile memory of the present invention. 3A is a schematic diagram of an example of a stylized operation of the present invention. Figure 3B is a schematic illustration of one example of a read operation of the present invention. Fig. 3c is a schematic view for explaining a phenomenon which occurs when a memory cell is read. Fig. 3D is a schematic view showing an example of the erasing operation of the present invention. Fig. 3E is a schematic view showing still another example of the erasing operation of the present invention. Figure 3F is a schematic illustration of another example of an erase operation 1265604 14372-ltwf.doc/g of the present invention. Fig. 3G is a schematic view showing still another example of the erasing operation of the present invention. Referring to FIG. 2, the non-volatile memory includes a plurality of memory cells Mil to M3n, a plurality of selection cells ST1 to ST3, a selection line SG, word lines WL1 to WLn, bit lines BL1 to BL3, and source lines SL ( Shared line). A plurality of memory cells, Mil~M3n, are disposed on the substrate and arranged in a row/column array, and the memory cells of the same row are connected in series with each other without gaps to form a memory cell row. For example, the memory cells Mil, M12, M13...Min constitute a memory cell line; the memory cells M21, M22, M23...M2n constitute a memory cell line; the memory cells M31, M32, M33...M3n constitute a memory cell line. The plurality of selection units ST1 to ST3 are respectively connected to the outermost memory cells on one side of each of the memory cell lines. For example, the selection unit ST1 is connected to the 板 board, the cell Mil, the selection unit ST2 is connected to the memory cell M21, and the selection unit ST3 is connected to the memory cell M31. The selection line SG is connected to the gates of the selection units ST1 to ST3 of the same column. The plurality of strip element lines WL1 WLWLn are arranged in parallel in the column direction to connect the gates of the memory cells of the same column. For example, the word line WL1 is connected to the gates of the cells Mi, M21, and M31; the gate of the WL2 is connected to the memory cells M12, M22, and M32: and so on, and the gate of the WLn is connected to the memory cells Mln, M2n, and M3n. . The plurality of bit lines BL1 to BL3 are arranged in parallel in the row direction, and are connected to the drain regions of the same row, and the drain regions are disposed in the substrate on the side of each of the selection units ST1 to ST3. The word lines WL1 to WLn and the bit lines BL1 to BL3 each correspond to a different memory cell Mil to M3n. The source line SL is connected to the source regions of the same column, and the source regions are disposed in the substrate on the other side of each of the memory cells. In the memory cell line, the two adjacent memory cells are the memory unit Q. For example, the memory cells Mil and M12 constitute a memory unit; the memory cells M13 and M14 constitute a memory unit; and so on, the memory cell M3 (n-1) and M3n constitute a memory unit. Please refer to FIG. 2 and FIG. 3A at the same time, in the case of stylizing operation,
憶胞M24為例做說明，於選定之位元線bl2施加〇伏特 左右之電壓，於非選定之位元線BL1、BL3施加3.3伏特 左右之電壓；於與選定之記憶胞M24所耦接之字元線WL4 相鄰、且靠近汲極區D的選定之字元線WL3上施加15 伏特左右之電壓，於其他非選定之字元線WL1、WL2、 WL4〜WLn及選擇線SG上施加9伏特左右之電壓，於源 極線SL施加4.5伏特左右之電壓，以利用源極側注入效應 (SourCe_Side Injection，SSI)使電子注入記憶胞搬4之電荷 陷入層中，以程式化選定之記憶胞聰。在記憶胞圓 的電荷陷人層中存人的電子係位於靠近汲極區⑽局部位 置0 在本务月之操作方法中，對選定之記憶胞進行程式化 :、=?選定之記憶胞、結近汲極區的另-記憶胞係作 =早70之用’使電子注人該選定之記憶胞。亦即要程 ^化記憶胞购時’記⑽购係作為選 Π擇單M23)n使奸注入選定 5己憶胞黯的靠奴㈣D之電荷陷人層巾。在本發明 20 1265604 14372-ltwf.doc/g 之非揮發性記憶體中’除了最靠近源極區s之記憶胞 Min、M2n、M3n只單純作為記憶胞之外，其他之記 可作為圮憶胞或選擇單元(選擇閘極)之用。 清同時參照圖2及圖3B，在進行讀取操作時，以記憶 胞M24為例做說明，於選定之位元線犯施加〇伏特左 右電壓，於非選定之位元線Bu、Bu施加15伏特左右 φ 之電壓’於選定之記憶胞M24所輕接之字元線WU施加 1.5伏特左右之電壓，於其他非選定之字元線wli〜 WL3 WL5〜WLn及通擇線SG上施力口 6伏特左右之電壓， 於源極線SL施加1·5伏特左右之電壓，以讀取選定之記憶 胞Μ24。由於此時電荷陷入層中總電荷量為負的記憶胞的 通道關閉且電流很小，而電荷陷入層中總電荷量略正的記 憶胞的通道打’電流大，故可藉由記憶胞之通道開關/ 通道電流大小來判斷儲存於此記憶胞中的數位資訊是Γι 還是「0」。 、。 」 • 另外，如圖3C所示，若記憶胞Μ25在程式化時，有 部分電子陷入記憶胞Μ24的電荷陷入層中靠近源極區s 的局部位置’而對記憶胞M24造成干擾。然而，本發明之 讀取方法’在讀取記憶胞M24時，可藉由施加的15伏特 左右之電壓形成缺乏區(depletion)，而將對記憶胞M24造 成干擾之電子遮擋住，可避免讀取記憶胞M24時的誤判。 請同時參照圖2及圖3D，在進行抹除操作時，於選定 之位7〇線BL2施加4.5伏特左右之電壓，於非選定之位元 21The memory cell M24 is taken as an example. A voltage of about volts is applied to the selected bit line bl2, and a voltage of about 3.3 volts is applied to the unselected bit lines BL1 and BL3; and coupled to the selected memory cell M24. A voltage of about 15 volts is applied to the selected word line WL3 adjacent to the word line WL4 and adjacent to the drain region D, and is applied to the other unselected word lines WL1, WL2, WL4 WLWLn and the selection line SG. A voltage of about volts is applied to the source line SL to apply a voltage of about 4.5 volts to the source line SL, so that the charge injected into the memory cell by the SourCe_Side Injection (SSI) is trapped in the layer to program the selected memory cell. Cong. The electron system stored in the charge trap layer of the memory cell is located close to the local position of the drain region (10). In the operation method of the current month, the selected memory cell is programmed: == selected memory cell, The other-memory cell line that is close to the bungee area is used as the '70' to make the selected memory cell. That is to say, when the memory is purchased, the memory is purchased (10), and the purchase is selected as the selection list. M23) n is used to inject the selected 5th memory of the slave (4) D. In the non-volatile memory of the invention 20 1265604 14372-ltwf.doc/g, except for the memory cells Min, M2n, and M3n closest to the source region s, which are simply used as memory cells, other records can be used as memory. Cell or selection unit (select gate). Referring to FIG. 2 and FIG. 3B simultaneously, in the case of performing a read operation, the memory cell M24 is taken as an example for description, and the left and right voltages of the volts are applied to the selected bit lines, and the unselected bit lines Bu and Bu are applied. The voltage of φ around volts applies a voltage of about 1.5 volts to the word line WU that is lightly connected to the selected memory cell M24, and applies force to other unselected word lines wli~WL3 WL5~WLn and the selection line SG. A voltage of about 6 volts is applied to the source line SL to apply a voltage of about 1. 5 volts to read the selected memory cell 24. Since the channel of the memory cell in which the total charge amount is negative in the charge trapping layer is closed and the current is small, and the channel of the memory cell in which the total charge amount in the charge trapping layer is slightly positive, the current is large, so it can be used by the memory cell. The channel switch / channel current size determines whether the digital information stored in this memory cell is Γι or "0". ,. • In addition, as shown in Fig. 3C, if the memory cell 25 is programmed, some of the electrons are trapped in the charge trapping layer of the memory cell 24, which is close to the local region s of the source region s, causing interference to the memory cell M24. However, the reading method of the present invention can form a depletion by applying a voltage of about 15 volts when reading the memory cell M24, and block the electrons that interfere with the memory cell M24, thereby avoiding reading. The misjudgment when taking memory cell M24. Referring to FIG. 2 and FIG. 3D simultaneously, when the erase operation is performed, a voltage of about 4.5 volts is applied to the selected bit line BL2 to the unselected bit 21
請同時參照圖2及圖3E，在進行抹除操作時，於所肩 子讀WU〜WLn上施加]2伏特左右之電壓，於基底勒 加〇伏特左右之電壓，以利用負閘極電壓F 庫 行整個記憶料狀抹除。 請同時參照圖2及圖3F，在進行抹除 字元線WL1〜WLn上施加〇伏特左右之電壓，於基g 井區)施加12伏特左右之電壓，以利用通道f_ 文 進行整個記憶胞陣列之抹除。 随放應 7同時參照圖2及圖3G，在進行抹 字元線WL1〜WLn上施加_6伏特左右 區=加6雌左右之輕，以_ F_ ’ 記憶胞陣列之抹除。 1265604 143 72-1 twf.doc/g 線BL1、BL3施加〇伏特左右之電壓，於選定之記憶胞 M24所麵接之字元線WL4施加_5伏特左右之電壓，於選 定之記憶胞M24所耦接之字元線WL4與汲極區D之間的 所有非選定之字元線WU〜WL3、選擇線SG上施加9伏 特左右之電壓，於選定之記憶胞M24所耦接之字元線 與源極區s之間的所有非選定之字元線WL5〜WLn上施 加〇伏特左右之電壓，使電洞注入電荷陷入層中，以利用 熱電洞注入效應抹除選定之記憶胞M24。 、在上述操作方法中，係以利用熱電洞注入效應以抹除 遠疋之記憶胞為例作制，當穌發明也可靖由於閉極 與基底之間形成-個電壓差，使電子由記憶胞之電荷陷入 層拉至基底中，· F_N穿遂效應抹除記憶胞。 22 1265604 14372-ltwf.doc/g 在上述的利用F-N穿隧效應進行抹除的例子中，以直 接於基底中施加12伏特左右之電壓的方式較為省電。但 ’ 疋，欲於基底中施加電壓，則必須在基底中形成一個井區。 在本發明之非揮發性記憶體之操作方法中，其係利用 源極側注入效應(S〇urce-Side Injection，SSI)以單一記憶胞 之單一位元為單位進行程式化，並利用熱電洞注入效應或 F_N牙隨效應進行記憶胞之抹除。因此，其電子注入效率 φ 較高，故可以降低操作時之記憶胞電流，並同時能提高操 作速度。因此，電流消耗小，可有效降低整個晶片之功 損耗。 接著說明本發明之非揮發性記憶體之製造方法，圖4八 至圖4E為繪示圖2A中沿A-A，線之製造流程剖面圖。 首先，請參照圖4A，提供一基底200，基底2〇〇例如 是矽基底/在此基底200中已形成有元件隔離結構(未圖 示）。接著，在基底200上形成多數個堆疊閘極結構202。 堆疊閘極結構202是由複合介電層204、導體層2〇6(閘 _ 極）、頂盍層208所構成。閘極堆疊結構202之形成方法例 如是依序於基底1〇〇上形成複合介電材料層、導體材料 層、絕緣材料層後，利用微影蝕刻技術圖案化上述材犀 而形成之。 θ 複合介電層204例如是由底介電層2〇4a、電荷陷入層 2〇4b、頂介電層204c所構成。底介電層2〇如之材質例= 是氧化矽，其形成方法例如是熱氧化法。電荷陷入層2〇4b 之材質例如是氮化矽，其形成方法例如是化學氣相沈積 23 1265604 14372-ltwf.d〇c/s 法。頂介電層職之材質例如是氧化秒，其形成方法例如 是化學氣相沈積法。當然，底介電層2〇4a及頂介電層2〇4c 也y以料他_的材質。電荷陷人層綱b之㈣並不限 於氮化秒’也可以是其他能夠使電荷陷人於其巾之材質， 例如纽氧化層、欽酸销層與給氧化層等。 導體層206之材質例如是摻雜的多晶石夕，此導體層2〇6 之形成方法例如是_化學氣相沈積法形成—層未換雜多 晶矽層後，進行離子植入步驟以形成之。 頂蓋層208之材質例如是氧化石夕，頂蓋層·之形成 方法例如是以四-乙基♦矽酸_以e_ 0— 二=ate ’ TEQS)/臭氧(〇3)為反應氣體源，利用化學氣相沈 積法而形成之。 接著’請參照圖4B，於各個堆疊閘極結構2〇2之侧壁 =成絕緣_壁21G。絕緣_壁21()之形成方法例如是 形成-層絕緣材料層後，進行自行對準非等向性侧势 只留下位於間極結構2〇2側壁的絕緣材料層。絕緣 間隙壁210之材質例如是氮化矽。 然後’於基底200上形成另一層複合介電層212。複 =電層212例如是由底介電層心、電荷陷入層鳩、 層212e所構成。底介電層之材f例如是氧化 夕八形成方法例如是熱氧化法。電荷陷入層21汍之 ^疋氮化々其形成方法例如是化學氣相沈積法。頂介 電曰212e讀_如是氧切，其形成方 學 相沈積法。當然，底介電層心及頂介電層心也= 24 1265604 143 72-1 twf.doc/g 疋其他類似的材質。電荷陷入層21沘之材質並不限於氮化 ，’也可以是其他能夠使電荷陷入於其中之材質，例如钽 - 氧化層、欽酸錄層與給氧化層等。 接著，於基底200上形成另一層導體層214，其中導 體層214填滿相鄰兩堆疊閘極結構2〇2之間的間隙。導體 層214之材質例如是摻雜的多晶矽，此導體層214之形成 /方法例如是利用化學氣相沈積法形成—層未摻雜多晶石夕層 .後，進行離子植入步驟以形成之。 #接著’請參照圖4C，移除部分導體層214直到暴露出 頂盍層208，而於堆疊閘極結構2〇2之間形成導體層 214a(閘極）。導體層214a將多數個堆疊閘極結構2〇2串聯 起來。移除部分導體層2H之方法例如是回钱刻法或化學 機械研磨法。導體層214a與複合介電層212構成另一種閘 極結構。值得注意的是，為了降低導體層214a之阻值，亦 可以在導體層214a之表面形成一層金屬矽化物。 然後，於基底200上形成一層圖案化之罩幕層216， > 暴露出後續欲形成源極區/汲極區的區域。接著，進行一蝕 刻製程，移除欲形成源極區/汲極區之區域上殘留之導體層 214及複合介電層212。 曰 之後，以罩幕層216為罩幕，進行一摻質植入步驟， 而於基底200中形成源極區218與汲極區22〇。源極區218 與汲極區220係位於串聯連接之堆疊閘極結構2〇2與導體 層214a兩側的基底2〇〇中。 接著’請參照圖4D ’於基底200上形成一層内層介電 25 1265604 14372-1 twf.doc/g 層222。此内層介電層222之材質例如是氧化石夕，其形成 方法例如是化學氣相沈積法。然後，於此内層介電層222 中形成與源極區218電性連接的源極線224。源極線224 之材質例如是鎢金屬。 之後’請參照圖4E ’於基底2〇〇上形成另一層内層介 電層226。於此内層介電層226中形成與汲極區22〇電性 連接的插塞228，並於内層介電層226上形成與插塞挪 =性連接的導線23G(位元線)。後續完成非揮發性記憶體之 製程為熟悉此項技術者所週知，在此不再贅述。 f上述實施例中’由於採用於堆疊閘極結構搬之間 支、入複合介電層212及導體層214a，不需要微影蝴 =於堆疊閘極結構搬之間製作出另一種閘極結構。因 =衣妹為簡單’且可以減少成本。此外，本發明之非 =記憶體’使用電荷陷入層綱b、電荷陷入層⑽作 ==存單元，因此不需要考慮閉_合率的概念，而 ，低，作所需之工作電壓，而提升記憶胞的操作效率。而 較為^明形成轉發性記憶體之步驟與習知的製程相比 孕乂為間早，因此可以減少製造成本。 外’在上述實施财，係卿紅個峨胞結構為 ^見ί二Γ，使用本發明之記憶胞行之製造方法， 一:際㊉要而形成適當的數目記憶胞，舉例來說 记憶胞行可以串接32至64個 ° 明之非揮發性記付的#方本=胞、-構。而且’本發 個記憶胞陣k方法，實際上是應用於形成整 26 1265604 14372-ltwf.doc/g —雖然本發明已以較佳實施例揭露如上，然其並非用以 限^本發明，任何熟習此技藝者，在不脫離本發明之精神 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 ^ 【圖式簡單說明】 圖1A為繪示本發明之非揮發性記憶體之上視圖。 圖1B為繪示圖1A中沿A_A，線之結構剖面圖。 面圖圖1C轉林發明之記鮮元及麟單元之結構剖 …圖2崎示為本發明之非揮發性記憶體的電路簡圖， 以》兒明本發明之非揮發性記憶體的操作模式。 圖3A為本發明之程式化操作之一實例的示意圖。 圖3B為本發明之讀取操作之一實例的示意圖。 圖3C為用以說明讀取記憶胞時所產生之—現象的示 思、圖。 圖3D為本發明之抹除操作之一實例的示意圖。 圖3E為本發明之抹除操作之再—實例的示意圖。 圖3F為本發明之抹除操作之另—實例的示意圖。 圖3G為本發明之抹除操作之又一實例的示意圖。 流程=至圖4E為緣示本發明之非揮發性記憶體之製造 【主要元件符號說明】 100、200 :基底 102 :元件隔離結構 27 1265604 14372-ltwf.doc/g 104 :主動區 106 :選擇單元 _ 108、220、D :汲極區 110、218、S :源極區 • 112、114 :記憶胞 116、124、130、204、212 :複合介電層 116a、124a、130a、204a、212a :底介電層 116b、124b、130b、204b、212b ··電荷陷入層 ® 116c、124c、130c、204c、212c :頂介電層 118、126、132 :閘極 120、134、208 :頂蓋層 122、136、210 :絕緣間隙壁 128 :記憶胞行 138、228 :插塞 140、230 ··位元線 142、224 :源極線 • 202 :堆疊閘極結構 206、214、214a :導體層 BL1〜BL3 ··位元線 Mil〜M3n :記憶胞 Q、Q1〜Qn :記憶單元 ST1〜ST3 :選擇單元 SG :選擇線 WL1〜WLn :字元線 28Referring to FIG. 2 and FIG. 3E simultaneously, when performing the erasing operation, a voltage of about 2 volts is applied to the shoulder readings WU to WLn, and a voltage of about volts is applied to the substrate to utilize the negative gate voltage F. The entire line of memory is erased. Referring to FIG. 2 and FIG. 3F simultaneously, a voltage of about volts is applied to the erase word lines WL1 WLWLn, and a voltage of about 12 volts is applied to the base g well region to perform the entire memory cell array using the channel f_ text. Wipe it off. Referring to Fig. 2 and Fig. 3G simultaneously, about _6 volts is applied to the erase word lines WL1 to WLn, and the light is applied to the _F_' memory cell array. 1265604 143 72-1 twf.doc/g Lines BL1, BL3 apply a voltage of about volts, and a voltage of about _5 volts is applied to the word line WL4 that is connected to the selected memory cell M24, in the selected memory cell M24. A voltage of about 9 volts is applied to all unselected word lines WU to WL3 between the coupled word line WL4 and the drain region D, and a word line coupled to the selected memory cell M24 is applied. A voltage of about volts is applied to all of the unselected word lines WL5 WLWLn between the source regions s, and the holes are injected into the charge trapping layer to erase the selected memory cells M24 by the hot hole injection effect. In the above operation method, the method of using the thermoelectric hole injection effect to erase the memory cell of the distant view is taken as an example, and when the invention is also formed, the electron is formed by the memory due to the formation of a voltage difference between the closed electrode and the substrate. The charge of the cell is pulled into the substrate, and the F_N piercing effect erases the memory cell. 22 1265604 14372-ltwf.doc/g In the above example of erasing by the F-N tunneling effect, power is applied in such a manner that a voltage of about 12 volts is applied directly to the substrate. However, 疋, in order to apply a voltage to the substrate, a well region must be formed in the substrate. In the method for operating a non-volatile memory of the present invention, it uses a source-side injection effect (SSI) to program a single bit unit of a single memory cell, and utilizes a thermoelectric hole. The injection effect or the F_N tooth is erased by the memory cell with the effect. Therefore, the electron injection efficiency φ is high, so that the memory cell current during operation can be reduced, and at the same time, the operation speed can be improved. Therefore, the current consumption is small, which can effectively reduce the power loss of the entire wafer. Next, a method of manufacturing the non-volatile memory of the present invention will be described. Figs. 4A to 4E are cross-sectional views showing the manufacturing process of the line along A-A in Fig. 2A. First, referring to Fig. 4A, a substrate 200 is provided. The substrate 2 is, for example, a germanium substrate/in which an element isolation structure (not shown) has been formed. Next, a plurality of stacked gate structures 202 are formed on the substrate 200. The stacked gate structure 202 is composed of a composite dielectric layer 204, a conductor layer 2〇6 (gate), and a top layer 208. The gate stack structure 202 is formed by, for example, forming a composite dielectric material layer, a conductor material layer, and an insulating material layer on the substrate 1 and then patterning the material rhinoceros by a photolithography technique. The θ composite dielectric layer 204 is composed of, for example, a bottom dielectric layer 2〇4a, a charge trapping layer 2〇4b, and a top dielectric layer 204c. The material of the bottom dielectric layer 2 is, for example, yttrium oxide, and the formation method thereof is, for example, a thermal oxidation method. The material of the charge trapping layer 2〇4b is, for example, tantalum nitride, which is formed by, for example, chemical vapor deposition 23 1265604 14372-ltwf.d〇c/s method. The material of the top dielectric layer is, for example, oxidized seconds, and its formation method is, for example, chemical vapor deposition. Of course, the bottom dielectric layer 2〇4a and the top dielectric layer 2〇4c are also made of the material of the material. The charge trapping layer b (4) is not limited to the nitriding second', and may be other materials capable of trapping the charge in the towel, such as a neo-oxide layer, a pin acid layer, and an oxide layer. The material of the conductor layer 206 is, for example, a doped polycrystalline stone. The method for forming the conductor layer 2〇6 is, for example, a chemical vapor deposition method to form a layer of unsubstituted polysilicon layer, and then performing an ion implantation step to form a layer. . The material of the top cover layer 208 is, for example, oxidized stone, and the method for forming the top cover layer is, for example, tetra-ethyl ♦ decanoic acid _ with e_ 0 - two = ate ' TEQS) / ozone (〇 3) as a reaction gas source , formed by chemical vapor deposition. Next, please refer to FIG. 4B, and the sidewalls of the respective stacked gate structures 2〇2 are insulated to the wall 21G. The insulating_wall 21() is formed by, for example, forming a layer of insulating material, and then self-aligning the anisotropic side leaving only the insulating material layer on the sidewall of the interpole structure 2〇2. The material of the insulating spacer 210 is, for example, tantalum nitride. Another layer of composite dielectric layer 212 is then formed on substrate 200. The complex = electrical layer 212 is composed of, for example, a bottom dielectric core, a charge trap layer, and a layer 212e. The material f of the bottom dielectric layer is, for example, an oxidation forming method such as a thermal oxidation method. The charge trapping layer 21 is formed by a chemical vapor deposition method. The top dielectric 212e reads _ if it is oxygen cut, which forms a stochastic phase deposition method. Of course, the bottom dielectric core and the top dielectric layer are also = 24 1265604 143 72-1 twf.doc/g 疋 other similar materials. The material of the charge trapping layer 21 is not limited to nitriding, and may be other materials capable of trapping charges therein, such as a ruthenium-oxide layer, a citric acid layer, and an oxide layer. Next, another layer of conductor layers 214 is formed on the substrate 200, wherein the conductor layer 214 fills the gap between the adjacent two stacked gate structures 2〇2. The material of the conductor layer 214 is, for example, a doped polysilicon. The formation/method of the conductor layer 214 is formed, for example, by chemical vapor deposition to form an undoped polycrystalline layer. After the ion implantation step is performed to form . Referring to Fig. 4C, a portion of the conductor layer 214 is removed until the top germanium layer 208 is exposed, and a conductor layer 214a (gate) is formed between the stacked gate structures 2〇2. The conductor layer 214a connects a plurality of stacked gate structures 2〇2 in series. The method of removing a part of the conductor layer 2H is, for example, a money cutting method or a chemical mechanical polishing method. Conductor layer 214a and composite dielectric layer 212 form another gate structure. It is to be noted that in order to lower the resistance of the conductor layer 214a, a metal halide may be formed on the surface of the conductor layer 214a. Then, a patterned mask layer 216 is formed on the substrate 200, > exposing a region where the source/drain regions are subsequently formed. Next, an etching process is performed to remove the conductor layer 214 and the composite dielectric layer 212 remaining on the region where the source/drain regions are to be formed. Thereafter, a doping implantation step is performed with the mask layer 216 as a mask, and a source region 218 and a drain region 22 are formed in the substrate 200. The source region 218 and the drain region 220 are located in the substrate 2〇〇 on both sides of the stacked gate structure 2〇2 and the conductor layer 214a connected in series. Next, please refer to FIG. 4D' to form an inner layer of dielectric 25 1265604 14372-1 twf.doc/g layer 222 on the substrate 200. The material of the inner dielectric layer 222 is, for example, oxidized stone, and the formation method thereof is, for example, chemical vapor deposition. Then, a source line 224 electrically connected to the source region 218 is formed in the inner dielectric layer 222. The material of the source line 224 is, for example, tungsten metal. Thereafter, please refer to Fig. 4E' to form another inner dielectric layer 226 on the substrate 2''. A plug 228 electrically connected to the drain region 22 is formed in the inner dielectric layer 226, and a wire 23G (bit line) connected to the plug is formed on the inner dielectric layer 226. The subsequent completion of the process of non-volatile memory is well known to those skilled in the art and will not be described here. f In the above embodiment, since the stacked gate structure is supported between the composite dielectric layer 212 and the conductor layer 214a, no lithography is required. Another gate structure is formed between the stacked gate structures. . Because = clothing sister is simple 'and can reduce costs. In addition, the non-memory body of the present invention uses the charge trapping layer b and the charge trapping layer (10) as the == memory cell, so that it is not necessary to consider the concept of the closed-close ratio, but low, to perform the required operating voltage, and Improve the efficiency of memory cells. The step of forming the forward-looking memory is relatively early compared to the conventional process, so that the manufacturing cost can be reduced. In the above-mentioned implementation of the financial system, the department of the red cell is the structure of the memory cell, and the method of manufacturing the memory cell of the present invention is used to form an appropriate number of memory cells, for example, memory. The cell line can be connected in series with 32 to 64 non-volatile notes of the #方本= cell, - structure. Moreover, the present method of memory cell array k is actually applied to form a whole 26 1265604 14372-ltwf.doc/g. Although the invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention. It is to be understood that the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a top view of a non-volatile memory of the present invention. 1B is a cross-sectional view showing the structure taken along line A_A of FIG. 1A. FIG. 1C is a schematic diagram of the structure of the non-volatile memory of the present invention. FIG. 2 is a schematic diagram of the non-volatile memory of the present invention. mode. 3A is a schematic diagram of an example of a stylized operation of the present invention. 3B is a schematic diagram of an example of a read operation of the present invention. Fig. 3C is a diagram and diagram for explaining a phenomenon which occurs when a memory cell is read. Figure 3D is a schematic illustration of one example of an erase operation of the present invention. Fig. 3E is a schematic view showing still another example of the erasing operation of the present invention. Figure 3F is a schematic illustration of another example of an erase operation of the present invention. 3G is a schematic view of still another example of the erasing operation of the present invention. Process = to FIG. 4E is a manufacturing of the non-volatile memory of the present invention [main element symbol description] 100, 200: substrate 102: element isolation structure 27 1265604 14372-ltwf.doc/g 104: active area 106: selection Units _ 108, 220, D: drain regions 110, 218, S: source regions • 112, 114: memory cells 116, 124, 130, 204, 212: composite dielectric layers 116a, 124a, 130a, 204a, 212a : bottom dielectric layer 116b, 124b, 130b, 204b, 212b · charge trapping layer ® 116c, 124c, 130c, 204c, 212c: top dielectric layer 118, 126, 132: gate 120, 134, 208: top cover Layers 122, 136, 210: insulating spacers 128: memory cell rows 138, 228: plugs 140, 230 · bit lines 142, 224: source lines • 202: stacked gate structures 206, 214, 214a: conductors Layers BL1 to BL3 · Bit lines Mil to M3n: Memory cells Q, Q1 to Qn: Memory cells ST1 to ST3: Selection unit SG: Selection lines WL1 to WLn: Word line 28