TWI263905B - Method and apparatus for interconnection of multiple buses with different clock frequencies - Google Patents
Method and apparatus for interconnection of multiple buses with different clock frequencies Download PDFInfo
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13692twf.doc/006 九、發明說明: 【發明所屬之技術領域】 本發明是關於-種轉換連接電腦系統匯流排的方法與 裝置’且特別是關於-種轉換連接多個使用不同時脈頻率 的匯流排的方法與裝置。 【先前技術】 在電細系統中,匯流排(bus)是非常重要的元件,有了 匯流排,中央處理單元(Central P職ssing unit,以下簡稱 為CPU)、記憶體、以及周邊裝置等重要組成元件才能互 相溝通。連接於匯流排上的元件可分社裝置(master)與從 屬裝置(slave)兩類,主裝置是請求(request)的發送者,例如 CPU ’而從屬裝置則;^請求的執行者,例如周邊裝置。匯 流排的作用,就是來回傳遞請求與執行請求後的回應。 匯肌排疋所有元件共用,自然會成為效能瓶頸,因為 同-時間内只有-魅裝置能使㈣流排,其他主裝置如 果想發送請求,必須先料上—個請求執行完畢。因此, 有人提出在系統内放置多個匯流排的構想,讓不同匯流排 上的主裝置所發送的請求,得以在各自的匯流排上同步執 行,例如ARM公司提出的muhi七抑AHB㈤獨⑽13692twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a method and apparatus for converting a busbar connected to a computer system, and in particular to a plurality of different connection clock frequencies using different clock frequencies The method and device of the bus bar. [Prior Art] In the electric system, the bus is a very important component. With the bus bar, the central processing unit (Central P ssing unit, hereinafter referred to as CPU), memory, and peripheral devices are important. Components can communicate with each other. The components connected to the busbar can be divided into two types: a master device and a slave device. The master device is a sender of a request, such as a CPU, and the slave device is a slave device. . The role of the bus is to pass the request back and forth and the response after the request is executed. The sharing of all components of the muscles is naturally a performance bottleneck, because only the enchanting device can make the (four) stream in the same time, and other master devices must first request the execution of the request if they want to send the request. Therefore, it has been proposed to place multiple busbars in the system, so that the requests sent by the master devices on different busbars can be executed simultaneously on their respective busbars, for example, the muhi seven AHB (5) alone (10) proposed by ARM.
High-Performance System Bus),就是其中之一。 有了多個匯流排之後,它們之間必須能互相溝通,而 在multi-layer AHB架構中是透過轉接矩陣(脱_來達到。 所謂轉接轉,是-種多細流排之關轉換連接裝置, 可讓個匯賴上的城置,細另—鋪流排上的從屬 1263狐 f._6 裝置,而不會影響其他匯流排的運作。 然而,在multi-layer AHB規格中並沒有提到匯流排使 用不同時脈頻率的問題。所以關於轉接矩陣如何接通多個 使用不同時脈頻率的匯流排,目前並沒有標準解決方案。High-Performance System Bus) is one of them. After having multiple bus bars, they must be able to communicate with each other, and in the multi-layer AHB architecture, it is achieved through the transfer matrix (disconnected). The so-called transfer transfer is a multi-fine flow switch connection. The device can be used to relocate the suburbs, and the subordinate 1263 fox f._6 device on the flow slab without affecting the operation of other busbars. However, it is not mentioned in the multi-layer AHB specification. There are problems with different clock frequencies to the bus, so there is currently no standard solution for how the switch matrix connects multiple bus bars with different clock frequencies.
美國專利申請案第20020162043號提出一種AMBAU.S. Patent Application No. 20020162043 proposes an AMBA
(Advanced Microcontroller Bus Architecture)中 AHB 和 APB (Advanced Peripheral Bus)的連接的架構,可讓較高速匯流 排(AHB)上的主裝置使用較低速匯流排(ApB)上的從屬裝 置,然而跡能處職屬裝置處於較高賴流排上的狀況。 此外,這個架構只能用在有兩個匯流排的系統,不能用在 有三個以上匯流排的系統。 因此,我們需要更有彈性的解決方案,以轉換連接三 的使用不㈣脈辭_流排,並且克服先前麟 的缺點。 【發明内容】 穿置本!=3=供—種多頻匯流排轉換連接方法與 恤』技術的缺點,連通多個使用不同時脈頻 為達成上述及其他目的,本發明提出 轉換連接方法,主要步驟如下:接收〔2、机排 -主裝置發送至-從屬裝置.甚明’’此5月求係由 過長,主裝置時脈頻率比從屬裝置Γ,虎Γ 稷接收此請求’則料此請衫餘之 、屬裝置重 裝置重複接收請求,然後轉送請求至“裝 1263¾¾ iwf.doc/006 包含之訊號持續過短,主裝置時脈頻率比從屬I置高,以 至於從屬裝置來不及接收此請求,職換延長此請求過短 之吼唬,使請求訊號與從屬裝置之時脈同步,以及轉送從 屬裝置所回應之輸出資料至主裝置。 、1另一觀點來看,本發明另提出一種多頻匯流排轉換 連接I置,此裝置係耦接於多數個匯流排之間,包括一接 ^模組、一遮罩邏輯模組、一仲裁轉送裝置、一轉換延長 2組、以及一回應模組。接收模組耦接於上述匯流排之中包 含主裝置之所有匯流排,接收並輸出一請求,其中此請求係 由-主裝置發送至一從屬裝置。遮罩邏輯模組接收接收模組 所輸出之請求,若請求所包含之訊號持續過長,以至於從 屬裝置重複接收此請求,則遮罩此請求多餘之訊號週期, 以免從屬裝置重複接收請求,並輸出遮罩後之請求。仲裁 轉送裝置接收接收模組所輸出之請求,並接收遮罩邏輯模 組所輸出之遮罩後之請求,排定發送至同一匯流排之請求 之執行順序,並依照執行順序輸出遮罩後之請求。轉換延 長模組接收仲裁轉送裝置所輸出之請求,若請求所包含之 訊號持續過短,以至於從屬裴置不及接收此請求,則轉換 延長此請求過短之訊號,使請求訊號與從屬裝置之時脈同 步,並且發送轉換延長後之請求至從屬裝置。回應模組則 接收從屬裝置所回應之一輪出資料,並轉送輸出資料至主 裝置。 依照本發明的較佳實施例所述,本發明提出的方法與 凌置,可在多個匯流排之間,來回傳遞請求與回應請求的 I26393〇9^twfd〇c/〇〇6 輸出資料,而且能遮罩或延長請求訊號料脈週期, 應各,匯流排之間的時脈差異,因此能達到本㈣的優點, 也就是轉換連接多個使用不同時脈頻率的匯流排。 >為讓本1明之上述和其他目的、特徵和優點能更明顯 易懂,下文特舉一較佳實施例,並配合所附圖式, 田 說明如下。 17 v 【實施方式】 本發明提出的多頻匯流排(bus)轉換連接裝置,是根據 先前技術的轉換矩陣(matrix)改進而來,可連接任意數量的 匯流排,每個匯流排上皆可包含任意數量的主裝置(master) 與從屬裝置(slave)。為了簡單說明起見,以下的實施例都 只連接兩個主裝置與兩個從屬裝置,各自佔用一個獨立的 匯流排,例如圖1所繪示的使用情形。 在圖1當中,多頻匯流排轉換連接裝置1〇1連接四個 匯流排,分別標示為1〇9至112。主裝置1〇2耦接於匯流 排109,主裝置103耦接於匯流排11〇,從屬裝置1〇4耦接 於匯流排111,從屬裝置1〇5則耦接於匯流排112。在這個 實施例中,匯流排Hi與112都使用最高的時脈頻率,匯 流排109與11〇使用較低的時脈頻率。這些匯流排的時脈 頻率之間必須有倍頻關係,也就是說,最高的時脈頻率, 必須為其他較低的時脈頻率的整數倍。 為了在多個使用不同時脈頻率的匯流排之間,傳遞請 求(request)與執行請求之後的回應,多頻匯流排轉換連接裝 置101必須參考各種不同的匯流排時脈頻率,因此有1〇6、 twf.doc/006 1263905 13692t 1〇7與應這三個輸入訊號。其中標準時脈訊號⑽是最高 頻的時脈訊號,也是多頻匯流排轉換連接裝置101,以及 匯流排111與112所共同使用的時脈訊號。1〇6與1〇7原本 應該是匯流排撕與110各自使用的時脈訊號,但因為在 同-個電路裝置内使用多個不同頻率的時脈訊號,會增加 設計上的困難與複雜程度,因此將刚與1()7改為分別對 應於匯流排與m㈣脈解的輕致能訊號。這種 時脈致能减’可以由外部供應,也可以由多頻匯流排轉 換連接裝置101根據最高頻的標準時脈訊號1〇8自行產生。 所謂時脈致能訊號,是用於在本發明提出的多頻匯流 排轉換連接裝置之内,取代S流排時脈訊號。時脈致能訊 號和匯流排使㈣時脈辭之間有―—對應關係,它的 變化頻率和標準時脈訊號相關,平時都處於低電位,只有 在對應的匯流排時脈頻率的每一週期結束時,出現一標準 _週期的高練’因此可取代鮮與它自料應頻率相 同的所有匯流排時脈訊號。圖2繪示標準時脈訊號cl〇ck、 匯流排時脈訊號cl〇ckx與時脈致能訊號d〇ck—三者之 間的時序_。圖2之巾的標準時脈訊#bdQek與匯流排時 脈訊號^lockx頻率相同,因此時脈致能訊號cl〇ck 始 ^於高電位。圖3是類似的時相,只獨標準時脈訊 \ Cl〇ck的頻率是匯流排時脈訊號clockx的兩倍,因此時 ,致能訊号虎cl0ck_enx每兩個週期才出現一次高^位,也就 =在匯流排時脈訊號cl〇ckx的每個週期結束時,出現一週 期的高電位。目4也錢似的時序圖,其中標準時脈訊號 9 I263^0l,d〇c/〇〇6 clock的頻率是匯流排時脈訊號d〇ckx的四倍。由圖4可以 看出日守脈致能訊號clock一enx每四個週期才出現一次高電 位。從圖2到圖4即可推斷出各種不同倍率時的狀況。 卜圖至圖5C是多頻匯流排轉換連接裝置的另一個實 施,=結構圖。圖5八繪示將請求由主裝置轉送到從屬裝置 的部分(此外尚包括繪示於圖5B的時脈模組518與繪示於 圖5C的回應模組52〇),其中多頻匯流排轉換連接裝置5〇〇 一樣^連接兩個主裝置(標示為M1與M2)和兩個從屬裝 置(標示為si與S2),主裝置與從屬裝置也都獨自佔用一 個匯流排。在這個實施例中,主裝置Ml與從屬裝置si的 時脈頻率,是主裝置M2與從屬裝£ a的兩倍。來自主裝 置Ml與M2的請求會先進入接收模組5〇8,由其中的接收 裝置509在時脈致能為高電位時閂鎖(latch)請求訊號,並予 以解碼(decode)。每個含有主裝置的匯流排,都有一個對應 的接收裝置509,負責接收這個匯流排所發送的請求。而 接受裝置509使用501的時脈並使用時脈致能訊號5〇2,5〇3 當作閂鎖相對應匯流排信號的致能訊號。 接下來,解碼後的請求會進入遮罩邏輯(masking 1〇gic) 才莫組511,如果請求訊號持續太長,以至於從屬裝置會重 複接收請求,遮罩邏輯模組511之内的遮罩邏輯裝置512 會遮罩請求喊之巾乡餘的職,以倾屬裝置^複接收 請求。關於請求的遮罩,後面有更詳細的解說。 、、離開遮罩邏輯模組Ml之後,請求訊號會進入仲裁轉 运裝置513。在這裡,如果有多個請求同時發送到同一個 126 職 f.d_ 裁器(arbiter)514會排定這些請求的順序,然後 序毛出准^執行訊號,讓對應的轉送多工器㈣tiplexer) 515將目則執行順序為最高優先的請求發送給從屬裝置。 在!t裁轉送衣置513之中只有一個仲裁器514,而轉送多 工器515,與含有從屬裝置的匯流排有一一對應關係。 、接下來,請求訊號會進入轉換延長模組516。如果請 求,號的持續時間太短,通常是因為主裝置的時脈頻率高 於攸屬裝置的時脈解,以至於則裝置來不及接收請求, 對應的轉換延長裝置517就會轉換延長請求訊號 ,使請求 馨 =號與從屬裝置的時脈訊號同步,如此從屬裝置才能接收 5月求。其中轉換延長裝f 517與含有從屬裝置的匯流排也 有對應的關係,然而在這個實施例中,因為從屬裝置S1 的時脈頻率是最高的,因此不需要對應的轉換延長裝置-517 〇 離開轉換延細組516讀,請求喊就會進入匯流 排,由從屬裝置si或η接收。至於有限狀態機(fmite state machine) 510,是貞責產生狀態訊號,並且輸出狀祕絲 接收模組508與遮罩邏輯模組5Π,藉以決定適當時機, 以閂鎖並遮罩來自主裝置的請求。 圖5B繪示時脈模組518與其中負責產生時脈致能訊號 的時脈裝置519。如圖所示,每個時脈裝置519負責根據 才示準時脈訊號501,產生一個時脈致能訊號(在圖中標示 為502與503),而且時脈裝置519與所有匯流排使用的 時脈頻率之間,有一一對應的關係。實際上要產生時脈致 π 能訊號非常容例如使㈣單的計數帥㈣㈣即可 生,因此多頻匯流排轉換連接裝置,可不必包括時脈模 組518,而直接自外界接收時脈致能訊號。 、 圖5C綠示負責將從屬裝置執行請求後所回應的輸 料’送回給主裝置的回應模組52〇,以及回應模組52〇所 包含的回應⑽器521與回應多工器522。為了簡單說明 起見,圖5C只繪示一組連通從屬裝置sl與主裝置的 回應閃鎖器521與回應多工器522。實際上的回應閃鎖器521 與回應多工器522,皆與含有從屬褒置的匯流排有一一對 應關係。每當從屬裝置sl產生輸出㈣,就會分成兩路, -,被回制鎖器521 _暫存,另—路直接到達回應多 工器522。如緖出資料與主裝置M2的時脈同步,回應多 工器522會直接發送輸出資料給主裝置M2,否則就輸出經 過回應f-Ι鎖H 521 _的輸出㈣,等待主裝置M2於猶 後時脈同步時接收。 下面以一些訊號時序圖為範例,說明本實施例如何在 多個不同時脈頻率的匯流排之間,來回傳遞請求與回應。 以下的範例所使用的匯流排訊號與傳輸協定,皆來自arm 公司提出的先進微控器匯流排架構(Advanced(Advanced Microcontroller Bus Architecture) The architecture of the connection between AHB and APB (Advanced Peripheral Bus) allows the master device on the higher speed bus (AHB) to use the slaves on the lower speed bus (ApB). The situation in which the device is on a higher level. In addition, this architecture can only be used in systems with two bus bars and not in systems with more than three bus bars. Therefore, we need a more flexible solution to convert the use of connection three without the four-word _ stream, and overcome the shortcomings of the previous lin. SUMMARY OF THE INVENTION The present invention proposes a conversion connection method, in which the above-mentioned and other objects are achieved by connecting a plurality of different clock frequencies to achieve the above and other objects. The main steps are as follows: Receive [2, the machine row - the master device sends to - the slave device. Very clear" 'This May is too long, the master device clock frequency is higher than the slave device, and the tiger cub receives this request' This device is the device reset device that repeatedly receives the request, and then forwards the request to "Load 12633⁄43⁄4 iwf.doc/006. The included signal continues to be too short. The master device clock frequency is higher than the slave I, so that the slave device does not have time to receive. The request, the job change extends the request too short, synchronizes the request signal with the slave device's clock, and forwards the output data that the slave device responds to the master device. 1 From another point of view, the present invention further proposes A multi-frequency busbar conversion connection I is disposed, and the device is coupled between a plurality of busbars, including a module, a mask logic module, an arbitration transfer device, and a conversion extension group. And a response module, the receiving module is coupled to the bus bar and includes all the bus bars of the main device, and receives and outputs a request, wherein the request is sent by the master device to a slave device. The mask logic module Receiving the request output by the receiving module, if the signal included in the request continues to be too long, so that the slave device repeatedly receives the request, masking the redundant signal period of the request, so that the slave device does not repeatedly receive the request, and outputs the mask The arbitration transfer device receives the request output by the receiving module, receives the masked request output by the mask logic module, schedules the execution order of the request sent to the same bus, and outputs the mask according to the execution order. The request after the cover. The conversion extension module receives the request output by the arbitration transfer device, and if the signal included in the request continues to be too short, so that the slave device does not receive the request, the conversion extends the short signal of the request to make the request The signal is synchronized with the slave device's clock, and the extended conversion request is sent to the slave device. The response module receives the slave device. One of the respondents rotates the data and forwards the output data to the host device. According to the preferred embodiment of the present invention, the method and the present invention provide a method for transmitting request and response requests between multiple bus bars. I26393〇9^twfd〇c/〇〇6 output data, and can mask or extend the request signal cycle, should be different, the clock difference between the bus, so can achieve the advantages of (4), that is, conversion Connecting a plurality of bus bars using different clock frequencies. The above and other objects, features and advantages of the present invention will become more apparent and obvious, and a preferred embodiment will be described hereinafter with reference to the drawings. The description is as follows: 17 v [Embodiment] The multi-frequency bus switching connection device proposed by the present invention is improved according to the prior art conversion matrix, and can connect any number of bus bars, each bus bar Any number of masters and slaves can be included. For the sake of simplicity, the following embodiments connect only two master devices and two slave devices, each occupying a separate bus bar, such as the use case illustrated in FIG. In Fig. 1, the multi-frequency busbar switching connection device 〇1 is connected to four busbars, which are labeled as 1〇9 to 112, respectively. The main device 1〇2 is coupled to the bus bar 109, the main device 103 is coupled to the bus bar 11〇, the slave device 1〇4 is coupled to the bus bar 111, and the slave device 1〇5 is coupled to the bus bar 112. In this embodiment, both busses Hi and 112 use the highest clock frequency, and busses 109 and 11 〇 use a lower clock frequency. There must be a multiplier relationship between the clock frequencies of these busses, that is, the highest clock frequency must be an integer multiple of the other lower clock frequencies. In order to transmit a request and a response after the execution of the request between a plurality of bus bars using different clock frequencies, the multi-frequency bus conversion connection device 101 must refer to various different bus clock frequencies, so there is 1〇 6, twf.doc/006 1263905 13692t 1〇7 and these three input signals. The standard clock signal (10) is the highest frequency clock signal, and is also a multi-frequency bus conversion connection device 101, and a clock signal used by the bus bars 111 and 112. 1〇6 and 1〇7 should originally be the clock signals used by the busbar tearing and 110, but because of the use of multiple clock signals of different frequencies in the same circuit device, the design difficulty and complexity will increase. Therefore, it will be changed to 1 () 7 to correspond to the light signal of the bus and m (four) pulse respectively. This clock enable reduction can be supplied externally or can be generated by the multi-frequency bus conversion connection device 101 based on the highest frequency standard clock signal 1〇8. The so-called clock enable signal is used in the multi-frequency bus conversion connection device proposed by the present invention instead of the S-stream clock signal. The clock-enabled signal and the bus bar have a (-) correspondence between the (4) clock words, and the frequency of change is related to the standard clock signal, and is usually at a low potential, only in each cycle of the corresponding bus clock frequency. At the end, a standard _ cycle of high practice appears, so it can replace all the bus line signals with the same frequency as its own. Figure 2 shows the timing_ between the standard clock signal cl〇ck, the bus clock signal cl〇ckx and the clock enable signal d〇ck. The standard time pulse #bdQek of the towel of Fig. 2 is the same as the frequency of the bus signal ^lockx, so the clock enable signal cl〇ck starts at a high potential. Figure 3 is a similar phase, only the standard time pulse \ Cl〇ck frequency is twice the bus clock signal clockx, so when the signal tiger cl0ck_enx occurs once every two cycles, That is, at the end of each cycle of the bus pulse signal cl〇ckx, a high level of one cycle occurs. The timing of the money is also similar, in which the standard clock signal 9 I263^0l, d〇c/〇〇6 clock is four times the frequency of the bus clock signal d〇ckx. It can be seen from Fig. 4 that the day-to-day pulse-enable signal clock-enx has a high potential every four cycles. From Fig. 2 to Fig. 4, it is possible to infer the situation at various magnifications. Fig. 5C is another embodiment of the multi-frequency busbar switching connection device, = structure diagram. Figure 5 shows a portion of the request for transfer from the host device to the slave device (in addition, the clock module 518 shown in Figure 5B and the response module 52A shown in Figure 5C), wherein the multi-frequency bus The switching device 5 is connected to two main devices (labeled M1 and M2) and two slave devices (labeled as si and S2), and the master device and the slave device also each occupy a bus bar. In this embodiment, the clock frequency of the master device M1 and the slave device si is twice that of the master device M2 and the slave device. Requests from the master devices M1 and M2 first enter the receiving module 5〇8, and the receiving device 509 latches the request signal and decodes it when the clock enable is high. Each bus bar containing the master device has a corresponding receiving device 509 that receives the request sent by the bus bar. The receiving device 509 uses the clock of 501 and uses the clock enable signal 5〇2, 5〇3 as the enable signal for latching the corresponding bus signal. Next, the decoded request enters the masking logic (masking 1〇gic). If the request signal continues for too long, the slave device repeatedly receives the request, masking the mask within the logic module 511. The logic device 512 will mask the request for the shouting of the hometown to receive the request. A more detailed explanation of the mask of the request. After leaving the mask logic module M1, the request signal will enter the arbitration transfer device 513. Here, if there are multiple requests sent to the same 126-position f.d_ arbiter 514, the order of these requests will be scheduled, and then the order will be executed to execute the signal, so that the corresponding transfer multiplexer (four) handleler) 515 sends the request with the highest priority to the slave device. There is only one arbiter 514 among the !t cutting clothes sets 513, and the transfer multiplexer 515 has a one-to-one correspondence with the bus bars containing the slave devices. Next, the request signal will enter the conversion extension module 516. If requested, the duration of the number is too short, usually because the clock frequency of the master device is higher than the clock solution of the slave device, so that the device does not have time to receive the request, and the corresponding conversion extension device 517 converts the extension request signal. The request xin=number is synchronized with the slave device's clock signal so that the slave device can receive the May request. The conversion extension f 517 also has a corresponding relationship with the bus bar containing the slave device. However, in this embodiment, since the clock frequency of the slave device S1 is the highest, the corresponding conversion extension device is not required - 517 〇 leaving the conversion The extension group 516 reads, and the request is shouted to enter the bus, which is received by the slave device si or n. As for the fmite state machine 510, it is responsible for generating a status signal, and the output secret wire receiving module 508 and the mask logic module 5 are used to determine an appropriate timing to latch and mask the slave device. request. FIG. 5B illustrates the clock module 518 and the clock device 519 responsible for generating the clock enable signal. As shown, each clock device 519 is responsible for generating a clock enable signal (labeled 502 and 503 in the figure) based on the quasi-clock signal 501, and the clock device 519 is used with all bus bars. There is a one-to-one correspondence between pulse frequencies. In fact, it is necessary to generate a clock-induced π-energy signal, for example, so that the (four) single-counting handsome (four) (four) can be born, so the multi-frequency busbar switching connection device does not need to include the clock module 518, but directly receives the clock from the outside. Can signal. Figure 5C shows the response module 52〇 that is responsible for sending the response sent by the slave device after the request is executed to the master device, and the response (10) device 521 and the response multiplexer 522 included in the response module 52〇. For the sake of simplicity, FIG. 5C shows only a set of response flashers 521 and response multiplexers 522 that communicate with slave devices sl and the master device. The actual response flash locker 521 and response multiplexer 522 have a one-way relationship with the busbars containing the slave devices. Whenever the slave device sl produces an output (4), it is divided into two paths, - the gate locker 521_ is temporarily stored, and the other route directly reaches the response multiplexer 522. If the data is synchronized with the clock of the master device M2, the response multiplexer 522 will directly send the output data to the master device M2, otherwise the output will be outputted after responding to the f-shackle H 521 _ (four), waiting for the master device M2 to Received when the clock is synchronized. In the following, some signal timing diagrams are taken as an example to illustrate how the present embodiment transfers requests and responses back and forth between bus channels of different clock frequencies. The bus signal and transmission protocol used in the following examples are all from the advanced micro controller bus architecture proposed by arm.
Microcontroller Bus Architecture,簡稱為 AMBA)其中的 咼放此糸、、充匯机排(Advanced High-performance system Bus,簡稱為AHB)。此外,除非特別聲明,在以下範例 中,主裝置的時脈頻率都只有從屬裝置的一半(例如圖5A 當中的主裝置M2與從屬裝置sl)。 12 f.doc/006 為了簡化說明,下面的表格是範例中所有訊號的解說。 很多匯流排訊號名稱都是Hxxxx一Μ或Hxxxx一s的格式, 它們其實是相同的訊號,只是出現位置不同,以‘‘ M,,处 尾的訊號是出現在主裝置所屬的匯流排上,而以“〜s,,結尾 的訊號是出現在從屬裝置的匯流排上,下面的表格是以 Hxxxx的名稱一併解釋。Microcontroller Bus Architecture (referred to as AMBA), which is the Advanced High-performance System Bus (AHB). Further, unless otherwise stated, in the following examples, the clock frequency of the master device is only half of the slave device (e.g., master device M2 and slave device sl in Fig. 5A). 12 f.doc/006 To simplify the explanation, the following table is an explanation of all the signals in the example. Many bus signal names are in the format of Hxxxx or Hxxxx-s. They are actually the same signal, but the position is different. To the ''M, the signal at the end appears on the busbar to which the main device belongs. The signal ending with "~s," appears on the busbar of the slave device. The following table is explained by the name of Hxxxx.
13 c/006 1263搬_ 訊號名稱 clock 說明 clockx clock enx 標準 1 脈訊號13 c/006 1263 _ signal name clock description clockx clock enx standard 1 pulse signal
f置的匯流排時脈頻率所對應的時脈致能訊 clocks clock ens 名 ::裝置的匯流排時脈頻率:所對應的_致能F-set clock frequency corresponding to the clock frequency clocks clock ens name :: device bus clock frequency: corresponding _ enable
HADDRHADDR
HBURSTHBURST
HRDATA HREADY HTRANSHRDATA HREADY HTRANS
HWDATA HWRITE 目前請求的_,職s代表非猶 rrtlfi求,也就是單—的請求或一㈣ 广印求的第一個單一請求;seq代表循月 sequential)晴求,也就是一組連續請求的 =後的單-請求;busy代表忙碌週期,,di i來·咖在本實施例中; 來j罩持、、、只過長的請求訊號週期,關 說 高電位表請求為 取請求_ 表格1,圖6至圖11B的訊號說明 14 1263概_ 從圖6可以看出,訊號會先出現在主裝置匯流排,經 過問鎖、解碼、遮罩等一連串處理之後,才出現在從屬裝 置的匯流排。本實施例是在標準時脈訊號cl〇ck的上升緣, 而且時脈致能訊號clock—enx處於高電位時,閃鎖來自主裝 置的請求。兩個匯流排上的訊號,除了 HTRANS會經過遮 罩之外,其餘訊號内容都沒有改變。在這個範例中,訊^ 過長是因為主裝置的時脈頻率較低。如圖所示,本實施例 會用閒置週期遮罩HTRANS訊號的前一個週期,留下後面 一個週期不變,如此一來,從屬裝置只會看到後面一個週 _ 期的HTRANS訊號,因此不會重複接收請求。 圖7是本實施例傳送單一讀取請求時的訊號時序圖。 本實k例會在標準時脈訊號cl〇ck的上升緣,hreaDY s 訊號處於高電位,而且時脈致能訊號d〇ck—enx處於低電位 · 時,閂鎖並轉送從屬裝置回應的輸出資料dl至主裝置所屬 的匯流排,以待主裝置接收。 圖$是本實施例傳送連續寫入請求時的訊號時序圖。 士組連續睛求包含多個單一請求,所謂連續寫入就是對連 續的位址寫入一連串資料。圖8當中的連續寫入請求共包 :^個寫入睛求’其中只有第一個是非循序請求(htrans 虎為non-sequential),後面兩個都是循序請求(htrans 訊號,SeqUential)。從圖中可以看出,連續請求的遮罩方 式和單-4求不同’其巾第—個請求是以閒置週期遮罩, 後面兩個週期疋以忙碌週期遮罩。使用忙碌週期是因為 的傳輸協定要求後面的循序請求中不能出現閒置週期,否 15 12639^^—06 則會被視為非循序請求,而破壞連續請求的結構。經過遮 罩後,每個單一請求的HTRANS訊號都只剩下最後_個週 期有效,因此從屬裝置不會重複接收請求。 圖9是本實施例傳送連續讀取請求時的訊號時序圖。 所謂連續讀取就是從一段連續的位址讀出一連串資料。圖9 的連續讀取請求包含三個讀取請求,從圖中可以看出有三 筆輸出資料(dl、d2和d3)依次被閂鎖轉送到主裝置匯流 排’等待主裝置接收。 圖10是同時有兩個主裝置發送請求給同一個從屬裝置 的訊號時序圖,其中cloclcl與clock2分別是第一主裝置與 弟一主裝置的匯流排時脈訊號,clock—enl與ci〇ck en2分 別是對應於第一主裝置與第二主裝置的時脈致能訊一號。^ 一主裝置的時脈頻率與從屬裝置相等(例如圖5八當中的主 辱置Ml與從屬裝置sl),而第二主裝置的時脈頻率只有 從屬裝置的-半(例如圖5Α#中駐裝置⑽與從屬裝置 sj)。至於匯流排訊號,名稱後面是“一Ml,,的,表示是在 第了主裝置的匯流排上,而名稱後面是“〜M2,,的,表 在第二主裝置的匯流排上。 =圖10可以看出,本實施例的仲裁轉送装置(在圖5A ::轉送=屬:2自:個主裝置的請求排定順序後’ 轉送到各^應社裝紐流排。 aW4 520) 到目前為止的範例中,主裝置使用的時脈頻率都沒有 16 Ϊ2639Μ twf.doc/006 f置,圖UA與圖UB就是繪示這種情況。圖中, 因此為了讓從屬裝置能接收到請Ϊ, 長請求訊號,使它與從屬裝置的時脈訊號 ^三圖11A綠示不需要轉換延長的請求訊號,而圖仙 、、曰不而要轉換延長的請求訊號。本實施例 將請求訊號延遲-個·,並且延長為兩倍,使 連接匯流排轉換 1,步驟12〇2會接收來自主裳置的請求,將它閃鎖, =以㈣,以雜面處理。然後步驟12G4 包含的訊號是爾續過長,以至於 求’如果不是’直接跳到步驟1212,如果是^接= ^更進一步判斷這個請求是否為循序請求,如果不是I6 2驟腫用^週期遮罩請求多餘的訊號週期二』 私置重複接收請求,如果是,就在 m = 遮罩請求多餘的訊號週期。 ^ d录週期 接下來二驟U12會判斷從屬裝置所屬的 正處於忙雜=如果不是,就_步驟㈣ m4會紋㈣請求的執行順序為最低優先,步否貝^驟 會在主裝置與從屬裝置的然後步驟咖 W日寻脈汛號同步時,轉送目前執行 »92twf.doc/006 順序為最高優先的請求到從屬裝置。從步驟1212到果驟 1218的用意,就是將發送到同一個匯流排的請求排定執^ 順序,然後依序轉送給從屬裝置執行。 订 這時候的請求還沒有真正被從屬裝置接收,在這之前, 步驟1220會先判斷請求所包含的訊號是否持續過短,以至 於從屬裝置會來不及接收請求,如果是,步驟1222會轉換 延長請求之中過短的訊號,使從屬裝置得以接收請求。然 後從屬裝置會接收並執行請求。接下來的步驟1224會判^ 從屬裝置執行請求後所回應的輸出資料,是否與主裝置 時脈訊號同步。如果是,步驟1226會直接發送輸出^料給 主裝置,否則步驟1228會先閂鎖輸出資料,以待主裝 時脈同步時接收。 X ^HWDATA HWRITE currently requests _, job s stands for non-still rrtlfi, that is, a single request or a (four) wide first request for a single request; seq represents a monthly sequence, which is a set of consecutive requests = after the single-request; busy represents the busy cycle, di i come to the coffee in this embodiment; to j, hold, and only the long request signal cycle, close the high-potential table request for the request _ form 1, the signal description of Figure 6 to Figure 11B 14 1263 overview _ can be seen from Figure 6, the signal will appear in the main device bus, after a series of processing such as lock, decode, mask, etc., appear in the slave device Bus bar. In this embodiment, when the rising edge of the standard clock signal cl〇ck is high, and the clock enable signal clock_enx is at a high level, the request from the main device is flashed. The signals on the two bus bars, except for HTRANS, will not change the contents of the other signals. In this example, the signal is too long because the clock frequency of the master device is low. As shown in the figure, in this embodiment, the idle period is used to mask the previous period of the HTRANS signal, leaving the next period unchanged, so that the slave device only sees the next week's HTRANS signal, so it will not Repeat the request. Fig. 7 is a timing chart of signals when a single read request is transmitted in this embodiment. The real k example will be at the rising edge of the standard clock signal cl〇ck, the hreaDY s signal is at a high potential, and the clock enable signal d〇ck-enx is at a low potential, latching and forwarding the output data of the slave device response dl To the busbar to which the master device belongs, to be received by the master device. Figure $ is a timing diagram of signals when the continuous write request is transmitted in this embodiment. The group continuously asks for multiple single requests. The so-called continuous write is to write a series of data to consecutive addresses. The consecutive write requests in Figure 8 are co-packaged: ^ writes to the request, where only the first one is a non-sequential request (htrans is non-sequential), and the latter two are sequential requests (htrans signal, SeqUential). As can be seen from the figure, the mask pattern of consecutive requests is different from that of the single-4. The first request is masked by the idle period, and the next two periods are masked by the busy period. The busy cycle is used because the transport protocol requires that no idle cycles can occur in subsequent sequential requests. No 15 12639^^—06 will be treated as a non-sequential request, destroying the structure of consecutive requests. After masking, each single request HRANNS signal is only valid for the last _ cycle, so the slave does not repeatedly receive the request. Fig. 9 is a timing chart showing the signal when the continuous read request is transmitted in the embodiment. The so-called continuous reading is to read a series of data from a continuous address. The sequential read request of Figure 9 contains three read requests. It can be seen from the figure that three pieces of output data (dl, d2, and d3) are sequentially latched to the master sink ‘waiting for master reception. FIG. 10 is a timing diagram of signals simultaneously sent by two master devices to the same slave device, where cloclcl and clock2 are bus-station signals of the first master device and the master device, respectively, clock_enl and ci〇ck En2 is a clock-enabled signal corresponding to the first master device and the second master device, respectively. ^ The clock frequency of a master device is equal to the slave device (for example, the master insult M1 and the slave device sl in FIG. 5), and the clock frequency of the second master device is only - half of the slave device (for example, FIG. 5Α# The resident device (10) and the slave device sj). As for the bus signal, the name is followed by "a Ml," indicating that it is on the busbar of the first master device, and the name is followed by "~M2," which is on the busbar of the second master device. As can be seen from Fig. 10, the arbitration transfer device of the present embodiment (in FIG. 5A::transfer=genus: 2: from the request scheduling sequence of one master device) is forwarded to each of the chores of the company. aW4 520 In the example so far, the clock frequency used by the master device is not set to 16 Ϊ 2639 Μ twf.doc/006 f. Figure UA and Figure UB show this situation. In the figure, therefore, in order to allow the slave device to receive the request, the long request signal is made so that it does not need to convert the extended request signal with the clock signal of the slave device, and the figure does not need to be converted. Convert extended request signals. In this embodiment, the request signal is delayed by -2, and is extended by two times, so that the connection bus is converted to 1, and the step 12〇2 receives the request from the main skirt, and flashes it, = (4), and is processed by the surface. . Then the signal contained in step 12G4 is too long, so that it is 'if not' directly jumps to step 1212, if it is ^ then = ^ further determines whether the request is a sequential request, if not I6 2 swollen with ^ cycle The mask requests an extra signal cycle 2" privately repeats the request, and if so, requests an extra signal cycle at m = mask. ^d recording cycle The next two steps U12 will determine that the slave device is busy. If not, then _step (4) m4 will print (4) the execution order of the request is the lowest priority, the step will be in the master device and the slave The device then forwards the current step to the highest priority request to the slave device when the device is synchronized. The intention from step 1212 to step 1218 is to schedule the requests sent to the same bus to be executed and then forward them to the slave device for execution. The request at this time has not been actually received by the slave device. Before this, step 1220 first determines whether the signal included in the request continues to be too short, so that the slave device will not have time to receive the request, and if so, step 1222 will convert the extension request. A short signal in the middle allows the slave device to receive the request. The slave then receives and executes the request. Subsequent step 1224 determines whether the output data responded to by the slave device after execution of the request is synchronized with the master device clock signal. If so, step 1226 will send the output directly to the master device, otherwise step 1228 will first latch the output data to be received when the master clock is synchronized. X ^
由以上說明可知,本發明提出的多頻匯流排轉換連接 方法與裝置,足以克服先前技術的缺點,轉換連接多 用不同時脈頻率的匯流排。 K 雖然本發明已以較佳實施例揭露如上,然其並 限;本發明、,,任何熟習此技藝者,在不脫離本發明之精神 ^犯圍當可作些許之更動與潤飾,因此本發明 範圍當視_之_請專利範騎界定者為準。 … 【圖式簡單說明】 H 為本發明提出的多麵流排轉換連接裝置的-實 施例的使用範例。 J 貫 的- ΐΛίΓΛ為本發明提出的多頻匯流排轉換連接裝置 、e 、淮/机排時脈訊號與時脈致能訊號的時序圖。 1263 狐 _ 圖jA至圖5C為本發明提出的多頻匯 置的一貫施例的結構圖。 褥侠逑接裝 、二為一本:明,多頻匯流排轉換連接裝置的-實 也丨專达早寫入,求時的訊號時序圖。 二為二明提出的多頻匯流排轉換連接裝置的-實 訑例傳达早一躓取請求時的訊號時序圖。 圖、8為本發明提出的多麵流排轉換連接裝置的—眘 施例傳送連績寫入請求時的訊號時序圖。 圖9為本發明提丨的乡麵流排轉換連接裝置的 施例傳送連續讀取請求時的訊號時序圖。 圖10為本發明提出的多頻匯流排轉換連接裝置的一 施例處理同時發生的請求時的訊號時序圖。 圖ΠΑ與圖ΠΒ為本發明提出的多頻匯流排轉換連接 裝置的一實施例轉換延長請求訊號時的訊號時序圖。 圖12為本發明提出的多頻匯流排轉換連接方法的一實 施例的流程圖。 【圖式標記說明】 101 :多頻匯流排轉換連接裝置 102、103 :主裝置 104、105 :從屬裝置 106、107 :時脈致能訊號 108 :標準時脈訊號 109、110、111、112 :匯流排 5〇〇:多頻匯流排轉換連接裝置 19 1263嫩 wf.doc/006 5〇1 :標準時脈訊號 502、503 :時脈致能訊號 508 :接收模組 509 :接收裝置 510 :有限狀態機 511 :遮罩邏輯模組 512 :遮罩邏輯裝置 513 :仲裁轉送裝置 514 :仲裁器 515 ··轉送多工器 516 :轉換延長模組 517 :轉送延長裝置 518 :時脈模組 519 :時脈裝置 520 :回應模組 521 :回應閂鎖器 522 :回應多工器 1202 :接收請求,加以閂鎖,並予以解碼 1204 :請求所包含之訊號持續過長? 1206 :循序請求? 1208 :使用閒置週期遮罩請求 1210 :使用忙碌週期遮罩請求 1212 :從屬裝置匯流排處於忙碌狀態? 1214 :設定請求之執行順序為最低優先 I2639lQLf.doc/006 I2639lQLf.doc/006 1216 1218 1220 1222 1224 1226 1228 待從屬裝置匯流排處於閒置狀態 =送執行順序為最高優先之請求至從屬裝置 凊求所包含之訊號持續過短? 轉換延長請求訊號 輸出資料與主裝置之時脈訊號同步? 直接發送輸出資料至主裝置 閃鎖輸出資料,以待主裝置接收It can be seen from the above description that the multi-frequency bus bar conversion connection method and device proposed by the present invention is sufficient to overcome the shortcomings of the prior art, and to convert the bus bars which are connected with different clock frequencies. Although the present invention has been disclosed in the above preferred embodiments, it is intended that the present invention, and those skilled in the art, may make some modifications and refinements without departing from the spirit of the invention. The scope of the invention is subject to the definition of the patent. [Simplified description of the drawings] H is an example of the use of the embodiment of the multi-faceted flow conversion connection device proposed by the present invention. J 的 - ΐΛίΓΛ is the timing diagram of the multi-frequency bus conversion connection device, e, Huai/machine row clock signal and clock enable signal proposed by the present invention. 1263 Fox _ Figure jA to Figure 5C are structural diagrams of a consistent embodiment of the multi-frequency sink proposed by the present invention.褥 逑 逑 逑 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The second is the multi-frequency bus conversion connection device proposed by Erming. The actual example conveys the signal timing diagram when the request is received earlier. Fig. 8 is a timing chart showing the timing of the transmission of the succession write request by the cautionary embodiment of the multi-faceted flow switching connection device proposed by the present invention. Fig. 9 is a timing chart showing the timing of transmitting a continuous read request by the embodiment of the noodle-side flow conversion switching device of the present invention. FIG. 10 is a timing diagram of signals when a request for simultaneous processing of a multi-frequency bus conversion connection device according to the present invention is performed. FIG. 1 is a timing diagram of signals when an extension request signal is converted according to an embodiment of the multi-frequency bus conversion connection device proposed by the present invention. Figure 12 is a flow chart showing an embodiment of a multi-frequency bus conversion connection method according to the present invention. [Description of Pattern Marking] 101: Multi-frequency busbar switching connection device 102, 103: Master device 104, 105: Slave device 106, 107: Clock-enabled signal 108: Standard clock signal 109, 110, 111, 112: Confluence Row 5: Multi-frequency busbar conversion connection device 19 1263 tender wf.doc/006 5〇1: standard clock signal 502, 503: clock enable signal 508: receiving module 509: receiving device 510: finite state machine 511: mask logic module 512: mask logic device 513: arbitration transfer device 514: arbiter 515 · · transfer multiplexer 516: conversion extension module 517: transfer extension device 518: clock module 519: clock Device 520: Response Module 521: Responsive Latch 522: Respond to multiplexer 1202: Receive request, latch, and decode 1204: The signal contained in the request continues to be too long? 1206: Sequential request? 1208: Mask request with idle period 1210: Mask request with busy period 1212: Is the slave bus busy? 1214: The execution order of the setting request is the lowest priority I2639lQLf.doc/006 I2639lQLf.doc/006 1216 1218 1220 1222 1224 1226 1228 The slave device bus is in an idle state = the execution order is the highest priority request to the slave device Does the included signal continue to be too short? Conversion extension request signal Output data is synchronized with the clock signal of the main device? Directly send the output data to the main device, the flash lock output data, to be received by the main device
Ml、M2 :主裝置 si、s2 :從屬裝置Ml, M2: main device si, s2: slave device
clock :標準時脈訊號 clockx:主裝置匯流排時脈訊號 clock—enx :對應主裝置的時脈致能訊號 dockn第-主裝置所屬匯流排的時脈訊號 d〇ck2:第二主裝置所屬匯流排的時脈訊號 dock_enl :對應第-主裝置的時脈致能訊號 dock—en2 :對應第二主襄置的時脈致能訊號 clocks :從屬裝置的匯流排時脈訊號 d〇ck_enS :對應從躲置的時脈致^訊號 A、Bl、B2 :請求的讀取或寫入位址 A+4 :連續請求的第二個讀取或寫入位址 A+8 :連續請求的第三個讀取或寫入位址 busy :表示忙碌週期 cn、d2、d3:從屬裝置所回應的輸出資料 data卜她2、她3 :請求所包含的欲寫入資料 21 c/006 1263¾^ idle :表示閒置週期 INCR ··表示目前請求為連續請求之一部分 nons :表示目前請求為非循序請求 seq :表示目前請求為循序請求 single ··表示目前請求並非連續請求之一部分Clock: standard clock signal clockx: master device bus clock signal clock_enx: corresponds to the clock-enabled signal of the master device dockn the clock signal of the busbar to which the master device belongs d〇ck2: the busbar of the second master device The clock signal dock_enl: corresponds to the clock-enabled signal of the first-master device dock-en2: the clock-enabled signal corresponding to the second master device clocks: the slave bus signal of the slave device d〇ck_enS: corresponding to hiding Set the clock to ^ signal, A, Bl, B2: the requested read or write address A + 4: the second read or write address A + 8 of consecutive requests: the third read of consecutive requests Take or write the address busy: indicates the busy period cn, d2, d3: the output data responded by the slave device datab 2, her 3: the request contains the data to be written 21 c/006 12633⁄4^ idle : indicates idle The period INCR ·· indicates that the current request is part of the continuous request nons: indicates that the current request is a non-sequential request seq: indicates that the current request is a sequential request single ·· indicates that the current request is not part of a continuous request
22twenty two
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