TWI263905B - Method and apparatus for interconnection of multiple buses with different clock frequencies - Google Patents

Abstract

A method and an apparatus which are used in a computer system for interconnection of multiple buses with different clock frequencies. The main steps of the method include: receive a request which is sent from a master to a slave; if the request signal spans too many cycles so that the slave will receive repeated requests, then mask redundant cycles of the request signal lest the slave receives repeated requests; transfer the request to the slave; if the request signal spans too few cycles so that the slave will not be able to receive the request, then lengthen and adjust the request signal such that the request signal is synchronous to the clock cycles of the slave; and transfer the response data of the slave back to the master.

Description

13692twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a method and apparatus for converting a busbar connected to a computer system, and in particular to a plurality of different connection clock frequencies using different clock frequencies The method and device of the bus bar. [Prior Art] In the electric system, the bus is a very important component. With the bus bar, the central processing unit (Central P ssing unit, hereinafter referred to as CPU), memory, and peripheral devices are important. Components can communicate with each other. The components connected to the busbar can be divided into two types: a master device and a slave device. The master device is a sender of a request, such as a CPU, and the slave device is a slave device. . The role of the bus is to pass the request back and forth and the response after the request is executed. The sharing of all components of the muscles is naturally a performance bottleneck, because only the enchanting device can make the (four) stream in the same time, and other master devices must first request the execution of the request if they want to send the request. Therefore, it has been proposed to place multiple busbars in the system, so that the requests sent by the master devices on different busbars can be executed simultaneously on their respective busbars, for example, the muhi seven AHB (5) alone (10) proposed by ARM.

High-Performance System Bus) is one of them. After having multiple bus bars, they must be able to communicate with each other, and in the multi-layer AHB architecture, it is achieved through the transfer matrix (disconnected). The so-called transfer transfer is a multi-fine flow switch connection. The device can be used to relocate the suburbs, and the subordinate 1263 fox f._6 device on the flow slab without affecting the operation of other busbars. However, it is not mentioned in the multi-layer AHB specification. There are problems with different clock frequencies to the bus, so there is currently no standard solution for how the switch matrix connects multiple bus bars with different clock frequencies.

U.S. Patent Application No. 20020162043 proposes an AMBA

(Advanced Microcontroller Bus Architecture) The architecture of the connection between AHB and APB (Advanced Peripheral Bus) allows the master device on the higher speed bus (AHB) to use the slaves on the lower speed bus (ApB). The situation in which the device is on a higher level. In addition, this architecture can only be used in systems with two bus bars and not in systems with more than three bus bars. Therefore, we need a more flexible solution to convert the use of connection three without the four-word _ stream, and overcome the shortcomings of the previous lin. SUMMARY OF THE INVENTION The present invention proposes a conversion connection method, in which the above-mentioned and other objects are achieved by connecting a plurality of different clock frequencies to achieve the above and other objects. The main steps are as follows: Receive [2, the machine row - the master device sends to - the slave device. Very clear" 'This May is too long, the master device clock frequency is higher than the slave device, and the tiger cub receives this request' This device is the device reset device that repeatedly receives the request, and then forwards the request to "Load 12633⁄43⁄4 iwf.doc/006. The included signal continues to be too short. The master device clock frequency is higher than the slave I, so that the slave device does not have time to receive. The request, the job change extends the request too short, synchronizes the request signal with the slave device's clock, and forwards the output data that the slave device responds to the master device. 1 From another point of view, the present invention further proposes A multi-frequency busbar conversion connection I is disposed, and the device is coupled between a plurality of busbars, including a module, a mask logic module, an arbitration transfer device, and a conversion extension group. And a response module, the receiving module is coupled to the bus bar and includes all the bus bars of the main device, and receives and outputs a request, wherein the request is sent by the master device to a slave device. The mask logic module Receiving the request output by the receiving module, if the signal included in the request continues to be too long, so that the slave device repeatedly receives the request, masking the redundant signal period of the request, so that the slave device does not repeatedly receive the request, and outputs the mask The arbitration transfer device receives the request output by the receiving module, receives the masked request output by the mask logic module, schedules the execution order of the request sent to the same bus, and outputs the mask according to the execution order. The request after the cover. The conversion extension module receives the request output by the arbitration transfer device, and if the signal included in the request continues to be too short, so that the slave device does not receive the request, the conversion extends the short signal of the request to make the request The signal is synchronized with the slave device's clock, and the extended conversion request is sent to the slave device. The response module receives the slave device. One of the respondents rotates the data and forwards the output data to the host device. According to the preferred embodiment of the present invention, the method and the present invention provide a method for transmitting request and response requests between multiple bus bars. I26393〇9^twfd〇c/〇〇6 output data, and can mask or extend the request signal cycle, should be different, the clock difference between the bus, so can achieve the advantages of (4), that is, conversion Connecting a plurality of bus bars using different clock frequencies. The above and other objects, features and advantages of the present invention will become more apparent and obvious, and a preferred embodiment will be described hereinafter with reference to the drawings. The description is as follows: 17 v [Embodiment] The multi-frequency bus switching connection device proposed by the present invention is improved according to the prior art conversion matrix, and can connect any number of bus bars, each bus bar Any number of masters and slaves can be included. For the sake of simplicity, the following embodiments connect only two master devices and two slave devices, each occupying a separate bus bar, such as the use case illustrated in FIG. In Fig. 1, the multi-frequency busbar switching connection device 〇1 is connected to four busbars, which are labeled as 1〇9 to 112, respectively. The main device 1〇2 is coupled to the bus bar 109, the main device 103 is coupled to the bus bar 11〇, the slave device 1〇4 is coupled to the bus bar 111, and the slave device 1〇5 is coupled to the bus bar 112. In this embodiment, both busses Hi and 112 use the highest clock frequency, and busses 109 and 11 〇 use a lower clock frequency. There must be a multiplier relationship between the clock frequencies of these busses, that is, the highest clock frequency must be an integer multiple of the other lower clock frequencies. In order to transmit a request and a response after the execution of the request between a plurality of bus bars using different clock frequencies, the multi-frequency bus conversion connection device 101 must refer to various different bus clock frequencies, so there is 1〇 6, twf.doc/006 1263905 13692t 1〇7 and these three input signals. The standard clock signal (10) is the highest frequency clock signal, and is also a multi-frequency bus conversion connection device 101, and a clock signal used by the bus bars 111 and 112. 1〇6 and 1〇7 should originally be the clock signals used by the busbar tearing and 110, but because of the use of multiple clock signals of different frequencies in the same circuit device, the design difficulty and complexity will increase. Therefore, it will be changed to 1 () 7 to correspond to the light signal of the bus and m (four) pulse respectively. This clock enable reduction can be supplied externally or can be generated by the multi-frequency bus conversion connection device 101 based on the highest frequency standard clock signal 1〇8. The so-called clock enable signal is used in the multi-frequency bus conversion connection device proposed by the present invention instead of the S-stream clock signal. The clock-enabled signal and the bus bar have a (-) correspondence between the (4) clock words, and the frequency of change is related to the standard clock signal, and is usually at a low potential, only in each cycle of the corresponding bus clock frequency. At the end, a standard _ cycle of high practice appears, so it can replace all the bus line signals with the same frequency as its own. Figure 2 shows the timing_ between the standard clock signal cl〇ck, the bus clock signal cl〇ckx and the clock enable signal d〇ck. The standard time pulse #bdQek of the towel of Fig. 2 is the same as the frequency of the bus signal ^lockx, so the clock enable signal cl〇ck starts at a high potential. Figure 3 is a similar phase, only the standard time pulse \ Cl〇ck frequency is twice the bus clock signal clockx, so when the signal tiger cl0ck_enx occurs once every two cycles, That is, at the end of each cycle of the bus pulse signal cl〇ckx, a high level of one cycle occurs. The timing of the money is also similar, in which the standard clock signal 9 I263^0l, d〇c/〇〇6 clock is four times the frequency of the bus clock signal d〇ckx. It can be seen from Fig. 4 that the day-to-day pulse-enable signal clock-enx has a high potential every four cycles. From Fig. 2 to Fig. 4, it is possible to infer the situation at various magnifications. Fig. 5C is another embodiment of the multi-frequency busbar switching connection device, = structure diagram. Figure 5 shows a portion of the request for transfer from the host device to the slave device (in addition, the clock module 518 shown in Figure 5B and the response module 52A shown in Figure 5C), wherein the multi-frequency bus The switching device 5 is connected to two main devices (labeled M1 and M2) and two slave devices (labeled as si and S2), and the master device and the slave device also each occupy a bus bar. In this embodiment, the clock frequency of the master device M1 and the slave device si is twice that of the master device M2 and the slave device. Requests from the master devices M1 and M2 first enter the receiving module 5〇8, and the receiving device 509 latches the request signal and decodes it when the clock enable is high. Each bus bar containing the master device has a corresponding receiving device 509 that receives the request sent by the bus bar. The receiving device 509 uses the clock of 501 and uses the clock enable signal 5〇2, 5〇3 as the enable signal for latching the corresponding bus signal. Next, the decoded request enters the masking logic (masking 1〇gic). If the request signal continues for too long, the slave device repeatedly receives the request, masking the mask within the logic module 511. The logic device 512 will mask the request for the shouting of the hometown to receive the request. A more detailed explanation of the mask of the request. After leaving the mask logic module M1, the request signal will enter the arbitration transfer device 513. Here, if there are multiple requests sent to the same 126-position f.d_ arbiter 514, the order of these requests will be scheduled, and then the order will be executed to execute the signal, so that the corresponding transfer multiplexer (four) handleler) 515 sends the request with the highest priority to the slave device. There is only one arbiter 514 among the !t cutting clothes sets 513, and the transfer multiplexer 515 has a one-to-one correspondence with the bus bars containing the slave devices. Next, the request signal will enter the conversion extension module 516. If requested, the duration of the number is too short, usually because the clock frequency of the master device is higher than the clock solution of the slave device, so that the device does not have time to receive the request, and the corresponding conversion extension device 517 converts the extension request signal. The request xin=number is synchronized with the slave device's clock signal so that the slave device can receive the May request. The conversion extension f 517 also has a corresponding relationship with the bus bar containing the slave device. However, in this embodiment, since the clock frequency of the slave device S1 is the highest, the corresponding conversion extension device is not required - 517 〇 leaving the conversion The extension group 516 reads, and the request is shouted to enter the bus, which is received by the slave device si or n. As for the fmite state machine 510, it is responsible for generating a status signal, and the output secret wire receiving module 508 and the mask logic module 5 are used to determine an appropriate timing to latch and mask the slave device. request. FIG. 5B illustrates the clock module 518 and the clock device 519 responsible for generating the clock enable signal. As shown, each clock device 519 is responsible for generating a clock enable signal (labeled 502 and 503 in the figure) based on the quasi-clock signal 501, and the clock device 519 is used with all bus bars. There is a one-to-one correspondence between pulse frequencies. In fact, it is necessary to generate a clock-induced π-energy signal, for example, so that the (four) single-counting handsome (four) (four) can be born, so the multi-frequency busbar switching connection device does not need to include the clock module 518, but directly receives the clock from the outside. Can signal. Figure 5C shows the response module 52〇 that is responsible for sending the response sent by the slave device after the request is executed to the master device, and the response (10) device 521 and the response multiplexer 522 included in the response module 52〇. For the sake of simplicity, FIG. 5C shows only a set of response flashers 521 and response multiplexers 522 that communicate with slave devices sl and the master device. The actual response flash locker 521 and response multiplexer 522 have a one-way relationship with the busbars containing the slave devices. Whenever the slave device sl produces an output (4), it is divided into two paths, - the gate locker 521_ is temporarily stored, and the other route directly reaches the response multiplexer 522. If the data is synchronized with the clock of the master device M2, the response multiplexer 522 will directly send the output data to the master device M2, otherwise the output will be outputted after responding to the f-shackle H 521 _ (four), waiting for the master device M2 to Received when the clock is synchronized. In the following, some signal timing diagrams are taken as an example to illustrate how the present embodiment transfers requests and responses back and forth between bus channels of different clock frequencies. The bus signal and transmission protocol used in the following examples are all from the advanced micro controller bus architecture proposed by arm.

Microcontroller Bus Architecture (referred to as AMBA), which is the Advanced High-performance System Bus (AHB). Further, unless otherwise stated, in the following examples, the clock frequency of the master device is only half of the slave device (e.g., master device M2 and slave device sl in Fig. 5A). 12 f.doc/006 To simplify the explanation, the following table is an explanation of all the signals in the example. Many bus signal names are in the format of Hxxxx or Hxxxx-s. They are actually the same signal, but the position is different. To the ''M, the signal at the end appears on the busbar to which the main device belongs. The signal ending with "~s," appears on the busbar of the slave device. The following table is explained by the name of Hxxxx.

13 c/006 1263 _ signal name clock description clockx clock enx standard 1 pulse signal

F-set clock frequency corresponding to the clock frequency clocks clock ens name :: device bus clock frequency: corresponding _ enable

HADDR

HBURST

HRDATA HREADY HTRANS

HWDATA HWRITE currently requests _, job s stands for non-still rrtlfi, that is, a single request or a (four) wide first request for a single request; seq represents a monthly sequence, which is a set of consecutive requests = after the single-request; busy represents the busy cycle, di i come to the coffee in this embodiment; to j, hold, and only the long request signal cycle, close the high-potential table request for the request _ form 1, the signal description of Figure 6 to Figure 11B 14 1263 overview _ can be seen from Figure 6, the signal will appear in the main device bus, after a series of processing such as lock, decode, mask, etc., appear in the slave device Bus bar. In this embodiment, when the rising edge of the standard clock signal cl〇ck is high, and the clock enable signal clock_enx is at a high level, the request from the main device is flashed. The signals on the two bus bars, except for HTRANS, will not change the contents of the other signals. In this example, the signal is too long because the clock frequency of the master device is low. As shown in the figure, in this embodiment, the idle period is used to mask the previous period of the HTRANS signal, leaving the next period unchanged, so that the slave device only sees the next week's HTRANS signal, so it will not Repeat the request. Fig. 7 is a timing chart of signals when a single read request is transmitted in this embodiment. The real k example will be at the rising edge of the standard clock signal cl〇ck, the hreaDY s signal is at a high potential, and the clock enable signal d〇ck-enx is at a low potential, latching and forwarding the output data of the slave device response dl To the busbar to which the master device belongs, to be received by the master device. Figure $ is a timing diagram of signals when the continuous write request is transmitted in this embodiment. The group continuously asks for multiple single requests. The so-called continuous write is to write a series of data to consecutive addresses. The consecutive write requests in Figure 8 are co-packaged: ^ writes to the request, where only the first one is a non-sequential request (htrans is non-sequential), and the latter two are sequential requests (htrans signal, SeqUential). As can be seen from the figure, the mask pattern of consecutive requests is different from that of the single-4. The first request is masked by the idle period, and the next two periods are masked by the busy period. The busy cycle is used because the transport protocol requires that no idle cycles can occur in subsequent sequential requests. No 15 12639^^—06 will be treated as a non-sequential request, destroying the structure of consecutive requests. After masking, each single request HRANNS signal is only valid for the last _ cycle, so the slave does not repeatedly receive the request. Fig. 9 is a timing chart showing the signal when the continuous read request is transmitted in the embodiment. The so-called continuous reading is to read a series of data from a continuous address. The sequential read request of Figure 9 contains three read requests. It can be seen from the figure that three pieces of output data (dl, d2, and d3) are sequentially latched to the master sink ‘waiting for master reception. FIG. 10 is a timing diagram of signals simultaneously sent by two master devices to the same slave device, where cloclcl and clock2 are bus-station signals of the first master device and the master device, respectively, clock_enl and ci〇ck En2 is a clock-enabled signal corresponding to the first master device and the second master device, respectively. ^ The clock frequency of a master device is equal to the slave device (for example, the master insult M1 and the slave device sl in FIG. 5), and the clock frequency of the second master device is only - half of the slave device (for example, FIG. 5Α# The resident device (10) and the slave device sj). As for the bus signal, the name is followed by "a Ml," indicating that it is on the busbar of the first master device, and the name is followed by "~M2," which is on the busbar of the second master device. As can be seen from Fig. 10, the arbitration transfer device of the present embodiment (in FIG. 5A::transfer=genus: 2: from the request scheduling sequence of one master device) is forwarded to each of the chores of the company. aW4 520 In the example so far, the clock frequency used by the master device is not set to 16 Ϊ 2639 Μ twf.doc/006 f. Figure UA and Figure UB show this situation. In the figure, therefore, in order to allow the slave device to receive the request, the long request signal is made so that it does not need to convert the extended request signal with the clock signal of the slave device, and the figure does not need to be converted. Convert extended request signals. In this embodiment, the request signal is delayed by -2, and is extended by two times, so that the connection bus is converted to 1, and the step 12〇2 receives the request from the main skirt, and flashes it, = (4), and is processed by the surface. . Then the signal contained in step 12G4 is too long, so that it is 'if not' directly jumps to step 1212, if it is ^ then = ^ further determines whether the request is a sequential request, if not I6 2 swollen with ^ cycle The mask requests an extra signal cycle 2" privately repeats the request, and if so, requests an extra signal cycle at m = mask. ^d recording cycle The next two steps U12 will determine that the slave device is busy. If not, then _step (4) m4 will print (4) the execution order of the request is the lowest priority, the step will be in the master device and the slave The device then forwards the current step to the highest priority request to the slave device when the device is synchronized. The intention from step 1212 to step 1218 is to schedule the requests sent to the same bus to be executed and then forward them to the slave device for execution. The request at this time has not been actually received by the slave device. Before this, step 1220 first determines whether the signal included in the request continues to be too short, so that the slave device will not have time to receive the request, and if so, step 1222 will convert the extension request. A short signal in the middle allows the slave device to receive the request. The slave then receives and executes the request. Subsequent step 1224 determines whether the output data responded to by the slave device after execution of the request is synchronized with the master device clock signal. If so, step 1226 will send the output directly to the master device, otherwise step 1228 will first latch the output data to be received when the master clock is synchronized. X ^

It can be seen from the above description that the multi-frequency bus bar conversion connection method and device proposed by the present invention is sufficient to overcome the shortcomings of the prior art, and to convert the bus bars which are connected with different clock frequencies. Although the present invention has been disclosed in the above preferred embodiments, it is intended that the present invention, and those skilled in the art, may make some modifications and refinements without departing from the spirit of the invention. The scope of the invention is subject to the definition of the patent. [Simplified description of the drawings] H is an example of the use of the embodiment of the multi-faceted flow conversion connection device proposed by the present invention. J 的 - ΐΛίΓΛ is the timing diagram of the multi-frequency bus conversion connection device, e, Huai/machine row clock signal and clock enable signal proposed by the present invention. 1263 Fox _ Figure jA to Figure 5C are structural diagrams of a consistent embodiment of the multi-frequency sink proposed by the present invention.褥 逑 逑 逑 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The second is the multi-frequency bus conversion connection device proposed by Erming. The actual example conveys the signal timing diagram when the request is received earlier. Fig. 8 is a timing chart showing the timing of the transmission of the succession write request by the cautionary embodiment of the multi-faceted flow switching connection device proposed by the present invention. Fig. 9 is a timing chart showing the timing of transmitting a continuous read request by the embodiment of the noodle-side flow conversion switching device of the present invention. FIG. 10 is a timing diagram of signals when a request for simultaneous processing of a multi-frequency bus conversion connection device according to the present invention is performed. FIG. 1 is a timing diagram of signals when an extension request signal is converted according to an embodiment of the multi-frequency bus conversion connection device proposed by the present invention. Figure 12 is a flow chart showing an embodiment of a multi-frequency bus conversion connection method according to the present invention. [Description of Pattern Marking] 101: Multi-frequency busbar switching connection device 102, 103: Master device 104, 105: Slave device 106, 107: Clock-enabled signal 108: Standard clock signal 109, 110, 111, 112: Confluence Row 5: Multi-frequency busbar conversion connection device 19 1263 tender wf.doc/006 5〇1: standard clock signal 502, 503: clock enable signal 508: receiving module 509: receiving device 510: finite state machine 511: mask logic module 512: mask logic device 513: arbitration transfer device 514: arbiter 515 · · transfer multiplexer 516: conversion extension module 517: transfer extension device 518: clock module 519: clock Device 520: Response Module 521: Responsive Latch 522: Respond to multiplexer 1202: Receive request, latch, and decode 1204: The signal contained in the request continues to be too long? 1206: Sequential request? 1208: Mask request with idle period 1210: Mask request with busy period 1212: Is the slave bus busy? 1214: The execution order of the setting request is the lowest priority I2639lQLf.doc/006 I2639lQLf.doc/006 1216 1218 1220 1222 1224 1226 1228 The slave device bus is in an idle state = the execution order is the highest priority request to the slave device Does the included signal continue to be too short? Conversion extension request signal Output data is synchronized with the clock signal of the main device? Directly send the output data to the main device, the flash lock output data, to be received by the main device

Ml, M2: main device si, s2: slave device

Clock: standard clock signal clockx: master device bus clock signal clock_enx: corresponds to the clock-enabled signal of the master device dockn the clock signal of the busbar to which the master device belongs d〇ck2: the busbar of the second master device The clock signal dock_enl: corresponds to the clock-enabled signal of the first-master device dock-en2: the clock-enabled signal corresponding to the second master device clocks: the slave bus signal of the slave device d〇ck_enS: corresponding to hiding Set the clock to ^ signal, A, Bl, B2: the requested read or write address A + 4: the second read or write address A + 8 of consecutive requests: the third read of consecutive requests Take or write the address busy: indicates the busy period cn, d2, d3: the output data responded by the slave device datab 2, her 3: the request contains the data to be written 21 c/006 12633⁄4^ idle : indicates idle The period INCR ·· indicates that the current request is part of the continuous request nons: indicates that the current request is a non-sequential request seq: indicates that the current request is a sequential request single ·· indicates that the current request is not part of a continuous request

twenty two

Claims (1)

Lj〇92twf.doc/006 X. Patent application scope: 1. A multi-frequency bus conversion connection method includes the following steps: (a) receiving a request, wherein the request is sent by a master device to a slave device; b) if the signal contained in the request continues to be too long, so that the slave device repeatedly receives the request', the unnecessary signal period of the request is masked to prevent the slave device from repeatedly receiving the request; / (c) forwarding the request to The slave device; (d) if the signal included in the request continues to be too short, so that the slave device does not receive the (4) request, the conversion extends the request signal, and the signal of the request is synchronized with the clock signal of the slave device. And (e) forwarding the output data responsive by the slave device to the main wearer. Method 2, the multi-frequency bus two-connected party described in item 1 latches the request; and decodes the request. 3. The multi-frequency method according to claim 1, wherein the step (b) further comprises: the bus conversion connection request, and if the request is a non-sequential request, the inter-period mask is used. If the request is a sequential request, , 'The account is covered by the request. The multi-frequency busbars described in the item are generated in the main H and the subordinate assembly 23 1263905 13692twf.d〇c/〇〇6 5 · The multi-frequency bus as described in claim 4 of the patent scope The conversion connection party is in the step where the step (C) further includes ································································································ After the bus is in an idle state, the transfer execution order is the highest priority request to the slave aggregation. 6. If you apply for a patent scope! The multi-frequency bus conversion connection method described in the item, wherein the step (e) further comprises: - if the output data is synchronized with the clock signal of the main device, directly transmitting the round-off data to the main device; and If the output data is not synchronized with the clock signal of the master device, the output data is flashed to be received by the master device. 7--a multi-frequency busbar conversion connection device, between a plurality of rows, comprising: a receiving module, which is connected to all the busbars of the busbars, and receives and outputs a request, wherein The request is sent from a master to a slave device; I place a mask logic module to receive the request output by the receiver module, and the signal on the right side of the request continues to be too long, so that the slave device is placed Receiving the request, (4) covering the request for the request for money, so as to prevent the device from repeatedly receiving the request, and outputting the request after the mask; μ, an arbitration transfer device receiving the output from the receiving module The request after the mask is sent to the same, the order of execution of the request to the same-bus, and in accordance with the execution order = 24 I2639ffiL f.doc/006 after the mask; The group receives the output from the arbitration transfer device. If the signal included in the request continues to be too short, so that the slave = does not receive the request, the conversion extends the signal that the request is too short, so that the signal is Wei The difficult time is rushed, and the request is sent to the slave device; and a response module receives the response from the slave device and forwards the output data to the master device. Pull out the bellows, 8. If you apply for the multi-faceted flow conversion connection described in item 7 of the special fiber, the 'including: μ-clock module' receives the standard pulse signal, for these busbars For all clock frequencies used, each generates a clock-enabled signal, and uses the clock signals used by the bus bars, and outputs the signals to the receiving module_conversion extension module. (4) 9. The multi-frequency bus conversion connection device of claim 8, wherein the frequency of the standard clock signal is equal to the highest of the clock frequencies of the bus bars. The multi-frequency bus conversion connection described in claim 9 of the patent application scope: wherein the frequency of the change of the clock-enabled signals is related to the standard clock and the clock-enabled signals Only for the corresponding clock frequency, corresponding to the end of each cycle, a high potential of one cycle occurs, and the remaining cycles are all low. U. The multi-frequency bus conversion connection according to item 8 of the scope of the patent application, wherein the clock module further comprises: 25 1263 viewing twf.doc/006 - more than one clock device, secret Between the output terminals of the pulse module, each of them corresponds to (4) the clock frequency, and each of them receives the standard clock, and generates and outputs the clock enable corresponding to the frequency. Signal. 12. The multi-surface flow reversing device of claim 7, wherein the receiving module further comprises: - more than one receiving device - each corresponding to - a main bus bar - w lock from the bus bar - request, skew the request, and output the decoded request to the secret module and the arbitration transfer device. When the mask logic 杈 group masks the request, the request is - the non-sequential request, the unused period is fresh, the request is If the request is a _ sequential request, the busy cycle is used to mask the request. The multi-frequency bus-discharging device of claim 7, wherein the mask logic module further comprises: , and more than one mask logic device, less than the receiving module and the cutting Between the devices, each of the corresponding busbars including the main device receives the scale ship mask-like arbitration transfer device from the ship's flow row that requests the mask logic group. In the above, the multi-frequency busbar conversion connection device described in the seventh aspect of the patent scope, the medium-side arbitration transfer device further comprises: - an arbitrator, receiving the output of the contig Request, schedule 26 1263 9 - the request number sent to the same bus; and the order 'and turn out - permit the execution message; more than one transfer multiplexer, each of the bus, receive the arbitration cry, : ???including the permission execution signal outputted by the slave device mask logic module and the execution sequence, and outputting the request to the "arbiter arranged by the arbitrator", as set forth in claim 7 of the patent scope, wherein The conversion extension module further includes: the sink-to-row conversion connection of the busbars, the respective ones of the corresponding ones, the slaves, the slaves, the request, the execution of the conversion, the extension of the replacement, and the request to the corresponding bus匕' and output the multi-frequency confluence and re-connection of the multi-frequency convergence device, the corresponding ones contain the slave device lock and output the round capital contribution; receive the wheel_'receive the corresponding corresponding to the round-up request locker The bus thief fills in and reads Send the output Lin 27