TWI263270B - A semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device - Google Patents

A semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device

Info

Publication number
TWI263270B
TWI263270B TW92103993A TW92103993A TWI263270B TW I263270 B TWI263270 B TW I263270B TW 92103993 A TW92103993 A TW 92103993A TW 92103993 A TW92103993 A TW 92103993A TW I263270 B TWI263270 B TW I263270B
Authority
TW
Taiwan
Prior art keywords
semiconductor
semiconductor device
region
fabricating
metal
Prior art date
Application number
TW92103993A
Other languages
Chinese (zh)
Other versions
TW200305942A (en
Inventor
Rolf Stephan
Manfred Horstmann
Karsten Wieczorek
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10209059A external-priority patent/DE10209059B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200305942A publication Critical patent/TW200305942A/en
Application granted granted Critical
Publication of TWI263270B publication Critical patent/TWI263270B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers, whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer.
TW92103993A 2002-03-01 2003-02-26 A semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device TWI263270B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10209059A DE10209059B4 (en) 2002-03-01 2002-03-01 A semiconductor element having different metal-semiconductor regions formed on a semiconductor region, and methods of manufacturing the semiconductor element
US10/259,016 US7115464B2 (en) 2002-03-01 2002-09-27 Semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device

Publications (2)

Publication Number Publication Date
TW200305942A TW200305942A (en) 2003-11-01
TWI263270B true TWI263270B (en) 2006-10-01

Family

ID=27789718

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92103993A TWI263270B (en) 2002-03-01 2003-02-26 A semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device

Country Status (3)

Country Link
AU (1) AU2002359813A1 (en)
TW (1) TWI263270B (en)
WO (1) WO2003075326A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE509369T1 (en) 2006-09-29 2011-05-15 Nxp Bv SILICIDE FORMATION ON A WAFER

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656519A (en) * 1995-02-14 1997-08-12 Nec Corporation Method for manufacturing salicide semiconductor device
JP2980057B2 (en) * 1997-04-30 1999-11-22 日本電気株式会社 Method for manufacturing semiconductor device
KR100257075B1 (en) * 1998-01-13 2000-05-15 김영환 Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
AU2002359813A8 (en) 2003-09-16
TW200305942A (en) 2003-11-01
WO2003075326A3 (en) 2004-04-01
AU2002359813A1 (en) 2003-09-16
WO2003075326A2 (en) 2003-09-12

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees