1259469 15849twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的使用方法，且特別 是有關於一種非揮發記憶體的使用方法與更新氓^代也)方 法，係應用於以電街捕卩曰層儲存資料的非揮發記情體上。 【先前技術】 ^1259469 15849twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a method of using a semiconductor device, and in particular to a method and an update method for a non-volatile memory. The method is applied to a non-volatile grammar that stores data in an electric street trapping layer. [Prior Art] ^
近年來，非揮發記憶體成員中的可電除可程式化唯讀 記憶體(E2PROM)及快閃記憶體(flash mem〇ry)已廣泛應用 於各類電子產品中。傳統的E2PR0M及快閃記憶^係^用 浮置閘(FG)來儲存電荷，故單一記憶胞僅能儲存丨位元。 為提南可程式化之非揮發記憶體的資料儲存密度，前 人提出使用電荷捕陷層的新型非揮發記憶體，其可在每一 記憶胞中儲存多位元的資訊，如美國專利υδ6,011，725所 述之氮化矽唯讀記憶體，其單一記憶胞可儲存2位元。請 簽照圖1A，此種多位元記憶胞通常包含夾在兩介電層11〇 與130之間的電荷捕陷層120,此三層11〇〜13〇係位在基 底100與閘極140之間。 電荷捕陷型多位元記憶胞通常使用通道熱電子注入法 (Channel Hot Electron Injection, CHEI)it^f^^(write)# 作。當通道電流方向由源/汲極區150至16〇時，熱電子係 產生在罪近源/汲極區150的通道區中，並被閘極140上的 高正電壓吸引至靠近源/汲極區150的電荷捕陷層12〇中； 反之則電子被吸引至靠近源/没極區160的電荷捕陷層120 中。因此’藉由改變二源/没極之間的電壓高低關係以切換 1259469 15849twf.doc/g 通道電流方向，即可分別寫入此多位元記憶胞的左右兩個 位元。 請參照目1B，電荷捕陷型多位元記憶胞常用的一種抹 ::方^係利用頻帶間穿曝電洞(btbthh)效應，將電洞 電子的儲存位置中。如-記憶胞的左右兩儲存位 白子電子，則該記憶胞之抹除操作即須分別自左右各 仃一次，以分別將電洞注入左右儲存位置中。 教電CHEI法局部注人熱電子時，仍會有少許 =子進入電荷捕陷層120的中間部分而被捕獲ia 戶^由於彻BTBTHH效歧行鎌岐有電 該處捕陷的電子不會被消除，如圖1B所 電子在tt?广欠寫入/抹除循環後，會有不少難抹除 立準)啟㈣壓( ;= 的才呆作窗口（寫入態Vt盥枯 〒双 所示。 〜t與抹除_之差)愈來愈小，如圖5 【發明内容】 法，揮發記憶體的使用方 祙除猶产°了，63 1軍發§己憶體之操作窗σ隨寫入/ 禾除循％次數之增加而愈來愈小的問題。 I現馬In recent years, E2PROMs and flash mem〇ry in non-volatile memory members have been widely used in various electronic products. The traditional E2PR0M and flash memory system use floating gates (FG) to store charge, so a single memory cell can only store the bits. For the data storage density of the stylized non-volatile memory of the South, a new non-volatile memory using a charge trapping layer has been proposed, which can store multi-bit information in each memory cell, such as the US patent υδ6. The nitrided read-only memory described in 011,725, wherein a single memory cell can store 2 bits. Please refer to FIG. 1A. The multi-bit memory cell generally includes a charge trapping layer 120 sandwiched between two dielectric layers 11 and 130. The three layers of 11 〇 13 13 are in the substrate 100 and the gate. Between 140. Charge trapping multi-bit memory cells are usually made using Channel Hot Electron Injection (CHEI) it^f^^(write)#. When the channel current direction is from the source/drain region 150 to 16 ,, the hot electrons are generated in the channel region of the sin near source/drain region 150 and are attracted to the source/汲 by the high positive voltage on the gate 140. The charge trap layer 12 of the polar region 150 is in the middle; otherwise, the electron is attracted to the charge trap layer 120 near the source/nopole region 160. Therefore, by changing the voltage relationship between the two sources and the dipoles to switch the direction of the 1259469 15849twf.doc/g channel current, the left and right bits of the multi-bit memory cell can be written separately. Please refer to item 1B. A type of smear used in charge trapping multi-bit memory cells uses the band-to-band exposure hole (btbthh) effect to store the hole electrons. For example, if the left and right storage bits of the memory cell are white electrons, the memory cell erase operation must be performed once from the left and right sides to inject the holes into the left and right storage locations, respectively. When the CHEI method is used to locally inject hot electrons, there will still be a little = sub-enterment into the middle part of the charge trapping layer 120 and be captured by the ia household ^ due to the complete BTBTHH effect, the electrons trapped there will not Was eliminated, as shown in Figure 1B, after the tt? wide under write/erase cycle, there will be a lot of hard to erase the vertical) (4) pressure ( ; = only stay in the window (write state Vt 盥 〒 The double is shown. The difference between ~t and erased _ is getting smaller and smaller, as shown in Fig. 5. [Invention content] The method of using volatile volatile memory is removed, and the operation of 63 jun ** The window σ is getting smaller and smaller as the number of times of writing/removing increases.
料供—種非揮發記憶體敎新方法，μ “::截層中所累積的難抹除電子-免操作窗J 本發明之非揮發記憶體的使用方法中的非揮發記憶體 1259469 15849twf.doc/g 包^基底二間極與二者間之電荷捕陷層，以及作為源/及極 之第一與第二摻雜區。此方法包括以下步驟(^〜(幻。步 ⑻係，此非揮發記憶體進行多次以電子寫入/以電洞抹除 的痛壞，致使其電荷捕陷層之一特定部分中累積有難抹除 電，。步驟(b)係檢驗此非揮發記憶體之一抹除態啟始電壓 與.玄非揮發§己憶體啟用時之一初始抹除態啟始電壓之差是 否超過-預設值。在步驟(c)中，如步驟⑼之結果為否，即 • 回到步驟繼續使用此非揮發記憶體；如結果為是，則進 行-更新步驟以消除電荷捕陷層之該特定部分中所累積的 電子，之後再回到步驟⑻。 、 在-較佳實施例中，上述更新步驟係將電洞注 捕陷層之該特定部分中。 $何 在某些實施例中，該非揮發記憶體係具有二儲存位置 的電荷捕陷型非揮發記憶體’此二儲雜置分別位在電荷 捕陷層之靠近第-摻雜區的部分與靠近第二摻雜區的部 分，此時電荷捕陷層中會累積電子之特定部分即此電荷捕 鬱陷紅中間部分’而更新步驟則係將電洞注入該中間部分 中。於此情形下，更新步驟例如可使用頻帶間穿隧熱電洞 (BTBTHH)效應將電洞注入該中間部分中。 •、… 至於使用BTBTHH效應將電洞注入電荷捕陷層之中 間部分的步驟，則例如是先在閘極、基底與第一換雜區上 施加適當電壓以產生BTBTHH效應，並使電洞注入電荷捕 陷層之中間部分之靠近第-摻雜區的部分；然後在問極、 基底與第二摻雜區上施加適當電壓以產生BTBTHH效 7 1259469 15849twf.doc/g ί的:i電洞注入電荷捕陷層之中間部分之靠近第二摻雜 於以上方法中，在閘極及第-與第二摻雜區各自 施加之電壓皆呈多脈衝型態。與同樣利用BTBTHH效庳 ίϊ除抹除用問極電壓與抹除用沒極電壓： , 处更新V驟中施加在閘極之每一脈衝的f庚比古 於前述之抹除用閘極_，且施加 =多的電洞，在每—次脈衝施加之後，^量== ”之—抹除態啟始電壓。‘ 二，記憶體啟用時之初始抹除態啟始 預。又值以下時，即停止施加脈衝。 如是=俞^此，步驟中所施加之一連串脈衝的高度例 亦可。〜而壬階梯狀增加；但各脈衝的高度皆固定 數千^者^多次寫入/抹除循環之多次例如是指係一或 檢驗步，的===。進行更新步驟之 憶體憶體的更新方法’即是在非_己 陷層之—特定部=^難=同抹除的循環’而在電荷捕 荷捕陷層之該特〜1 積有難抹除電子之後，將電洞注入電 新方法的其他二:於。此更 方法的說明中。 承毛月之非揮體使用 1259469 15849twf.doc/g 由於本务明係在非揮一 環之後，進行-更新步 ^體歷經多次寫人/抹除循 抹除電子，所以此非揎〜，肖除電荷捕陷層中所累積的難 不會隨寫入/抹除循的抹除.tvt (低位準叫 口不致隨寫人/抹除循環次d而不斷升高，使其操作窗 為讓本發明之上述和而f來愈小。Material supply - a new method for non-volatile memory, μ ":: difficult to erase electrons accumulated in the intercept layer - free operation window J Non-volatile memory in the use of the non-volatile memory of the present invention 1259469 15849twf. Doc/g includes the charge trapping layer between the two interpoles and the first and second doping regions as the source/pole. The method includes the following steps (^~ (phantom step (8), The non-volatile memory is subjected to multiple times of electronic writing/hole cleaning, so that a certain portion of the charge trapping layer is accumulated in a certain portion of the charge trapping layer. Step (b) is to test the non-volatile memory. Whether the difference between the initial erase voltage and the start voltage of one of the initial erase states when the erased state start voltage is enabled exceeds the preset value. In step (c), the result of step (9) is no. , ie, return to the step to continue using the non-volatile memory; if the result is yes, the -update step is performed to eliminate the electrons accumulated in the specific portion of the charge trap layer, and then return to step (8). In a preferred embodiment, the updating step is to apply a hole to the specific portion of the trap layer. In some embodiments, the non-volatile memory system has a charge trapping type non-volatile memory at two storage locations. The second storage is located in a portion of the charge trapping layer adjacent to the first doped region. a portion near the second doped region, at which point a specific portion of the electron trapping layer accumulates, that is, the charge trapping the red intermediate portion', and the updating step injects a hole into the intermediate portion. In this case The updating step may, for example, inject a hole into the intermediate portion using an inter-band tunneling thermoelectric hole (BTBTHH) effect. •,... As for the step of injecting a hole into the middle portion of the charge trapping layer using the BTBTHH effect, for example, Appropriating voltage is applied to the gate, the substrate and the first impurity-exchanging region to generate a BTBTHH effect, and the hole is injected into a portion of the middle portion of the charge trapping layer close to the first-doped region; and then at the gate, the substrate and the first Appropriate voltage is applied to the two doped regions to produce BTBTHH effect 7 1259469 15849twf.doc/g ί: i hole is injected into the middle portion of the charge trapping layer close to the second doping in the above method, at the gate and the first - versus The voltages applied to each of the two doped regions are in a multi-pulse mode. The same applies to the BTBTHH effect. In addition to erasing the gate voltage and erasing the gate voltage: , the update V is applied to each of the gates. The f-height ratio of the pulse is the same as the above-mentioned erase gate _, and the application of more holes, after each pulse is applied, ^ quantity == "--the erase state start voltage." When the body is enabled, the initial erasing state starts. When the value is below, the pulse is stopped. If it is = Yu ^, the height of one of the series of pulses applied in the step may also be increased. The height of the pulse is fixed by several thousand ^ ^ multiple times of multiple write / erase cycles, for example, refers to the system or the test step, == =. The update method of the memory step of the update step is 'in the The non-self-trapped layer—the specific part=^difficult = the same as the erased cycle', and after the special charge of the charge trapping trap layer has a hard to erase electron, the hole is injected into the other two of the new method: to. In the description of this more method. Non-swing use of Maoyue 1259469 15849twf.doc/g Since the main task is after the non-floating ring, the process of updating - updating the body has been written and erased many times, so this is not 揎~, The difficulty accumulated in the charge trapping layer is not erased by the write/erase cycle. tvt (the low-level quasi-mouth does not rise with the writer/erase cycle d, so that its operation window is Let the above and the f of the present invention be smaller.
=下Γ文轉錄貫施例，並配合所_式，作詳細說 【實施方式】 照圖2，其係繪示本發難佳實施例之非揮發記 用方法的流程圖。在啟用非揮發記憶體之後 (S20(^) ’即進仃多次寫人/抹除循環⑽⑻，其中寫入操作 例如疋彻CHEI㈣將電子局部注人非揮發記憶體的電 荷捕陷層中，且抹除操作例如是利用BTBTHH效應將電洞 局部注入電荷捕陷層中，因此在電荷捕陷層中會殘留難以 抹除之電子(hard-to_erase electrons)。 對電荷捕陷型多位元記憶胞這種將電荷儲存在靠近二 源/汲極區之電荷捕陷層的兩個部分中的雙儲存位置非揮 發記憶胞而言，如欲以CHEI法寫入一側的儲存位置，則 例如可在閘極上加11V，欲寫入側之源/汲極加5V，且在 基底與另一側源/汲極加0V ;如欲以BTBTHH效應抹除一 側的已寫入儲存位置，則例如可在閘極上加一5V，欲抹除 侧之源/>及極加5V，且在基底與另一側源/汲極加0V。 另外，對電荷捕陷型多位元記憶胞之類的雙儲存位置The following is a detailed description of the non-volatile method of the present invention. Referring to Fig. 2, a flow chart of the non-volatile recording method of the presently difficult embodiment is shown. After the non-volatile memory is enabled (S20(^)', the write/erase cycle (10) (8) is performed multiple times, wherein the write operation, for example, the CHEI (4), is used to locally inject the electrons into the charge trapping layer of the non-volatile memory. And the erasing operation is, for example, that the hole is locally injected into the charge trapping layer by the BTBTHH effect, so that hard-to-ease electrons remain in the charge trapping layer. For a double storage location non-volatile memory cell that stores charge in two portions of the charge trapping layer near the two source/drain regions, if it is to be written to the storage location on one side by the CHEI method, for example, You can add 11V to the gate, add 5V to the source/drain to the side, and add 0V to the source/drain on the other side. If you want to erase the written storage location on the side with the BTBTHH effect, For example, a 5V can be added to the gate, the source of the side is removed, and 5V is added, and 0V is applied to the source and the drain of the other side. In addition, for the charge trap type multi-bit memory cell Double storage location
1259469 15849twf.doc/g 非揮發記憶胞而言，其多次寫入/抹除循環所造成之難抹除 電子係位在電荷捕陷層的中間部分，如圖1C所示。 接著，在進行多次寫入/抹除循環之後，檢驗非揮發記 fe、體之抹除態Vt，視其與該非揮發記憶體啟用時之抹除態 Vt之間的差值是否大於預設值(S220)，此預設值例如是1259469 15849twf.doc/g For non-volatile memory cells, the hard-to-erase electrons caused by multiple write/erase cycles are in the middle of the charge trapping layer, as shown in Figure 1C. Then, after performing a plurality of write/erase cycles, the non-volatile mark and the erased state Vt of the body are checked, and whether the difference between the erased state and the erased state Vt when the non-volatile memory is activated is greater than a preset. Value (S220), this preset value is for example
0.2V ^右。如該差值不超過預設值，則回到步驟21〇繼續使用非揮 考X。己fe體，反之’如该差值超過預設值，則進行更新步驟 以消除電荷捕陷層中所累積之難抹除電子，之後再回到步 驟210繼續使用此非揮發記憶體。 上述更新步驟S230例如是將電洞注入電荷捕陷層中累 積=難抹除電子的部分，以消除該處之難抹除電子。在此 種情形下，當轉揮發域胞係如電荷捕陷型乡位元 胞般將電_存在靠近源/汲極區之電荷漏層巾時，此^ 新步驟S230 gP是將電洞注入電荷捕陷層的中間部分 如是利用BTBTHH效應來進行。 岣苓照圖3A〜3B，如欲以BTBTHH效應進行更新牛 驟’則例如可以先在間才亟14〇上施加高於btbth = =所用之閘極電壓的負電壓(Vg)、右源級極區湖上二木 π於BTBTHH抹除操作所用之汲極電壓的正電墨(，、， 在左源/沒極區150與基底1〇〇上加〇v(Vs、外），以: 間偏右的電荷捕陷層12〇下方產生頻帶間穿隨哉電 : ^其:主入上方的電荷捕_ 12G以消除該處的難抹除j 雷^圖3A_ °上述之BTBTHH抹除操作所用之^ i/、/及極電壓例如分別為—5V與5V。 ° 10 1259469 15849twf.doc/g A接著，在閘極140上施加相同的Vg、左源/汲極區150 上把加相同的Vd，並在右源/汲極㉟160與基底1〇0上加 0V(Vs Vb) ’以在中間偏左的電荷捕陷層下方產生 帶間穿隨熱電洞，並使其注入上方的電荷捕陷層12〇以消 除口亥處的難抹除電子，如圖3B所示。當然，將圖3A、犯 之步驟對調，先除去電荷捕陷層120之中間偏左部分中所 累積的難抹除電子，再除去電荷捕陷層12〇之中間偏右部 φ 分中所累積的難抹除電子亦可。 ，圖3A、3B所繪之兩階段更新步驟中的任一階段， 閘電壓vg與汲極電壓Vd各自較佳呈多脈衝型態，其中施 加在閘極140上的每一脈衝的高度皆大於上述 除用之閘極電壓，且施加在源/汲極區15〇或16〇上的每一 脈衝的，度皆大於上述BTBTHH抹除用之汲極電壓。如此 即可在每一次施加脈衝之後，檢驗非揮發記憶體之抹除態 啟始電壓與其啟用時之初始抹除態啟始電壓之差值是否小 =一預設值(例如〇·2ν)，並在該差值小於該預設值時停止 施加脈衝，以免注入過多電洞而使抹除態啟始電壓過低。 另外’上述更新步驟中於閘極14〇、左S/D區15〇或 右S/D區160上所施加之脈衝序列的高度例如是愈來愈 大，而呈階梯狀增加。詳言之，即任一脈衝之高度皆較其 如一脈衝咼出一定值，例如，施加在閘極14〇的負電壓脈 衝可以-0.5V之階差逐步增加，且施加在左或右S/E)區15〇 或160的正電壓脈衝可以〇.1¥之階差逐步增加。各脈衝序 列的咼度亦可採固定方式，例如，施加在閘極丨4〇的每一 11 1259469 15849twf.doc/g 負電壓脈衝的高度可固定為一MV，且施加在左或右S/D區 150或160的每一正電壓脈衝的高度可固定為7.7V。 為證貫本發明之功效，以下特舉一些實驗結果作參考。 〈實驗1> 乂 本貫驗係以FN穿隧效應將電子全面注入電荷捕陷型 夕位元6己胞的電荷陷層中，以模擬其電荷捕陷層的中間 部分累積有難抹除電子的情形。此記憶胞原先之啟始電壓 為1.9V，而在以FN效穿隧應注入電子後的啟始電壓為 5.0V 〇 圖4Α/4Β顯示本發明之模擬實驗中，以高度呈階梯狀 遞增/高度固定之脈衝序列，對上述&FN穿隧效應注入電 子之非揮發記憶體進行更新步驟的結果，其中更新時間為 脈衝日守間之累#值，且每—次脈衝後皆測量記憶胞的啟始 電壓。 卜對圖4A與4B任一者之實驗而言，皆可分為從左S/D 施加Vd脈衝、從右s/D測量通道電流以推得左半部通道 之啟始電壓，以及從右S/D施加Vd脈衝、從左s/d測量 通迢電流以推得右半部通道之啟始電壓這兩部分。在從左 (右)S/D測量記憶胞電麟，於左(右)S/D上所加的電壓足 夠高\使此測量不受左（右）半部電荷捕陷層中所注入之電 子的衫響’而可用以推算右(左）半部通道的啟始電壓，從 而推知電荷麵層之右(左）半部的電子抹除程度。再者， FN效應注入之電子在電荷捕陷層中的分佈係左右 對稱，所以在左S/D施加Vd脈衝與在右S/D施加Vd脈 1259469 15849twf.doc/g 衝所得之結果大致相同0.2V ^ right. If the difference does not exceed the preset value, return to step 21 and continue to use the non-swap X. If the difference exceeds the preset value, an update step is performed to eliminate the hard-to-erase electrons accumulated in the charge trap layer, and then return to step 210 to continue using the non-volatile memory. The above updating step S230 is, for example, injecting a hole into a portion of the charge trapping layer which is accumulated = hard to erase electrons, thereby eliminating the hard-to-erasing electrons there. In this case, when the volatile domain cell, such as a charge trapping type cell, is present in the charge/drain region near the source/drain region, the new step S230 gP is to inject the hole. The intermediate portion of the charge trapping layer is performed using the BTBTHH effect. Referring to Figures 3A to 3B, if the bullish peak is to be updated by the BTBTHH effect, for example, a negative voltage (Vg) higher than the gate voltage used for btbth = =, and a right source level may be applied first. The positive electric ink of the bungee voltage used for the BTBTHH erasing operation on the pole area lake (,,, on the left source/nothing area 150 and the base 1〇〇, 〇v (Vs, outer), to: The right-handed charge trapping layer 12 produces an inter-band crossing 哉: ^: The charge trapping _ 12G above the main input to eliminate the hard-to-remove j Ray ^ Figure 3A_ ° used in the above BTBTHH erasing operation The ^ i / , / and the extreme voltage are, for example, -5 V and 5 V. ° 10 1259469 15849twf.doc / g A, then apply the same Vg on the gate 140, the left source / drain region 150 plus the same Vd, and add 0V(Vs Vb) ' to the right source/drain 35160 and the substrate 1〇0 to create a band-to-slip thermal hole under the center-left charge trapping layer and inject it into the upper charge trap. The trap layer 12 is used to eliminate the hard-to-erase electrons at the mouth of the sea, as shown in Fig. 3B. Of course, the steps of FIG. 3A and the criminal steps are reversed, and the middle left portion of the charge trapping layer 120 is first removed. It is also difficult to erase the electrons, and then remove the hard-to-erase electrons accumulated in the middle right φ of the charge trap layer 12, and any of the two-stage update steps depicted in Figures 3A and 3B. The gate voltage vg and the drain voltage Vd are each preferably in a multi-pulse type, wherein each pulse applied to the gate 140 has a height greater than the above-mentioned drain voltage and is applied to the source/drain region 15 Each pulse on 〇 or 16〇 is greater than the drain voltage of the above BTBTHH erase. This allows the erase voltage of the non-volatile memory to be tested and activated when each pulse is applied. Whether the difference between the initial erasing state starting voltage is small=a preset value (for example, 〇·2ν), and the pulse is stopped when the difference is less than the preset value, so as to avoid injecting too many holes and erasing the state The starting voltage is too low. In addition, the height of the pulse sequence applied to the gate 14 〇, the left S/D region 15 〇 or the right S/D region 160 in the above updating step is, for example, larger and larger, and is stepped. In particular, the height of any pulse is higher than that of a pulse. For example, a negative voltage pulse applied to the gate 14〇 may be gradually increased by a step of -0.5V, and a positive voltage pulse applied to the left or right S/E) region 15 or 160 may be a step of 11. Gradually increase. The intensity of each pulse sequence can also be fixed. For example, each 11 1259469 15849twf.doc/g negative voltage pulse applied to the gate 丨4〇 can be fixed to a MV and applied to the left or right S/ The height of each positive voltage pulse of the D zone 150 or 160 can be fixed to 7.7V. In order to prove the efficacy of the present invention, some experimental results are cited below for reference. <Experiment 1> The 贯 贯 贯 将 将 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以situation. The initial voltage of this memory cell is 1.9V, and the starting voltage after electron injection through FN tunneling is 5.0V. Figure 4Α/4Β shows that in the simulation experiment of the present invention, the height is stepped up/ a highly fixed pulse sequence, the result of the updating step of injecting electrons into the non-volatile memory of the above & FN tunneling effect, wherein the update time is the accumulated # value of the pulse day and the measured memory cell after each pulse The starting voltage. For any of the experiments of any of Figures 4A and 4B, it can be divided into applying a Vd pulse from the left S/D, measuring the channel current from the right s/D to derive the initial voltage of the left half channel, and from the right. The S/D applies a Vd pulse and measures the wanted current from the left s/d to derive the starting voltage of the right half channel. Measuring the memory cell from the left (right) S/D, the voltage applied to the left (right) S/D is high enough that this measurement is not injected into the left (right) half charge trapping layer. The electronic shirt can be used to estimate the starting voltage of the right (left) half channel, thereby inferring the degree of electron erasure of the right (left) half of the charge surface layer. Furthermore, the distribution of electrons injected by the FN effect in the charge trapping layer is bilaterally symmetric, so the Vd pulse applied to the left S/D is approximately the same as the result of applying Vd pulse 1259469 15849 twf.doc/g in the right S/D.
請見圖4A，該部分實驗所用之脈衝寬度為i〇ms， 極電壓㈤脈衝起始值為—8V，其後每—負電壓脈衝之言 度皆比其前-脈衝多—Q 5V ;沒極電壓(Vd)脈衝起始值= 6V ’其後每-脈衝之高度皆比其前—脈衝多Q iv。由圖 4A可知，此種使用高度呈階梯狀增加之脈衝序列的更新= 的確可使以FN穿隧效應注人電子之記憶胞的啟 壓由注入電子後的5.0V逐步回到注入電子前的i 9V , 2 即表示電荷捕陷層之中間部分的電子已被消除。Please refer to Fig. 4A. The pulse width used in this part of the experiment is i〇ms, the initial value of the pole voltage (five) pulse is -8V, and then the pulse of each negative voltage is more than its pre-pulse - Q 5V; The pole voltage (Vd) pulse start value = 6V 'the height of each pulse is thereafter more than the front - pulse multi Q iv. As can be seen from Fig. 4A, the update of the pulse sequence with a stepwise increase in height can indeed make the voltage of the memory cell in which the electrons are injected by the FN tunneling effect gradually return from the 5.0V after the electron injection back to the electron injection. i 9V , 2 means that the electrons in the middle part of the charge trap layer have been eliminated.
請見圖4B 琢―分貫驗所用之脈衝寬度為50ms，間 極電壓(vg)脈衝高度固定為—14V，且汲極電壓(vd)脈衝言 度固定為7.7V。由圖4B可知，此使用高度固 = 列的更新方法，的確可使以FN穿隨效應注入電 胞的啟始電壓逐步回到注入電子前的19V，此^ 雪^ 捕陷層之中間部分的電子已被消除。 、不電何 〜，不論是使用高度呈階梯狀增加的脈衝序列 退疋南度固疋之脈衝序列，本發明之更新方法 去電荷捕陷層之中間部分中的電子，故可用在經夕土’效除 抹除循環而在電荷懸層之巾間部分累積難抹^=、、入 儲存位置非揮發記憶體上，以除去該些難抹除十的 非揮發記憶體可以繼續正常地使用。 ’、i ’使此 〈實驗2> 請參照圖5,此實驗係分別在第5、1〇、3〇、5 5000、10000次的CHEI寫入/BTBTHH抹除循琴〇之驗 1259469 15849twf.doc/s 非揮無δ己丨思體的啟始雷慰（ν、 ^ 類似實驗i所述之()’亚在私Vt檢驗後即進行 憶體。由圖5中績使用此非揮發記 變化可知，；HS ^ 的未更新之抹除態(低位準)Vt 抹除循環之次!抹除態(低位準)Vt隨寫入/ 窗口愈來愈小 來恩南，而不致使記憶體的操作 以前再^更^^抹5=’在寫入/抹除循環次數達1_次 實際應用時，在cd!會過高而影響正常操作，故 檢驗vt叫if=除=:域㈣達1錢千次後再 yVSI. ^疋疋否進仃更新步驟即可。如圖ό所示，苴係 口變小。驟，但仍能有效地防止記憶體的操作窗 限定ϊϊί發Γ已Γ較佳實施例揭露如上’然其並非用以 .^ χ 、’.壬何熟習此技藝者，在不脫離本發明之粹神 内’當可作些許之更 ： ，圍當視後附之申請專利範圍所界定者為準月之保護 【圖式簡單說明】 寫入示習知電荷捕陷型非揮發記憶體之二位元 =之二二r示經多次寫顺操作心 ㈣心累積有難抹除電子的情形。 法的:本發明較佳實施例之非揮發記憶體的使用方 圖3a〜3b繪示本發明之非揮發記憶體的更新方法的 14 1259469 15849twf.doc/g 一例0 遞增圖顯示本發明之模擬實驗$ ’ Μ度呈階梯狀 難^抹陝；子,，脈衝序列’對以FN效應注入電子以模擬 、示非揮發記憶體進行更新步驟的結果。 中，本發明之非揮發記憶體使用^的一實例 1，抹除態vt隨寫瑪除循環次數增加的變 次vt檢驗之後”行—:欠更新步驟。 圖頌不本發明之另一實例中寫入態Vt與抹 v Ik寫入/抹除循環次數增加的變化， ’、〜 循環次數累計達1_讀賴始鱗=財寫入/抹除 【主要元件符號說明】 100 半導體基底 110 底氧化層 120 氮化矽捕陷層 130 頂氧化層 140 ： :閘極 150、 ‘ 160 :左、右 S200〜S230 ·•步驟標號 15See Figure 4B. The pulse width used for the test is 50ms, the voltage of the inter-electrode voltage (vg) is fixed at -14V, and the voltage of the drain voltage (vd) is fixed at 7.7V. As can be seen from FIG. 4B, this method of updating using a high solid-column column can surely return the starting voltage of the cell injected with the FN follow-up effect back to 19V before the electron injection, which is the middle portion of the trapping layer. The electronics have been eliminated. No matter what, no matter whether it is a pulse sequence with a stepped increase in height, the update method of the present invention removes the electrons in the middle part of the charge trap layer, so it can be used in the night sky. The effect of the erase cycle is that the non-volatile memory on the non-volatile memory of the storage area is accumulated in the non-volatile memory of the storage layer to remove the non-volatile memory which is difficult to erase. ', i 'Let this <Experiment 2> Please refer to Figure 5, this experiment is in the 5th, 1st, 3rd, 5th, 5th, and 10,000th CHEI write /BTBTHH erased the test of the piano 1259469 15849twf. Doc/s is not the beginning of the δ 丨 丨 丨 雷 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Changes can be seen; HS ^'s unupdated erase state (low level) Vt erase cycle second! erase state (low level) Vt with write / window is getting smaller and smaller, without causing memory Before the operation, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ After 1 thousand times, then yVSI. ^疋疋No, please update the steps. As shown in Figure 苴, the 苴 口 is small. However, it can still effectively prevent the operation window of the memory from being limited. The preferred embodiment discloses the above, but it is not used for .^ χ , '. 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟patent The scope defined by the scope is the protection of the quasi-month [simplified description of the schema] Write the two-dimensional element of the trapped non-volatile memory of the trap-type memory = the second-two r shows the multi-write operation of the heart (four) heart accumulation is difficult to wipe In addition to the case of electrons, the method of using the non-volatile memory of the preferred embodiment of the present invention, FIGS. 3a to 3b, illustrate a method for updating the non-volatile memory of the present invention. 14 1259469 15849twf.doc/g The simulation experiment of the present invention is shown. The results of the present invention are the results of the step of updating the electrons in the FN effect to simulate and show the non-volatile memory. The volatilization memory uses an example 1 of ^, and the erased state vt follows the variable vt test with the increase of the number of cycles of the write-and-make cycle. "Line-: under-update step. Figure 颂 is not written in another instance of the present invention Vt and Wipe v Ik write / erase cycle increase in the number of changes, ', ~ cycle count up to 1_ read 鳞 start scale = financial write / erase [main component symbol description] 100 semiconductor substrate 110 bottom oxide layer 120 nitride矽 trap layer 130 top oxide layer 140 : : Pole 150, '160: left, right S200~S230 · • step numbers 15