1259437 九、發明說明： 【發明所屬之技術領域】1259437 IX. Description of invention: [Technical field to which the invention belongs]
LVDS 本發明係有關-種高速輸入輪出緩衝器，特別是有關—種呈有 與咖S兩種規格之平面顯示H高速輸人輸峻衝器。 【先前技術】 今日平面齡_在提供其色彩濃度與解析度的增加，很多面板製 造業者都已經可以量產解析度超過SVGA⑽〇 χ _像素）和xga 時脈控制H到面板鶴f路的介面賴操作於更高的資料傳輸速度。 乂往TTL或CMOS的方式，易產生較高的細，而系統中的各個單元， 均須通過EMI認證，若搭配㈣系統時，解決聽之方式獨，可能造成 生產時的_ ’所以現在普遍制lvds/rsds傳輸介面祕大幅減少耗 (1024 X 768像素）的平面顯示器，隨著平面顯示器解析度的快速增加位 於平面顯示麵裡直接連接顯示卡到液晶顯示時脈控制器以及液晶顯示 電里及$磁波’並精簡數位電視為解決電磁波干擾及輻射問題所需之零組 件’降低生產成本。因此，位於平面顯示器系統介面的冑速輸入輸出緩衝 器設計是有其必要的。 t知美國專利申請案號us67262%·細4 *脳7川35·2撕，均為有關 低屢差動几姻輸人輸出緩衝器的設計，以及目前在低擺幅差動訊號中的 ，又。十上亦制緩衝II的設計，然而低壓差動訊號與低擺幅差動訊號最主要 的不同疋在於兩者應用的標的及傳輸的速率，兩者在功能上大致相同都是 一種輸入輸出緩衝器。 1259437 有鑑於此，本發明係針對上述之問題，提出-種具低壓差動訊號 (LVDS)與低擺幅絲訊號（RSDS)兩種規格之平蝴示㈣速輸入輸 出緩衝〃係將運跡平面齡料統介面的低電壓差動峨傳輸規格 與更小擺幅絲W傳輸整合於輸出緩齡f路巾，且可轉作到很 高的資料傳輸速度並可財援解析度為刪A(1_ x 像素)的平面 顯示器系統。 【發明内容】 本發明之主要目的，餘提供—低縣動訊賊健幅差動訊號 規格之平賴㈣高賴人㈣緩_，祕制制設制緩衝器將低 壓差動峨與低擺幅差動峨兩種規格的傳輸介面整合在—起，可以節省 平面顯示器在資料傳輸介面的電路設計以及靈活·在兩種規格的資料傳 輸。 本發明之另—目的’餘提供—祕健絲職與倾幅差動訊號 規格之平_示轉速輸人輪峡《，魏《制設計賴衝器增加 賁料傳輸速率，使其可以支援高解析度的平面顯示器系統。 毛月之再目的’係在提供—種具健差動喊與倾幅差動訊號 規格之平_示轉速輸人輪崎衝器，其係設有睡嗤式可以在高速輸 入輸出緩衝ϋ未使用時關閉電路以節省電源的消耗， 根據本發明’其餘括―轉換電路可接收—單職壓訊餘輸出一差 動電壓訊號’-輸議魏㈣接嶋_纖嶋訊號，二 個電流供應提㈣流至__叹-輸人_電料_-低 1259437 電壓差動訊號的輸入並將其轉換成一 種賁料傳輸之標準介面，節省電路面 以節省電源 早&電壓訊號，可使得本發明適合兩 積’另有省電模式避免不必要的運作 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明 之目的、技術内容、特點及其所達成之功效。 【實施方式】 本發明係_高速輸人輸出緩衝H將健絲峨（LVDS)輸入輸出 緩衝器與低魏差動減（RSDS)輸端峡觸整合在—起，以簡化平 面顯示器系統介面的電路設計。 h閱第目為具有低壓差動訊號（LVDS)與低擺幅差動訊號（RSDS) 規袼的平_不||資料傳輸之架構，再參閱第二圖為本發明之輸出緩衝器 電路示思圖，輸出緩衝為1可將先前的序列全擺幅資料訊號經由一傳輸線 傳輸至低壓差動訊號或低擺幅差動訊號接收端，包括一轉換電路12可以將 單一資料訊號轉換成差動資料訊號，差動訊號一極接至M2和M4，另一極 接至Ml和M3，一輸出緩衝電路11連接轉換電路12接收其傳送之差動訊號 並輸出標準差動訊號，如低壓差動訊號或低擺幅差動訊號，一共態回授電 路13，其一端M9經由兩個偵測電阻ra1-Rb〗（1〇〇 ]^Ω)與輸出緩衝電路u 連接’可保持輸出緩衝電路11之輸出偏移電壓在低壓差動訊號和低擺幅差 動訊號標準規格的電壓範圍内，另一端Μ12則連接至Μ7，另有兩個電流 鏡電路14、15連接輸出緩衝電路11之Μ5及Μ6，可提供電流至輪出緩衝 電路11，另一端則連接共態回授電路13之Μ10及Mil，最後有一控制開 1259437 電路16連接兩個電流鏡電路14、i5，可控制兩個電流鏡電路、巧提 u輪出缓衝電路u ;其中，輸出緩衝電路丨丨是由4個開關組 “ 方M5 M6有兩個電流源，下方M7亦有一個電流源，輸出緩衝LVDS The present invention relates to a high-speed input wheel-out buffer, and in particular to a flat-panel display H-speed input and output spurter of the present invention. [Prior Art] Today's Plane Age _ In the increase in color density and resolution, many panel manufacturers have been able to mass-produce resolutions beyond SVGA (10) _ _ pixels) and xga clock control H to panel crane interface Lai operates at a higher data transfer speed. The way to TTL or CMOS is easy to produce higher fineness, and each unit in the system must pass EMI certification. If it is matched with (4) system, it can solve the problem of listening alone, which may cause _ ' at the time of production. The lvds/rsds transmission interface has greatly reduced the consumption (1024 X 768 pixels) of the flat panel display. With the rapid increase of the flat panel display resolution, the display card is directly connected to the liquid crystal display clock controller and the liquid crystal display. And $magnetic wave' and streamline digital TV to solve the electromagnetic interference and radiation problems required components to reduce production costs. Therefore, the design of the idle input and output buffer located in the interface of the flat panel display system is necessary. t know that the US patent application number is us67262%·fine 4 *脳7川35·2 tearing, all of which are related to the design of the output buffer of the low-incremental differential input, and the current low-swing differential signal, also. The design of the buffer II is also the same. However, the main difference between the low-voltage differential signal and the low-swing differential signal is the target and transmission rate of the two applications. The two functions are roughly the same as an input/output buffer. Device. In view of the above, the present invention proposes a flat-panel (four) speed input/output buffer system with low-voltage differential signal (LVDS) and low-swing wire signal (RSDS) for the above problems. The low-voltage differential transmission specification of the plane-level material interface and the smaller swing-wire transmission are integrated in the output slow-down f-road towel, and can be converted to a high data transmission speed and the resolution of the financial aid is deleted. (1_ x pixels) flat panel display system. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a low-level difference between the low-level differential singer and the low-slung singer. The wide-format transmission interface of the two types of differential transmission can save the circuit design of the flat display in the data transmission interface and the flexible data transmission in two specifications. The other purpose of the present invention is that the remaining - the secret of the silk and the differential signal specifications of the flat _ shows the speed of the input wheel gorge ", Wei "designed by the rusher to increase the transfer rate of the feed, so that it can support high Resolution flat panel display system. The re-purpose of Maoyue is based on the provision of a kind of differential swaying and swaying differential signal specifications. The slewing speed is input to the shovel, which is equipped with a sleep-sleeping type that can be buffered at high speed. In use, the circuit is turned off to save power consumption. According to the present invention, the "others include" conversion circuit can receive - single job pressure residual output, a differential voltage signal' - the transmission of the Wei (four) interface _ fiber signal, two current supply (4) flow to __ sigh - lose people _ electricity _ - low 1259437 voltage differential signal input and convert it into a standard interface for data transmission, saving circuit surface to save power early & voltage signal, can make The present invention is suitable for two products' and another power saving mode to avoid unnecessary operations. The specific embodiments are explained in detail by the accompanying drawings, and it is easier to understand the purpose, technical content, characteristics and the achieved efficacy. [Embodiment] The present invention is a high-speed input output buffer H that integrates the LVDS input and output buffers with the low-differential differential-decrement (RSDS) output torsion to simplify the interface of the flat panel display system. Circuit design. h read the head is the structure of the data transmission with low voltage differential signal (LVDS) and low swing differential signal (RSDS) specifications, and then refer to the second figure for the output buffer circuit of the present invention. In the figure, the output buffer is 1 to transmit the previous sequence full swing data signal to the low-voltage differential signal or the low-swing differential signal receiving end via a transmission line, and includes a conversion circuit 12 for converting a single data signal into a differential signal. The data signal, the differential signal is connected to M2 and M4, and the other terminal is connected to M1 and M3. An output buffer circuit 11 is connected to the conversion circuit 12 to receive the differential signal transmitted by the signal and output a standard differential signal, such as a low voltage differential. Signal or low swing differential signal, a common state feedback circuit 13, one end M9 is connected to the output buffer circuit u via two detecting resistors ra1-Rb (1〇〇]^Ω) to maintain the output buffer circuit 11 The output offset voltage is within the voltage range of the low-voltage differential signal and the low-swing differential signal standard specification, the other end 12 is connected to the Μ7, and the other two current mirror circuits 14, 15 are connected to the output buffer circuit 11 and 5 Μ6, can provide current to the wheel The circuit 11 is connected to the Μ10 and the Mil of the common-state feedback circuit 13 at the other end, and finally has a control circuit 1259437. The circuit 16 is connected to the two current mirror circuits 14, i5, which can control two current mirror circuits and help the u-wheel to slow down. Punch circuit u; wherein, the output buffer circuit 丨丨 is composed of 4 switch groups "square M5 M6 has two current sources, and the lower M7 also has a current source, output buffer
Hi Ά像個具有彳的開關，有適當的電流產生後會經過一終端電 Rtt以建立-適當的輪出電壓擺幅符合低壓差動訊號（lvds)和低擺幅 差動Λ遽（RSDS)的標準，當繼和奶開啟時則輸出緩衝電w輸出電 机為正’而當議和綱開啟時則輸出緩衝電路（輸出電流為負，因為輸出 緩衝電路1的㈣傳輸率為每秒十億位元，在輸出輸人介社因為阻抗的 不匹配使得資料在傳輸時的信魏量反獅破壞信制品f，因此其輸出 端為-雙終端電路’可以減低信號能量的反射，此雙終端電路為在兩個終 端線的發射端跨接了電阻RTT在另_端接受端跨接了電阻Rtr，且兩電阻值 為 100Ω。 再者，共恶回授電路13可以將緩衝電路1輸出補償電壓保持在低壓差 動訊號（LVDS)和低擺幅差動訊號（RSDS)的標準範圍内，由二個電阻 Ra1 - Rm (Rai = Rbi = 1〇〇 kQ )而得到共態電壓其再與差動放大器通_鳩3 的一個輸入參考電壓1·25 V比較，其中電阻(2〇 kQ)可以降低共態 電壓的雜訊’ Rb2(201cQ)加在另一電壓輸入端以平衡差動輸入Mg -M9，一 補償網路Cc - Rc (Cc = 6pF and Rc = 4尬)被加在共態回授電路的迴路可在 處理-供給電壓-溫度（Process，suppiy Voltage，Temperature，pVT)參數上得 到穩定。 在控制電路16上LR和EN兩個控制腳可以控制輸出緩衝器，當LR為 1259437 邏輯訊號“1，，(3.3 V)以及ΕΝ是邏輯訊號“r，（3.3 v)時，兩個電流鏡電路Μ , 分別提供適當之電流至M5 M6以建立LVDS所需之差崎出電壓，另外， 當LR為邏輯訊號“〇，，(〇 V)以及EN是邏輯訊號“Γ，（3 3 v)時，電流鏡電路5 被Μ28關閉，電流鏡電路4則會提供祕一電流，以建立汉犯所需之電壓 擺幅，最後當EN是邏輯T(〇V)且輪入電壓Vm奶”（33v)時而兩:電 流鏡電路4、5，分別被M28-M29關閉以防止電流通過。 另外請參閱第三圖為本發明之轉換電路電路示意圖，當一邏輯為”丨，，俨 號（3.3V)到達Vin時，結點A和結點B會充電上升到3·3ν而結點c則會 放電成為0V，最後使得Voutp成為邏輯，T，，v〇utn成為邏輯”〇,，，相反的若 是Viri的邏信號輯為”〇”時則會使得Voutp成為邏輯，，〇，，，ν〇_成為邏 輯”1” ；請參閱第四圖為本發明輸出之差動訊號的模擬圖，圖a為低壓差動 訊號，圖b為低*擺幅差動訊號。 請參閱第五圖為本發明輸入緩衝器電路示意圖，輸入緩衝器2可以偵測 低電壓差動訊號的輸入並將其轉換成單端全擺幅電壓訊號，差動對 (M2卜M22)可以偵測低壓差動訊號和低擺幅差動訊號標準規格輪入之低 電壓差動訊號，並有一正回饋電路（M23、M24) 22可以立即在結點(；及結 點D得到大的差動電壓，輸入緩衝器電路上方為一差動至單端轉換電路21， 轉換電路21並可以將結點C及結點D之間的差動訊號放大；其中，當控制腳 EN是邏輯訊號“〇”（0 V)及輸入緩衝器輸出端被M25鉗為“〇，，（〇 v)時，輸入 緩衝器為睡眠模式，請參閱第六圖為輸入緩衝器的模擬圖，虛線為當接收 訊號為最差的情況(V0D = ± 100mV)，然而在實線部分則顯示輸出訊號可回Hi Ά is like a switch with 彳, after a suitable current is generated, it will pass through a terminal Rtt to establish - the appropriate wheel-out voltage swing meets the low-voltage differential signal (lvds) and the low-swing differential sigma (RSDS). The standard, when the milk and the milk are turned on, the output buffer power w output motor is positive 'and the output buffer circuit when the discussion and the class are turned on (the output current is negative, because the output buffer circuit 1 (four) transmission rate is ten per second In the output of the input and output, because of the impedance mismatch, the information in the transmission of the information, the anti-lion destroys the letter f, so its output is - double terminal circuit 'can reduce the reflection of signal energy, this pair The terminal circuit is connected to the resistor RTT at the transmitting end of the two terminal lines, and the resistor Rtr is connected across the other end of the terminal, and the two resistor values are 100 Ω. Furthermore, the common evil feedback circuit 13 can output the buffer circuit 1 The compensation voltage is maintained within the standard range of low-voltage differential signal (LVDS) and low-swing differential signal (RSDS). The two resistors Ra1 - Rm (Rai = Rbi = 1〇〇kQ) obtain the common-state voltage. An input reference to the differential amplifier _鸠3 Voltage 1·25 V comparison, where the resistance (2〇kQ) can reduce the noise of the common state voltage 'Rb2(201cQ) is added to the other voltage input terminal to balance the differential input Mg-M9, a compensation network Cc - Rc (Cc = 6pF and Rc = 4尬) The loop applied to the common-state feedback circuit can be stabilized on the Process-supply Voltage (Temperature, pVT) parameter. LR and on the control circuit 16 The EN control pin can control the output buffer. When LR is 1259437 logic signals "1,, (3.3 V) and ΕΝ is the logic signal "r, (3.3 v), the two current mirror circuits 提供 provide appropriate Current to M5 M6 to establish the differential voltage required for LVDS. In addition, when LR is the logic signal "〇,, (〇V) and EN is the logic signal "Γ, (3 3 v), the current mirror circuit 5 is Μ28 is turned off, the current mirror circuit 4 will provide a secret current to establish the voltage swing required by the Chinese criminal, and finally when EN is logic T (〇V) and wheel voltage Vm milk (33v) and two: current The mirror circuits 4, 5 are respectively closed by M28-M29 to prevent current from passing. Please also refer to the third figure for the conversion of the present invention. Circuit circuit diagram, when a logic is "丨,, 俨 (3.3V) reaches Vin, node A and node B will charge up to 3·3ν and node c will discharge to 0V, finally making Voutp Logic, T,, v〇utn become logical "〇,,, on the contrary, if Viri's logic signal is "〇", Voutp becomes logic, 〇,,, ν〇_ becomes logic "1"; Referring to the fourth figure, a simulation diagram of the differential signal outputted by the present invention is shown in Figure a, which is a low-voltage differential signal, and Figure b is a low-swing differential signal. Please refer to FIG. 5 is a schematic diagram of the input buffer circuit of the present invention. The input buffer 2 can detect the input of the low voltage differential signal and convert it into a single-ended full swing voltage signal, and the differential pair (M2 Bu M22) can Detect low-voltage differential signals and low-swing differential signals with standard low-voltage differential signals, and have a positive feedback circuit (M23, M24) 22 that can immediately get a large difference at the node (and node D) The dynamic voltage, above the input buffer circuit is a differential to single-ended conversion circuit 21, and the conversion circuit 21 can amplify the differential signal between the node C and the node D; wherein, when the control pin EN is a logic signal " 〇” (0 V) and the input buffer output is clamped to “〇,, (〇v) by M25, the input buffer is in sleep mode. Please refer to the sixth figure for the analog buffer of the input buffer, and the dotted line for receiving. The signal is the worst case (V0D = ± 100mV), but in the solid line, the output signal can be returned.