TWI256640B - Non-volatile semiconductor memory cell with separated bitline structure - Google Patents

Non-volatile semiconductor memory cell with separated bitline structure

Info

Publication number
TWI256640B
TWI256640B TW090107844A TW90107844A TWI256640B TW I256640 B TWI256640 B TW I256640B TW 090107844 A TW090107844 A TW 090107844A TW 90107844 A TW90107844 A TW 90107844A TW I256640 B TWI256640 B TW I256640B
Authority
TW
Taiwan
Prior art keywords
bitline
memory cell
separated
semiconductor memory
volatile semiconductor
Prior art date
Application number
TW090107844A
Other languages
Chinese (zh)
Inventor
Ching-Hsiang Hsu
Ching-Sung Yang
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW090107844A priority Critical patent/TWI256640B/en
Priority to JP2001254126A priority patent/JP2002298592A/en
Application granted granted Critical
Publication of TWI256640B publication Critical patent/TWI256640B/en

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  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The present invention provides a non-volatile semiconductor memory cell with separated bitline structure, wherein the main bitline is controlled by at least one bitline selection device to transmit the potential to the selected sub-bitline, so as to operate the memory cell transistors in the selected sector. Thus, the present invention can prevent the parasitic capacitor from generating bitline loading, and the memory cell transistors and bitline selection devices are designed in parallel P-well and N-well, so as to further avoid the programming (writing) bitline interference or the erase bitline interference.
TW090107844A 2001-04-02 2001-04-02 Non-volatile semiconductor memory cell with separated bitline structure TWI256640B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW090107844A TWI256640B (en) 2001-04-02 2001-04-02 Non-volatile semiconductor memory cell with separated bitline structure
JP2001254126A JP2002298592A (en) 2001-04-02 2001-08-24 Non-volatile semiconductor memory having divided bit lines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW090107844A TWI256640B (en) 2001-04-02 2001-04-02 Non-volatile semiconductor memory cell with separated bitline structure

Publications (1)

Publication Number Publication Date
TWI256640B true TWI256640B (en) 2006-06-11

Family

ID=21677830

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090107844A TWI256640B (en) 2001-04-02 2001-04-02 Non-volatile semiconductor memory cell with separated bitline structure

Country Status (2)

Country Link
JP (1) JP2002298592A (en)
TW (1) TWI256640B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995414B2 (en) * 2001-11-16 2006-02-07 Kabushiki Kaisha Toshiba Semiconductor memory device including multi-layer gate structure

Also Published As

Publication number Publication date
JP2002298592A (en) 2002-10-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees