1255399 玖、發明說明： 【發明所屬技術領域】 本發明是有關一種由TTL轉換至CMOS之輸入緩衝器所用 之電路。此緩衝器所用之電路可在電源電壓、半導體製程、 以及溫度發生變化時，將此緩衝器之輸入/輸出電壓之邏輯 轉換點保持穩定，且可達成降低此緩衝器之新增偏壓電路所 消耗功率之目的與效果。 【先前技術】 根據一般瞭解，在目前所使用電晶體之邏輯家族大致包括以下 數種，其名稱與特性為： 1· TTL(Transistor-Transistor-Logic ):技術複雜、面積大、 功率消耗大。 2. ECL(Emitter Coupled Logic):特性與 TTL 類似’且速度相 當快，但邏輯位準特殊、雜訊免疫能力低’不適用於較高 密度之積體電路設計； 3. M0S(Metal Oxide Semiconductor): 4 分為 PM〇S、NMOS 與 CMOS，製程較簡單，電路密集度高、面積小，但速度較慢； 4· BiCMOS(Bipolar Complementary-MOS):利用 BJT 之南驅動 能力來當輸出級，因此具有BJT之快速、M0S局密集度等優 點，但製程相當複雜。 其中TTL(74系列1C中使用之技術）與ECL可以得到較快之操作 速度，但其製程較複雜，所佔用面積較大，功率消耗亦大’因此在 同一晶片上所能製成之電路也較少。所以晶片上電路緊密程度較 小，亦使得相同大小之電路須要使用較多晶片來完成。 M0S製程技術最簡單，所佔用晶片面積最小，可以在相同大小 之晶片上容納較大型電路。雖然M0S之功率消耗較BJT少井多’但 其操作速度較慢。 因而，在高速度低功率之要求下，發展出技術’其結合 M0S與BJT兩種技術之特點，因此在製程上比較複雜’但其在操作 1255399 速度與功率消耗上可以得到平衡點。通常BlCM〇S電路用來作傳輸 級’這是利用它的高操作速度與高的驅動能力。 因此，由以上說明可知，TTL為一種電晶體-電晶體-邏輯電路， 其為使用多個雙載子電晶體所組成之邏輯電路，其相較於輸 出驅動力強、操作速度快，但電流之消耗量亦大。然而，CM0S為互 補式金屬氧化物半導體電晶體（C〇mplementary mefal 〇xide semiconductor transistor)，其輸出驅動能力較弱，速度較慢， 但電流之消耗量較小。因此，在當設計電路時，必須依據整個電路 所區分各不同區塊（block)中，在其操作運算所須速度之快慢、輸 出驅動能力之強弱、以及所消耗功率等參數因素之間作抉擇，以決 定各該電路區塊使用TTL或CMOS作建構元件，以使得由其所建構 之區塊所組成之電路之速度、性能以及成本能達其最適功能盥效 由以上說明可知，在一般電子數位系統中，可以同時存在TTL 與CMOS電晶體。然而，由於驅動操作此等TTL與CM〇s電晶體所須 電壓位準不同，因此，通常在此等電子數位系統電路之TTL電晶體 所構成區塊與CMOS電晶體所構成區塊之間設有緩衝器er stage)，以作電壓位準之轉換。 傳統習知技術所設計之此種由TTL輸出轉換至CMOS輸入之緩衝 器，僅為單純地以PM0S電晶體與NM0S電晶體w/L比例之配置，以 達成其調整邏輯轉換點之目的，但其缺點為其邏輯轉換點會隨著· 所提供之電源電壓、半導體製程、以及溫度而大幅變化。此為習知 技術此種緩衝器電路之重大缺點與限制，茲說明如下。 首先請參考第1圖，其顯示根據習知技術之由TTL轉換至CM0S 之輸入緩衝器之電路結構圖。其中，第1(A)圖為其電路功能方塊 圖，第1(B)圖為其電路結構詳細圖式，以及第kC)圖為此緩衝器 由TTL輸入電壓以及其輸ώ至CMOS電壓之波形時序圖，其中，a、 B、C、以及D為邏輯轉換點。由第1(A)圖可知，此緩衝器（1〇)是由 第一反相級（Π )與第二反相級（12)所構成。由第1(B)圖可知，此緩 衝器是由電晶體T10K其寬度/長度比，w/L=10/0. 6)、 丁 102(W/L=l〇/〇· 6)、Tl〇3(W/L=6/0· 3)、以及 t1〇4(W/L=3/0· 28)所 構成，其中T101、T103為PM0S (其閘極繪有圓圈者為PM〇s)，τΐ〇2、 丁104為簡OS ;而T101與Tl〇2、T103與T104各分別串聯成反相器 1255399 (inverter) ; VD為電源電壓VS為接地電壓。其次，說明此緩衝器 在其電源電壓變動下其邏輯轉換點之變動情形。通常將邏輯轉換點 定義為其輸入電壓曲線與其輸出電壓曲線相交之點，亦即其輸入電 壓值與輸出電壓值相等之點。如圖第1(C)圖所示，此緩衝器之輸入 電壓（即，由TTL輸出電壓）範圍為0.8至2V，此緩衝器之輸出電壓 範圍為0至3. 3V，而其邏輯轉換點為1. 4V。在此第1(B)圖之反相 器中，當PMOS之強度〉丽OS之強度時，此反相器輸出電壓提高， 當PMOS之強度〈丽OS之強度時，此反相器輸出電壓降低。因此， 當此PMOS T101之電源VD從3. 3V變動增加至3. 6V時，則PMOS T101 變強，而此反相器之輸出電壓提高；為了將輸出電壓維持在原所設 定位準，則必須將此緩衝器左端輸入（其值例如為1.4V)之電壓提 高，而使NMOS T102變強、使PMOS T101變弱，以使得此緩衝器之 輸出電壓可.因此調降回原所設定位準。然而，在上述過程中，此緩 衝器之輸入電壓提高，因此其邏輯轉換點之電壓值偏離原設定值而 產生相當幅度變動。 第2圖說明上述習知技術中電源電壓發生變動時，此緩衝器輸 入/輸出電壓邏輯轉換點之變動情形，此邏輯轉換點是藉由輸入/輸 出電壓特性曲線而顯示。如同於第2圖中所示，其橫軸為輸入電壓， 其縱軸為輸出電壓，其單位均為伏特，其中所示之三條曲線即代表 電晶體T101之電源電壓分別為VD=3V、3. 3V、3. 6V時之電壓轉換 曲線。由此圖中可以明顯看出，在當電源電壓VD=3V時，此緩衝器 之邏輯轉換點約為1.285V;當電源電壓VD=3.3V時，此緩衝器之邏 輯轉換點約為1. 410V ;以及當電源電壓VD=3. 6V時，此緩衝器之邏 輯轉換點約為1.523V。因此，在習知技術中，當電源電壓發生變動 時，此緩衝器之輸入/輸出電壓邏輯轉換點呈現相當幅度之變化。 第3圖說明上述習知技術中此緩衝器之製程發生變化時，其輸 入/輸出電壓之邏輯轉換點變動之情形，如同於第3圖中所示，其 橫軸為輸入電壓，其縱軸為輸出電壓，其單位均為伏特。其中FS、 FF、TYPICAL、SS、SF各代表於各不同製程下之電壓轉換曲線，其 各對應於各不同之邏輯轉換點；而FS表示：此製程所製成之NM0S 電晶體之速度快、PMOS電晶體之速度慢；FF表示：此製程所製成 之NM0S電晶體之速度快、PMOS電晶體之速度快；TYPICAL表示：此 製程所製成之丽0S電晶體、PMOS電晶體為典型速度；SS表示：此 1255399 製程所製成之NMOS電晶體之速度慢、PMOS電晶體之速度慢；SF 表示：此製程所製成之NM0S電晶體之速度慢、PM0S電晶體之速度 快；以及Delta VSW表示：FS曲線之邏輯轉換點與SF曲線之邏輯 轉換點之差異為20OmV。因此，在習知技術中，當製程發生變化時， 此緩衝器之輸入/輸出電壓之邏輯轉換點呈現相當幅度之變化。 以上所述之由TTL轉換至CMOS之緩衝器之輸入/輸出電壓邏輯 轉換點所呈現大幅變動之情形，其會造成此緩衝器之低至高位準 傳輸時間（tLH)、與高至低位準傳輸時間（tHL)之差異過大，以及 高、低位準之雜訊餘裕（noise margin)變差，在嚴重情形下甚 至會導致信號轉換錯誤，以致使整個CMOS電路失效等缺點與限 制。 為了改善習知技術中此種緩衝器電路設計之缺點與限制， 本案發明人於93年6月17日提出之本國專利申請案號No 0931 1 7477，其提供一種由TTL轉換至CMOS之緩衝器電路，而可 在電壓電源、半導體製程、以及溫度發生變化時，達成穩定此緩衝 器輸入/輸出電壓邏輯轉換點之目的與功能。有關於此，請參考該 前申請案内容即可得知，在此不再重複，其整個内容在此併入作為 參考。因此，本發明可視為該前申請案發明之延續。 然而，由於在該上述前申請案之緩衝器電路設計中添加偏壓 器，因此導致大幅增加該電路所消耗之靜態電流與靜態功率。例 如，在此裝置之電源電壓為3V時，添加設置此偏壓器其本身會耗 用大約104//A之電流，因此會增加TTL至CMOS輸入緩衝器之整體 功率消耗。 為了降低上述該電路（偏壓器）中所消耗電流與功率，因此本案 發明人（其他熟習此技術人士亦可能）提出一種改良式電路設計 其：（1) 一方面藉由增添偏壓器，以使得此緩衝器之輸入/輸出電壓 之邏輯轉換點不隨電源電壓、半導體製程、以及周圍溫度之改變而 呈現大幅變化；（2)另一方面，藉由電晶體之大小比例中之通道長 度（channel 1 ength)與通道寬度（channel w idth)之寬度/長度 (W/L)比之調整，以降低此偏壓器之靜態電流與靜態功率消耗。然 1255399 而，此種設計仍存有缺失，以致於以此種設計所製成之緩衝器雖可 達成降低電流與功率消耗之功能與目的，但該緩衝器之輸入/輸出 電壓之邏輯轉換點卻因此會隨電源電壓、半導體製程、以及周圍溫 度之改變而呈現大幅變化。 本發明之目的即在改善相關習知技術與上述改良式電路設計之 缺點寒限制，而可同時達成具有高度穩定之邏輯轉換點，以及降低 靜態功率消耗之功能與目的。 有酿針對上述前案緩衝器電路之改良式電路設計之内容、特 徵、與其所受到限制，以及本案之内容與優點，將在以下”實施方 式”中詳細說明。 【發明内容】 因此，本發明之目的為提供一種由TTL轉換至CMOS輸入緩 衝器電路，其可在電源電壓、半導體製程、以及溫度（PVT: process、supply vol tage、temperature)名务生變 4匕日寺，達成 定此緩衝器輸入/輸出電壓邏輯轉換點以及降低靜態功率消耗 之功能與目的。 為了穩定此輸入緩衝器之邏輯轉換點，本發明增設一偏壓器， 用以產生對此輸入緩衝器之負回饋控制信號，以便對其實施控制與 調變。而且，為了監控此輸入緩衝器之邏輯轉換點，本發明將此輸 入緩衝器電路之第一級（即輸入級）複製成為此新增偏壓器之第一 級（即複製輸入級），而在此新增設之偏壓器内設置比較器作為偏壓 器内之第二級，此比較器一方面對此所複製之輸入級實施比較與控 制，另一方面根據此比較結果產生偏壓回饋信號（BI AS)對此輸入緩 衝器進行監控與調變。因而使得緩衝器之輸入/輸出電壓邏輯轉換 點穩定，以避免造成此緩衝器之低至高位準傳輸時間（tLH)、與 高至低位準傳輸時間（tHL)之差異過大，以及高、低位準之雜訊 餘裕（noise margin)變差，在嚴重情形下甚至會導致信號轉換 錯誤，以致使整個CMOS電路失效等缺點與限制。因此，可以確 保此整個CMOS電路操作正常。 1255399 应並發λ之特殊設計，可將各別電晶體經由串聯 ^度崎κ得本發明之緩效以 度穩定邏輯轉換點，以及降低靜態功率消耗之功 =目的“ 明並目岡的、特徵以及其他之優點與特點將由以下之說 月亚♦考所附圖式而獲得更佳瞭解。 【實施方式】 現在參考所附圖式說明本發明之實施例。 -二下使Λ本發明第1 i10圖說明:相對於上述該前申請案緩衝 為電路之改良式電路之特徵與限制，^ 與操作原理；其中 月緩衝為電路之设計 ⑴VI::兒？相對於該前申請案緩衝器電路之改良式電 入/’=電路 =計僅· 幅以!^ 卻會隨電源電壓與製程變化而大 電£破輯轉換點、且可降低其靜態功率消耗。 前I 該一 對 路| 電 式 良 改 之I 作I 所j 路| 電j 器 衝 緩 案 制I 限i 之 受 所 其I 及i 第 至 圖 n 7t> 換至CMOS:輸二弟二，電(二冓；顯：f康本發明之由m轉 功能方《，㈣第4⑽為其電路 由第4(A)圖可知，此緩衝器（4〇)是 計之詳細電路圖，其包^⑽s之輸人緩衝器電路之改良式電路設 輸入緩衝器（40)，其接收由TTL輸、^ 位準電壓而輸出供應⑽s電路，包括：之電£將其轉換成適當 10 1255399 第一反相器級（41)，其為輸入級，接收由TTL輸入之電壓將其 反相且轉換成CMOS所適用位準之電壓，其由以下串聯構成： T40KW/L-10/0. 6) 、 402(W/L^l〇/〇. 6) 、 T403(W/L=5/0. 6)、以及 T404(W/L二5/0· 6); 第二反相級（42)，將第一反相級輸出之反相電壓再予以反相輸 出’其由以下所構成· T405(W/L= 6/0·3) 、 T4〇6(W/L= 3/0.28); 偏壓器（43)，藉由使用比較器監控複製輸入級，以產生至輸入 緩衔器之輸入級之回饋信號，其包括： 複製輸入級（44)，用於複製輸入級之電路，其由以下串聯而構 成： T407(W/L=2/3) 、 T408(W/L=2/3) 、 T409(W/L=l/3)、以 春 及 T410(W/L=l/3); 比較器（45)，用於監控該複製輸入級，以產生至輸入級之回饋 信號，其由以下所構成： T411 (W/L= 12/0.8) > T412 (W/L= 12/0.8) T413 (W/L二 12/1) 、 T414 (W/L= 12/1); T415 (W/L= 3/4) 、 T416 (W/L= 3/4); 由以上說明可知，此第4(B)圖之電路設計結構與本發明人前申 請案之由TTL轉換至CMOS之輸入緩衝器電路設計大致相同，所不 同者只是將其中偏壓器電路第一級中之電晶體T407、T408、T409 _ 以及T410之寬度/長度（W/L)比相對應於輸入緩衝器第一級中電晶 ® 體T401、T402、T403以及T404之寬度/長度比縮減25倍。例如， 於此例中，將電晶體T401、T402之寬度/長度（W/L)比10/0. 6縮減 25倍至電晶體T407、T408之2/3 ;且將電晶體T403、T404之寬度 /長度（W/L)比5/0. 6縮減25倍至電晶體T409、T410之1/3。在此 種電路設計結構之電源電壓VD=3. 0V之供應下，經實際測量得知， 此流經偏壓器第一級中電晶體T407、T408、T409以及T410之電流 可由本案發明人前申請案緩衝器電路設計中所示之104 // A縮小約 25倍而成為5· 2//A。此種電路設計可達成減少電流消耗與功率消 耗之功能與目的，但其在供應電源與製程改變下，輸入/輸出電壓 曲線之邏輯轉換點卻會呈現大幅變動，茲將其原因說明如下： π 1255399 依據下式電晶體之等效電阻R之倒數為， 1/R- β C οχ · (W/L) · (Vgs-Vt) 式（1) 其=，"為電子之遷移率，C為氧化物之電容，W/L為電晶體 之見度/長度比，Vgs為閘極至源極電壓，Vt為此電晶體之臨 【電壓。由上式可知，R與寬度/長度比成反比，若W/L縮減 ，原來之1/25，則等效電阻R成為原來之25倍，因此，在給 ===電壓V之供應下丨=V/R，流經此電晶體之電流亦縮減為 。*之丨/25 ;且由於所消耗功率P=V2/R，因此，此電晶體所 消耗功率P減少為原1/25。 由^於，在本案實施例中所使用電晶體之pM〇s與丽〇s電晶體之 二並非一直為一固定常數值，其會隨著電晶體不同 度而有所改變。因此，若將此等電晶體之寬度/長度（W/L) 5乜，則PM0S電晶體之強度（因此，其驅動能力）例如可能 之1/24, “廳電晶體之強度（因此，其驅動能力） 複^級為ΐ來之1/26 °所以，當例如將此偏壓器之輸人 因此:ί生:二比1小25倍時，此緩衝器之第一反相級之電壓輸出 壓等於其輸出電壓之點（之電廢值）。因此，當此緩 ::或半等體製程改變時，會造成此緩衝 】 ，曲線之邏輯轉換點呈現較大幅度變動，如同於第5與j = 7日* Λ茶考第5圖。第5圖說明根據上述例中當電源電壓發 二緩衝器輸入/輸出電壓轉換侧 為輸於第5圖中所示，其橫軸為輸入電壓，其It τμΙ ，，、單位均為伏特。其中所示之三條曲線即代表I曰_ Τ401之電源電壓分別為VD4V、3.3V、3·6Υ時之輸入 由此圖中可以明顯看出，在當電源電壓VD,日ΓΐίΪ 口口别入/輸出電壓邏輯轉換點與當電源電壓vd=3 6V日士 器輸)/輪出電壓之邏輯轉換點有相當大之變動。3肩此緩衝 j 6圖為緩衝器輸入/輸出電壓特性曲線圖，A :二當製程發生變動時，此緩衝器輸入/輸出電壓邏輯員^^ 之情形。如同於第6圖中所示，其橫轴為輸入電壓，； 12 1255399 電壓，其單位均為伏特◦其中，fast，typical，slow各代表不同 製程下之緩衝器之電壓轉換曲線，而fast代表：此製程所製成之 半導體元件速度快，typical代表：此製程所製成之半導體元件為 典型速度，slow代表：此製程所製成之半導體元件速度慢。由此圖 中可以明顯看出，在當此半導體製程發生變化時，此緩衝器之輸入 /輸出電壓特性曲線及其邏輯轉換點會產生相當大之變化而呈現不 穩定之現象。此種針對該前申請案中緩衝器電路設計之改良式設計 之效果並不理想，仍有改善之必要，因此導致以下本案實施例之產 生0 本發明實施例 以下說明本發明實施例，其目的為：藉由使用由TTL轉換至CMOS 之輸入緩衝器，而確實達成穩定邏輯轉換點與降低偏壓電路靜態功 率消耗之目的。 由第7(A)圖可知，此緩衝器（70)是由第一反相級（71)、第二反 相級（72)、以及偏壓器（73)所構成。請參考第7(B)圖，其顯示根據 本發明實施例之由TTL轉換至CMOS之輸入緩衝器之電路，其包括： 輸入緩衝器（70)，其接收由TTL輸八之電壓，將其轉換成適當 位準電壓而輸出供應CMOS電路，包括： 第一反相級（71)，其為輸入級，接收由TTL輸入之電壓將其反 相且轉換成CMOS所適用位準之電壓，其由以下串聯構成： 並聯之 T701-1、T701-2、T701-3、T7(H-4、以及 T701-5 所構成之電晶體組合結構1 (其W/L均為2/0.6); 並聯之 T702-1、T702-2、T702-3、T702-4、以及 T702-5 所構成之電晶體組合結構2 (其W/L均為2/0. 6); 並聯之 T703-：l、T703-2、T703-3、T703-4、以及 T703-5 所構成之電晶體組合結構3 (其W/L均為1/0.6);以及 並聯之 T704-：l、Τ704-2、Τ704-3、Τ704-4、以及 Τ704-5 所構成之電晶體組合結構4(其W/L均為1/0. 6); 第二反相級(7 2 )，將第一反相級輸出之反相電壓再予以反相輸 出，其由以下所構成： T705(W/L= 6/0.3) ， T706CW/L- 3/0.3)； 13 1255399 偏壓器（7 3)，藉由使用比較器監控複製輸入級，以產生至輸 入緩衝器之輸入級之回饋信號，其包括： 複製輸入級（74)，用於複製輸入級之電路，其由以下串聯 而構成： 串聯之 T707-：l、T707-2、T707-3、T707-4、以及 T707-5 所構成之電晶體組合結構7(其W/L均為2/0. 6); 串聯之 Τ708-1、Τ708-2、Τ708-3、Τ708-4、以及 Τ708-5 所構成之電晶體組合結構8(其W/L均為2/0. 6); 串聯之 T709-：l、T709-2、T709-3、T709-4 ' 以及 Τ709-5 所構成之電晶體組合結構9(其W/L均為1/0. 6); 以及 串聯之 Τ71(Μ、Τ710-2、Τ710-3、Τ710-4、以及 Τ710-5 φ 所構成之電晶體組合結構10(其W/L均為1/0.6); 比較器（75)，用於監控該複製輸入級，以產生至輸入級之 回饋信號，其由以下所構成： T711 (W/L= 12/0.8)、 T712 (W/L= 12/0.8) T713 (W/L= 12/1) 、 T714 (W/L= 12/1) T715 (W/L= 3/4) 、 T716 (W/L= 3/4)； 其特徵為 此等並聯之T701-1至-5所構成之電晶體組合結構1之等效寬 度/長度比W/L= 10/0. 6 ; T702-1至-5所構成之電晶體組合結構2之等效寬 _ 度/長度比 W/L: 10/0. 6 ; ^ T703-1至-5所構成之電晶體組合結構3之等效寬 度/長度比W/L= 5/0. 6 ; T704-1至-5所構成之電晶體組合結構4之等效寬 度/長度比W/L= 5/0. 6 ;以及 此等串聯之T707-1至-5所構成之電晶體組合結構7之等效寬 度/長度比W/L= 2/3 ; T708-1至-5所構成之電晶體組合結構8之等效寬 度/長度比W/L= 2/3 ； T709-1至-5所構成之電晶體組合結構9之等效寬 度/長度比W/L= 1/3 ;以及 14 1255399 T710-1至-5所構成之電晶體組合結構10之等效 寬度/長度比W/L= 1/3。 以下說明本實施例電路之設計與操作原理： 為了穩定此輸入緩衝器之輸出電壓位準與邏輯轉換點，本案另 增設一偏壓級，用以產生對此輸入緩衝器之負回饋，以便對其實施 控制與調變。 此外，為了監控此輸入緩衝器之邏輯轉換點，於此實施例中將 此輸入緩衝器電路之第一級（即輸入級）複製至此新增偏壓器之第 一級（即複製輸入級），而在此新增設之偏壓器内另設置比較器為偏 壓器内之第二級，其一方面對此所複製之輸入級實施比較與控制， 另一方面根據此比較結果產生偏壓回饋信號（BIAS)對此輸入緩衝 _ 器進行監控與調變。因而使得輸入緩衝器之邏輯轉換點穩定。以下 將以實際電路作詳細說明。 請參考第7(B)圖，其中此輸入緩衝器包括串聯之電晶體組合結 構2、3，其閘極並聯至輸入，此輸入來自TTL之輸出；此兩電晶體 組合結構2、3各串聯至控制電晶體組合結構1、4。此由以上方式 構成之反相器連接至另一反相器，其由電晶體T705、T706串聯而 成。此偏壓器之第一級由電晶體組合結構7、8、9以及10依序串 聯形成，其為輸入緩衝器輸入級之複製輸入級。其中，電晶體組合 結構7、10之閘極分別連接至電晶體組合結構1、4之閘極；此偏 壓器之上述第一級之輸出節點Ml與輸入節點N1相連接而至比較器 之電晶體T713之閘極，此閘極之電壓為VREFI。此偏壓器73之第 ® 二級為比較器，其由以下所構成：T711、T712、T713、T714、T715、 以及T716。此比較器之功能為：將T713閘極上之電壓VREFI與T714 閘極上之參考電壓VREF比較而在此比較器之輸出節點K1產生偏壓 (BIAS)，作為輸出至複製輸入級74與第一反相級71之回饋信號。 其中此VREF為所欲設定之邏輯轉換點之電壓值，此電壓通常來 自能帶間隙參考電壓（bandgap)電路或電源分壓電路。在當電源電 壓或半導體製程改變時，此電路利用負回饋原理，藉由調整BIAS 點之電壓值即可達成穩定緩衝器邏輯轉換點之目的。通常，於上述 15 1255399 ， 反相器結構中，當PMOS電晶體之強度〉丽OS電晶體之強度時，則 此反相器之輸出電壓上升，當PM0S電晶體之強度<NM0S電晶體之 強度時，則此反相器之輸出電壓下降。 現在說明本發明以偏壓器控制輸入緩衝器，而使緩衝器輸入/ 輸出電壓之邏輯轉換點保持穩定之操作方式。 (a) 當 VREFI>VREF 時 在實際應用中例如將此比較器之參考電壓VREF設定為1. 4V， 當此比較器之另一輸入電壓（即，此複製輸入級之輸出電壓）VREFI >參考電壓VREF (即，1.4V)時，則經由此比較器將此兩個輸入電 壓VREF與VREF I比較，而使此比較器之輸出電壓BI AS上升，因而 使電晶體組合結構7、8減弱、電晶體組合結構9、10增強，因此 鲁 使得此複製輸入級之輸出電壓，即，VREFI之電壓下降，經由此比 較器將VREFI與VREF比較而使其輸出電壓BIAS調整，其再經由複 製輸入級使其輸出電壓VREFI調整至接近原來參考電壓VREF之位 準。 (b) 當 VREFI < VREF 時 在實際應用中例如將此比較器之參考電壓VREF設定為1. 4V， 當此比較器之另一輸入電壓（即，此複製輸入級之輸出電壓）VREFI 〈參考電壓VREF (即，1.4V)時，則經由該比較器將此兩個輸入電 壓VREF與VREF I比較，而使此比較器之輸出電壓BI AS下降，因而 使電晶體組合結構7、8增強、電晶體組合結構9、10減弱，因而 使得此複製輸入級之輸出電壓，即，VREF I之電壓上升，經由比較 器將VREFI與VREF比較而使其輸出電壓BIAS調整，其再經由複製 輸入級使其輸出電壓VREFI調整至接近原來參考電壓VREF之位準。 (c) 當第一反相級之電源電壓VD上升時 此外，當此輸入緩衝器第一反相級之電源電壓VD上升時，會使 得電晶體組合結構1、2之強度增強、且使得電晶體組合結構7、8 之強度增強，因此可使得偏壓器之複製輸入級之輸出（即，比較器 之輸入）VREFI升高，因而使得偏壓器之輸出電壓BIAS上升。經由 此提升之BIAS回饋電壓，可使得電晶體組合結構1、2之強度減弱， 16 1255399 且使得電晶體組合結構3、4之強度增強。因而電晶體組合結構1、 2之總和強度與電晶體組合結構3、4之總和強度，大致仍可保持電 源電壓VD提高前之相對強度，以致於此輸入緩衝器之第一反相級 之輸出電壓仍可保持在電源電壓VD提高前之原來位準。因此，可 將上述本案之TTL至CMOS輸入緩衝器之輸入/輸出電壓邏輯轉換點 之變動保持在相當小之範圍内，而可達成使其穩定之目的與效果。 (d)當第一反相級之電源電壓VD下降時 其次，當此輸入缓衝器之第一反相級之電源電壓VD下降時，可 使得電晶體組合結構1、2之強度減弱、且使得電晶體組合結構7、 8之強度減弱，因此使此複製輸出級之輸出VREFI之電壓降低，而 使得比較器之輸出電壓BIAS下降；經由此下降之BIAS回饋電壓， 可使得電晶體組合結構1、2之強度增強，且使得電晶體組合結構 3、4之強度減弱，因而電晶體組合結構1、2之總和強度與電晶體 組合結構3、4之總和強度，大致可保持電源電壓VD下降前之相對 強度，以致於此輸入緩衝器之第一反相級之輸出電壓仍可保持在接 近電源電壓VD提高前之原來位準；因此，可將該TTL至CMOS輸入 緩衝器之輸入/輸出電壓邏輯轉換點之變動保持在相當小之範圍 内，而達成使其穩定之目的與效果。 因此，由本發明緩衝器之電路結構可知，本實施例主要之目的 在於改善上述第4(B)圖改良式電路設計之缺失，其中為了降低在複 製輸入級之電流消耗，而使此緩衝器之輸入/輸出電壓特性曲線之 邏輯轉換點隨供應電壓或此半導體製程改變而大幅變化。在本實 施例中並不採用如同於第4(B)圖中所用之方法，直接將此複製輸入 級中之所構成電晶體（包括：PM0S電晶體與NM0S電晶體）之寬度/ 長度（W/L)比縮小數十倍（例如：25倍）成為2/3與1/3 ;因為此種 方式之設計會造成PM0S與NM0S電晶體之強度呈不同比例之增強或 減弱，而造成緩衝器輸入/輪出電壓邏輯轉換點之大幅變化。而是， 本實施例所採用之方法為：（1)藉由將複製輸入級之各個電晶體， 以串聯方式組成電晶體組合結構7-10，將其等效寬度/長度比縮 小，以降低此複製輸入級之靜態電流與靜態功率之消耗（請參考以 上關於式（1)之說明）；以及 (2)由於此等輸入級與複製輸入級中所組成之電晶體組合結構之相 1255399 對應位置之各個組成電晶體之寬度/長度比均未改變（為2/0. 6 或1/0· 6)，因此，此等在複製輸入級中之與丽的之強度 相對於輸入級中之PMOS與丽OS之強度並未改變'。以此方式， 即可達成穩定此緩衝器輸入/輸出電壓邏輯轉換點之目的與效 果。 因此，使用本實施例之方法可達成：降低該緩衝器靜態功率消 耗，以及穩定其輸入/輸出電壓邏輯轉換點之功能與目的。 具體而言，本實施例在第7(B)圖中對於第4(b)圖中設計之改進 是以下列方式達成： (1) 將第 7(B)圖中輸入級之 T701-1 至 T701-5 (W/L=2/0. 6) 之五個PMOS電晶體並聯而成具有等效w/l=1 〇/〇· 6之電晶 體組合結構1。以此電晶體組合結構對應且取代第4(B)圖 修 中之電晶體 T401(W/L=10/0. 6); (2) 將第 7(B)圖中輸入級之 T702-1 至 T702-5 (W/L=2/0· 6) 之五個PMOS電晶體並聯而成具有等效w/L=10/0. 6之電晶 體組合結構2。以此電晶體組合結構對應且取代第4(B)圖 中之電晶體 T402(W/L二 10/0. 6); (3) 將第 7(B)圖中輸入級之 T703-1 至 T703-5 (W/L=l/0. 6) 之五個丽OS電晶體並聯而成具有等效w/l=5/〇. 6之電晶體 組合結構3。此電晶體組合結構對應且取代第4(B)圖中之 電晶體 T403(W/L=5/0· 6); (4) 將第 7(B)圖中輸入級之 T704-1 至 T704-5 (W/L=l/0· 6) 之五個NM0S電晶體並聯而成具有等效W/L=5/0. 6之電晶體 春 組合結構4。以此電晶體組合結構對應且取代第4(B)圖中 之電晶體 T404(W/L=5/0· 6); (5) 將第7(B)圖中複製輸入級之T707-1至T707-5 (W/L=2/0. 6) 之五個PM0S電晶體串聯而成具有等效w/L=2/3之電晶體組 合結構7。以此電晶體組合結構對應且取代第4(B)圖中之 電晶體 T407(W/L二2/3); (6) 將第7(B)圖中複製輸入級之T708-1至T708-5 (W/L=2/0. 6) 之五個PM0S電晶體串聯而成具有等效w/L=2/3之電晶體組 合結構8。以電晶體組合結構對應且取代第4(B)圖中之電 晶體 T408(W/L二2/3); 18 1255399 (7) 將第7(8)圖中複製輸入級之丁709-1至丁709-5 ^几=1/0.6) 之五個丽OS電晶體串聯而成具有等效W/L4/3之電晶體組 合結構9。以此電晶體組合結構對應且取代第4(B)圖中之 電晶體 T409(W/L=l/3); (8) 將第7(B)圖中複製輸入級之T710-1至T710-5 (W/L=l/0. 6) 之五個丽OS電晶體串聯而成具有等效W/L=l/3之電晶體組 合結構10。以此電晶體組合結構對應且取代第4(B)圖中之 電晶體 T410(W/L=l/3)。 因此，由以上說明可知，經由上述第7(B)圖中之設計，此複製 輸入級中之電晶體組合結構7、8、9、以及10各相對應於輸入級電 路中之電晶體組合結構1、2、3、以及4 ;其等效寬度/長度（W/L) φ 比’由原輸入級電路中上述各電晶體組合結構之1〇/〇. 6、1〇/〇. 6、 5/0· 6、5/0. 6分別縮減至複製輸入級電路中各上述電晶體組合結構 之2/3、2/3、1/3、1/3，即縮減為原來之1/25。因此，此複製輸 入級之電阻上升為原電阻之25倍，其耗用電流與耗用功率亦減少 至原來之1/25。 然而，由於此輸入級電路與複製輸入極電路中電晶體組合結構 之谷個組成電晶體（包括PM0S電晶體與丽0S電晶體）之寬度與長度 並未改變，因此，其各個PM0S、丽〇S電晶體之強度亦不變。所以， 此由TTL轉換至CMOS之輸入緩衝極所輸出之電壓、以及因此豆輸 輸出電壓之邏輯轉換點，在電源電壓或製程變化之下可保持穩 疋而不^作大巾田改艾。以此方式達成穩定邏輯轉換點之功能與目Φ 的。 其次，請參考第8圖。第8圖說明根據本發明實施例當電源電 壓發生變動時，此緩衝器輸入/輪出電壓特性曲線、及豆邏輯轉換 點之變動情形。^同於第8圖中所示，其橫軸為輸入電壓，其縱軸 為輸出電壓，其早位均為伏特。其中所示之三條曲線即代表電晶體 組合結構1之電源電壓分別為VD=3V、3·3ν、3·6ν時之輸入/輸出 電壓轉換曲線。由此圖中可以明顯看出，在當電源電壓¥1)=扒時， 此緩衝器之邏輯轉換點VSW為i· 436V;當電源電壓VD=3· 3V時，此 緩衝器之邏輯轉換點VSW為1.429V;以及當電源電壓VD=3.6V時， 此緩衝器之邏輯轉換點| 1.423V。由第8圖可知，當電源電壓由 19 1255399 3此31 Γ:3·6"寺，其邏輯轉換點電壓值之變化僅為i3mv。 r衝哭：於^月貫施例、’當此緩衝器之電源電壓發生變動時，此 σσ力人力出電壓邏輯轉換點僅呈現小幅度變化而可保持穩 明杏=么為緩f器f入/輸出電麼特性曲線圖，其顯示根據本發 «二⑦蜂田衣矛王皂生變動時，此緩衝器輸入/輸出電壓邏輯轉換點 變動之情形。如同於第q.圖由成-好w 调山电科丹供點 |^+ # 00/ ' f θ中所不，其板軸為輸入電壓，其縱軸為 typica1' slow^^ :2;ί:=Γ轉換曲線’…代表：此製程所製 件為血型、亲声，Υ又ί主typicai代表：此製程所製成之半導體元 H_冃二1 k又，S 〇W代表：此製程所製成之半導體元件速度慢。由 中可以明顯看出，此三條電壓轉換線非常接近。因此 Ξΐί發^變化時’此緩衝器之其由sl⑽與fast所代表之3轉 = 換點之差異僅為㈣，因此其輸入/輸出電壓 特丨生曲線之邏輯轉換點可保持相當穩定。 第10圖為輸入/輸出電壓之瞬間暫態圖，其顯示根據本 =緩; ⑻，縱軸為電壓、單位為伏特(V)。其中， 貝線颁不该緩衝為之由丁孔所輸入電壓之波形變化，虛線 H出0電4^波Γ變化。由此圖中可知，此輸出電壓波形之二 π 間 TR=0· 49ns，其下降時間為 TF=: 〇. 46ns。 服-因Λ:+由以上說明可知，本發明之電路確實可以改善盥克 I /Λ之厂由TTL轉換至CM0S緩衝器之缺點與限制，即1 輪入/輸出電壓邏輯轉換點呈現大幅變動之缺失，以成ς 高:準傳輸時陶、與高至低位議 才。。舌it t咼、低位準之雜訊餘裕（noisemargln)變差， =等缺點與限制。藉由使用本發明之緩衝器電路：】； ^轉換點趨於穩定，確保此整個CMOS電路操作正常，且^ IV低其功率消耗。因此，本案確具專利價值，且符合專利要件： U上所述僅為本發明之較佳實施例而已，其僅用於說 限:申請專利範圍之内容;凡是其他在未偏離本發 明所揭不之精神與範圍下所作之等效改變或修姊，均應包含在以下 20 1255399 所述之申請專利範圍之範圍中 【圖式簡單說明】 第1(A)圖為根據習知技術之由TTL轉換至之輸入 之電路概要方塊圖； 戌衡為 第1(B)圖為根據習知技術之由TTL轉換至CM〇s之輸入 之詳細電路圖； 、及_為 第1(c)圖為由TTL轉換至CM〇s之輸入緩衝器 之瞬間暫態圖； 别出屯壓 一 f為第1(B)圖中所示緩衝器於不同電源電壓下^^ 卜出電壓轉換特性曲線； 电i卜之輪入/輸 第3圖為第KB)圖中所示緩衝器於不同半導體製裎 〃輸出電壓轉換特性曲線； 千等體良私下之輸入/ 第=)圖圖為對於前申請案緩衝器電路之改良式電路之概要方 第4 =)圖圖為對於前申請案緩衝器電路之改良式電路之詳細電1255399 BRIEF DESCRIPTION OF THE INVENTION The present invention relates to a circuit for converting an input buffer from TTL to CMOS. The circuit used by the buffer stabilizes the logic switching point of the input/output voltage of the buffer when the power supply voltage, the semiconductor process, and the temperature change, and a new bias circuit for reducing the buffer can be achieved. The purpose and effect of the power consumed. [Prior Art] According to the general understanding, the logic families of the transistors currently used include the following types, and their names and characteristics are as follows: 1. TTL (Transistor-Transistor-Logic): complex technology, large area, and large power consumption. 2. ECL (Emitter Coupled Logic): The characteristics are similar to TTL 'and the speed is quite fast, but the logic level is special, the noise immunity is low' is not applicable to the higher density integrated circuit design; 3. M0S (Metal Oxide Semiconductor ): 4 is divided into PM〇S, NMOS and CMOS, the process is simple, the circuit density is high, the area is small, but the speed is slow; 4· BiCMOS (Bipolar Complementary-MOS): use the south drive capability of BJT as the output stage Therefore, it has the advantages of fast BJT, density of M0S, etc., but the process is quite complicated. Among them, TTL (the technology used in 74 series 1C) and ECL can get faster operation speed, but the process is more complicated, the occupied area is larger, and the power consumption is also larger. Therefore, the circuit that can be fabricated on the same chip is also less. Therefore, the tightness of the circuit on the wafer is relatively small, and the circuit of the same size needs to use more wafers to complete. The M0S process technology is the simplest and occupies the smallest wafer area and can accommodate larger circuits on wafers of the same size. Although the power consumption of the MOS is much lower than that of the BJT, its operation speed is slower. Therefore, under the requirement of high speed and low power, the technology has been developed, which combines the characteristics of the two technologies of M0S and BJT, so it is complicated in the process, but it can achieve a balance between speed and power consumption in operation 1255399. Usually the BlCM〇S circuit is used for the transmission stage' which is exploited for its high operating speed and high drive capability. Therefore, as can be seen from the above description, TTL is a transistor-transistor-logic circuit, which is a logic circuit composed of a plurality of bi-carrier transistors, which is stronger than the output driving force and has a fast operating speed. The consumption is also large. However, CM0S is a C 〇 ment ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide ide Therefore, when designing a circuit, it is necessary to distinguish between different blocks according to the entire circuit, between the speed of the operation required for the operation, the strength of the output drive capability, and the parameter factors such as the power consumed. In order to determine that each circuit block uses TTL or CMOS as a construction component, so that the speed, performance and cost of the circuit composed of the blocks constructed by it can reach its optimum function. As can be seen from the above description, in general electronics In digital systems, both TTL and CMOS transistors can be present. However, since the TTL of the driving operation is different from the voltage level required by the CM〇s transistor, it is usually set between the block formed by the TTL transistor of the electronic digital system circuit and the block formed by the CMOS transistor. There is a buffer er stage) for voltage level conversion. The buffer designed by the conventional art to convert from the TTL output to the CMOS input is simply configured by the ratio of the PM0S transistor to the NM0S transistor w/L to achieve the purpose of adjusting the logic switching point, but The disadvantage is that the logic switching point varies greatly with the supply voltage, semiconductor process, and temperature provided. This is a major drawback and limitation of the conventional buffer circuit of the prior art, as explained below. First, please refer to FIG. 1, which shows a circuit structure diagram of an input buffer converted from TTL to CM0S according to the prior art. Among them, the first (A) diagram is its circuit function block diagram, the first (B) diagram is its circuit structure detailed diagram, and the kC) diagram for this buffer is the TTL input voltage and its input to the CMOS voltage. Waveform timing diagram, where a, B, C, and D are logical transition points. As can be seen from Fig. 1(A), the buffer (1〇) is composed of a first inverting stage (Π) and a second inverting stage (12). As can be seen from the first (B) diagram, the buffer is made up of the width/length ratio of the transistor T10K, w/L=10/0. 6), D: 102 (W/L=l〇/〇·6), Tl 〇3 (W/L=6/0·3) and t1〇4 (W/L=3/0·28), where T101 and T103 are PM0S (the gate is drawn with a circle as PM〇s) ), τ ΐ〇 2, D 104 is a simple OS; and T101 and Tl 〇 2, T103 and T104 are respectively connected in series to an inverter 1255399 (inverter); VD is a power supply voltage VS is a ground voltage. Next, the variation of the logic switching point of this buffer under the variation of its power supply voltage will be described. The logic transition point is usually defined as the point at which the input voltage curve intersects its output voltage curve, that is, the point at which the input voltage value is equal to the output voltage value. As shown in Figure 1(C), the input voltage of this buffer (that is, the TTL output voltage) ranges from 0.8 to 2V, and the output voltage range of this buffer is 0 to 3. 3V, and its logic switching point Is 1. 4V. In the inverter of the first (B) diagram, when the intensity of the PMOS is the intensity of the NMOS, the output voltage of the inverter is increased, and when the intensity of the PMOS is the intensity of the NMOS, the output voltage of the inverter is reduce. Therefore, when the power supply VD of the PMOS T101 is increased from 3.3 V to 3. 6 V, the PMOS T101 becomes strong, and the output voltage of the inverter is increased; in order to maintain the output voltage at the originally set level, it is necessary to The voltage of the left input of the buffer (the value of which is, for example, 1.4V) is increased, and the NMOS T102 is made stronger, so that the PMOS T101 is weakened, so that the output voltage of the buffer can be adjusted. Therefore, the voltage is adjusted back to the original set level. . However, in the above process, the input voltage of the buffer is increased, so that the voltage value of the logic switching point deviates from the original set value and varies considerably. Fig. 2 is a view showing the variation of the logical conversion point of the buffer input/output voltage when the power supply voltage fluctuates in the above-mentioned prior art, and the logical conversion point is displayed by the input/output voltage characteristic curve. As shown in Fig. 2, the horizontal axis is the input voltage, and the vertical axis is the output voltage, and its unit is volt. The three curves shown represent the power supply voltage of the transistor T101 are VD=3V, 3 respectively. . 3V, 3. 6V voltage conversion curve. As can be seen from the figure, when the power supply voltage VD=3V, the logic conversion point of this buffer is about 1.285V; when the power supply voltage VD=3.3V, the logical conversion point of this buffer is about 1. 410V; and when the power supply voltage VD = 3. 6V, the logical conversion point of this buffer is about 1.523V. Therefore, in the prior art, when the power supply voltage fluctuates, the input/output voltage logic switching point of the buffer exhibits a considerable change. Figure 3 is a diagram showing the variation of the logical transition point of the input/output voltage when the process of the buffer changes in the above-mentioned prior art. As shown in Fig. 3, the horizontal axis is the input voltage, and the vertical axis thereof. For the output voltage, the unit is volts. FS, FF, TYPICAL, SS, SF each represent voltage conversion curves under different processes, each of which corresponds to a different logical conversion point; and FS means: the speed of the NM0S transistor made by this process is fast, The speed of the PMOS transistor is slow; FF means: the speed of the NM0S transistor made by this process is fast, and the speed of the PMOS transistor is fast; TYPICAL means that the MOS transistor and the PMOS transistor made by this process are typical speeds. SS indicates that the speed of the NMOS transistor made by this 1255399 process is slow and the speed of the PMOS transistor is slow; SF means: the speed of the NM0S transistor made by this process is slow, the speed of the PM0S transistor is fast; and Delta VSW indicates that the difference between the logical transition point of the FS curve and the logical transition point of the SF curve is 20OmV. Therefore, in the prior art, when the process changes, the logical conversion point of the input/output voltage of the buffer exhibits a considerable change. The above-mentioned logic conversion point of the input/output voltage of the buffer converted from TTL to CMOS is greatly changed, which causes low to high level transmission time (tLH) and high to low level transmission of the buffer. The difference in time (tHL) is too large, and the noise margin of high and low levels deteriorates, and in severe cases, even signal conversion errors may occur, resulting in failures and limitations of the entire CMOS circuit. In order to improve the shortcomings and limitations of such a snubber circuit design in the prior art, the inventor of the present application, No. 0931 1 7477, filed on June 17, 1993, provides a buffer that is converted from TTL to CMOS. A circuit that achieves the purpose and function of stabilizing the logic conversion point of the buffer input/output voltage when voltage supply, semiconductor process, and temperature change. In this regard, reference is made to the content of the prior application, which is hereby incorporated by reference in its entirety herein in its entirety herein in its entirety herein in its entirety Accordingly, the invention is considered to be a continuation of the invention of the prior application. However, since the bias voltage is added to the snubber circuit design of the above-mentioned prior application, the quiescent current and static power consumed by the circuit are greatly increased. For example, when the device's supply voltage is 3V, the addition of this biaser will consume approximately 104//A of its own current, thus increasing the overall power consumption of the TTL to CMOS input buffer. In order to reduce the current and power consumption in the above-mentioned circuit (bias), the inventors of the present invention (others skilled in the art) may also propose an improved circuit design: (1) on the one hand, by adding a bias voltage, So that the logic switching point of the input/output voltage of the buffer does not change greatly with the change of the power supply voltage, the semiconductor process, and the ambient temperature; (2) on the other hand, the channel length in the size ratio of the transistor (channel 1 ength) is adjusted in comparison with the width/length (W/L) of the channel width (channel w idth) to reduce the quiescent current and static power consumption of the biaser. However, 1255399, there is still a lack of such a design, so that the buffer made by this design can achieve the function and purpose of reducing current and power consumption, but the logical conversion point of the input/output voltage of the buffer. However, it will vary greatly with changes in supply voltage, semiconductor process, and ambient temperature. SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages associated with the prior art and the improved circuit design described above, while at the same time achieving a highly stable logic switching point and reducing the static power consumption. The contents, features, limitations, and contents and advantages of the improved circuit design for the above-described buffer circuit will be described in detail in the following "embodiments". SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a TTL-to-CMOS input buffer circuit that can be used in power supply voltage, semiconductor process, and temperature (PVT: process, supply vol, tage, temperature). Riji, the function and purpose of determining the logical conversion point of the buffer input/output voltage and reducing the static power consumption. In order to stabilize the logic switching point of the input buffer, the present invention adds a bias voltage for generating a negative feedback control signal for the input buffer for control and modulation thereof. Moreover, in order to monitor the logical transition point of the input buffer, the present invention copies the first stage (ie, the input stage) of the input buffer circuit to the first stage of the newly added bias (ie, the copy input stage), and A comparator is provided in the newly added biaser as the second stage in the biaser. On the one hand, the comparator performs comparison and control on the copied input stage, and on the other hand, generates a bias according to the comparison result. The feedback signal (BI AS) monitors and modulates this input buffer. Therefore, the input/output voltage logic switching point of the buffer is stabilized to avoid the low to high level transmission time (tLH) of the buffer, the difference from the high to low level transmission time (tHL), and the high and low levels. The noise margin of the noise deteriorates, and in severe cases, it may even cause signal conversion errors, which may cause disadvantages and limitations such as failure of the entire CMOS circuit. Therefore, it is possible to ensure that the entire CMOS circuit operates normally. 1255399 should be concurrently with the special design of λ, the individual crystals can be stabilized by the series of degrees and the slowness of the invention to stabilize the logic conversion point, and reduce the power of static power consumption = the purpose of And other advantages and features will be better understood from the following description of the invention. [Embodiment] An embodiment of the present invention will now be described with reference to the accompanying drawings. I10 diagram illustrates: characteristics and limitations of the improved circuit buffered as a circuit in the above-mentioned prior application, and operation principle; wherein the monthly buffer is the design of the circuit (1) VI:: relative to the buffer circuit of the prior application The improved electric input / '= circuit = meter only · the amplitude of !^ will vary with the power supply voltage and process, and the power will be broken, and the static power consumption can be reduced. Front I The pair of roads | I am a good change I do I j road | electric j device to slow down the case I limit i to receive its I and i to the figure n 7t> to CMOS: lose two brothers two, electricity (two 冓; display: f Kang this invention from the m to functional party ", (4) 4 (10) for its circuit As shown in Fig. 4(A), the buffer (4〇) is a detailed circuit diagram, and the improved circuit of the input buffer circuit of the package (10)s is provided with an input buffer (40), and the reception is received by TTL, ^ The level voltage is output to the supply (10)s circuit, including: the electricity is converted to the appropriate 10 1255399 first inverter stage (41), which is the input stage, receiving the voltage from the TTL input to invert it and convert it to CMOS The voltage of the applicable level is composed of the following series: T40KW/L-10/0. 6), 402 (W/L^l〇/〇. 6), T403 (W/L=5/0. 6) And T404 (W/L 2/0·6); the second inverting stage (42), and the inverted voltage of the output of the first inverting stage is further inverted and outputted, which is composed of the following: T405 (W) /L= 6/0·3) , T4〇6 (W/L= 3/0.28); a biaser (43) that monitors the copy input stage by using a comparator to generate an input stage to the input terminator The feedback signal comprises: a copy input stage (44) for copying the circuit of the input stage, which is composed of the following series: T407 (W/L=2/3), T408 (W/L=2/3) , T409 (W/L=l/3), Spring and T410 (W/L=l/3); Comparator (45) for monitoring The input stage is copied to generate a feedback signal to the input stage, which is composed of the following: T411 (W/L = 12/0.8) > T412 (W/L = 12/0.8) T413 (W/L II 12/1 ), T414 (W/L= 12/1); T415 (W/L= 3/4), T416 (W/L= 3/4); As can be seen from the above description, the circuit design of this 4th (B) diagram The structure is substantially the same as the input buffer circuit design of the present inventor from TTL to CMOS, except that the width of the transistors T407, T408, T409 _ and T410 in the first stage of the bias circuit is / The length (W/L) is reduced by a factor of 25 compared to the width/length ratio of the electromorphic bodies T401, T402, T403, and T404 in the first stage of the input buffer. For example, in this example, the width/length (W/L) ratio of the transistors T401 and T402 is reduced by 25 times to 2/3 of the transistors T407 and T408; and the transistors T403 and T404 are The width/length (W/L) is reduced by 25 times to 5/0. 6 to 1/3 of the transistors T409 and T410. Under the supply of the power supply voltage VD=3.0V of the circuit design structure, it is known from the actual measurement that the current flowing through the transistors T407, T408, T409 and T410 in the first stage of the biaser can be applied by the inventor of the present invention. The 104 // A shown in the case of the buffer circuit design is reduced by about 25 times to become 5.2/A. This kind of circuit design can achieve the function and purpose of reducing current consumption and power consumption. However, under the supply power and process change, the logic conversion point of the input/output voltage curve will change greatly. The reason is explained as follows: π 1255399 According to the reciprocal of the equivalent resistance R of the following transistor, 1/R- β C οχ · (W/L) · (Vgs-Vt) (1) where =, " is the mobility of electrons, C For the capacitance of the oxide, W/L is the visibility/length ratio of the transistor, Vgs is the gate-to-source voltage, and Vt is the voltage of the transistor. It can be seen from the above equation that R is inversely proportional to the width/length ratio. If W/L is reduced, the original resistance is R2, which is 25 times the original resistance. Therefore, under the supply of === voltage V丨=V/R, the current flowing through this transistor is also reduced to. *丨/25; and since the power consumed is P=V2/R, the power P consumed by this transistor is reduced to the original 1/25. As a result, the pM 〇s and the 〇 s transistors of the transistor used in the embodiment of the present invention are not always a constant constant value, which varies with the difference in the crystal. Therefore, if the width/length (W/L) of the transistor is 5 乜, the strength of the PMOS transistor (hence, its driving ability) may be, for example, 1/24, "the strength of the hall transistor (hence, its The driving ability) is equal to 1/26 ° of the ΐ. Therefore, when, for example, the input of the biaser is such that: ίsheng: two to two times smaller than 25, the voltage of the first inverting phase of the buffer The output voltage is equal to the point of its output voltage (the electrical waste value). Therefore, when this slow:: or semi-equal system process changes, this buffer will be caused], the logical transition point of the curve shows a large change, as in the first 5 and j = 7 days * Λ tea test Figure 5. Figure 5 illustrates the power supply voltage according to the above example. The two buffer input/output voltage conversion side is the input shown in Figure 5, and its horizontal axis is the input. The voltage, its It τμΙ , , and the unit are volts. The three curves shown in it are the inputs when the power supply voltage of I曰_ Τ 401 is VD4V, 3.3V, 3·6Υ, respectively. When the power supply voltage VD, Γΐ Γΐ 别 port input / output voltage logic conversion point and when the power supply voltage vd = 3 6V day ) / The logical conversion point of the wheel voltage has a considerable change. 3 shoulder buffer j 6 picture is the buffer input / output voltage characteristic curve, A : 2 when the process changes, the buffer input / output voltage logic In the case of ^^, as shown in Figure 6, the horizontal axis is the input voltage, 12 1255399 voltage, the unit is volts, and fast, usually, slow each represents the voltage of the buffer under different processes. Conversion curve, and fast means: the semiconductor component made by this process is fast, typically means that the semiconductor component made by this process is a typical speed, and slow means that the semiconductor component made by this process is slow. It can be clearly seen that when the semiconductor process changes, the input/output voltage characteristic curve of the buffer and its logic switching point will undergo considerable changes and appear unstable. The effect of the improved design of the buffer circuit design is not satisfactory, and there is still a need for improvement, thus resulting in the following examples of the present invention. The purpose of the embodiment of the present invention is to achieve the purpose of stabilizing the logic switching point and reducing the static power consumption of the bias circuit by using an input buffer converted from TTL to CMOS. As can be seen from the figure 7(A), The buffer (70) is composed of a first inverting stage (71), a second inverting stage (72), and a biaser (73). Please refer to FIG. 7(B), which shows according to the present invention. An embodiment of a circuit for converting a TTL to an input buffer of a CMOS, comprising: an input buffer (70) that receives a voltage input by TTL, converts it to an appropriate level voltage, and outputs the output to the CMOS circuit, including: The first inverting stage (71), which is an input stage, receives a voltage which is inverted by a voltage of the TTL input and converted into a level applicable to the CMOS, and is composed of the following series: T701-1, T701-2 in parallel , T701-3, T7 (H-4, and T701-5 composed of transistor combination structure 1 (W/L are 2/0.6); parallel T702-1, T702-2, T702-3, T702 -4, and the transistor combination structure 2 composed of T702-5 (whose W/L are 2/0.6); parallel T703-:l, T703-2, T703-3, T703-4, and T 703-5 consists of a transistor assembly structure 3 (whose W/L is 1/0.6); and a parallel connection of T704-:l, Τ704-2, Τ704-3, Τ704-4, and Τ704-5 The transistor combination structure 4 (whose W/L is 1/0.6); the second inverting stage (7 2 ), and the inverted voltage of the output of the first inverting stage is further inverted and outputted by the following Composition: T705 (W/L = 6/0.3), T706CW/L-3/0.3); 13 1255399 Bias (7 3), by using a comparator to monitor the copy input stage to generate input to the input buffer The feedback signal of the stage includes: a replica input stage (74) for replicating the circuit of the input stage, which is composed of the following series: T707-:l, T707-2, T707-3, T707-4, and T707-5 consists of a transistor assembly structure 7 (whose W/L is 2/0.6); a series of Τ708-1, Τ708-2, Τ708-3, Τ708-4, and Τ708-5 The transistor assembly structure 8 (whose W/L is 2/0.6); the transistor combination structure composed of T709-:l, T709-2, T709-3, T709-4' and Τ709-5 in series (its W/L are 1/0. 6); and tandem 71 (Μ, Τ710-2, Τ710-3, Τ710-4, And a transistor combination structure 10 of Τ710-5 φ (whose W/L is 1/0.6); a comparator (75) for monitoring the replica input stage to generate a feedback signal to the input stage, The following components are: T711 (W/L= 12/0.8), T712 (W/L= 12/0.8) T713 (W/L= 12/1), T714 (W/L= 12/1) T715 (W/ L = 3/4), T716 (W/L = 3/4); characterized by the equivalent width/length ratio W/L = of the transistor composite structure 1 composed of T701-1 to -5 connected in parallel. 10/0. 6 ; Equivalent width _ degree/length ratio of transistor composite structure 2 composed of T702-1 to -5: W/L: 10/0. 6 ; ^ Electricity composed of T703-1 to -5 The equivalent width/length ratio of the crystal composite structure 3 is W/L=5/0. 6; the equivalent width/length ratio of the transistor composite structure 4 composed of T704-1 to -5 is W/L=5/0. 6; and the equivalent width/length ratio W/L=2/3 of the transistor assembly structure 7 composed of the series T707-1 to -5; the transistor combination structure 8 composed of T708-1 to -5 The equivalent width/length ratio W/L = 2/3; the equivalent width/length ratio of the transistor composite structure 9 composed of T709-1 to -5 is W/L = 1/3; and 14 1255399 T710-1 a transistor composed of -5 Laminate structure equivalent width / length ratio of 10 W / L = 1/3. The following describes the design and operation principle of the circuit of this embodiment: In order to stabilize the output voltage level and the logic conversion point of the input buffer, a bias stage is additionally provided in the present case to generate a negative feedback for the input buffer, so as to It implements control and modulation. In addition, in order to monitor the logical conversion point of the input buffer, the first stage (ie, the input stage) of the input buffer circuit is copied to the first stage of the newly added biaser (ie, the copy input stage) in this embodiment. In the newly added biaser, the comparator is further set as the second stage in the biaser, which performs comparison and control on the copied input stage on the one hand, and generates a bias according to the comparison result on the other hand. The voltage feedback signal (BIAS) monitors and modulates this input buffer. This makes the logical transition point of the input buffer stable. The actual circuit will be described in detail below. Please refer to the 7th (B) diagram, wherein the input buffer comprises a series of transistor assembly structures 2, 3, the gates of which are connected in parallel to the input, the input is from the output of the TTL; the two transistor combination structures 2, 3 are connected in series To control the transistor combination structure 1, 4. The inverter constructed in the above manner is connected to another inverter which is formed by connecting transistors T705 and T706 in series. The first stage of the biaser is formed in series by transistor combination structures 7, 8, 9 and 10 which are the replica input stages of the input buffer input stage. Wherein, the gates of the transistor assembly structures 7, 10 are respectively connected to the gates of the transistor combination structures 1, 4; the output node M1 of the first stage of the biaser is connected to the input node N1 to the comparator The gate of transistor T713, the voltage of this gate is VREFI. The second stage of the biaser 73 is a comparator, which is composed of: T711, T712, T713, T714, T715, and T716. The function of the comparator is to compare the voltage VREFI on the T713 gate with the reference voltage VREF on the T714 gate and generate a bias voltage (BIAS) at the output node K1 of the comparator as the output to the replica input stage 74 and the first counter. The feedback signal of phase 71. The VREF is the voltage value of the logic switching point to be set. This voltage is usually derived from a bandgap circuit or a power divider circuit. When the power supply voltage or semiconductor process changes, this circuit uses the negative feedback principle to stabilize the buffer logic switching point by adjusting the voltage value of the BIAS point. Generally, in the above-mentioned 15 1255399, in the inverter structure, when the intensity of the PMOS transistor is the intensity of the NMOS transistor, the output voltage of the inverter rises, when the strength of the PMOS transistor <In the case of the intensity of the NM0S transistor, the output voltage of the inverter drops. The present invention will now be described in a manner in which the bias voltage is used to control the input buffer to maintain a stable logic switching point of the buffer input/output voltage. (a) When VREFI>VREF, in practical applications, for example, the reference voltage VREF of the comparator is set to 1. 4V, when the other input voltage of the comparator (ie, the output voltage of the replica input stage) VREFI > When the reference voltage VREF (ie, 1.4V) is compared, the two input voltages VREF and VREF I are compared via the comparator, and the output voltage BI AS of the comparator is increased, thereby weakening the transistor combination structures 7, 8. The transistor combination structure 9, 10 is enhanced, so Lu makes the output voltage of the replica input stage, that is, the voltage of VREFI drops, and the comparator compares VREFI with VREF to adjust its output voltage BIAS, which is then copied through the input. The stage adjusts its output voltage VREFI to a level close to the original reference voltage VREF. (b) When VREFI < VREF In practical applications, for example, the reference voltage VREF of the comparator is set to 1. 4V, when the other input voltage of the comparator (ie, the output voltage of the replica input stage) VREFI <reference voltage VREF (ie At 1.4V), the two input voltages VREF and VREF I are compared via the comparator, and the output voltage BI AS of the comparator is lowered, thereby enhancing the transistor combination structure 7, 8 and the transistor combination structure. 9, 10 is weakened, thus causing the output voltage of the replica input stage, that is, the voltage of VREF I to rise, comparing VREFI with VREF via the comparator to adjust its output voltage BIAS, and then outputting the voltage VREFI via the replica input stage. Adjust to the level close to the original reference voltage VREF. (c) When the power supply voltage VD of the first inverting stage rises, in addition, when the power supply voltage VD of the first inverting stage of the input buffer rises, the strength of the transistor combination structure 1, 2 is enhanced, and the power is made The strength of the crystal combination structure 7, 8 is enhanced so that the output of the replica input stage of the bias (i.e., the input of the comparator) VREFI is raised, thereby causing the output voltage BIAS of the biaser to rise. Via this enhanced BIAS feedback voltage, the strength of the transistor assembly structures 1, 2 is attenuated, 16 1255399 and the strength of the transistor assembly structures 3, 4 is enhanced. Therefore, the sum of the sum of the crystal combination structures 1, 2 and the sum of the crystal combination structures 3, 4 can still maintain the relative strength before the increase of the power supply voltage VD, so that the output of the first inverting stage of the input buffer The voltage can still be maintained at the original level before the power supply voltage VD increases. Therefore, the fluctuation of the input/output voltage logic switching point of the above TTL to CMOS input buffer can be kept within a relatively small range, and the purpose and effect of stabilizing can be achieved. (d) when the power supply voltage VD of the first inverting stage is decreased, and when the power supply voltage VD of the first inverting stage of the input buffer is decreased, the strength of the transistor combination structure 1, 2 is weakened, and The strength of the transistor assembly structure 7, 8 is weakened, so that the voltage of the output VREFI of the replica output stage is lowered, and the output voltage BIAS of the comparator is decreased; via the falling BIAS feedback voltage, the transistor combination structure 1 can be made. The strength of 2, and the strength of the crystal composite structure 3, 4 is weakened, so that the sum of the strength of the crystal composite structures 1, 2 and the sum of the crystal combined structures 3, 4 can substantially maintain the power supply voltage VD before falling. The relative strength so that the output voltage of the first inverting stage of the input buffer can still remain close to the original level before the power supply voltage VD is increased; therefore, the input/output voltage of the TTL to the CMOS input buffer can be The change in the logical transition point is kept within a relatively small range, and the purpose and effect of stabilizing it are achieved. Therefore, it is known from the circuit structure of the buffer of the present invention that the main purpose of the present embodiment is to improve the lack of the improved circuit design of the above FIG. 4(B), wherein the buffer is used to reduce the current consumption in the replica input stage. The logic transition point of the input/output voltage characteristic curve varies greatly with the supply voltage or the semiconductor process change. In the present embodiment, the width/length of the formed transistor (including: PMOS transistor and NMOS transistor) in the input stage is directly copied as in the method used in FIG. 4(B) (W). /L) is tens of times smaller (for example, 25 times) to become 2/3 and 1/3; because the design of this method will increase or decrease the intensity of PM0S and NM0S transistors in different proportions, resulting in a buffer Significant changes in the input/round-out voltage logic transition point. Rather, the method used in this embodiment is: (1) by combining the respective transistors of the input stage, the transistor combination structure 7-10 is formed in series, and the equivalent width/length ratio is reduced to reduce The quiescent current and static power consumption of this replica input stage (please refer to the description of equation (1) above); and (2) because these input stages correspond to the phase 1255399 of the crystal combination structure formed in the replica input stage The width/length ratio of each of the constituent transistors of the position is unchanged (2/0.6 or 1/0·6), so the intensity of these and the entangled in the input stage is relative to the input stage. The strength of PMOS and MN has not changed'. In this way, the purpose and effect of stabilizing the logic conversion point of the buffer input/output voltage can be achieved. Therefore, the function and purpose of reducing the static power consumption of the buffer and stabilizing the logic switching point of its input/output voltage can be achieved by using the method of the embodiment. Specifically, the improvement of the design in Fig. 4(b) in Fig. 7(B) in the present embodiment is achieved in the following manner: (1) The T701-1 of the input stage in Fig. 7(B) is The five PMOS transistors of T701-5 (W/L=2/0. 6) are connected in parallel to form a transistor combination structure 1 having an equivalent w/l=1 〇/〇·6. This transistor combination structure corresponds to and replaces the transistor T401 (W/L=10/0.6) in the repair of Fig. 4(B); (2) T702-1 of the input stage in Fig. 7(B) The five PMOS transistors of T702-5 (W/L=2/0·6) are connected in parallel to form a transistor combination structure 2 having an equivalent w/L=10/0.6. The transistor combination structure corresponds to and replaces the transistor T402 in FIG. 4(B) (W/L 2/0. 6); (3) the input stage T703-1 in the 7(B) diagram is The five crystal oscillators of T703-5 (W/L=l/0. 6) are connected in parallel to form a transistor combination structure 3 having an equivalent w/l=5/〇. This transistor combination structure corresponds to and replaces the transistor T403 in FIG. 4(B) (W/L=5/0·6); (4) T704-1 to T704 of the input stage in the figure 7(B) The five NM0S transistors of -5 (W/L=l/0·6) are connected in parallel to form a transistor spring combination structure 4 having an equivalent W/L=5/0.6. This transistor combination structure corresponds to and replaces the transistor T404 in FIG. 4(B) (W/L=5/0·6); (5) Copy the input stage T707-1 in the 7(B) diagram. The five PMOS transistors to T707-5 (W/L=2/0.6) are connected in series to form a transistor combination structure 7 having an equivalent w/L=2/3. This transistor combination structure corresponds to and replaces the transistor T407 (W/L 2/3) in the 4th (B) diagram; (6) Copy the input stage T708-1 to T708 in the 7th (B) diagram Five PMOS transistors of -5 (W/L = 2/0. 6) are connected in series to form a transistor combination structure 8 having an equivalent w/L = 2/3. Corresponding to and replacing the transistor T408 (W/L 2/3) in the 4th (B) diagram; 18 1255399 (7) Copying the input stage of the 7th (8) diagram The five MOS circuits connected to Ding 709-5 ^ =1/0.6) are connected in series to form a transistor combination structure 9 having an equivalent W/L 4/3. This transistor combination structure corresponds to and replaces the transistor T409 in FIG. 4(B) (W/L=l/3); (8) Copy the input stage T710-1 to T710 in the 7th (B) diagram. The five MN OSs of -5 (W/L = 1/0. 6) are connected in series to form a transistor combination structure 10 having an equivalent W/L = 1/3. This transistor combination structure corresponds to and replaces the transistor T410 (W/L = 1/3) in Fig. 4(B). Therefore, as apparent from the above description, the transistor combination structures 7, 8, 9, and 10 in the replica input stage correspond to the transistor combination structure in the input stage circuit via the design in the seventh (B) above. 1, 2, 3, and 4; the equivalent width / length (W / L) φ ratio '1 〇 / 由. 6, 1 〇 / 〇. 6 of the above-mentioned respective transistor combination structure in the original input stage circuit. 5/0·6, 5/0. 6 are respectively reduced to 2/3, 2/3, 1/3, 1/3 of each of the above-mentioned transistor combination structures in the replica input stage circuit, that is, reduced to 1/25 of the original . Therefore, the resistance of the replica input stage rises to 25 times the original resistance, and the current consumption and power consumption are also reduced to 1/25 of the original. However, since the width and length of the valley-constituting transistors (including the PMOS transistor and the CMOS transistor) of the combination structure of the input-stage circuit and the replica input-pole circuit are not changed, each of the PMOS, MN The strength of the S transistor is also unchanged. Therefore, the voltage converted from the TTL to the input buffer of the CMOS, and thus the logic switching point of the output voltage of the bean, can be kept stable under the power supply voltage or process variation without being modified. In this way, the function and target of the stable logic switching point are achieved. Next, please refer to Figure 8. Figure 8 is a diagram showing the variation of the buffer input/wheeling voltage characteristic curve and the bean logic switching point when the power source voltage fluctuates according to an embodiment of the present invention. ^ is the same as shown in Fig. 8, whose horizontal axis is the input voltage, and its vertical axis is the output voltage, and its early position is volt. The three curves shown therein represent the input/output voltage conversion curves when the power supply voltages of the transistor combination structure 1 are VD=3V, 3·3ν, and 3·6ν, respectively. As can be seen from the figure, when the power supply voltage is ¥1)=扒, the logic conversion point VSW of this buffer is i·436V; when the power supply voltage VD=3·3V, the logical conversion point of this buffer VSW is 1.429V; and when the power supply voltage VD = 3.6V, the logical conversion point of this buffer | 1.423V. It can be seen from Fig. 8 that when the power supply voltage is 19 1255399 3 this 31 Γ:3·6" Temple, its logic switching point voltage value changes only i3mv. r Cry Cry: In the case of ^ month, "When the power supply voltage of this buffer changes, this σσ force human voltage out of the logic conversion point only shows a small change and can maintain a stable april = what is the slow f The characteristic curve of the input/output electric power shows the case where the logical conversion point of the input/output voltage of the buffer changes according to the change of the second and the fourth. As in the q. Figure by Cheng-good w adjustment Shandian Kedan supply point | ^ + # 00 / ' f θ no, its plate axis is the input voltage, its vertical axis is typica1' slow^^: 2; ί:=Γ conversion curve '...represents: the parts made by this process are blood type, pro-sound, Υ and ί main typicai representative: the semiconductor element made by this process H_冃二1 k, S 〇W stands for: The semiconductor components fabricated by the process are slow. It can be clearly seen from the above that the three voltage conversion lines are very close. Therefore, when the Ξΐί sends a change, the difference between the slew represented by sl(10) and fast is only (4), so the logical transition point of the input/output voltage characteristic curve can be kept fairly stable. Figure 10 is an instantaneous transient diagram of the input/output voltage, which is shown according to this = (8), the vertical axis is the voltage, and the unit is volt (V). Among them, the line of the bus line should not be buffered for the waveform change of the input voltage from the D-hole, and the dotted line H is 0. As can be seen from the figure, the output voltage waveform has a period of two π TR=0·49ns, and the fall time is TF=: 〇. 46ns. Service-Cause: + As can be seen from the above description, the circuit of the present invention can indeed improve the shortcomings and limitations of the TTL conversion to the CM0S buffer of the factory, that is, the logical transition point of the 1 wheel input/output voltage changes greatly. The lack of it, to become a high: quasi-transmission of pottery, and high to low level. . The tongue is t咼, the low level of noise margin (noisemargln) is worse, = and other shortcomings and limitations. By using the snubber circuit of the present invention: ^; The conversion point tends to be stable, ensuring that the entire CMOS circuit operates normally, and that its power consumption is low. Therefore, the present invention is of patent value and conforms to the patent requirements: U is only a preferred embodiment of the present invention, and is only used to limit the scope of the patent application; any other disclosure without departing from the invention Equivalent changes or modifications made in the spirit and scope of the invention shall be included in the scope of the patent application described in the following 20 1255399 [Simple description of the drawings] Figure 1 (A) is based on the prior art A schematic diagram of the circuit of the input to which the TTL is converted; Figure 1(B) is a detailed circuit diagram of the input from TTL to CM〇s according to the prior art; and _ is the first (c) diagram The instantaneous transient map of the input buffer converted from TTL to CM〇s; the voltage f is a characteristic of the buffer shown in the first (B) diagram at different power supply voltages; Figure 3 shows the output voltage conversion characteristic curve of the buffer shown in the figure for the different semiconductors. The input of the first class private / the figure of the figure is for the previous application. The outline of the improved circuit of the snubber circuit is 4:) The picture is for the previous application. Detailed circuit of the improved circuit of the punch circuit
弟5出UiBi圖中所示緩衝器於不同電源電壓下之輸入/輸 出ΐ壓轉換特性曲線； W 第中所示緩衝器於不同半導體製程下之輸入/ 物出電壓轉換特性曲線； 弟7(A)圖為根據本發明實施例之由TTL轉換至 衝器之電路概要方塊圖； 第圖為根據本發明實施例之纟TTL轉換i CM〇s之輸入緩 衝為之詳細電路圖； #8 mu)圖中所示緩衝器於不同電源電壓下之輸入/輸 出冤μ轉換特性曲線； 第9圖為第7⑻圖中所示緩衝器於不同半導體製程下之輸入/ 21 1255399 輸出電壓轉換特性曲線；以及 第10圖為第7(B)圖中所示緩衝器於特定電源電壓下之輸入/輸 出電壓之瞬間暫態圖。 【符號元件說明】The output voltage curve of the input/output voltage of the buffer shown in the UiBi diagram at different power supply voltages; W is the input/output voltage conversion characteristic curve of the buffer shown in different semiconductor processes; A) is a block diagram showing the circuit of a TTL conversion to a buffer according to an embodiment of the present invention; the figure is a detailed circuit diagram of the input buffer of the TTL conversion i CM〇s according to an embodiment of the present invention; #8 mu) The input buffer shown in Figure 7 is the input/output 冤μ conversion characteristic curve at different power supply voltages; Figure 9 is the input/21 1255399 output voltage conversion characteristic curve of the buffer shown in Figure 7(8) for different semiconductor processes; Figure 10 is an instantaneous transient diagram of the input/output voltage of the buffer shown in Figure 7(B) at a particular supply voltage. [Signature Component Description]
10 、 40 、 70 緩衝器 1卜4卜71 第一反相器 12 、 42 、 72 第二反相器 • 43、73 偏壓器 44、74 複製輸入級 45、75 比較器 T101 > T103 T4(U 、 T402 T405 、 T407 T408 、 T411 T412 T70H，-5 T702小-5 T707-1 ^ -5 T708小-5 T7U、T712 PMOS • T102 、 T104 T403 、 T404 T406 、 T409 T410 、 T413 T414 、 T415 T416 T703-；l，-5 Τ704-：1，-5 NMOS 22 125539910, 40, 70 Buffer 1 Bu 4 71 First Inverter 12, 42 , 72 Second Inverter • 43, 73 Bias 44, 74 Copy Input Stage 45, 75 Comparator T101 > T103 T4 (U, T402 T405, T407 T408, T411 T412 T70H, -5 T702 small-5 T707-1 ^ -5 T708 small-5 T7U, T712 PMOS • T102, T104 T403, T404 T406, T409 T410, T413 T414, T415 T416 T703-;l,-5 Τ704-:1,-5 NMOS 22 1255399
邏輯轉換點Logical transition point
T709-：l，-5 T71(M，-5 T713-T716 K、Μ、N K1 > Ml > N1 A、B、C、DT709-:l,-5 T71(M,-5 T713-T716 K, Μ, N K1 > Ml > N1 A, B, C, D
23twenty three