TWI255029B - Electrostatic discharge protection device - Google Patents

Abstract

The present invention provides an electrostatic discharge protection device used to protect an internal circuit having a positive voltage output and a negative output consisting of two metal oxide semiconductors. One end of the first metal oxide semiconductors is connected to a positive working voltage, and the other end is grounded with a gate while its substrate connecting to the end of grounded terminal. One end of the second metal oxide semiconductors is grounded, and the other end is connected to a negative working voltage with the gate while the two ends connected to each other with its substrate connected to the end of the negative working voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device, particularly to an electrostatic discharge protection device for a high voltage component. [Prior Art] Gate grounding (ga te - gr ound ) N-type (ggN) or P-type (ggP) metal oxide semiconductor (M0S) structure, generally applied to the electrostatic discharge protection device of the current class of micrometer integrated circuit The main feature of the component is its parasitic bi-carrier (bi ρ ο 1 ar ) component. When an instantaneous high voltage occurs, its parasitic bi-carrier will be triggered to properly guide the high current generated by its high voltage to V ss or Vdd 〇 - The first figure shows the schematic diagram of the circuit structure of a gate-grounded N-type or P-type MOS semiconductor generally used for high-voltage components for electrostatic discharge protection. An electrostatic discharge protection device, such as g g N Μ 0 S 1 1 5 , has its gate connected to an input terminal such as a source or a drain, and the other end of which is connected to an internal circuit 1 13 to a working voltage. When there is a momentary positive high voltage, the parasitic bi-carrier component in ggNM0S 1 15 is activated to direct high current to Vss. The second figure shows the application principle of the first figure. When an ESD event occurs on an input pad, the ggNMOS 11 5 will be triggered and enter the snapback region, where the ggNMOS 11 5 will clamp across. One of its own low potential voltages maintains a high current, so this electrostatic discharge current can be effectively directed out. However, since the high voltage component is used in high voltage environmental operation, the electrostatic discharge protection device for the high voltage component is designed to be triggered when an electrostatic discharge attack is applied. But if the input/output terminals have both positive and negative operating voltages

1255029 5. In the invention description (2), the conventional electrostatic discharge protection cannot protect all the input/output terminals. [Inventive content] For the above, to ensure protection to all input/output terminals, an electrostatic discharge protection device, The use of MOS semiconductors in the ESD protection device can avoid simultaneous attack by positive and negative voltages.

According to the above, an electrostatic discharge protection device for protecting an internal circuit having a positive voltage output terminal and a negative voltage output terminal includes two MOS semiconductors. One of the ends is connected to a positive working voltage, the other end is grounded to the gate, and the substrate is connected to one end of the ground - the other end of the metal oxide semiconductor is grounded, and the gate is connected to the other end to a negative operating voltage, and The two ends are connected, and the substrate is also connected to one end connected to the negative working voltage. [Embodiment]

Referring to the third figure, the electrostatic discharge protection device comprises two MOS semiconductors 15 and 17, such as an N-type MOS. One end a1 of the MOS semiconductor 15 is, for example, a source or a drain, connected to an operating voltage for supplying a positive voltage, and the other end a3, such as a source or a drain, is grounded to the gate a 2 and bottomed. The material is connected to the other end a 3 of the ground, and functions as the same diode. One end b1 of the MOS semiconductor 17 is grounded, for example, the source or the drain, and the gate b 2 and the other end b 3 , such as the source or the drain, are connected to a working voltage for supplying a negative voltage, and the substrate thereof It is connected to the other end b 3 of the connection, and both ends bl of the MOS 17 are connected to b 3 and function as a resistor. On the other hand, an internal circuit 13 is also connected to the operating voltage pad and the ground pad for supplying positive and negative voltages, respectively. Internal circuit 13 can receive -1 2 to 0 volts

Page 6 1255029 V. Description of the invention (3) Special input and input from 0 to 12 volts. The internal circuit 13 includes two N-type MOSs 14 and 18, and P-type MOSs 12 and 16. The gates of the P-type MOS 12 and the N-type MOS 14 are connected to the input of 0 to 12 volts, and one end is connected in common to output 0 to 12 volts to an output pad. Secondly, the gates of P-type MOS 1 2, 16 are connected to the input of 0 to -1 volt, and one end is connected to output 0 to -1 2 volts to an output pad. One end of the P-type MOS semiconductor 1, 2, and N-type MOS 14 is connected to the substrate to form a diode. The N-type MOS semiconductor 18 further includes two ends connected to form a resistor function.

According to the above, when the output/input terminal is subjected to electrostatic attack, whether it is the output/input of the positive operating voltage or the output/input of the negative operating voltage, a large amount of excess current generated by the output can be smoothly discharged by the appropriate channel. To positive, negative operating voltage or ground.

The fourth figure shows an electrostatic discharge protection device in accordance with another embodiment of the present invention. Referring to the fourth figure, the connection and action of the MOS semiconductors 15 and 17 are the same as those of the third figure, and all the components in the internal circuit 13 are, for example, two N-type MOS semiconductors 14 and 18, and P. The MOSs 1 2 and 16 are also the same as in the third figure. However, in this embodiment, the electrostatic discharge protection device further includes two other gold-iridium semiconductors 2 1 and 2 3, such as an N-type gold oxide semiconductor. For the MOS 2 1 , one end c 1 , such as a source or a drain, is connected to supply a working voltage for a positive voltage, and the other end c 3 , such as a source or a drain, is connected to the internal circuit 1 3 . The output of 0 to -1 2 volts. Furthermore, the gate _ pole c 2 is connected to the one end c 3 and functions as the same diode. Similarly, for MOS 2 3, one end d 3 , such as a source or a drain

Page 7 1255029 V. Inventive Note (4), connected to provide a working voltage of negative voltage, the gate d 2 is connected to d 3 , and the other end d 1 is connected to 0 to 12 volts in the internal circuit 13 The output is also the same diode. The fifth figure is a circuit diagram in accordance with another embodiment of the present invention. Similar to the fourth figure, the gold oxide half bodies 21 and 23 in the fourth figure are replaced by two diodes 25 and 27, but the action is the same as that of the metal oxide semiconductors 21 and 23. Fig. 6 is a cross-sectional view showing the MOSs 2 1 and 2 3 of the electrostatic discharge protection device of the embodiment of the fourth embodiment. Two N-type wells 3 2 are formed in the P-type substrate 30. The spacer element 34 is formed under the surface of the P-type substrate 30, and the N-type i-doped region 3 is formed between the two adjacent spacer elements 34. The conductive element 3 of the P-type substrate 30 is electrically conductive. Structure 3 8. In operation, for example, when an electrostatic discharge attack occurs between a negative voltage input terminal and a positive operating voltage terminal, two parasitic bipolar transistor transistors need to be triggered. When a parallel N-type MOS device is added in this embodiment, the application is applied. The general well concentration control in the CMOS process can achieve the appropriate trigger voltage in the structure of electrostatic discharge protection. Fig. 7 is a cross-sectional view showing the diodes 25 and 27 of the electrostatic discharge protection device of the embodiment in the fourth embodiment. The P-type substrate 40 has a deep N-type well 4 4 , and the deep N-type well 4 4 has a P-type well region 42 and a N-type well 46 6 on both sides. Similar to the sixth figure, when a parallel diode is added to the embodiment, the general well concentration control in the CMOS process can be used to achieve an appropriate trigger voltage in the electrostatic discharge protection structure. It is to be noted that the above embodiment is described with + 1 2 or -1 2 volts, but is not limited thereto, and any high-voltage component, that is, a high-voltage component having an operating voltage greater than 5 volts, does not depart from the scope of the invention.

1255029 V. INSTRUCTIONS (5) The above-described embodiments are merely illustrative of the technical spirit and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and implement them. The scope of the invention is defined by the scope of the invention, which is to be construed as being limited by the scope of the invention.

Page 9

1255029 Brief description of the diagram [Simplified description of the diagram] The first diagram is a schematic diagram of the circuit arrangement of the gate grounded N-type or P-type MOS conductor for electrostatic discharge protection. The second picture is the application principle of the first figure. The third figure is a schematic diagram of a line device for electrostatic discharge protection according to an embodiment of the present invention. The fourth figure is a schematic diagram of a line device for electrostatic discharge protection according to another embodiment of the present invention. Fig. 5 is a circuit diagram showing electrostatic discharge protection according to another embodiment of the present invention. Figure 6 is a schematic cross-sectional view of an embodiment of the present invention for electrostatic discharge protection. Figure 7 is a schematic cross-sectional view of an embodiment of the present invention for electrostatic discharge protection. [Main component symbol description] 1 0 input terminal 1 2P type MOS semiconductor 1 3 internal circuit 14N type MOS semiconductor . . 15 MOS semiconductor 1 6 P type MOS semiconductor 1 7 MOS semiconductor 1 8 N type MOS semiconductor 21 MOS semiconductor

Page 10 1255029

Brief description of the diagram 2 3 MOS 2 5 diode 2 7 diode 1 1 0 input 1 1 2 resistance 1 1 3 internal circuit 115ggNM0S 1 1 7ggPM0S

Claims (1)

1255029 VI. Patent Application No. 1 · An electrostatic discharge protection device for protecting an internal circuit having a positive voltage output terminal and a negative voltage output terminal, the electrostatic discharge protection device comprising: a first gold oxide semiconductor, the first a first end of the MOS is connected to a positive working voltage, a second end is grounded to a first gate, and a first substrate is connected to the second end; and a second MOS, a third terminal of the second MOS is grounded, a second gate and a fourth terminal are connected to a negative operating voltage, and the third terminal is connected to the fourth terminal, and A second substrate is coupled to the fourth end. The electrostatic discharge protection device according to claim 1, wherein the first oxynitride is an N-type MOS. 3. The electrostatic discharge protection device of claim 1, wherein the second MOS semiconductor is an N-type MOS. 4. The electrostatic discharge protection device of claim 1, further comprising a third gold-oxide semiconductor connected in parallel, wherein a fifth end of the third metal oxide semiconductor is connected to the positive working voltage, a sixth end Connected to the third gate to the negative voltage output. 5) The electrostatic discharge protection device according to claim 4, wherein The third MOS semiconductor is an N-type MOS. 6. The electrostatic discharge protection device of claim 4, further comprising a fourth gold-oxide semiconductor connected in parallel, wherein a seventh end of the fourth metal oxide semiconductor is connected to the positive voltage output terminal, an eighth The terminal and the fourth gate are connected to a negative operating voltage. ^ Page 12 1255029 6. Patent application scope 7. The electrostatic discharge protection device according to claim 6, wherein the fourth MOS semiconductor is an N-type MOS. The electrostatic discharge protection device of claim 1, further comprising a first diode connected in parallel, wherein a fifth end of the first diode is connected to the positive working voltage, a sixth end Connect to the negative voltage output - terminal. 9. The electrostatic discharge protection device of claim 8, further comprising a second diode connected in parallel, wherein a seventh end of the second diode is connected to the positive voltage output terminal, an eighth The terminal is connected to a negative operating voltage. -