1254446 第93137163號專利說明書修正本 - 修正日期：94.12.:27 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種積體電路的製造與形成方法，且 特別有關於一種積體電路之多晶石夕層的製造與形成方法。 【先前技術 由於目前產生許多需要高密度儲存元件的新應用，所 以對具有小構裝尺寸（package size)與高 儲存密度的儲存 元件之需求越來越高，而半導體元件幾何尺寸持續地大幅 縮小’其中一般存在元件具有小於65 nm構件幾何尺寸的 範圍13 然而，記憶體元件與其它儲存元件的製造常會面臨各 式問題’如記憶體元件與周邊（SUpp0rting )微電子元件間 在表面構形地形上（t〇p0graphic)的差異’這些問題可與 過度蝕刻、過度平坦化與/或其它對某些構件造成損傷等因 素相關’但同時其它構件並未被損傷。 有鑑於此，業界亟需提出一種積體電路元件與其製造 方法，以解決上述問題。 【發明内容】 有鑑於此，本發明的目的之一就是提供一種製造微電 子電路元件的方法與積體電路元件，以解決上述問題。 為達上述目的，本發明提供一種製造微電子元件的方 法’包括：提供具有複數個部分完成的微電子元件的基底， 微電子元件包括至少部份完成的記憶體元件與至少部份完 0503-A30208TWFl/ice 5 1254446 第93137163號專利說明書修正本 修正日期：94.12.27 成的電晶體；在部分完成的電晶體部分土形成第一層，以 在隨後的材料移除步驟中保護至少部分完成的電晶體的部 分；形成第二層大體上覆蓋部分完成的記憶體元件與部分 完成的電晶體；移除部分第二層，留下部分的第二層於部 分完成的記憶體元件上；以及在第二層的部分移除後，從 部分完成的電晶體移除至少實質部分的第一層。 為達上述目的，本發明尚提供一種製造微電子元件的 方法，包括：提供具有護層與複數個絕緣結構的基底，其 中護層位於基底中，且複數個絕緣結構延伸過護層且至少 部分延伸至基底上；形成罩幕於護層與複數個絕緣結構所 共同構成的平面的第一部份上，以使該遮蔽的表面的第一 部份與未遮蔽的表面的第二部份共享邊界；將護層的犧牲 部分從未遮蔽的第二部份中移除；移除罩幕；形成順應層 於護層的殘留的部分上、絕緣結構上與藉由移除護層的犧 牲的部分所形成之空隙中；平坦化順應層，以使順應層、 絕緣結構與護層的殘留的部分共平面；移除殘留的該護層 部分；以及形成電晶體於移除護層的殘留的部分所造成的 空隙中。 為達上述目的，本發明尚提供一種製造微電子元件的 方法，包括：提供具有護層與複數個絕緣結構的基底，其 中護層位於基底上，且複數個絕緣結構延伸過護層且至少 部分延伸至基底中，基底包括至少記憶體單元區與至少周 邊電路區；形成罩幕於至少周邊電路區的部份與露出的至 少記憶體單元區的部份上；將護層的犧牲的部分從記憶體 0503-A30208TWFl/ice 6 1254446 第93137163號專利說明書修正本 元件區中移除；移除罩幕；形成順應層於讓佟足日期：94·η··27 刀上、絕緣結構上與藉由移除護層的犧牲的、的或留的部 空隙中；平坦化順應層，以使順應層、絕緣2分所形成之 殘留的部分共平面；移除殘留的護層部分·、構與瘦層的 體於移除護層的殘留的部分所造成的空隙中^及形成電晶 為達上述目的’本發明提供一種積體電 %元件， 具有至少記憶體單元區與至少周邊電路 件，包括的基底；複數個 絕緣結構位於記憶體單元區中；複數個 主動區， 每個主動 區皆位於複數個絕緣結構的鄰近處間；以 二 極層’每層閘極電極層皆位於複數個絕緣&欠數層閘極電且位於所對應的複數個主動區上，每屑笳二请的鄰近處間 曰>^歎層Ρ的寬度大於與閘極電極層接觸的相鄰絕緣二閉極電極層 度。 …、、、結攝的間隔寬 [實施方式] 為使本發明之上述和其它目的、特彳曼# 易懂，下文特舉出較佳實施例，並配合戶斤·“、七月b更明顾 說明如下： 、圖式，作詳細 請參閱第1圖，此圖為本揭露製裎、 此/ 甲之分閘場效電晶 體（split gate field effect transistor，簡稱 Sgfet) 一 4 的剖面圖，此SGFET元件100可為單—垃 ^ 接面（junction) 半導體元件’此元件1〇〇也可為複數個SGFET或SGFET 單元陣列之一，然而，為清楚與簡化起見，第1圖顯示一 個單一元件100，此外，雖然本揭露係描述SGFET元件， 0503-A30208TWFl/ice 7 1254446 第93137163號專利說明書修正本 … 修正日期-：94.19 27 但熟習此技藝之人士應可瞭解本揭露尚可適用於其— 體元件，例如快閃記憶體中的堆疊閘極技街與1二二曰> 導 技術。 ”匕電晶體 元件100包括具有源極區120於其中 1;。可為單晶……、心1二基； (S1l1Ccm-〇n-msulator，簡稱s〇I)基底包括矽 後曰 於矽或藍寶石基底上、塑膠或其它彈性基底、或其：：二 或未來會發明出的基底；此基底11〇可為或包括:車：： 導體70件上的接觸插塞或内連線，例如，基底 赤 包括半導體晶圓或形成於半導體基底上的其它^極^ ^可藉由佈_、硼與/或藉由擴散、離子佈植 形成’在—實施例中，源極區12。可形成 = 更重!參雜區或主動區禮。基底no尚可： 括匕未在乐1圖中顧示的構件， 側的絕緣區，此絕緣區包括 二二120㈣ 。一簡一)舆'*溝隔離 源極區120與其它形成在基底 ）故基底110、 揭露所限定。 —中的特定組成並未被本1254446 Patent Revision No. 93137163 - Revision Date: 94.12.:27 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing and forming an integrated circuit, and more particularly to an integrated body A method of fabricating and forming a polycrystalline layer of a circuit. [Prior Art Due to the current generation of many new applications requiring high-density storage elements, there is an increasing demand for storage elements having small package sizes and high storage densities, and the geometry of semiconductor elements continues to shrink substantially. 'There are generally components with a range of less than 65 nm component geometries. However, the fabrication of memory components and other storage components often faces various problems, such as surface topography between memory components and peripheral (SUpp0rting) microelectronic components. Differences in (t〇p0graphic) 'These problems can be related to factors such as over-etching, excessive planarization, and/or other damage to certain components' while other components are not damaged. In view of this, it is urgent to propose an integrated circuit component and a manufacturing method thereof to solve the above problems. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method of manufacturing a microelectronic circuit component and an integrated circuit component to solve the above problems. To achieve the above object, the present invention provides a method of fabricating a microelectronic component comprising: providing a substrate having a plurality of partially completed microelectronic components, the microelectronic component comprising at least a partially completed memory component and at least a portion of the 0503- A30208TWFl/ice 5 1254446 Patent specification No. 93137163 modifies this modification date: 94.12.27 into a transistor; the first layer is formed in the partially completed transistor portion soil to protect at least partially completed in the subsequent material removal step a portion of the transistor; forming a second layer that substantially covers a portion of the completed memory component and the partially completed transistor; removing a portion of the second layer, leaving a portion of the second layer on the partially completed memory component; After the portion of the second layer is removed, at least a substantial portion of the first layer is removed from the partially completed transistor. To achieve the above object, the present invention still provides a method of fabricating a microelectronic component, comprising: providing a substrate having a sheath and a plurality of insulating structures, wherein the sheath is located in the substrate, and the plurality of insulating structures extend through the sheath and at least partially Extending onto the substrate; forming a mask on the first portion of the plane formed by the sheath and the plurality of insulating structures such that the first portion of the masked surface is shared with the second portion of the unmasked surface Boundary; removing the sacrificial portion of the sheath from the unmasked second portion; removing the mask; forming a compliant layer on the remaining portion of the sheath, insulating the structure, and sacrificing by removing the sheath Part of the formed void; flattening the compliant layer such that the compliant layer, the insulating structure and the remaining portion of the sheath are coplanar; removing the remaining portion of the sheath; and forming a residual of the transistor in the removal of the sheath Part of the gap created. To achieve the above object, the present invention still provides a method of fabricating a microelectronic component, comprising: providing a substrate having a sheath and a plurality of insulating structures, wherein the sheath is on the substrate, and the plurality of insulating structures extend over the sheath and at least partially Extending into the substrate, the substrate includes at least a memory cell region and at least a peripheral circuit region; forming a mask on at least a portion of the peripheral circuit region and a portion of the exposed at least memory cell region; and the sacrificial portion of the sheath Memory 0503-A30208TWFl/ice 6 1254446 Patent specification No. 93137163 to correct the removal of this component area; remove the mask; form a compliant layer on the date of the lame: 94·η··27 knife, insulation structure and borrow By removing the sacrificial or residual voids of the sheath; flattening the compliant layer so that the remaining portions formed by the compliant layer and the insulating layer are coplanar; removing the residual sheath portion, The thin layer body is in the void caused by the removal of the remaining portion of the sheath and the formation of the electromorphic crystal for the above purpose. The present invention provides an integrated electrical component having at least a memory cell region and a peripheral circuit component, including a substrate; a plurality of insulating structures are located in the memory cell region; a plurality of active regions, each active region being located adjacent to the plurality of insulating structures; and a gate electrode of each layer The layers are all located in a plurality of insulating & sluice gates and are located on the corresponding plurality of active regions, and the width of each smear layer is greater than the contact with the gate electrode layer The adjacent insulated two closed electrode layers. The interval between the ..., and the photographing is wide [Embodiment] In order to make the above and other objects of the present invention, the specifics of the present invention are easy to understand, the following is a preferred embodiment, and is compatible with the households, ", July b The description of the following is as follows: , drawings, for details, please refer to FIG. 1 , which is a cross-sectional view of the split gate field effect transistor (Sgfet) 1-4 of the present disclosure. The SGFET device 100 can be a single-junction semiconductor device. This device 1 can also be one of a plurality of SGFET or SGFET cell arrays. However, for clarity and simplicity, FIG. 1 shows A single component 100, in addition, although the disclosure describes a SGFET component, 0503-A30208TWFl/ice 7 1254446 Patent Specification No. 93137163 Revision Date:: 94.19 27 However, those skilled in the art should understand that the disclosure is applicable. In its body element, such as a stacked gate in a flash memory, and a technique of "two-two", the germanium transistor element 100 includes a source region 120 therein. It may be a single crystal..., a core 1 base; (S1l1Ccm-〇n-msulator, abbreviated as s〇I) a substrate comprising a crucible or a sapphire substrate, a plastic or other elastic substrate, or its: a substrate that can be invented; the substrate 11 can be or include: a contact plug or an interconnect on a conductor: 70, for example, the base red includes a semiconductor wafer or other electrodes formed on the semiconductor substrate. ^ Source region 12 may be formed by cloth, boron, and/or by diffusion, ion implantation. Can form = heavier! Miscellaneous area or active area. The base no is acceptable: the member is not shown in the picture of the music, the insulating area on the side, and the insulating area includes two two 120 (four). A simple one) 舆 '* trench isolation source region 120 and other formed on the substrate) is defined by the substrate 110, the disclosure. - the specific composition of the
元件⑽也包括形成於基底11Q 形成於閘極氧化層130上的m ’才虱化層130 . 刀雕閘極140、形志於分離 極140上的間隙壁15〇、形 v成於刀離閘 上的源極内連線⑽，其中閑極^150間與源極區120 與間隙壁150統稱為閑極結平〇 '分離閘極140 方式如下：首先在基底no :二=結構105的形成 上/儿積虱化層與閘極材料層； 0503-A30208TWFl/ice 1254446 第9j1j716j號專利說明書修正 严 " 修正日期14.12.27 钕刻氧化層與_材料層以露出部分基底，且【義出閑極 乳化層13G與分離閘極Mq ;在氧化層與露出的基底部分 形成間隙_料層；以及侧間隙壁材料層以形成間隙壁 1)〇 一貫施例中，源極區120的形成可在沉積間隙壁材 料之Η以分離閘極14〇作為罩幕，在間隙壁15〇形成後， 再於源極區12G與間隙壁15G間形成雜内連線16〇，且 源極内連線16〇高度可小於閘極結構1〇5的高度η，如第 1圖^示。在一實施例中，間隙壁15〇可從源極内連線 將为離閘極140隔離，且可藉由經源極内連線16〇的電容 病合將偏壓加在分離閘才虽14〇 i。上述之目案化步驟包括 光锨影、幾罩幕式光微影、接觸插塞微影、電漿與/或乾蝕 刻、離子碾磨、化學蝕刻與/或其它製程。 閑極氧化層130可包括Si〇2、Ta2〇5、Hf2〇、Zr〇2與/ 或其它介電材料，以提供所需之等效氧化物厚度，且可藉 由原子層"L 積（atomic layer deposition，簡稱 ALD)、化 學氣相沉積（CVD)、電漿增進式化學氣相沉積（pECVD)、 物理氣相沉積（PVD)熱或快速熱製程（RTp)氧化與/或The component (10) also includes an m'-deposited layer 130 formed on the gate oxide layer 130 on the substrate 11Q. The blade gate 140, the spacer 15 formed on the separation electrode 140, and the shape v are formed in the blade The source interconnection line (10) on the gate, wherein the idle pole ^150 and the source region 120 and the spacer wall 150 are collectively referred to as the idle pole junction 〇 'separation gate 140 as follows: first in the substrate no: two = structure 105 Forming an upper/child accumulation layer and a gate material layer; 0503-A30208TWFl/ice 1254446 Patent Specification No. 9j1j716j Amendment to the strict revision of the date 14.12.27 etching the oxide layer and the _ material layer to expose part of the substrate, and The idle electrode layer 13G and the separation gate Mq are formed; a gap layer is formed between the oxide layer and the exposed base portion; and a side spacer material layer is formed to form the gap 1). In the consistent embodiment, the source region 120 After forming the spacer material, the gate 14 is separated as a mask. After the spacer 15 is formed, a hetero interconnect 16 〇 is formed between the source region 12G and the spacer 15G, and the source is inside. The height of the connection 16 可 can be smaller than the height η of the gate structure 1 〇 5, as shown in Fig. 1. In one embodiment, the spacer 15 〇 can be isolated from the gate 140 from the source interconnect, and can be biased to the split gate by a capacitive connection through the source interconnect 16 〇 14〇i. The above described visualization steps include photomasking, masking lithography, contact plug lithography, plasma and/or dry etching, ion milling, chemical etching, and/or other processes. The idler oxide layer 130 may comprise Si 〇 2, Ta 2 〇 5, Hf 2 〇, Zr 〇 2 and/or other dielectric materials to provide the desired equivalent oxide thickness, and may be formed by the atomic layer "L product Atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (pECVD), physical vapor deposition (PVD) thermal or rapid thermal process (RTp) oxidation and/or
同處產生?m (In Situ Steam Generation，簡稱 isSG ) RTP 氧化所形成，且此閘極氧化層13〇的厚度約為1〇〇埃或更 薄。 、 分離閘極140可包括金屬矽化物、摻雜與/或未摻雜多 晶矽、金屬氧化物、阻障層與金屬導體、阻障層與非金屬 導體與/或其它可提供應用之特定需求之同等電性元件效 能的材料，此分離閘極14〇可藉由ALD、CVD、pec：vd、 0503-A30208TWFl/ice 9 1254446 修正日期：94.12.27 第93137163號專利說明書修正本 PVD與/或其它製程形成，其寬度約為1〇〇〜4〇〇〇埃，且厚 度約為1〜800埃。 間隙壁150可包括si02與/或其它介電材料，且可選擇 與元件製程熱預算相符的材料，間隙壁150可藉由ALD、 CVD、PECVD、熱或 RTP 氧化、ISSGRTP 氧化、PVD 與/ 或其它製程形成，其厚度約為1〇〜4〇〇埃，且寬度約為1〇 〜4 0 0 〇埃。 源極内連線160可包括一種或多種導體材料，包括多 晶矽、金屬矽化物與/或金屬氧化物，且也可包括阻隔層與 /或鍍層（cladding)，如 Ti、Ta、TiN、TaN、TiW、CN、 SiC 與 SiCO，源極内連線 160 可以 ALD、CVD、PECVD、 PVD 與/或電鍍銅製程（electroplating copper process，簡稱 ECP)形成，其厚度約為1〇〇〜4〇〇〇埃，且寬度約為1〇〜 4000埃，再者，如第1圖所示，源極内連線160的剖面輪 廓可根據於其周圍構件之幾何形狀逐漸變小或呈垂直狀。 SGFET元件1〇〇也可包括絕緣層170以使前述構件與 之後所形成之内連線絕緣，此絕緣層170可包括Si〇2、Si3N4 與/或其它介電材料，盡量選擇與製程熱預算相符的材料， 絕緣層170可以ALD、CVD、PECVD、旋轉塗佈製程、熱 或RTP氧化、ISSGRTP氧化與/或PVD形成，且其厚度約 為1〜300埃。 SGFET元件1〇〇也可包括内連線層，此内連線層 可為位元線、字元線與/或其它内連線（在此統稱為内 連線），在如第丨圖所示之實施例中，内連線層18〇是於 〇503-A30208TWFl/ice 10 1254446 第:93137163號專利說明書修βΓ… 一修正日期：94.12.27 絕緣層170上作全®性洗積所形成，但也可利用選擇性沈 積形成，内連線層180可包括一種或多種導體材料，如摻 雜或未摻雜多晶破、金屬石夕化物與/或金屬氧化物，且可包 括阻隔層如 Ti、Ta、TiN、TaN、TiW、CN、SiC 與 SiCO， 此内連線層180可以ALD、CVD、PECVD、ECP與/或PVD 形成，其厚度約為50〜4000埃，且其寬度約為50〜4000 埃，在一實施例中，内連線層180厚度可小於閘極結構105 的高度Η。 上述構件為本發明之構件結構，如第1圖所示，許多 構件具有相對於蒼考平面115之相對南度’且此蒼考平面 115與基底110的主要平面平行，例如，閘極結構105的 高度Η高於參考平面115，但源極内連線160的厚度就小 於閘極結構105的高度Η，同樣地，内連線層180包括具 小於高度Η的第一部份185與小於高度Η的第二部份 187，如上所述，在一般平坦化的方法中，而構件的地形因 素會產生不想見到的結果，如圓角（rounded corners )、過 量殘留增加（excessive residue build_up)與具有尖突的邊 緣（jagged edges)。 請參閱第2圖，此圖為第1圖所示之元件1 〇〇在内導 線層180上形成蓋層190後的剖面圖，蓋層190可包括 Si〇2、Si3N4與/或其它介電材料’且這些材料可與熱預算以 及隨後CMP製程的機械應力相符，蓋層190可以ALD、 CVD、PECVD、旋轉塗佈製程、熱或RTP氧化、ISSGRTP 氧化與/或PVD形成，其厚度約為100〜2000埃，在一實 0503-A30208TWFl/ice 11 1254446 1—93ΉΤ簡..號專利說明書修正衣一“ 卜 … 七正日期：94.12.27 鈿例中’蓋層190的一部份195可低於閘極結構ι〇5的高 度Η，如同内連線層18〇可低於閘極結構1〇5的高产 在隨後的製程中，可將蓋層19〇的一部份195作幕。’ 制請參閱第3圖，此圖為第2圖SGFET元件1〇〇經平坦 化製耘的剖面圖，此平坦化製程可同時平坦化間隙壁Μ。、 源極内連線160、絕緣層170、内連線層18〇與/或罢層π。， 或其它依然存在的部分，以形成平坦平面31〇，在一實施 例中，CMP的錄，以使蓋層⑽的部份厚度在經研磨後 依然約為200埃，此2〇〇埃的蓋層190厚度可提供在後續 製程中的適當保護，以防止氧化。 貝 △ *第3圖說明平坦化可包括在一般化學機械研磨（cMp) 參數下執行CMP，但在一實施例中，CMp的參數可從這些 一般所利用的參數加以變化，以減少或消除_般平坦化方 法中所不想見到的結果，例如在CPM時藉由基底載具或研 磨頭對基底110施加更大的下壓力（downwardf〇rce)，以 增加研磨率比，在一實施例中，此下壓力可約為5·0 ， 此下壓力也可约為5·〇〜i〇.〇pSi，相反地，一般CivIp傳統 上的下壓力小於約4.2psi。 研磨率比可為具有較高輪廓的構件之基底區域的研磨 率與具有較低輪廓的構件之基底區域的研磨率之比，有鑑 於此，增加研磨率比，可以一比較低構件之移除速率快的 速¥將較咼構件的材料移除，如藉由在研磨時增加下壓 力’換句話說，當達到較高研磨率比時，高地形區域可比 較低地形區域更快被研磨，藉由從基底11()上將較高地形 〇503-A3G208TWFl/ice 12 1254446 第93137163號專利說明書修正本 修正日期：94·12·27 區域以比在低地形區域較快將材料移除時，可減吵或消除 在一般平坦化方法中在介於較高地形構件間所造成之圓角 (rounded corners)與具有尖突的邊緣（jagged edges)， 如此，邊角可被更明確定義、鄰近地形構件間的界面可更 加清楚、且大體上不會有殘留增加（residue build-up )與具 有缺口的邊緣（jagged edges )的產生。 增加下壓力並非提供較高研磨率比的唯一方式，例 如，增加在CMP時的旋轉速度也可增加研磨率比，因此， 在一實施例中，研磨頭對基底110的旋轉速率約為75〜200 rpm，在一更特定的實施例中，研磨頭速率可為90〜1〇〇 rpm，相反地，一般CMP製程傳統上的研磨頭速率小於約 63 rpm 〇 同樣地，在CMP時用來研磨基底110上之地形構件所 使用之平台的轉速約為65〜150 rpm，在一更特定的實施例 中，平台轉速約為8S〜95 rpm，相反地，一般CMP製程傳 統上的平台轉速小於約 57 rpm 〇 構件之CMP選擇率也可調整至一想要的研磨率比，也 就疋根據材料對CMP的抗性（resistance)來選擇地形構件 所用的材料，所以較高的地形構件可包括對CMp具有較低 抗性的材料，而較低的地形構件可包括對具有較高抗 性的材料，換句話說，較高地形構件所利用之材料的選擇 性咼於較低地形構件所利用之材料的選擇性，在一實施例 中’較高地形構件的選擇性可為較低地形構件的選擇性之 約3〜5倍，所以研磨率比可約為3 :丨，或3 ::工間， 0503-A30208TWFl/ice 13 1254446 修正日期-:94.12 97 弟931j716j>號專利說明書修正本 例如’在第1圖與第2圖所示的實施例中，蓋層19〇可包 括SUN#且内連線層ι8〇可包括多晶矽，因為多晶矽在 中的抗性約為SisN4的3倍，所以就可得到3 : 1的研声去 調整CMP研磨漿的化學組也可用來達成增加研磨率 比，也就是在較高地形構件的研磨漿之選擇性較較低地= 構件的大，在一實施例中，較高地形構件的研磨漿選擇性 可為較低地形構件的研磨漿選擇性的3倍。 再者，一般利用電漿與/或化學回蝕刻的製程不與蓋眉 190的CMP製程合併，以避免增加殘留增加（^5汾二 build-up)與具有尖突的邊緣（jagged edges)的可能性， 然而，藉由本揭露之蓋層19〇的合併使用，如其具有對其 下方層（如内逑線層18〇)之1/3的抗性，可減少或消除殘 留增加（residue build-up)的發生，且可預防在較高地形二 件間形成不一致的邊緣。 請參閱第4圖，此圖說明第3圖所顯示之元件1〇〇在 經隨後製造步驟處理後的剖面圖，罩幕層4〇2可形成在源 極内連線160與因為前述平坦製程而露出之内連線層工肋 上，包括在一些實施例中，罩幕4〇2也可形成在相對薄的 間隙壁150與内連線160上。在一實施例中，蓋層包 括Si〇2且罩幕層402包括以3队；在另一實施例中，蓋| 190包括Si#4且罩幕層402包括Si〇2。罩幕層402可二 ALD、CVD、PECVD、旋轉塗佈方法、ISSG氧化與/或 全面性或运擇性形成，罩幕層402的形成尚可包括退火擎 0503-A30208TWFl/ice 14 1254446 第93137163號專利說明書修正本 — 修正曰期-·· 94.12.27 程，如熱或RTP氧化，沉積罩幕層402-的製老條件可包括 550〜950°C間的製程溫度，且其製程環境可包括N2、02 與/或1,2-二氯乙烯，罩幕層402的厚度約為1〜2000埃， 此厚度是根據SGFET元件100的設計規格而變化，罩幕層 402可提供在之後之蝕刻製程中對多晶矽區域的保護。 請參閱第5圖，此圖為第4圖的元件100在移除部分 之蓋層190、絕緣層170與内連線層180後之剖面圖，罩 幕層402可用在此移除中，如第5圖所示，然後再被移除， 蓋層190、絕緣層170、内連線層180與/或罩幕層402的 移除可藉由選擇性電漿與/或化學蝕刻來達成，罩幕層402 可防止其下材料被蝕刻，Si02間隙壁150尚可防止其下層 被蝕刻，然而，蓋層190下的材料可被移除。 根據本揭露結合使用罩幕層402與CMP製程以提供所 欲之SGFET之箱型結構中，此罩幕層402可在絕緣層170 與内連線層180的部分移除後使源極與汲極的接觸插塞大 體上乾淨且具有平坦表面，而乾淨且具有平坦表面的源極 與汲極接觸插塞可在之後形成良好之金屬矽化物、耐火阻 隔金屬與/或填充金屬接觸插塞，相反地，若具有圓形與/ 或具有缺口之SGFET接觸插塞之表面常會造成高接觸阻 性，且在隨後形成之構件的針孔與金屬擴散的穿遂現象也 很有可能造成SGFET在電性上的失敗。 請參閱第6圖，此圖為本揭露之平坦化系統600的透 視圖，此平坦化系統600可用在上述第2圖中之SGFET元 件的平坦化，熟習此技藝之人士應可瞭解此系統600只顯 0503-A30208TWFl/ice 15 1254446 第93137163號專利說明書修正本 修正日期：94.12.27 示部分構件，且其實此系統600尚包括許多未在第6圖中 描述或未顯示的構件。 系統600包括可分開的研磨頭61〇與基底620 (如第2 圖所示之基底100)對，研磨頭610可藉由柄630與第一 驅動裝置640連接，第一驅動裝置64〇可驅動研磨頭610 以箭頭657的方向旋轉，且其旋轉速率約為75〜200 rpm， 且研磨速度也可為200 rpm以上，第一驅動裝置640尚可 對研磨頭610施力，以使形成在基底620上的地形構件與 研磨平台650接觸，第一驅動裝置64〇所施的力可約為20 〜10.0 psi，且此力也可更大。 平台650可包括一般或未來發明之組成與形狀的研磨 墊655，平台650可藉由柄66〇與第二驅動裝置670結合， 以使平台650以箭頭657的方向旋轉，此第二驅動裝置670 可以約65〜150 rpm的速度旋轉平台650,且此轉速也可高 於150 rpm ’第二驅動裝置67〇尚可施力於平台650上，以 使平台650(或研磨墊655 )與基底“ο上的地形構件接觸， 第二驅動裝置67〇所施的力可約為2.0〜10.0 psi，再者， 可同時操縱第一與第二驅動裝置64〇、67〇以提供對基底 620上的地形構件施加約5·〇〜1〇·〇 psi的研磨力，且此力 可更南，控制第一與第二驅動裝置64〇、67〇以提供對基底 620上的地形構件研磨力，且旋轉研磨頭61〇與/或平台65〇 尚可藉未顯不於第6圖中的裝置所控制，如專用電腦元件。 研磨系統600尚可包括研磨漿傳送系統680,此研磨漿 傳迗系統680可經導管687將研磨漿砧5傳送至平台65〇 0503-A30208TWFl/ice 16 1254446 第93137163號專利說明書修正本 修正日期：94.12.27 (或研磨墊655 )上，研磨漿685的組成可根據基底620 上的地形構件來選擇，如上述之第5圖所述。 藉由使用比傳統之平坦化方法更大的研磨力與/或更快 的研磨速度，系統600就可減少或消除一般平坦化所產生 的圓角（rounded corners )、殘留增加（residue build-up ) 與具有央突的邊緣（jagged edges )，例如，如上所述，第 一與/或第二驅動裝置640、670施加約5.0 psi的力、約93 rpm的研磨頭610轉速與約87 rpm平台650轉速，可在CMP 時提供更高的研磨率比，以使形成於基底62〇上的地形構 件可比較低地形構件在一更快的速率下研磨，且利用特定 的研磨漿685組成也可有效地達成更高研磨率比或增加研 磨率比。 请蒼閱第7圖，此圖為本揭露積體電路元件7〇〇的剖 面圖，此積體電路元件7〇〇為上述元件1〇〇的結構之一， 例如，積體電路元件7〇〇包括複數個元件722於基底71〇 上或中，其中之一或更多的元件與第5圖所示之微電子元 件大體上類似’ A件722可被㈣連接與/或被連接至基底 7;0 1或中的微電子元件724其一或更多，此微電子元件 7一4可為或包括金屬氧化物半導體場效電晶體 (MOSFETs)、FmFET與/或其它一般與/或未來所研發的 半導體元件。 積體電路元件 沿著與/或延伸過介 電子元件722、724 7〇〇尚包括内連線740，此内連線740 電層730、750之一或更多至複數個微 之一，此介電層73Ό、750可包括二氧 0503-A30208TWFl/ice 17 1254446 第9*3ΐ·3716〕號專利說明書修正本 、 修正曰期：94.1:2.27 它材料，且可以cv™、旋轉塗伟與/或其= 程形成，介電層730、750的厚度約為2〇00〜15000埃，内 連線740可包括銅、鎢、金、鋁、奈米碳管、碳富勒烯 (FU11^1^)、耐火金屬與/或其它材料，且可以CVD、 PECVD、ALD、PVD與/或其它製程形成。 積體電路元件700可包括元件722、724之不平坦地形 層，例如，元件722可包括快閃記憶體元件如SGFET，同 時元件724可包括M0SFET^/或其它微電子元件，元件 722可包括在纪憶體陣列或記憶體單元區中，且元件724 可包括在積體電路元件700的周邊電路區中，在元件722、 724間的地形可有許多變化，此變化會在cmp製程中產生 更多問題，如凹陷、圍欄（fence)的形成、碎裂與/或其它 製程所併發之現象。此揭露適用於積體電路元件中之周邊 電路區域與記憶體陣列區域中，提供自行對準閘極電極或 其它接觸插塞的提供方法。 在一實施例中，元件722、724可包括構件760、762， 此構件760、762可在不同製程步驟中分別形成，例如，在 構件760形成時，構件762可被保護以防止對其下構件之 傷害，構件762可以一暫時層保護，包括光阻、Si3N4、聚 合物、Si〇2與/或其它材料；此外，在構件762形成時，構 件760可被保護以防止對構件下與/或鄰近的構件76〇造成 傷害，構件760可以一暫時層保護，包括光阻、si3N4、聚 合物、Si02與/或其它材料。 0503-A30208TWFl/ice 18 1254446 修正日期：-94.12.27 第93137163號專利說明書修正本 構件760、762的形成順序可取決於是否可預防鄰近構 件與元件層的破壞，例如，構件76〇之多晶矽、金屬矽化 物與/或多晶矽氧化物的形成可包括藉由暫時層保護構件 760，暫時層可在構件760的形成時預防CMp凹陷與^或損 傷的發生，所以，藉由保護構件762可使元件722之電性 接觸以自行對準方式形成在源極/汲極區。 請參閱第8a圖與第8b圖，這些圖說明本揭露另一實 施例之積體電路元件800的剖面圖，第8a與第8b圖的積 體電路元件800為製程中的元件，此積體電路元件8〇〇包 括陣列基底810與次要基底815。 陣列基底810包括一個或多個記憶體元件8〇4，此記憶 體元件804可介於絕緣結構820間、陣列基底81〇中與/或 上，此記憶體元件804與第5圖所示之微電子元件1〇〇與/ 或第7圖所示之微電子元件700大體上類似，此記憶體元 件804可大體上與元件806垂直，以使元件8〇4的主平面 812與元件806的主平面814大體上垂直，例如，平面812 與平面814具有90度的夾角，如箭頭85〇所示，在另一實 施例中，平面812、814的夾角可為〇〜9〇度，此陣列基底 810可包括Si、SOI、SON、鑽石、聚合物與/或其它材料。 次要基底815包括一個或多個元件8〇6，此元件8〇6 可位於絕緣結構820間、次要基底815中與/或上，元件8〇6 與第7圖中的微電子元件700大體上類似，此次要基底815 可包括Si、SOI、SON、鑽石、聚合物與/或其它材料，形 成於基底815中的元件可用作訊號放大器、記憶體元件8〇4 0503-A30208TWFl/ice 19 1254446 弟1 j71 6j號專利說明書修正本 修正曰期：94 與/或其它形成於陣列基底810中的元件。 請參閱第8a圖，元件800包括半導體層840，此半導 體層840位於陣列基底810的主動區830上且鄰近於絕緣 結構820侧，此半導體層840包括磊晶Si、多晶矽、多晶 碎氧化物' CoSi、NiSi與/或其它材料，且可在陣列基底810 與或次要基底815上藉由CVD、PECVD、PVD、ALD與/ 或其它方法作全面性與/或選擇性沉積，之後再藉由CMP、 電漿蝕刻與/或化學蝕刻對絕緣結構820作回蝕刻或其它平 坦化處理。 元件800尚可包括護層860,以保護其下之構件，如保 護主動區830與絕緣結構820，此護層860可包括Si〇2、 SiN、S^N4、TiN、聚合物與/或其它材料，這些材料的介 電常數約為5.5〜9，護層860可全面性與/或選擇性沉積在 次要基底815與/或陣列基底810上，且此層可以CVD、 PECVD、PVD、ALD與/或其它方式形成，此護層可在陣列 基底810上進行圖案化與蝕刻移除，以留下在次要基底815 上的護層860。 請參閱第8b圖，此圖為護層860已從次要基底815上 經隨後之製程移除，在一實施例中，護層860可在次要基 底815的主動區830上形成其它材料之前移除，以形成電 晶體元件。 陣列基底810與次要基底815可為結合之分離基底或 其它搞合在一起的結構，或可為一般鄰近之區域，在一實 施例中’次要基底815可包括一基底材料，而陣列基底§ 1〇 0503-A30208TWFl/ice 20 1254446 弟9j1j716j號專利說明書修正本 修正日期：94.12.27 可包括其它基底材料，例如，次要基底815可包、括SON基 底’同時陣列基底810可包括SOI基底。 請參閱第9a圖，此圖說明本揭露製造步驟中之微電子 元件900的剖面圖，此微電子元件9〇〇包括基底905、形 成在基底905上的護層910與延伸過護層910與至少部分 基底的絕緣結構920,此微電子元件9〇〇尚包括單元區902 與周邊電路區904，例如，複數個元件可位於與/或大體上 开>成於單元區902中，且複數邏輯元件可位於與/或大體上 形成於周邊電路區904中，在一實施例中，記憶體元件位 於與/或大體上形成於包括記憶體電晶體元件的單元區9〇2 中，且與第5圖所示之元件大體上類似，且邏輯元件位於 與/或大體上形成在周邊電路區904中，此周邊電路區904 可為用在邏輯電路與/或感應電路的M〇SFET元件、FinFET 元件與/或其它電晶體元件。 基底905可大體上與第丨圖所示之基底11〇的組成與 製造相似，基底905可為單晶或其它石夕基底、基底包 括在矽或監寶石基底上的矽或鍺磊晶層、塑膠或其它彈性 基底與/或其它-般或未來發展之基底，基底9〇5可包括複 數種掺雜區，以形成摻雜井、通道區、源極/絲區與/或其 它結構，在-實施例中，摻雜區可以交替或西洋棋盤狀的 圖型掺雜，以使it件位於與/或大體上形成於單元區與 /或周邊電路區904中，包括CMOS元件。 痩層910可包括氧化石夕、氮化矽（腿、^抓等）與/ 或其它材料，以作為蝕刻停止或CMp停止用，護層91〇可 0503-A30208TWFl/ice 1254446 第93137163號專利說明書修正本 修正日期：94.12.27 藉由 CVD、LPCVD、PECVD、熱製程、ALD、PVD 與/或 其它製程全面性或選擇性沉積於單元區902與周邊電路區 904中的基底905上，其厚度約為500〜5000埃，在一實 施例中，護層910與第8a圖中的護層860大體上相似，護 層910尚可包括約50〜200埃的氧化矽層與1〇〇〇〜2500埃 的氮化梦層。 絕緣結構920可為或包括Sll或其它電性絕緣構件， 例如，絕緣構件920由下列方式形成：利用蝕刻或其它方 式形成延伸過護層910與至少部分基底905之開口，再以 -一氧化带與/或其匕介電材料填充此開口。在一實施例中， 絕緣結構920可藉由乾钱刻製程形成，其厚度約為2〇〇〇〜 5000埃，此用於絕緣結構920之塊狀絕緣材可以CVD、 HDPCVD、PECVD、LPCVD、SACVD 與/或旋轉塗佈製程 形成，且其厚度約為3000〜8000埃，此絕緣結構92〇尚可 藉由CMP製程平坦化，以移除部分之塊狀絕緣材，而所移 除之厚度約為1〇〇〇〜8000埃，且絕緣結構920大體上與護 層910同平面，如第9a圖所示，CMP製程可具有一約？ 〜30之塊狀絕緣材對護層的研磨選擇率。 請參閱第9b圖，此圖說明第9a圖的微電子元件9〇〇 經隨後製程處理後的剖面圖，其中圖案化光阻或其它罩幕 層930可在部分護層910上形成，此罩幕層930可包括厚 度約為3000〜10000埃的光阻層，罩幕層930可形成於周 邊電路區904的表面上，且也可延伸形成於周邊電路區9〇4 與單元區902之部分絕緣結構920上。 0503-A30208TWFl/ice 22 1254446 第9313Ή63號專利說明書修正本 修正日期—「94.12:27 請參閱第9c圖，此圖說明第9b圖的微電子元件900 經隨後製程處理後的剖面圖，其中罩幕層930在移除部分 護層910之蝕刻製程中是作為罩幕用，由於罩幕層930大 體上未覆蓋單元區902，所以在單元區902上的護層910 就會在蝕刻製程中被移除，然而，部分位於罩幕層930下 方的護層910在蝕刻製程中被保護著，此蝕刻製程可為乾 钮刻、化學钱刻、上述钮刻方式之組合與/或其它製程’在 一實施例中，部分護層910以濕蝕刻製程移除，且此濕蝕 刻製程之護層910對絕緣結構920的蝕刻選擇率約為5〜 30間。 請參閱第9d圖，此圖說明第9ca圖的微電子元件900 經隨後製程處理後的剖面圖，其中罩幕層930被#刻移除 或經由其它方式移除，此罩幕層930可藉由電漿灰化或伴 隨著H2S〇4的化學蝕刻之一或多種製程移除，在移除罩幕 層930後，就利用移除後所殘留的部分護層910進行閘極 介電前清潔製程，在一實施例中，閘極介電前清潔製程包 括利用稀釋的HF或利用缓衝氧化物钱刻（buffer oxide etching，簡稱BOE)之濕製程，此製程可能會在絕緣結構 920的上頂角鄰近處產生一個或多個凹陷（divots) 921， 然而，凹陷（divots) 921尚可能在之前的製程中已形成， 如第9c圖所示，凹陷（divots) 921可為多重製程所累積 的結果，包括平坦化、護層910的移除、罩幕層930的移 除與閘極介電前清潔製程。 如第9d圖所示，閘極介電層940與閘極電極層950可 0503-A30208TWFl/ice 23 1254446 修正日期：94.12.27 第93137163號專利說明書修正本 $基底9Cb上形成，閘極介電層940可藉由將因之前蝕刻 衣秋所路出的部分基底置於氧化環境中，此外，也可 趴閘極介電層940藉由CVD、pECVD、ALD、pVD與/或 其匕製程沉積在露出的部分基底905上，此閘極介電層940 可包括一氧化矽、氧化矽、氮氧化矽與/或其它材料，且其 厚度約為10〜300埃。 辦閘極電極層950可包括多晶石夕、非晶石夕與/或其它半導 版材料，且可以全面性（如實施例中所述）或選擇性沉積 的方式形成，閘極電極層95〇可藉由CVD、pECVD、ALD、 PVD與/或其它製程所形成，且其厚度約為 500〜4000 埃。 一 1請參閱第9e圖，此圖說明第9d圖的微電子元件9〇〇 經Ik後製程處理後的剖面圖，其中部分閘極電極層被 移除，以形成閘極電極955，此部分閘極電極層謂可以 乾钱刻製程、祕㈣程、賴刻製程、化學機械平坦化 或化學機械研磨（在此CMp)與/或其它製程所移 除’且可利用絕緣結構92G與/或護I 9iq作為移除終點， 在一實施例中，閘極電極層95〇約被移除2〇〇〜2〇〇〇埃， 以留下在主動區960上3〇〇〜2_埃的閘極電極層95〇, 而閑極電極層950對護層9U)的選擇率約為5〜3〇，且閘 極電極層950對絕緣結構92〇的選擇率約為$〜列。 形成於單元區的元件尚可以過度餘刻或過度研磨製程 將絕緣結構920上所殘留之部分閘極電極層950移除，此 過度_或過度研磨製程尚可包括移除介於絕緣結構92〇 間之閘極電極層95〇的贿部分，如第％圖所示，例如， 0503-A30208TWFl/ice 24 1254446 第93137163號專利說明書修正本 修正日期：94.12.27 所形成的閘極電極955可具有與絕緣結構920直接接觸的 侧表面，且具有與凹陷（divots ) 921表面一般的邊界，閘 極電極955之前所形成的凹陷（divots) 921之一部分尚可 延伸至絕緣結構920，所以，閘極電極955可具有比主動 區960更大的寬度，在一實施例中，由於閘極電極955具 有凹钱處，所以閘極電極955的上表面956可低於絕緣結 構920的上表面926，如第10圖所示，在一實施例中，閘 極電極955的凹蝕深度約為10〜500埃，在此製程步驟與/ 或之後的步驟中，形成於單元區902的元件可在移除殘留 部分護層910前大致完成。 請參閱第9f圖，此圖說明第9e圖的微電子元件900 經隨後製程處理後的剖面圖，其中護層910的任何殘留部 分皆被移除，例如，藉由乾蝕刻、化學蝕刻與/或其它製程 將護層910殘留部分移除’以使在周邊電路區904中的基 底905露出，在一實施例中，部分護層910被濕钱刻製程 所移除，且此濕蝕刻之護層910對絕緣結構的選擇率約為 5〜30,此濕蝕刻尚可具有5〜30的護層910對閘極電極層 955的選擇率。 所以，在周邊電路區904所露出的基底905可進一步 藉由一般與/或未來所發展的裝置在周邊電路區904中製成 MOSFETs與/或其它電晶體與邏輯與/或感應電路，在一實 施例中，微電子元件900大體上與第7圖中的積體電路元 件700與/或第8b圖中的元件800類似。 請再次參閱第10圖，此圖說明本揭露另一實施例之積 0503-A30208TWFl/ice 25 1254446 第93U7163號專利說明書修正 ^ 修正曰期·· 94.12.27 體電路元件900，以雜 岵/、有至夕5己仏體單元區9〇2與至少一周邊電路區_ 之，底且有衩數個絕緣區92〇位於記憶體單元區9⑽中， 且每個稷數個主動區960位於絕緣區92〇間，元件卯2尚 包括複數個閘極電極層955,且每個閉極電極層奶皆位 於絕緣結構920間且位於所對應的主動區96〇上，其中每 個閘極電極層955的寬度大於閘極層955接觸的相鄰絕緣 結構920的間隔寬度。 每個閘極電極955包括延伸至鄰近的絕緣結構92〇的 一部伤，例如，每個閘極電極955可包括與鄰近絕緣結構 920之一接觸的侧表面，如每個閘極電極955都會超過對 應的主動區960，每個絕緣結構920也包括凹陷（div〇ts) 921，此凹陷（divots) 921具有凸向鄰近閘極電極955之 一的輪廓。 母個緣結構920也南過基底905與鄰近的閘極電才系 955，所以，每個絕緣結構920可以遠離基底905的方向延 伸過鄰近的閘極電極955，或每個複數個閘極電極955可 不比鄰近的絕緣結構920更遠離基底905。 雖然本發明已揭露較佳貫施例如上，然其並非用以pp 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作些許之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 0503-A30208TWFl/ice 26 1254446 第93137163號專利說明書修正本 修正日期94.12.27 【圖式簡單說明】 第1〜5圖為一系列剖面圖，用以說明本揭露之一實施 例在製程步驟中的微電子元件。 第6圖為一示意圖，用以說明本揭露之一實施例用以 平坦化形成在基底上之地形構件的糸統。 第7圖為一剖面圖，用以說明本揭露之一實施例的積 體電路元件。 第8a與8b圖為一系列剖面圖，用以說明本揭露之另 一實施例的微電子元件。 第9a〜9f圖為一系列剖面圖，用以說明本揭露之另一 實施例的微電子元件。 第10圖為一剖面圖，用以說明本揭露之另一實施例且 顯示於第9f圖中之微電子元件。 【主要元件符號說明】 100 、 722 、 724 、 804 、 105〜閘極結構； 115〜參考平面； 130〜閘極氧化層； 150〜間隙壁； 17 0〜絕緣層； 185〜内連線層180的 187〜内連線層180的 190〜蓋層； 310〜平坦平面； 、992〜元件； 110、620、710、905〜基底； 120〜源極區； 140〜分離閘極； 160〜源極内連線； 180、740〜内連線層； 第一部份； 第二部份； 195〜蓋層190的一部份； 402、930〜罩幕層； 0503-A30208TWFl/ice 27 1254446 一 ·第93137163號專利說明書修正本 修正日期94.12:27 600〜 平坦化系統； 610〜 •研磨頭； 630〜 柄， 640〜 第一驅動裝置； 650〜 研磨平台； 655〜 研磨墊； 657、 850〜箭頭； 670〜第二驅動裝置； 680〜 研磨漿傳送系統； 685〜 研磨漿； 687〜 導管； 700、 800〜積體電路元件； 730、 750〜介電層； 760、 762〜構件； 804〜記憶體元件； 810〜陣列基底； 812〜 元件804的主平面 814〜 元件806的主平面 j 815〜 次要基底； 820、 920〜絕緣結構， 830、 960〜主動區； 840〜 半導體層； 860、 910〜護層； 900〜 微電子元件； 902〜 單元區； 904〜 周邊電路區， 921〜 凹陷（divots ); 926〜 絕緣結構920的上表面； 940〜 閘極介電層； 950〜 •閘極電極層； 955〜 '閘極電極， 956〜 '問極電極9 5 5的上表面， 990〜 '積體電路元件； Η〜閘極結構105的高度 0 0503-A30208TWFl/ice 28In the same place, ?m (In Situ Steam Generation, isSG) is formed by RTP oxidation, and the thickness of the gate oxide layer 13 is about 1 Å or less. The separation gate 140 may include metal telluride, doped and/or undoped polysilicon, metal oxide, barrier and metal conductors, barrier layers and non-metallic conductors, and/or other specific requirements that may provide application. For the material of the same electrical component, the separation gate 14 can be modified by ALD, CVD, pec: vd, 0503-A30208TWFl/ice 9 1254446 Date: 94.12.27 Patent specification 93137163 to correct this PVD and / or other The process is formed to have a width of about 1 〇〇 to 4 〇〇〇 and a thickness of about 1 to 800 angstroms. The spacers 150 may comprise si02 and/or other dielectric materials and may be selected to conform to the component process thermal budget. The spacers 150 may be ALD, CVD, PECVD, thermal or RTP oxidized, ISSGRTP oxidized, PVD and/or Other processes are formed having a thickness of about 1 〇 4 〇〇 Å and a width of about 1 〇 to 4 0 0 〇. The source interconnect 160 may comprise one or more conductor materials, including polysilicon, metal halides and/or metal oxides, and may also include barrier layers and/or cladding, such as Ti, Ta, TiN, TaN, TiW, CN, SiC and SiCO, the source interconnect 160 can be formed by ALD, CVD, PECVD, PVD and/or electroplating copper process (ECP), and has a thickness of about 1 〇〇 to 4 〇〇〇. An angstrom, and having a width of about 1 〇 to 4000 angstroms, further, as shown in Fig. 1, the cross-sectional profile of the source interconnect 160 may gradually become smaller or perpendicular depending on the geometry of the surrounding members. The SGFET element 1A may also include an insulating layer 170 to insulate the aforementioned components from interconnects formed thereafter. The insulating layer 170 may include Si〇2, Si3N4 and/or other dielectric materials, and the thermal budget is selected as much as possible. For conforming materials, the insulating layer 170 can be formed by ALD, CVD, PECVD, spin coating process, thermal or RTP oxidation, ISSGRTP oxidation and/or PVD, and has a thickness of about 1 to 300 angstroms. The SGFET component 1 〇〇 may also include an interconnect layer, which may be a bit line, a word line, and/or other interconnect (collectively referred to herein as an interconnect), as in FIG. In the illustrated embodiment, the interconnect layer 18 is formed by 全503-A30208TWFl/ice 10 1254446 No. 93137163. The date of revision is 94.12.27. The insulating layer 170 is formed by full-scale cleaning. Alternatively, but also by selective deposition, the interconnect layer 180 may comprise one or more conductor materials, such as doped or undoped polycrystalline, metallazine and/or metal oxide, and may include a barrier layer Such as Ti, Ta, TiN, TaN, TiW, CN, SiC and SiCO, the interconnect layer 180 can be formed by ALD, CVD, PECVD, ECP and/or PVD, and has a thickness of about 50 to 4000 angstroms and a width of about For an embodiment of 50 to 4000 angstroms, in one embodiment, the thickness of the interconnect layer 180 can be less than the height Η of the gate structure 105. The above-described members are the member structures of the present invention. As shown in FIG. 1, a plurality of members have a relative southness ' with respect to the plane 105 of the test, and the plane 105 is parallel to the main plane of the substrate 110, for example, the gate structure 105. The height Η is higher than the reference plane 115, but the thickness of the source interconnect 160 is less than the height 闸 of the gate structure 105. Similarly, the interconnect layer 180 includes a first portion 185 having less than the height 与 and less than the height. The second part 187 of the crucible, as described above, is in the general planarization method, and the topographical factors of the components produce undesirable results, such as rounded corners, excess residue build_up, and With jagged edges. Referring to FIG. 2, which is a cross-sectional view of the component 1 shown in FIG. 1 after the cap layer 190 is formed on the inner conductor layer 180, the cap layer 190 may include Si〇2, Si3N4, and/or other dielectric. The material 'and these materials can be consistent with the thermal budget and subsequent mechanical stresses of the CMP process. The cap layer 190 can be formed by ALD, CVD, PECVD, spin coating process, thermal or RTP oxidation, ISSGRTP oxidation and/or PVD, and the thickness is about 100~2000 angstroms, in a real 0503-A30208TWFl/ice 11 1254446 1-93 ΉΤ ... patent specification to modify the clothing one "b... seven dates: 94.12.27 钿 中 ' 盖 盖 盖 190 190 190 Below the height 闸 of the gate structure 〇5, as the interconnect layer 18 〇 can be lower than the gate structure 1 〇 5 high yield in the subsequent process, a portion 195 of the cap layer 19 作 can be curtained. Please refer to Figure 3, which is a cross-sectional view of the SGFET device 1 through planarization in Figure 2. This planarization process can simultaneously planarize the spacers. Source interconnection 160, insulation 170, an interconnect layer 18 〇 and / or a layer of π, or other parts that still exist to form a flat plane 31 〇, In one embodiment, the CMP is recorded such that the thickness of the portion of the cap layer (10) is still about 200 angstroms after grinding, and the thickness of the cap layer 190 of 2 angstroms provides appropriate protection in subsequent processes to prevent Oxidation. Bayer * Figure 3 illustrates that planarization can include performing CMP under general chemical mechanical polishing (cMp) parameters, but in one embodiment, the parameters of CMp can be varied from these generally utilized parameters to reduce or Eliminating the results that are not desired in the method of planarization, such as applying a lower downforce (downward) to the substrate 110 by the substrate carrier or the polishing head during CPM to increase the polishing ratio, in an implementation In this case, the lower pressure may be about 5.00, and the lower pressure may be about 5 〇 〇 〇 〇 Si pSi. Conversely, the conventional CivIp conventional downforce is less than about 4.2 psi. The ratio of the polishing rate of the base region of the component having a higher profile to the polishing rate of the base region of the component having the lower profile, in view of this, increasing the ratio of the polishing rate can be faster than the removal rate of the lower component. Remove the material of the lower member, By increasing the downforce during grinding', in other words, when a higher grind ratio is reached, the high terrain area can be ground faster than the lower terrain area, by placing a higher topography 基底 503- from the substrate 11() A3G208TWFl/ice 12 1254446 Patent Specification No. 93137163 This revision date: 94·12·27 The area can be reduced or eliminated in the general flattening method when the material is removed faster than in the low terrain area. Rounded corners and jagged edges between high terrain members, so that the corners can be more clearly defined, the interface between adjacent terrain members can be more clear, and generally there will be no Residual build-up and the generation of jagged edges. Increasing the downforce is not the only way to provide a higher grind ratio. For example, increasing the spin speed at CMP can also increase the grind ratio. Thus, in one embodiment, the spin rate of the bead to substrate 110 is about 75~ 200 rpm, in a more specific embodiment, the head speed can be 90 to 1 rpm, and conversely, the conventional CMP process conventionally has a head rate of less than about 63 rpm. Similarly, for CMP. The speed of the platform used for the terrain members on the substrate 110 is about 65 to 150 rpm. In a more specific embodiment, the platform speed is about 8 s to 95 rpm. Conversely, the conventional CMP process is conventionally less than about rpm. The CMP selectivity of the 57 rpm 〇 member can also be adjusted to a desired grinding ratio, ie the material used for the terrain component is selected based on the resistance of the material to CMP, so higher terrain components may include CMp has a less resistant material, while lower topographical members may include materials that are more resistant to deformation, in other words, the selectivity of the materials utilized by higher terrain components is lower than that of lower terrain components. The selectivity of the material used, in one embodiment, the selectivity of the higher topographical member may be about 3 to 5 times greater than the selectivity of the lower topographical member, so the abrasive ratio may be about 3: 丨, or 3: :Work, 0503-A30208TWFl/ice 13 1254446 Revision date -: 94.12 97 931j716j> Patent specification revisions For example, in the embodiments shown in Figures 1 and 2, the cover layer 19 can include SUN# And the interconnect layer ι8〇 may include polycrystalline germanium, because the resistance of the polycrystalline germanium is about three times that of SisN4, so that a 3:1 sound can be obtained to adjust the chemical group of the CMP slurry, which can also be used to achieve an increased grinding rate. Ratio, that is, the selectivity of the slurry of the higher terrain member is lower = the size of the member is large. In one embodiment, the selectivity of the slurry of the higher terrain member may be the selectivity of the slurry of the lower terrain member. 3 times. Furthermore, processes that typically utilize plasma and/or chemical etchback are not combined with the CMP process of the eyebrow 190 to avoid increased residual buildup and jagged edges. Possibility, however, by the combined use of the cover layer 19 of the present disclosure, as it has a resistance to 1/3 of its underlying layer (e.g., the inner layer 18 〇), the residual build can be reduced or eliminated (residue build- The occurrence of up) can prevent the formation of inconsistent edges between the two pieces of higher terrain. Please refer to FIG. 4, which illustrates a cross-sectional view of the component 1 shown in FIG. 3 after being processed by a subsequent manufacturing step. The mask layer 4〇2 can be formed in the source interconnect 160 and because of the aforementioned flat process. The exposed curtain ribs are included, and in some embodiments, the mask 4〇2 may also be formed on the relatively thin spacers 150 and interconnects 160. In one embodiment, the cap layer comprises Si〇2 and the mask layer 402 comprises 3 teams; in another embodiment, the cap | 190 comprises Si #4 and the mask layer 402 comprises Si〇2. The mask layer 402 can be formed by two ALD, CVD, PECVD, spin coating methods, ISSG oxidation and/or comprehensive or selective formation, and the formation of the mask layer 402 can still include an annealing engine 0503-A30208TWFl/ice 14 1254446 No. 93137163 No. Patent Specification Amendment - Amendment Period - 94.12.27, such as heat or RTP oxidation, deposition mask layer 402 - the ageing conditions may include a process temperature between 550 ° 950 ° C, and the process environment can be Including N2, 02 and/or 1,2-dichloroethylene, the thickness of the mask layer 402 is about 1 to 2000 angstroms, the thickness is varied according to the design specifications of the SGFET element 100, and the mask layer 402 can be provided later. Protection of the polysilicon region during the etching process. Referring to FIG. 5, which is a cross-sectional view of the component 100 of FIG. 4 after removing portions of the cap layer 190, the insulating layer 170 and the interconnect layer 180, the mask layer 402 can be used for removal. As shown in FIG. 5, and then removed, removal of the cap layer 190, the insulating layer 170, the interconnect layer 180, and/or the mask layer 402 can be achieved by selective plasma and/or chemical etching. The mask layer 402 prevents the underlying material from being etched, and the SiO 2 spacers 150 prevent the underlying layer from being etched, however, the material under the cap layer 190 can be removed. In accordance with the present disclosure, in combination with a mask layer 402 and a CMP process to provide a desired SGFET box structure, the mask layer 402 can be sourced and removed after portions of the insulating layer 170 and interconnect layer 180 are removed. The pole contact plug is substantially clean and has a flat surface, while the clean and flat surface source and drain contact plugs can later form a good metal halide, fire resistant barrier metal and/or metal filled contact plug. Conversely, the surface of a SGFET contact plug with a circular and/or notched gap often results in high contact resistance, and the pinhole of the subsequently formed member and the diffusion of metal diffusion are also likely to cause the SGFET to be electrically Sexual failure. Please refer to FIG. 6 , which is a perspective view of the planarization system 600 of the present disclosure. The planarization system 600 can be used for planarization of the SGFET elements in FIG. 2 above. Those skilled in the art should be aware of the system 600. Only 0503-A30208TWFl/ice 15 1254446 Patent Specification No. 93137163 This revision date: 94.12.27 shows some components, and in fact this system 600 also includes many components that are not described or shown in Figure 6. The system 600 includes a separable polishing head 61 〇 and a base 620 (such as the base 100 shown in FIG. 2). The polishing head 610 can be coupled to the first driving device 640 by a handle 630, and the first driving device 64 can be driven. The polishing head 610 rotates in the direction of the arrow 657, and its rotation rate is about 75 to 200 rpm, and the polishing speed can also be 200 rpm or more. The first driving device 640 can also apply force to the polishing head 610 to form on the substrate. The terrain member on the 620 is in contact with the grinding platform 650, and the force applied by the first drive unit 64 can be about 20 to 10.0 psi, and the force can be greater. The platform 650 can include a polishing pad 655 of a general or future invention composition and shape. The platform 650 can be coupled to the second drive 670 by the handle 66 , to rotate the platform 650 in the direction of arrow 657. This second drive 670 The platform 650 can be rotated at a speed of about 65 to 150 rpm, and the rotational speed can also be higher than 150 rpm. 'The second driving device 67 can also be applied to the platform 650 to make the platform 650 (or the polishing pad 655) and the substrate " The top member is in contact with the top member, and the force applied by the second driving device 67 can be about 2.0 to 10.0 psi. Further, the first and second driving devices 64, 67 can be simultaneously manipulated to provide alignment on the substrate 620. The terrain member applies a grinding force of about 5·〇~1〇·〇psi, and the force can be further south, controlling the first and second driving devices 64〇, 67〇 to provide a grinding force on the topographic member on the substrate 620, and The rotary grinding head 61 and/or the platform 65 can be controlled by a device not shown in Fig. 6, such as a dedicated computer component. The grinding system 600 can also include a slurry transfer system 680, which is a slurry transfer system 680 can transport the slurry anvil 5 to the platform 65 via conduit 687 0503-A30208TWFl/ice 16 1254446 Patent Specification No. 93137163 This revision date: 94.12.27 (or polishing pad 655), the composition of the slurry 685 can be selected according to the topographical components on the substrate 620, as shown in Figure 5 above. By using a greater abrasive force and/or faster polishing speed than conventional planarization methods, system 600 can reduce or eliminate rounded corners, residual buildup caused by general planarization (residue) Build-up) and jagged edges, for example, as described above, the first and/or second drive means 640, 670 apply a force of about 5.0 psi, a grinding head 610 speed of about 93 rpm and about The 87 rpm platform 650 rpm provides a higher grind ratio at CMP so that the topographical members formed on the substrate 62 can be ground at a faster rate than the lower terrain components, and utilize a specific slurry 685 The composition can also effectively achieve a higher polishing ratio or increase the polishing ratio. Please refer to Fig. 7, which is a cross-sectional view of the integrated circuit component 7〇〇, which is the above-mentioned integrated circuit component 7 Component 1 One of the configurations, for example, the integrated circuit component 7A includes a plurality of components 722 on or in the substrate 71, one or more of which are substantially similar to the microelectronic component shown in FIG. 722 may be (iv) connected and/or connected to one or more of the microelectronic elements 724 in the substrate 7; 0 1 or . The microelectronic elements 7 - 4 may be or include metal oxide semiconductor field effect transistors (MOSFETs) ), FmFETs and/or other semiconductor components that are generally and/or developed in the future. The integrated circuit component extends along and/or extends through the dielectric components 722, 724, and includes an interconnect 740, which interconnects 740 one or more of the electrical layers 730, 750 to a plurality of micros. The dielectric layer 73Ό, 750 may include a dioxy 0503-A30208TWFl/ice 17 1254446 No. 9*3ΐ·3716] patent specification revision, revision period: 94.1: 2.27 its material, and can be cvTM, rotating Tu Wei and / Or its formation, the thickness of the dielectric layers 730, 750 is about 2 00~15000 angstroms, and the interconnect 740 may include copper, tungsten, gold, aluminum, carbon nanotubes, carbon fullerene (FU11^1) ^), refractory metals and/or other materials, and may be formed by CVD, PECVD, ALD, PVD, and/or other processes. Integrated circuit component 700 can include an uneven topographical layer of components 722, 724, for example, component 722 can include a flash memory component such as a SGFET, while component 724 can include a MOSFET or other microelectronic component, and component 722 can be included In the memory cell array or memory cell region, and the component 724 can be included in the peripheral circuit region of the integrated circuit component 700, there can be many variations in the topography between the components 722, 724, and this change can be generated in the cmp process. Many problems, such as depressions, formation of fences, fragmentation and/or other processes. This disclosure is applicable to the provision of self-aligned gate electrodes or other contact plugs in the peripheral circuit area and memory array area of an integrated circuit component. In an embodiment, the elements 722, 724 can include members 760, 762 that can be formed separately in different process steps, for example, when the member 760 is formed, the member 762 can be protected from the lower member thereof. Injury, member 762 can be temporarily protected by a layer including photoresist, Si3N4, polymer, Si〇2, and/or other materials; further, when member 762 is formed, member 760 can be protected from underlying members and/or Adjacent members 76 cause damage and member 760 can be temporarily protected by a layer including photoresist, si3N4, polymer, SiO 2 and/or other materials. 0503-A30208TWFl/ice 18 1254446 Revised: -94.12.27 Patent Specification No. 93137163 The order in which the members 760, 762 are formed may depend on whether damage to adjacent members and element layers can be prevented, for example, polystyrene of member 76, The formation of the metal telluride and/or the polysilicon oxide may include the temporary layer protecting member 760, which may prevent the occurrence of CMp depressions and damages when the member 760 is formed, so that the component can be made by the protective member 762 The electrical contact of 722 is formed in the source/drain region in a self-aligned manner. Please refer to FIG. 8a and FIG. 8b. These figures illustrate a cross-sectional view of an integrated circuit component 800 according to another embodiment of the present disclosure. The integrated circuit component 800 of FIGS. 8a and 8b is a component in the process. The circuit component 8A includes an array substrate 810 and a secondary substrate 815. The array substrate 810 includes one or more memory elements 804, which may be interposed between the insulating structures 820 and the array substrate 81, and the memory elements 804 and 5 are shown. The microelectronic component 1 is substantially similar to the microelectronic component 700 shown in FIG. 7, and the memory component 804 can be substantially perpendicular to the component 806 such that the major plane 812 of the component 8〇4 and the component 806 The main plane 814 is substantially perpendicular, for example, the plane 812 has an angle of 90 degrees with the plane 814, as indicated by the arrow 85 ,. In another embodiment, the angle of the planes 812, 814 can be 〇 〇 9 ,, the array Substrate 810 can include Si, SOI, SON, diamonds, polymers, and/or other materials. Secondary substrate 815 includes one or more components 8〇6 that may be located between insulating structures 820, in and/or on secondary substrate 815, components 8〇6 and microelectronic components 700 in FIG. In general, the substrate 815 may include Si, SOI, SON, diamond, polymer, and/or other materials. The components formed in the substrate 815 can be used as a signal amplifier, memory device 8〇4 0503-A30208TWFl/ Ice 19 1254446 Brother 1 j71 6j Patent Specification Revision This revision: 94 and/or other components formed in array substrate 810. Referring to FIG. 8a, the component 800 includes a semiconductor layer 840 on the active region 830 of the array substrate 810 adjacent to the side of the insulating structure 820. The semiconductor layer 840 includes epitaxial Si, polycrystalline germanium, polycrystalline oxide 'CoSi, NiSi and/or other materials, and may be fully and/or selectively deposited on the array substrate 810 and/or the secondary substrate 815 by CVD, PECVD, PVD, ALD, and/or other methods, and then borrowed The insulating structure 820 is etched back or otherwise planarized by CMP, plasma etching, and/or chemical etching. The component 800 may also include a sheath 860 to protect the underlying components, such as the active region 830 and the insulating structure 820, which may include Si〇2, SiN, S^N4, TiN, polymer, and/or the like. Materials, these materials have a dielectric constant of about 5.5 to 9, and the cap layer 860 can be deposited on the secondary substrate 815 and/or the array substrate 810 in a comprehensive and/or selective manner, and the layer can be CVD, PECVD, PVD, ALD. Formed and/or otherwise, the cover layer can be patterned and etched away on the array substrate 810 to leave a blanket 860 on the secondary substrate 815. Referring to FIG. 8b, the protective layer 860 has been removed from the secondary substrate 815 by subsequent processes. In one embodiment, the protective layer 860 can be formed prior to forming other materials on the active region 830 of the secondary substrate 815. Removed to form a transistor element. Array substrate 810 and secondary substrate 815 can be bonded separate substrates or other structures that are brought together, or can be generally adjacent regions. In an embodiment, 'secondary substrate 815 can include a substrate material, and the array substrate § 1〇0503-A30208TWFl/ice 20 1254446 Rev. 9j1j716j Patent Specification Revision This revision date: 94.12.27 may include other substrate materials, for example, the secondary substrate 815 may include a SON substrate' while the array substrate 810 may include an SOI substrate . Please refer to FIG. 9a, which illustrates a cross-sectional view of a microelectronic device 900 in a manufacturing step. The microelectronic device 9 includes a substrate 905, a cover layer 910 formed on the substrate 905, and an extended protective layer 910. At least a portion of the substrate's insulating structure 920, the microelectronic element 9 further includes a cell region 902 and a peripheral circuit region 904, for example, a plurality of components may be located in and/or substantially open into the cell region 902, and The logic elements can be located and/or substantially formed in the peripheral circuit region 904. In one embodiment, the memory device is located and/or substantially formed in the cell region 9〇2 including the memory transistor device, and The elements shown in FIG. 5 are generally similar, and the logic elements are located and/or generally formed in a peripheral circuit region 904, which may be an M〇SFET component used in logic and/or inductive circuits, FinFET components and/or other transistor components. The substrate 905 can be substantially similar in composition and fabrication to the substrate 11A shown in FIG. 1, the substrate 905 can be a single crystal or other stone substrate, and the substrate includes a germanium or germanium epitaxial layer on the germanium or gemstone substrate. A plastic or other elastic substrate and/or other substrate for general or future development, the substrate 9〇5 may include a plurality of doped regions to form doped wells, channel regions, source/wire regions, and/or other structures, In an embodiment, the doped regions may be doped alternately or in a checkerboard pattern such that the etc is located and/or substantially formed in the cell region and/or peripheral circuitry region 904, including CMOS components. The ruthenium layer 910 may include oxidized stone, tantalum nitride (legs, scratches, etc.) and/or other materials for use as an etch stop or CMp stop, and the protective layer 91 〇 0503-A30208TWFl/ice 1254446 Patent No. 93137163 Amendment of this revision date: 94.12.27 is deposited on the substrate 905 in the cell region 902 and the peripheral circuit region 904 by CVD, LPCVD, PECVD, thermal process, ALD, PVD, and/or other processes. Approximately 500 to 5000 angstroms, in one embodiment, the sheath 910 is substantially similar to the sheath 860 of FIG. 8a, and the sheath 910 may further comprise a yttrium oxide layer of about 50 to 200 angstroms and 1 〇〇〇~ 2500 angstroms of nitride layer. The insulating structure 920 can be or include S11 or other electrically insulating members. For example, the insulating member 920 can be formed by etching or otherwise forming an opening extending through the protective layer 910 and at least a portion of the substrate 905, and then using an oxidized band. This opening is filled with/or its dielectric material. In one embodiment, the insulating structure 920 can be formed by a dry etching process having a thickness of about 2 〇〇〇 to 5000 Å. The bulk insulating material for the insulating structure 920 can be CVD, HDPCVD, PECVD, LPCVD, The SACVD and/or spin coating process is formed and has a thickness of about 3000 to 8000 angstroms. The insulating structure 92 can be planarized by a CMP process to remove a portion of the bulk insulating material, and the removed thickness is removed. The insulating structure 920 is substantially in the same plane as the protective layer 910. As shown in FIG. 9a, the CMP process can have an approximate ratio of about 10,000 Å to about 10,000 Å. The grinding selectivity of the layer of insulating material of ~30. Please refer to FIG. 9b, which illustrates a cross-sectional view of the microelectronic component 9 of FIG. 9a after subsequent processing, in which a patterned photoresist or other mask layer 930 can be formed on a portion of the sheath 910. The curtain layer 930 may include a photoresist layer having a thickness of about 3000 10000 Å. The mask layer 930 may be formed on the surface of the peripheral circuit region 904, and may also be extended to form a portion of the peripheral circuit region 9.4 and the cell region 902. On the insulating structure 920. 0503-A30208TWFl/ice 22 1254446 Patent Specification No. 9313Ή63 Amendment of this revision date—“94.12:27 Please refer to Figure 9c, which illustrates a cross-sectional view of the microelectronic component 900 of Figure 9b after subsequent processing, in which the mask The layer 930 is used as a mask in the etching process for removing a portion of the cap layer 910. Since the mask layer 930 does not substantially cover the cell region 902, the cap layer 910 on the cell region 902 is removed during the etching process. In addition, however, a portion of the cap layer 910 underlying the mask layer 930 is protected during the etching process. The etching process may be a dry button engraving, a chemical engraving, a combination of the above-described button engraving methods, and/or other processes. In the embodiment, part of the protective layer 910 is removed by a wet etching process, and the etching selectivity of the protective layer 910 of the wet etching process to the insulating structure 920 is about 5 to 30. Please refer to FIG. 9d, which illustrates the 9th The cross-sectional view of the microelectronic component 900 of the figure after subsequent processing, wherein the mask layer 930 is removed or otherwise removed, the mask layer 930 may be ashed by plasma or accompanied by H2S〇4 One or more processes of chemical etching In addition, after the mask layer 930 is removed, the gate dielectric pre-cleaning process is performed using a portion of the protective layer 910 remaining after the removal. In one embodiment, the gate dielectric pre-cleaning process includes the use of diluted HF. Or a buffer oxide etching (BOE) wet process, which may generate one or more divots 921 near the top corner of the insulating structure 920, however, the divots 921 may have been formed in the previous process. As shown in Figure 9c, the divots 921 may be the result of multiple processes, including planarization, removal of the cover 910, and removal of the mask layer 930. In addition to the gate dielectric cleaning process, as shown in Figure 9d, the gate dielectric layer 940 and the gate electrode layer 950 can be 0503-A30208TWFl/ice 23 1254446 Revision date: 94.12.27 Amendment to Patent Specification No. 93137163 Formed on the substrate 9Cb, the gate dielectric layer 940 can be placed in an oxidizing environment by a portion of the substrate that has been removed from the previous etching, or the gate dielectric layer 940 can be CVD, pECVD, ALD, pVD and / or its tantalum deposition is exposed The portion of the gate dielectric layer 940 may include germanium oxide, hafnium oxide, hafnium oxynitride and/or other materials, and has a thickness of about 10 to 300 angstroms. The gate electrode layer 950 may include more Crystalline, amorphous, and/or other semi-conductive materials, and may be formed in a comprehensive manner (as described in the examples) or selectively deposited, and the gate electrode layer 95 may be CVD, pECVD, ALD, PVD and/or other processes are formed and have a thickness of about 500 to 4000 angstroms. 1 to FIG. 9e, which illustrates a cross-sectional view of the microelectronic device 9 of FIG. 9d after Ik post processing, in which part of the gate electrode layer is removed to form a gate electrode 955, this portion The gate electrode layer can be used for dry etching process, secret (four) process, etching process, chemical mechanical planarization or chemical mechanical polishing (here CMp) and/or other processes are removed' and the insulating structure 92G and/or can be utilized. I 9iq is used as the removal end point. In one embodiment, the gate electrode layer 95 is removed by about 2 〇〇 2 〇〇〇 , to leave 3 〇〇 2 2 Å on the active area 960. The gate electrode layer 95 is, and the selectivity of the pad electrode layer 950 to the cap layer 9U is about 5 to 3 Å, and the gate electrode layer 950 has a selectivity to the insulating structure 92 约为 of about $0. The components formed in the cell region may also remove portions of the gate electrode layer 950 remaining on the insulating structure 920 by excessive or excessive polishing processes. This excessive or excessive polishing process may also include removal of the insulating structure 92. The brittle portion of the gate electrode layer 95 is, as shown in the figure %, for example, 0503-A30208TWFl/ice 24 1254446 Patent Specification No. 93137163, the correction electrode date: 94.12.27, the gate electrode 955 may have a side surface in direct contact with the insulating structure 920 and having a general boundary with the surface of the divots 921, a portion of the divots 921 formed before the gate electrode 955 may extend to the insulating structure 920, so the gate The electrode 955 can have a greater width than the active region 960. In one embodiment, since the gate electrode 955 has a recess, the upper surface 956 of the gate electrode 955 can be lower than the upper surface 926 of the insulating structure 920, such as As shown in FIG. 10, in one embodiment, the gate electrode 955 has a recess depth of about 10 to 500 angstroms. In the process step and/or subsequent steps, the elements formed in the cell region 902 can be moved. Except for the residual portion of the sheath 910, it is substantially completed. Please refer to FIG. 9f, which illustrates a cross-sectional view of the microelectronic device 900 of FIG. 9e after subsequent processing, in which any residual portions of the cap layer 910 are removed, for example, by dry etching, chemical etching, and/or Or other processes remove the residual portion of the cap layer 910 'to expose the substrate 905 in the peripheral circuit region 904. In one embodiment, the portion of the cap layer 910 is removed by the wet etching process, and the wet etching is protected. The selectivity of layer 910 to the insulating structure is about 5 to 30. This wet etching may have a selectivity of the protective layer 910 of 5 to 30 to the gate electrode layer 955. Therefore, the substrate 905 exposed in the peripheral circuit region 904 can be further fabricated into MOSFETs and/or other transistors and logic and/or sensing circuits in the peripheral circuit region 904 by means of general and/or future developments. In an embodiment, the microelectronic component 900 is substantially similar to the integrated circuit component 700 of FIG. 7 and/or the component 800 of FIG. 8b. Please refer to FIG. 10 again, which illustrates another embodiment of the present disclosure. 0503-A30208TWFl/ice 25 1254446 Patent Specification 93U7163 Amendment ^ Correction Period·· 94.12.27 Body Circuit Element 900, with 岵 /, There are 仏5 仏 单元 单元 unit area 9 〇 2 and at least one peripheral circuit area _, bottom and a plurality of insulating areas 92 〇 are located in the memory unit area 9 (10), and each of the plurality of active areas 960 is located In the region 92, the component 卯 2 further includes a plurality of gate electrode layers 955, and each of the closed electrode layer milks is located between the insulating structures 920 and located on the corresponding active regions 96 ,, wherein each gate electrode layer The width of 955 is greater than the spacing width of adjacent insulating structures 920 that gate layer 955 contacts. Each gate electrode 955 includes a lesion that extends to an adjacent insulating structure 92, for example, each gate electrode 955 can include a side surface that is in contact with one of the adjacent insulating structures 920, such as each gate electrode 955 Exceeding the corresponding active region 960, each of the insulating structures 920 also includes a recess 921 having a profile that is convex toward one of the gate electrodes 955. The parent edge structure 920 also passes south the substrate 905 and the adjacent gate electrode 955, so each insulating structure 920 can extend past the adjacent gate electrode 955 away from the substrate 905, or each of the plurality of gate electrodes 955 may be no further away from substrate 905 than adjacent insulating structure 920. While the present invention has been described in terms of a preferred embodiment of the present invention, it is to be understood that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 0503-A30208TWFl/ice 26 1254446 Patent Specification No. 93137163 Revision of this amendment date 94.12.27 [Simple description of the drawings] Figures 1 to 5 are a series of sectional views for explaining an embodiment of the present disclosure in the process steps Microelectronic components. Fig. 6 is a schematic view for explaining a system for planarizing a topographic member formed on a substrate in an embodiment of the present disclosure. Figure 7 is a cross-sectional view showing an integrated circuit component of one embodiment of the present disclosure. Figures 8a and 8b are a series of cross-sectional views illustrating the microelectronic components of another embodiment of the present disclosure. Figures 9a through 9f are a series of cross-sectional views for illustrating microelectronic components of another embodiment of the present disclosure. Figure 10 is a cross-sectional view showing a microelectronic component of another embodiment of the present disclosure and shown in Figure 9f. [Main component symbol description] 100, 722, 724, 804, 105~ gate structure; 115~ reference plane; 130~ gate oxide layer; 150~ spacer; 17 0~ insulating layer; 185~ interconnect layer 180 187~interconnect layer 180 190~cap layer; 310~flat plane; 992~element; 110, 620, 710, 905~ substrate; 120~source region; 140~separation gate; 160~source Interconnecting line; 180, 740~ interconnecting layer; first part; second part; 195~ part of capping layer 190; 402, 930~ mask layer; 0503-A30208TWFl/ice 27 1254446 Patent Specification No. 93137163, Amendment Date 94.12: 27 600~ Flattening System; 610~• Grinding Head; 630~ Handle, 640~ First Drive; 650~ Grinding Platform; 655~ Grinding Pad; 657, 850~ Arrow 670~second drive unit; 680~ slurry transfer system; 685~ slurry; 687~ conduit; 700, 800~ integrated circuit components; 730, 750~ dielectric layer; 760, 762~ components; Body element; 810~array substrate; 812~ component 804 main plane 814~ element 806 main plane j 815~ secondary substrate; 820, 920~ insulation structure, 830, 960~ active area; 840~ semiconductor layer; 860, 910~ sheath; 900~ microelectronic component; 902~ unit area; 904~ peripheral circuit area, 921~ recessed (divots); 926~ upper surface of insulating structure 920; 940~ gate dielectric layer; 950~•gate electrode layer; 955~' gate electrode 956~ 'The upper surface of the pole electrode 9 5 5, 990~' integrated circuit component; Η~the height of the gate structure 105 0 0503-A30208TWFl/ice 28