TWI254244B - Method and apparatus for upgradable computer design - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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1254244 銮號 93125038 年月曰 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種升級電腦系統的方法及裝置,特 別是有關於一種在電腦系統之主機板上的升級方法及裝 置。 【先前技術】 中央處理單元(central processing unit, CPU)為電 腦系統的核心元件,處理資料的搬移及運算、電腦程式的 執行並控制所有電腦系統内之裝置。在早期的電腦系統 中’所有電腦系統内之裝置均透過相同的匯流排(s )與 中央處理單元直接連接,並由中央處理單元透過命令直接 控制。 隨著科技的進步,中央處理單元之運算速度以及命BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method and apparatus for upgrading a computer system, and more particularly to an upgrade method on a motherboard of a computer system. And equipment. [Prior Art] The central processing unit (CPU) is the core component of the computer system, handles the movement and calculation of data, executes computer programs, and controls devices in all computer systems. In the early computer systems, all devices in the computer system were directly connected to the central processing unit via the same busbar (s) and directly controlled by the central processing unit through commands. With the advancement of technology, the speed and life of the central processing unit
及接收信號。 普遍使用的I S A介面卡。一個電腦系統f 置’分別使用各種適合該裴置特性或限 1在工業電腦界仍 】之各種不同的裝 制的匯流排傳送以 马上述之現象而產 資料的翻譯。所有裝 匯流排橋接(bus bridge)裳置因為 生。其功能為不同匯流排之間命令及資 置在傳送、讀取、輸出或輸 7貝 1254244 案號 93125038 五、發明說明(2) 時’均透過不同功能的匯流排橋接裝置。因為有匯流排橋 接裝置的存在,一個電腦系m中可以存在各種利用不規格 匯流排之裝置。 系統邏輯(system core logic)晶片為整合多種匯流 排橋接裝置的積體電路元件。當一個電腦系統想要使用的 裝置所使用之不同規格匯流排數量眾多時,為了主機板使 用裝置之信號走線(signal r〇uting)方便進而節省使用之 積體電路數量以及主機板之尺寸大小,很多内含多種匯流 排橋接裝置的系統邏輯晶片被因此而設計出來。系統邏輯 晶片因為基本上為多種匯流排橋接裝置所組成,在某些系 統中使用一組兩顆系統邏輯晶片,稱為系統晶片組 (system chipset)。其中一處理高速匯流排如中央處理單 元匯流排、系統記憶體匯流排、加速圖形處理匯流排…… 等等之間匯流排溝通之晶片通常稱為北橋(n〇rth bridge),而另一處理較低速匯流排如輸出入介面以及系 統儲存裝置介面匯流排等之匯流排之間的晶片 产、 (一 bridge)。南北橋之間透過一組匯流排二J:, 該匯流排可與其他裝置共用或為南北橋之間傳輪命令/ 料所專用。 ' 很多系統邏輯晶片内部甚至植入多種系統裝置,進一 步節省主機板上需要的元件數量。例如加速圖形處理裝置 或系統記憶體裝置可以植入已含有該裝置使用之匯流排的 北橋中,或是輸出入介面裝置可植入已含有該裝置使用之 匯流排的南橋中。 對於每一個系…统上的裝置^言,只要連接該裝置的匯And receiving signals. The commonly used I S A interface card. A computer system provides a translation of the data produced by the above-mentioned phenomenon using a variety of different bus bars suitable for the device characteristics or limits 1 in the industrial computer industry. All bus bridges are worn out. Its function is that the commands and resources between different busbars are transmitted, read, output or transmitted. 7B 1254244 Case No. 93125038 V. Inventive Note (2) Both pass through the busbar bridges with different functions. Because of the presence of busbar bridges, there are a variety of devices in a computer system that utilize non-standard busbars. A system core logic chip is an integrated circuit component that integrates a plurality of bus bar bridges. When a computer system wants to use a device with a large number of different types of bus bars, the number of integrated circuits and the size of the motherboard are saved for the signal board of the motherboard to facilitate the signal r〇uting. Many system logic chips containing a variety of busbar bridges have been designed. System Logic Wafers consist essentially of a variety of busbar bridges. In some systems, a set of two system logic chips, called a system chipset, is used. One of the processing high-speed bus bars, such as the central processing unit bus, the system memory bus, the accelerated graphics processing bus, etc., is commonly referred to as the north bridge (n〇rth bridge), and the other processing The lower speed bus, such as the output interface, and the bus storage between the busbars of the system storage device interface bus, etc. (a bridge). Between the North and South Bridges, through a set of busbars J:, the busbars can be shared with other devices or used for transmission commands/materials between the North and South Bridges. 'Many system logic chips are even embedded inside a variety of system devices, further saving the number of components required on the motherboard. For example, an accelerated graphics processing device or system memory device can be implanted in a north bridge that already contains a busbar for use with the device, or an input/output interface device can be implanted in a south bridge that already contains a busbar for use with the device. For each device, the device is connected to the device.
:排::運作,而且其電源、時脈以及設定元件連接正 確 5亥叙置就能夠正常動作。 第1圖舉例說明一個電腦系統中主機板之方塊圖。圖 機板主要分為系統北橋區1 1以及系統南橋區1 2。 =肢Π3、加速圖形處理裝置114以及系統北橋區控制電路 。其中該系統北橋區控制電路115 —般包括系統北橋 J上所有裝置之電源電路以及風扇電路,主要功能為控 制糸統北橋區11上所有裝置在一般工作期間以及省電期間 工作之電壓以及中央處理單元產生熱能之正常傳導。系统 北橋區11以及系統南橋區12透過系統邏輯匯流排131連、、 接。系統邏輯匯流排1 3 1上的信號包括系統南橋區丨2與北 橋晶/片11 2以及系統北橋區控制電路丨丨5溝通的信號集合。 系/統圯憶體11 3為系統暫時存放包括中央處理單元在内 所有系統裝置於系統執行動作時所需要資料的位置。系統 記憶體11 3通常只在該裝置被供給電源時可以儲存資料, 一般使用的記憶體型態為動態隨機存取記憶體(dynamic random access memory, DRAM)。其中依據系統設計的不 同,系統§己憶體11 3可透過系統記憶體匯流神連接到中央 處理單元11 1或北橋晶片11 2之上。系統記憶體匯流排可為 一個或多個,而個別的系統記憶體匯流排可以連接一個或 多個系統記憶體11 3裝置。舉例來說,某些系統可以同時 存在同步動態隨機存取記憶體(synchronQus DRAM, SDRAM)以及雙倍貧料率同步動態隨機存取記憶體(d〇uble data rateSDRAM,DDR SDRAM) ’或是某些系統具有兩個: 排:: Operation, and its power, clock and setting components are connected correctly. Figure 1 illustrates a block diagram of a motherboard in a computer system. The board is mainly divided into the system North Bridge Area 1 1 and the System South Bridge Area 1 2 . = limbs 3, accelerated graphics processing device 114 and system north bridge control circuit. The north bridge area control circuit 115 of the system generally includes the power circuit and the fan circuit of all devices on the system north bridge J, and the main function is to control the voltage of all devices on the north bridge area 11 during normal operation and during power saving, and central processing. The unit produces normal conduction of thermal energy. The system north bridge area 11 and the system south bridge area 12 are connected and connected through the system logic bus bar 131. The signals on the system logic bus 1 31 include the signal set of the system south bridge area 丨2 and the north bridge crystal/chip 11 2 and the system north bridge area control circuit 丨丨5. The system/system memory 11 3 is a location for the system to temporarily store the data required by all system devices including the central processing unit when the system performs an action. The system memory 113 generally stores data only when the device is powered, and the commonly used memory type is dynamic random access memory (DRAM). Depending on the system design, the system § Resonance 11 can be connected to the central processing unit 11 1 or the north bridge wafer 11 2 through the system memory sink. The system memory bus can be one or more, and individual system memory busses can be connected to one or more system memory devices. For example, some systems can have both synchronous dynamic random access memory (SDRAM) and double-difference data rate SDRAM (DDR SDRAM) or some The system has two
0774-A40337TWF2(N2)93065;VICTORCH0.ptc 第9頁 案號 931250380774-A40337TWF2(N2)93065; VICTORCH0.ptc Page 9 Case No. 93125038
1254244 五、發明說明(4) 相同規格記憶體匯流排的雔 、六排%十·甘士通道(dUal Channel)記憶體匯 ▲排=§十其中母個個別的,匯流排都可依照系 一個或多個記憶體裝置。 T逆接 系統南橋區12主要包括南橋晶片121、透過系統輪出/ 入匯流排1 3 3連接到南柊曰Η ] 9 ] 出/ 同橋日日片1 2 1之糸統輸出/入控制哭 以及透過系統南橋區控制匯流排132連接到南橋晶片 系統南橋區控制電路1 2 2。 透過系統輸出/入匯流排133連接到南橋晶片121之李 統輸出/入控制器1 23功能為控制電腦系統與外界溝通的各 種介面。一個系統中的系統輸出/入匯流排丨3 3可以為一個 或多個,而個別的系統輸出/入匯流排1 3 3可以連接一種或 多種系統輸出/入控制器丨23裝置。舉例來說,系統輸出/ 入匯流,133可以是pCI匯流排或是ISA匯流排等不同的規 格。而每種規格的系統输出/入匯流排丨3 3都有相對其規格 設計的系統輸出/入控制器丨23,其可以是音訊、視訊 存裝置或是資料通訊裝置。不同的系統輸出/入控制器1 控制不同規格的輸出/入介面匯流排丨34,透過各種預先訂 定的輸出/入介面連接器124與外界之元件或訊號電纜線連 接。 系統南橋區控制電路122 一般包括系統南橋區各項妒 置之電源電路以及風扇電路,主要功能為控制系統邏輯衣區 各項裝置在一般工作期間以及省電期間工作之電壓以 統邏輯區各項裝置產生熱能之正常傳導。 ,、 一個電腦系統的主機板在製作完成後,所選 邏輯晶片直接焊接在主機板上無法改變。隨著所選擇的系 m 1254244 -—--一 案號‘ 五、發明說明(5) 統邏輯,中央 板上只能支援 要升級該主機 位不同的裝置 法造成主機板 可外接元件之 接元件因為規 必須另外購買 用以及時間上 裝置。 【發明内容】 本發明的 之南橋晶片的 方法以及裝置 央處理單元、 級0 931250381254244 V. Description of invention (4) 雔, six rows of the same size memory bus, dUal Channel memory ▲ row = § ten of the mother individual, the bus can be according to a Or multiple memory devices. T reverse system Nanqiao District 12 mainly includes South Bridge Chip 121, through system wheeling/inflow busbar 1 3 3 connected to Nanxun] 9] Out / Same Bridge Day Film 1 2 1 糸 System Output / Incoming Control Cry And through the system south bridge control bus 132 connected to the south bridge chip system south bridge control circuit 1 2 2 . The system output/input controller 1 connected to the south bridge chip 121 through the system output/input bus bar 133 functions to control various interfaces of the computer system to communicate with the outside world. The system output/input bus 丨3 3 in one system may be one or more, and the individual system output/incoming bus 133 may be connected to one or more system output/in controller 丨23 devices. For example, the system output/incoming stream, 133 can be a different specification such as a pCI bus or an ISA bus. Each type of system output/input bus 丨3 3 has a system output/input controller 相对23 designed according to its specifications, which can be an audio, video storage device or data communication device. Different system output/input controllers 1 control different sizes of output/input interface busbars 34, and are connected to external components or signal cables through various pre-defined output/input interface connectors 124. The system south bridge control circuit 122 generally includes power circuits and fan circuits of various devices in the south bridge area of the system, and the main function is to control the voltages of various devices in the logic working area of the system during normal operation and during power saving. The device produces normal conduction of thermal energy. After the motherboard of a computer system is completed, the selected logic chip is directly soldered on the motherboard and cannot be changed. With the selected system m 1254244 - a case number ' five, invention description (5) system logic, the central board can only support the device method to upgrade the host bit differently to cause the external components of the motherboard to connect components Because the rules must be purchased separately and the device on time. SUMMARY OF THE INVENTION Method and apparatus for a south bridge wafer of the present invention Central processing unit, stage 0 93125038
處理器 同樣類 板的中 時,現 上仍可 規格替 格已淘 同樣功 都會耗 電腦糸 將系統 系統記 以及記 型且聊 央處理 今的做 使用之 換快速 次而益 /、、、 能但規 費許多 憶體的 位相同 單元或 法是更 元件的 ’可能 法在新 格不同 ,而且 類型也 的裝置 記憶體 換整個 浪費, 使原本 的主機 的裝置 浪費仍 ;主機 如果想 型且朋P 這種做 機板上 用之外 用’而 級的費 使用之 使用-可支援多種型式北橋晶片 、,先之主機板,可以利用本發明提供之 中所使用之與北橋連接之裝置包含中 隐體以及加速圖形處理裝置等後置升 已經決定 之升級。 到不同類 主機板。 並因為主 可繼續使 板繼續使 。這對升 可以繼續 本發明提供一種升級電腦系統的方法,該方法包括· (1)將一個主機板上一南橋晶片與該主機板上一第一系统 北橋區之間溝通之一組第一匯流排信號,連接至一匯流排 切換裝置;其中該第一系統北橋區包含一第一中央處理單 兀,、一第一系統記憶體區、一第一加速圖形處理區以及 一第一北橋晶片;(2)製作一個升級模組,該升級模組包 含一升級系統北橋區,其中該升級系統北橋區包含一升級 中央處理單元區、一升級系統記憶體區、一升級加速圖形 處理區以及一升級北橋晶片;(3)於該主機板上設置一擴When the processor is in the same class, it can still be used in the specification. The same function will consume the computer, the system will be recorded and remembered, and the user will be able to use it for fast times. However, the fee is the same as the unit or the method is more component. The possible method is different in the new case, and the type of device memory is replaced by the whole waste, so that the original host device is wasted; if the host wants the type and the friend P This type of use on the board is used for the use of the 'class of fees' - can support a variety of types of North Bridge chips, the first board, can be used in the device provided by the present invention to connect with the North Bridge contains Zhongyin The body and the accelerated graphics processing device have been upgraded after the upgrade. Go to different types of motherboards. And because the Lord can continue to make the board continue. The pair can continue the present invention to provide a method for upgrading a computer system, the method comprising: (1) communicating a first bridge between a south bridge wafer on a motherboard and a first system north bridge region on the motherboard The row signal is connected to a busbar switching device; wherein the first system north bridge region comprises a first central processing unit, a first system memory region, a first acceleration graphics processing region, and a first north bridge wafer; (2) Making an upgrade module, the upgrade module includes an upgrade system North Bridge area, wherein the upgrade system North Bridge area includes an upgrade central processing unit area, an upgrade system memory area, an upgrade acceleration graphics processing area, and an upgrade Northbridge chip; (3) set an expansion on the motherboard
0774-A40337TWF2(N2)93065;VICTORCHO.ptc 第11頁 1254244 五、發明說明(6) 充插槽,用來連接該升級模組使用以升級該電腦系統,发 中該升級模組透過與該第一匯流排相同之信號與該擴充其 槽連接;(4 )當該升級模組插入該擴充插槽時,該匯^括 切換裝置將該第一中央處理單元區從該第—匯流排'斷1L排、, 將該擴充插槽連接到該第一匯流排上。 汗亚 本發明另提供一可透過插入一升級模組升 機板,其中該升級模組包括一升級系統北4'.及3 = 、,北橋區包含—升級中央處理單元區、m统記情體 ^、一升級加速圖形處理區以及一升級北橋: =括第⑴中一/;一區,其中該第 包3 一弟一中央處理單元區、一第一系統記情體區、一 :加理區以及一第一北橋晶片;(2)二系統弟 该糸統南橋區可同時支援該第一系統北橋區以及該 、、及糸統北橋區’·該系統南橋區於主機板上透 ,與該第-系統北橋區連接;(3) 一擴充插槽,該弟擴充匯: 槽设置於該主機板供連接該升級模 ° 統,其中該升級模組透過與該第升級該電腦系 /、成乐進流排相同之作铐盥纺 心充插槽連接;(4) 一匯流排切換裝置,該匯流 置於該升級模組插入時將該第一奉 ;丨1 、衣 排斷開並將該擴充插槽連接到該第_匯^ 2该第一匯流 本發明進一步提供一種可升級的電 升級模組,該升級模組包括一升二、、、,匕括·— 、、先北橋區包含一升級中央處理單 、一 ^ 、、糸 區、-升級加速圖形處理區以及一; :^統5己fe體 板,包含:⑴-第-系统北r升/由北橋晶片;一主機 北橋&,其中該第-系統北橋 1254244 修正 93125038 五、發明說明(7) 區包含一第一中央處理單元區、一 ^ 第一加诘同五/石 卑一系統記憶體區、一 弟加逑圖形處理區以及一第一 橋區,該李缔左抵广 橋晶片;(2 ) —系統南 怡匕 糸統南橋區可同時支接兮哲 4 μ , & 升級系統北橋區;該系統南橋區:==區:及該 流排與該第-系統北橋區連接;(3)=板上透過,一弟—匯 系统,复中3斗ί 升級模組使用以升級該電腦 宁、,允^中该升級杈組透過與該第一匯流排相同$ f _冷 該擴充插槽連接· ^ ^ χ 匯*排相同之k唬與 曰%丧,u) —匯流排切換奘詈,苛六 裝置於該升級模組插人砗脾j Μ 、衣置▲匯机排切換 一匯流排斷開並將亏艉右杯姚* r天地里早兀&仗该弟 【實施方式】 Η擴充插槽連接到該第-11流排上。 本發明提供之一種升級電腦 κ ^ m ^ ^ ^ ^ 但开叹电細糸統的方法,其目的主要 亓,註註+ φm 仁疋不同類型之中央處理單 ^吊要使用不同的北橋晶片。在現今的季统邏輯曰 η ^ ^ ^ -Γ ^ 月匕$南橋日日片,通常可以支援多種不 同規才口而可以連接不同中本声 -個主機^ : 處早元的北橋晶片。透過將 之間溝通之一組第—羅汚排产咕 々u 糸、,死北橋& Μ έΗ # ffl ^ ^ 匚瓜排化唬,作能夠切換給一個升級 模組便用之没计,领可丨7太店 ^ ^ ^ ; I便了以在原有的主機板連接使用新的中 央處理卓兀以及北棟s )4。丁、 裡諼分吉拉、垂社A °日日片不過現今與北橋晶片和中央處 圖形處理裝置在内;如果迻此n τ衣置以及加速0774-A40337TWF2(N2)93065; VICTORCHO.ptc Page 11 1254244 V. Invention Description (6) A charging slot is used to connect the upgrade module to upgrade the computer system, and the upgrade module transmits the same a bus with the same signal is connected to the expansion slot; (4) when the upgrade module is inserted into the expansion slot, the switching device disconnects the first central processing unit region from the first bus bar 1L row, connect the expansion slot to the first bus. Khanya provides a upgrade module that can be inserted into an upgrade module, wherein the upgrade module includes an upgrade system north 4'. and 3 = , and the north bridge area includes - upgrade the central processing unit area, m system record Body ^, an upgrade accelerated graphics processing area and an upgraded North Bridge: = include (1) in the first /; a district, where the first package 3 a brother - a central processing unit area, a first system of the body area, a: plus The district and a first north bridge chip; (2) the second system brother, the Nanqiao district can support the first system of the North Bridge area and the North Bridge area of the system, and the South Bridge area of the system is transparent on the main board. Connected to the North-bridge area of the first system; (3) an expansion slot, the expansion port: the slot is disposed on the motherboard for connecting to the upgrade module, wherein the upgrade module is upgraded with the computer system/ , the Chengle inflow row is the same as the 铐盥 spinning core filling slot connection; (4) a bus bar switching device, the confluence is placed when the upgrade module is inserted, the first 丨1, the clothing row is disconnected And connecting the expansion slot to the first sink 2, the first sink is further provided by the present invention An upgradeable power upgrade module, the upgrade module includes a liter, a second, and a squad, and the north bridge area includes an upgrade central processing unit, a ^, a 糸 area, an upgrade acceleration graphics processing area And a; : ^ system 5 fel body board, including: (1) - the first system north r / by the North Bridge chip; a host North Bridge &, the first - system North Bridge 1254244 amendment 93125038 five, invention description (7) area The invention comprises a first central processing unit area, a first plus 诘5/Shibei system memory area, a younger 逑 graphics processing area and a first bridge area, and the Li is left to the Guangqiao wafer; 2) - The system Nanyi District Nanqiao District can simultaneously support the Zhezhe 4 μ, & upgrade system North Bridge District; the system South Bridge District: == District: and the flow line is connected to the first system North Bridge; ( 3) = On-board transmission, one brother-sink system, the third-in-one ί upgrade module is used to upgrade the computer, and the upgrade group is the same as the first bus. Slot connection · ^ ^ χ sink * row the same k唬 and 曰% mourning, u) - bus bar switching 奘詈, harsh The device is inserted into the upgrade module, the spleen j Μ, the clothes set ▲ the switch machine switch, the bus is disconnected, and the right cup is lost. Yao r 天 里 姚 兀 amp amp 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗 仗The trough is connected to the -11th flow row. The invention provides a method for upgrading a computer κ ^ m ^ ^ ^ ^ but to open a sigh system, the main purpose of which is 亓, note + φm 仁 疋 different types of central processing single hangs use different north bridge wafers. In today's chronological logic η η ^ ^ ^ - Γ ^ 匕 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南Through the communication between the group, the first group, the sputum, the sputum, the sputum, the sputum, the sputum, the sputum, the squad, the squad, the squad, the squad, the squad, the Collar 丨 7 too shop ^ ^ ^ ; I will use the new central processing Zhuo Yu and North Building s) 4 in the original motherboard connection. Ding, Li Ji, Gila, and the A ° Japanese film, but now with the North Bridge chip and the central graphics processing device; if you move this n τ clothes and accelerate
弟13頁 上,要將升級後之中央處理單元以及北橋 記憶體裝置以及加速圖形處理袭置之信號連接回:::、,先 上,±度將提南過_多而並不^實施之效益〇本發明之升級 案號931250狀 1254244On page 13 of the younger brother, the upgraded central processing unit and the north bridge memory device and the signal for accelerating the graphics processing are connected back to:::, first, ± degrees will be over _ more than not implemented Benefits 升级 The upgrade number of the invention is 931250 1254244
發明說明(8) _ 方式為將一個主機板上一南橋晶片與該主機板上 統北橋區之間溝通之一組第一匯流排信號,連 糸 排切換裝置,而該裝置能將爷第一 丨 至一匯流 模組插入時連接至該升:;:弟其於-升級 該升級模組相對於系統之功能m均包含與 τ兀區:—系統記憶體區、-加速圖形處理區以及二ϊ 晶片。該主機板上將設置一擴夺杆 匕橋 模组之用。各爷升级y έ 4 5 g,用來做連接該升級 換裝置Ξ該;充:槽時,流排切 充插槽連接到該第一並將該擴 =為一組跳接器’將該第—匯流排上所有信號用跳=5Z :接往該第-北橋區或是接往該擴充插槽。該u匯 ::、 i置也可以為一匯流排開關積體電路匯^刀、 積體電路元件接收從該主機板來之一切:二匯;=關 於該升級模組未插入時將該切換信號設為第:狀:,機板 该升級模組插入時將該切換信號設;^於 該第-匯流排之信號切換到連接該第—中J = ”之 並於該切換信號為第二狀態時將料統邏輯 ’ 以及系統繞線自第一匯流排上斷開,不4=匕裝置 線對高速信號之反射干擾信號:更了以避免板子上之繞 第2圖表示一個根據本發明實施例之 的方塊圖。該主機板包括_第一夺统 ^、、、先主機板Description of the Invention (8) _ The method is to communicate a group of first bus signals between a south bridge chip on a motherboard and a north bridge area on the motherboard, and even switch the switching device, and the device can be first Connect to the liter when the plug-in module is inserted:;: The other function of the upgrade module relative to the system includes the τ兀 area: the system memory area, the acceleration graphics processing area, and the second ϊ Wafer. A booster bar bridge module will be installed on the motherboard. Each y is upgraded y έ 4 5 g, which is used to connect to the upgrade device; when charging: slot, the flow line is connected to the first slot and the expansion is a set of jumpers' The first signal on the busbar is hop = 5Z: it is connected to the first-north bridge or to the expansion slot. The u sink::, i can also be a bus bar switch integrated circuit sink knife, the integrated circuit component receives everything from the motherboard: two sinks; = about the upgrade module is not inserted when the switch The signal is set to the first: shape: when the upgrade module is inserted, the switching signal is set; ^ the signal of the first bus bar is switched to connect to the first - middle J = "" and the switching signal is the second In the state, the system logic 'and the system winding are disconnected from the first bus bar, not 4=匕 device line to the high-speed signal reflection interference signal: more to avoid the winding on the board. FIG. 2 shows a according to the present invention. A block diagram of an embodiment. The motherboard includes a first motherboard, a first motherboard
0774-A40337TWF2(N2)93065;VICTORCHO 第14頁 ---^~手」先,區21、一系統南0774-A40337TWF2(N2)93065; VICTORCHO Page 14 ---^~手" first, District 21, a system south
;二哲 j吳 Μ 1254244 修正 MM 93125038 五、發明說明(9) 、一匯流排切換裝置23以及一擴充插槽24。 一斤第一系統北橋區包括一第一中央處理單元區211、 第北橋晶片2 1 2、一第一系統記憶體區2 1 3以及一第一 加速圖形處理區2 1 4。第一系統北橋區2 1另包含第一系統 北橋區之控制電路,其控制第一系統北橋區21上所有裝置 之電源及散熱處理功能。 系統南橋區22包括南橋晶片221。系統南橋區22另包 括所有不與第一系統北橋區2 1相連之裝置,其主要功能為 主枝板上所有其他裝置與第一系統北橋區2 1之溝通以及控 制主機板與外界之裝置之資料交換。 ' 系統南橋區2 2透過匯流排2 3 1與匯流排切換裝置2 4連 接。匯流排切換裝置24透過匯流排2311與第一系統北橋區 21連接並透過匯流排23 12與擴充插槽23連接。匯流排切換 裝置24在擴充插槽23未連接其他裝置時將匯流排231之信' ?虎與匯流排2 3 11相對應之k號連接在一起並與匯流排2 31 2 之彳§號斷開。在此情形下’系統南橋區2 2與第一系統北橋 £ 2 1相連接’組成^一個元整的糸統架構而可以正常開機^ 行0 第3圖表示一個配合第2圖本發明實施例之可升級主機 板的升級模組3 1的方塊圖。升級模組3 1包括一升級中央處 理單元區3 1 1、一升级北橋晶片3 1 2、一升級系統記憶體區 3 1 3、一升級加速圖形處理區3 1 4以及一升級信號連接哭 316。升級模組31另包含該升級模組之控制電路(圖中未顯 示),其控制該升级模組上所有裝置之電源及散熱處理功 能。 …、Erzhe j Wu Μ 1254244 Amendment MM 93125038 V. Invention description (9), a busbar switching device 23 and an expansion slot 24. One kilogram of the first system north bridge area includes a first central processing unit area 211, a north bridge wafer 2 1 2, a first system memory area 2 1 3, and a first accelerated graphics processing area 2 1 4 . The first system north bridge area 2 1 further includes a control circuit of the first system north bridge area, which controls the power supply and heat dissipation processing functions of all devices on the north bridge area 21 of the first system. The system south bridge area 22 includes a south bridge wafer 221. The system south bridge area 22 further includes all devices not connected to the first system north bridge area 21, and its main function is to communicate with all other devices on the main branch board and the first system north bridge area 21 and to control the main board and the external device. Exchange of information. The system south bridge area 2 2 is connected to the bus bar switching device 24 through the bus bar 2 3 1 . The busbar switching device 24 is connected to the first system north bridge region 21 via the bus bar 2311 and to the expansion slot 23 via the bus bar 2312. The busbar switching device 24 connects the letter of the bus bar 231 to the k number corresponding to the bus bar 2 3 11 when the expansion slot 23 is not connected to other devices, and disconnects the k number corresponding to the bus bar 2 31 2 open. In this case, 'the system south bridge area 2 2 is connected with the first system north bridge £ 2 1 'to form a unitary system architecture and can be normally turned on ^ row 0. FIG. 3 shows a cooperation with the second diagram of the embodiment of the invention. A block diagram of the upgrade module 3 1 of the upgradeable motherboard. The upgrade module 3 1 includes an upgrade central processing unit area 31, an upgraded north bridge chip 3 1 2, an upgrade system memory area 3 1 3, an upgrade acceleration graphics processing area 3 1 4, and an upgrade signal connection crying 316. . The upgrade module 31 further includes a control circuit (not shown) of the upgrade module, which controls power and heat dissipation processing functions of all devices on the upgrade module. ...,
〇774-A40337TWF2(N2)93065;VICTORCHO.ptc 第15頁 1254244 / __ti虎93125038__年 月 日 修正 五、發明說明(10) 與擴充插槽2 3連接的信號連接器3丨6上之信號與匯流 排2 3 1 2之信號定義相同。匯流排23丨丨及匯流排2 3丨2上之信 號之疋義在一般情形下均相同。只有在少數情形中,控制 第一系統北橋區2 1及升級模組3 1之信號有不同的定義時, 匯流排2 3 11及匯流排2 3 1 2會有信號定義的差異。 在升級模組3 1連接至擴充插槽2 3時,匯流排切換裝置 2 4將匯流排2 3 1之信號與匯流排2 3 1 2相對應之信號連接在 一起並與匯流排2 3 11之信號斷開。在此情形下,系統邏輯 區22與升級中央處理單元區311連接,組成一個完整的系 統而可以正常開機執行。 第4圖表示另一個根據本發明一實施例之電腦系統主 機板40的方塊圖。該主機板4〇包括一第一系統北橋區41、 一系統南橋區42 ' —匯流排切換裝置44以及一擴充插槽 4 3。該主機板4 0另包含一加速圖形處理轉接插槽4 5及一第 二加速圖形處理插槽4 6 ’其中加速圖形處理轉接插槽& 5及 第二加速圖形處理插槽4 6之相對應信號直接連接作為傳遞 匯流排信號之用。 弟一系統北橋區41包括一 AMD K7 462腳位型式中央處 理單元411、一 VIA KT88 0北橋晶片412、4個DDR SDRAM記〇774-A40337TWF2(N2)93065; VICTORCHO.ptc Page 15 1254244 / __ti Tiger 93125038__年月日日 Revision 5, invention description (10) Signal connector 3丨6 connected to expansion slot 2 3 The signals of bus 2 2 1 2 are defined identically. The signals on the bus bar 23丨丨 and the bus bar 2 3丨2 are the same in the general case. Only in a few cases, when the signals controlling the first system north bridge area 2 1 and the upgrade module 3 1 have different definitions, the bus line 2 3 11 and the bus bar 2 3 1 2 have signal definition differences. When the upgrade module 31 is connected to the expansion slot 23, the busbar switching device 24 connects the signal of the busbar 2 31 to the signal corresponding to the busbar 2 3 1 2 and the busbar 2 3 11 The signal is disconnected. In this case, the system logic area 22 is connected to the upgraded central processing unit area 311 to form a complete system that can be booted normally. Figure 4 is a block diagram showing another computer system main board 40 in accordance with an embodiment of the present invention. The motherboard 4A includes a first system north bridge area 41, a system south bridge area 42'-bus bar switching device 44, and an expansion slot 43. The motherboard 40 further includes an accelerated graphics processing transfer slot 45 and a second accelerated graphics processing slot 4 6 'where the accelerated graphics processing adapter slot & 5 and the second accelerated graphics processing slot 4 6 The corresponding signal is directly connected as a signal for transmitting the bus. The first system of the North Bridge District 41 includes an AMD K7 462 pin type central processing unit 411, a VIA KT88 0 north bridge chip 412, and four DDR SDRAM records.
憶體插槽4 1 3以及第一加速圖形處理插槽4 1 4。第一系統北 橋£ 4 1另包含電源/時脈控制電路4 1 5,其控制第一系统北 橋區4 1上所有裝置之時脈、電源及散熱處理功能。 由於所使用之AMD K 7462腳位型式中央處理單元411 以及VIA KT880北橋晶片412的設計方式,4個DDR SDRAM記The memory slot 4 1 3 and the first accelerated graphics processing slot 4 1 4 are used. The first system north bridge £4 1 further includes a power/clock control circuit 4 1 5 that controls the clock, power and thermal processing functions of all devices on the north bridge 4 1 of the first system. Due to the design of the AMD K 7462 pin type central processing unit 411 and the VIA KT880 north bridge chip 412 used, four DDR SDRAMs are recorded.
0774- A403 37TWF2 (N2) 93065; VICTORCHO. p t c 第16頁 1254244 .月 曰 修正 93125088 五、發明說明(11) 北橋晶片4 1 2。 、系統南橋區42包括VIA KT8327CD南橋晶片421,其透 過^^ l—UNK匯流排與ΠΑ KT88 0北橋晶片412溝通。如圖 所不=系統邏輯區42另包括所有不與第一系統北橋區41相 連之衣置’其主要功能為主機板上所有其他裝置盘第一系 =北橋區41之溝通以及控制主機板與外界之裝置^資料交 系統南橋區42透過匯流排431與匯流排切換裝置44連 接。匯流排43 1之信號包含VIA南北橋之間溝通之v —UNK匯 流排信號以及時脈及電源控制信號。匯流排切換裝置44透 過匯流排43U與第一系統北橋區41連接並透過匯流排4312 與擴充插槽43連接。匯流排切換裝置44在擴充插槽43未連 接其他I置時將匯流排4 3 1之信號與匯流排4 3 1丨相對應之 信號連接在一起並與匯流排43丨2之信號斷開。在此情形 下’系統南橋區42與第一系統北橋區4 1相連接,組成一個 完整的系統架構而可以正常開機執行。 第5圖表示一個配合第4圖本發明實施例之可升級主機 板的升級模組5 1的方塊圖。升級模組5 1包括一 y I a γ 8 7 5 4 腳位型式中央處理單元511、一 via Κ8Τ800北橋晶片512、 2個DDR SDRAM記憶體插槽513、一升級加速圖形處理連接 器514以及一升級信號連接器516。升級模組51另包含該升 級模組之時脈/電源控制電路51 5,其控制該升級模組上所 有裝置之時脈/電源及散熱處理功能。 由於所使用之VIA K8 754腳位型式中央處理單元hi 以及VIA K8丁800北橋晶片512之設計,2個DDR SDRAM記憶 — 丨丨 | ------ -- _0774- A403 37TWF2 (N2) 93065; VICTORCHO. p t c Page 16 1254244 .月 曰 Amendment 93125088 V. Description of invention (11) Northbridge wafer 4 1 2 . The system south bridge area 42 includes a VIA KT8327CD south bridge wafer 421 which communicates with the KT88 0 north bridge wafer 412 through the ^^ l-UNK bus bar. As shown in the figure, the system logic area 42 further includes all the clothes that are not connected to the first system north bridge area 41. The main function of the system is that all the other devices on the motherboard are connected to the first system = the north bridge area 41 and the control board and the control board are The external device ^ data exchange system south bridge area 42 is connected to the bus bar switching device 44 via the bus bar 431. The signal of the bus bar 43 1 includes the v-UNK bus signal and the clock and power control signals communicated between the VIA North and South Bridges. The busbar switching device 44 is connected to the first system north bridge region 41 via the bus bar 43U and to the expansion slot 43 via the bus bar 4312. The busbar switching device 44 connects the signal of the busbar 433 to the signal corresponding to the busbar 433 when the expansion slot 43 is not connected to the other I, and disconnects from the signal of the busbar 丨2. In this case, the system south bridge area 42 is connected to the first system north bridge area 4 1 to form a complete system architecture and can be booted normally. Fig. 5 is a block diagram showing an upgrade module 51 for an upgradeable motherboard in accordance with an embodiment of the present invention in Fig. 4. The upgrade module 51 includes a y I a γ 8 7 5 4 pin type central processing unit 511, a via Κ8Τ800 north bridge chip 512, two DDR SDRAM memory slots 513, an upgrade acceleration graphics processing connector 514, and a Upgrade signal connector 516. The upgrade module 51 further includes a clock/power control circuit 51 5 of the upgrade module, which controls the clock/power and heat dissipation processing functions of all devices on the upgrade module. Due to the VIA K8 754 pin type central processing unit hi and the VIA K8 Ding 800 North Bridge chip 512 design, 2 DDR SDRAM memories — 丨丨 | ------ -- _
W °774-A40337TWF2(N2)93065;VICTORCH0.ptc 第17頁 1254244 __案號 93125038_年月日 絛正_ 五、發明說明(12) 體插槽51 3在本實施例中之升級模組51上連接到VIA K8 754腳位型式中央處理單元511。 與擴充插槽4 4連接的信號連接器5 1 6上之信號與匯流 才非4 3 1 2之信號定義相同。匯流排4 3 1 1及匯流排4 3 1 2上之信 號之定義相同’均包含V IA V-LI NK匯流排信號以及時脈及 電源控制信號。 在升級板組5 1連接至擴充插槽4 3時,匯流排切換裝置 4 4將匯流排4 3 1之信號與匯流排4 3 1 2相對應之信號連接在 一起並與匯流排4311之信號斷開。在此情形下,系統邏輯 區4 2與升級模組5 1連接’組成一個完整的系統而可以正常 開機執行。W °774-A40337TWF2(N2)93065; VICTORCH0.ptc Page 17 1254244 __ Case No. 93125038_年月日日正正 _ 5, invention description (12) body slot 51 3 in this embodiment of the upgrade module 51 is connected to the VIA K8 754 pin type central processing unit 511. The signal on the signal connector 5 1 6 connected to the expansion slot 44 is the same as the signal defined by the sink. The signals on the bus 4 3 1 1 and the bus 4 3 1 2 have the same definitions ‘both V IA V-LI NK bus signals and clock and power control signals. When the upgrade board group 51 is connected to the expansion slot 4 3 , the bus bar switching device 4 4 connects the signal of the bus bar 4 3 1 with the signal corresponding to the bus bar 4 3 1 2 and the signal of the bus bar 4311. disconnect. In this case, the system logic area 42 is connected to the upgrade module 51 to form a complete system that can be booted normally.
請注意在本實施例的設計中,北橋晶片5丨2控制之加 速圖形處理匯流排信號透過升級加速圖形處理連接器5 14 於升級模組5 1插入主機板4〇時連接到加速圖形處理轉接插 槽45 ’將匯流排信號連接到第二加速圖形處理插槽“上。 加速圖幵> 處理裝置於系統插入升級模組5 1後應連接在第二 加速圖形處理插槽46上因為第一加速圖形處理插槽414於 升級模組插入後,匯流排43 11於系統上斷開,北橋晶片 4 1 2已失去功用而無法作用。透過此實施例之設計,升級 模組之尺寸可以更小而且升級後之加速圖形處理裝置可 以繼續使用原本配合主機板4〇之機殼之機構。 ^透過應用本發明,電腦系統在升級時,只需增加升級 Ϊ t以及升級模組上所需要之裝置而非整個系統,大部分 弘細系統中原有之裝置都可以繼續使用。如果升級模組的Please note that in the design of this embodiment, the north bridge chip 5丨2 controlled acceleration graphics processing bus signal is connected to the accelerated graphics processing through the upgrade acceleration graphics processing connector 5 14 when the upgrade module 51 is inserted into the motherboard 4 The socket 45' connects the bus signal to the second accelerated graphics processing slot "on. Acceleration map". The processing device should be connected to the second accelerated graphics processing slot 46 after the system is inserted into the upgrade module 51. After the first acceleration graphics processing slot 414 is inserted into the upgrade module, the bus bar 43 11 is disconnected from the system, and the north bridge chip 42 has lost its function and cannot function. Through the design of the embodiment, the size of the upgrade module can be The smaller and upgraded accelerated graphics processing device can continue to use the mechanism that originally fits the motherboard of the motherboard. ^ Through the application of the present invention, the computer system needs to be upgraded and upgraded when needed. The device, not the entire system, can be used in most of the original systems. If you upgrade the module
1254244 ㈣ _案號93125038,_年' 月 曰 修正_ 五、發明說明(13) 甚至系統的機殼都可以繼續適用。升級電腦的人工以及金 錢上的花費,因此而可以大幅的減少。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。1254244 (four) _ case number 93125038, _ year 'month 曰 correction _ five, invention description (13) Even the system's casing can continue to apply. The cost of upgrading the computer and the money spent on the computer can be greatly reduced. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
0774-A40337TWF2(N2)93065;VICTORCHO.ptc 第19頁 _案號 93125038:0774-A40337TWF2(N2)93065; VICTORCHO.ptc Page 19 _Case No. 93125038:
1254244 圖式簡單說明 【圖示簡單說明】 本發明透過後附綠纟 盤了解,其僅為“::::= 第i圖舉例說明_個電^將本\明=制於圖示範圍。 m 1U電恥糸統中主機板之方塊圖。 的方::。表不一個根據本發明實施例之電腦系統主機板 第3圖表示一個配合第2圖本發明實施例之可升級 板的升級模組31的方塊圖。 』开、.及主機 第4圖表不另一個根據本發明一實施例之電腦系統主 機板4 0的方塊圖。 第5圖表示一個配合第4圖本發明實施例之可升級主機 板的升級模組5 1的方塊圖。 【主要元件符號說明】 11 系統北橋區 1 2、2 2、4 2 系統南橋區 2 1、41 第一系統北橋區 131 、 132 、 133 、 231 、 431 、 432 、 2311 、 2312 、 431 1、4312 匯流排1254244 Brief description of the drawing [Simplified illustration of the illustration] The present invention is known by the accompanying green disk, which is only "::::= ith. The block diagram of the motherboard in the m 1U electrosurgical system. The table: Figure 3 shows a computer system motherboard according to an embodiment of the present invention. FIG. 3 shows an upgrade of the upgradeable board in accordance with the embodiment of the present invention. The block diagram of the module 31. The opening and the fourth diagram of the host computer is not a block diagram of the computer system motherboard 40 according to an embodiment of the present invention. FIG. 5 is a diagram showing an embodiment of the present invention in conjunction with FIG. Block diagram of upgrade module 5 of upgradeable motherboard. [Key component symbol description] 11 System North Bridge Zone 1, 2, 2 2, 4 2 System South Bridge Zone 2 1, 41 First System North Bridge Zone 131, 132, 133 231, 431, 432, 2311, 2312, 431 1, 4312 bus
〇774-A40337TWF2(N2)93065;VICTORCHO.ptc 第20頁〇774-A40337TWF2(N2)93065; VICTORCHO.ptc第20页
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070139898A1 (en) * | 2005-12-16 | 2007-06-21 | Inventec Corporation | System motherboard having expansibility and variability |
US7930532B2 (en) * | 2006-11-15 | 2011-04-19 | Via Technologies, Inc. | Systems and methods for basic input output system (BIOS) management |
US9524262B2 (en) * | 2011-08-18 | 2016-12-20 | Hewlett-Packard Development Company, L.P. | Connecting expansion slots |
JP2019096007A (en) * | 2017-11-21 | 2019-06-20 | 富士ゼロックス株式会社 | Electronic device and image formation system |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5321827A (en) * | 1989-08-02 | 1994-06-14 | Advanced Logic Research, Inc. | Computer system with modular upgrade capability |
AU1971992A (en) * | 1991-04-18 | 1992-11-17 | Intel Corporation | Method and apparatus for upgrading a computer processing system |
EP0510241A3 (en) * | 1991-04-22 | 1993-01-13 | Acer Incorporated | Upgradeable/downgradeable computer |
EP0529142A1 (en) * | 1991-08-30 | 1993-03-03 | Acer Incorporated | Upgradeable/downgradeable computers |
US5848250A (en) * | 1993-04-01 | 1998-12-08 | Packard Bell Nec | Processor upgrade system for a personal computer |
US5586270A (en) * | 1993-09-30 | 1996-12-17 | Intel Corporation | Method and apparatus for upgrading a central processing unit and existing memory structure in a computer system |
US5884091A (en) * | 1993-12-08 | 1999-03-16 | Intel Corporation | Computer system having a central processing unit responsive to the identity of an upgrade processor |
US5384692A (en) * | 1993-12-16 | 1995-01-24 | Intel Corporation | Socket with in-socket embedded integrated circuit |
US5781774A (en) * | 1994-06-29 | 1998-07-14 | Intel Corporation | Processor having operating modes for an upgradeable multiprocessor computer system |
US5841287A (en) * | 1997-02-26 | 1998-11-24 | Advanced Micro Devices, Inc. | System for detecting motherboard operation to ensure compatibility of a microprocessor to be coupled thereto |
US6851002B1 (en) * | 1998-04-01 | 2005-02-01 | Omron Corporation | Processing device with parallel mounting regions for component exchange |
WO2000019292A2 (en) * | 1998-09-29 | 2000-04-06 | Evergreen Technologies, Inc. | Upgrade card for a computer system |
US6292859B1 (en) * | 1998-10-27 | 2001-09-18 | Compaq Computer Corporation | Automatic selection of an upgrade controller in an expansion slot of a computer system motherboard having an existing on-board controller |
CN2594855Y (en) * | 2002-09-27 | 2003-12-24 | 威达电股份有限公司 | Computer board with drawing acceleration port |
-
2004
- 2004-08-18 TW TW093125038A patent/TWI254244B/en active
-
2005
- 2005-07-20 US US11/184,792 patent/US20060041703A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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TW200608284A (en) | 2006-03-01 |
US20060041703A1 (en) | 2006-02-23 |
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