1253230 15197twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種限制放大器架構，且特別是有關 於-種用於差動直流電壓消除以節省晶片佈局面積的限制 放大器架構。 【先前技術】 在無線通訊系統，特別是藍牙無線接收器，在高斯頻 移鍵控（GFSK，Gaussian Frequency Shift Keying)接收器 解调交使用限制放大器消耗功率較自動增益控制放大器為 小，且限制放大杰的動態範圍較自動增益控制放大器為 大。此應用可適用於對數放大器。 請對照圖1，其係繪示習知一種限制放大器架構之電 路圖。在習知技術中，限制放大器架構1〇〇係包括多數個 增益放大器102,每個增益放大器1〇2均具有正輸入端及 負輸入端來接收輸入訊號，以及正、負輸出端以與下一個 增盈放大為102電性連接，而如圖1所示，將會有一個增 益放大器102接收所輸入之訊號Vin，在將訊號作一級級 的放大後，由最後一級的增益放大器1〇2將訊號v〇ut輸 出。而因為在多級的增益放大器102對電晶體之差動偏移 直流作放大，因此訊號將因此差動直流偏移電壓而偏離， 而使得最後一級增益放大器102所輸出之訊號產生偏移。 故，為了調整所偏移之電壓，如圖1所示，將會配置 一偏移取消電路以負回授方式降低差動直流電壓偏移來消 除對訊號處理過程中所產生之偏移。 5 1253230 15197twf.doc/g 但在如圖1的架構中，僅取最後一級的增益放大器102 所輸出之訊號來對第一級的增益放大器102的直流偏壓作 調整，將需要很大的電阻（R)與電容（C)來萃取直流偏 移電壓。 因此，在習知之技術中，即產生了如圖2A與圖2B所 示之兩種不同的配置直流偏壓的限制放大器。如圖2A所 示，此種配置方式係為配置一輸出固定值至增益放大器 春 202之直流偏壓電路204,而且在增益放大器202之正、負 輸入端前還配置有阻絕電容206與208，以阻絕上一級傳 來之訊號中的直流電壓，此為開路式差動直流電壓消去法 而習知還有另一種配置直流偏壓的限制放大器，如圖 2B所示，此種配置方式係為配置根據增益放大器2〇2所輸 出之直流偏移電壓回授至至增益放大器202之直流電壓的 自直流偏壓及偏移取消電路210。同樣地，在增益放大器、 202之正、負輸入端前還配置有阻絕電容2〇6與2〇8，以阻 絕輸出傳來之訊號，此即直流電壓萃取動作。 _ 綜合圖2A與2B這樣的配置，可以在每一級即正確的 對訊號作調整而後輸出，因此，便發展成了如圖3所示之 架構。請參照圖3,以具五級之閉迴路限制放大器架構3〇〇 來說，其係包括五個增益放大器302，且每一個增益放大 為302均配置一個自直流偏壓及偏移取消電路，且其 可以是正迴授或負迴授。而每個增益放大器3〇2的正、負 輸入端前還配置阻絕電容306與3〇8，以阻絕直流偏壓。' 但這樣每個增益放大器302都配置自直流偏壓及偏移 1253230 |5197twf.doc/g 取消電路304的結果，雖然可讓輸出的訊號變準確，但將 造成在晶片的面積比例偏大。然而，在現今講求任何電路 都盡量能設計在一個晶片的時代，這樣的設計將不符合趨 〇 【發明内容】1253230 15197twf.doc/g IX. Description of the Invention: Technical Field of the Invention The present invention relates to a limiting amplifier architecture, and more particularly to a limiting amplifier for differential DC voltage cancellation to save wafer layout area. Architecture. [Prior Art] In wireless communication systems, especially Bluetooth wireless receivers, the GFSK (Gaussian Frequency Shift Keying) receiver demodulates the use of the limiting amplifier to consume less power than the automatic gain control amplifier. The dynamic range of the amplifier is larger than that of the automatic gain control amplifier. This application is suitable for logarithmic amplifiers. Referring to Figure 1, there is shown a circuit diagram of a conventional limiting amplifier architecture. In the prior art, the limiting amplifier architecture 1 includes a plurality of gain amplifiers 102, each of which has a positive input terminal and a negative input terminal for receiving input signals, and positive and negative output terminals for A gain amplification is 102 electrical connection, and as shown in FIG. 1, there will be a gain amplifier 102 receiving the input signal Vin, after the signal is first-stage amplified, by the last stage gain amplifier 1〇2 Output the signal v〇ut. Since the multi-stage gain amplifier 102 amplifies the differential offset DC of the transistor, the signal will thus deviate from the differential DC offset voltage, causing the signal output by the last stage gain amplifier 102 to shift. Therefore, in order to adjust the offset voltage, as shown in Fig. 1, an offset cancellation circuit will be configured to reduce the differential DC voltage offset in a negative feedback manner to eliminate the offset generated during the signal processing. 5 1253230 15197twf.doc/g However, in the architecture of Figure 1, only the signal output from the gain amplifier 102 of the last stage is used to adjust the DC bias of the gain amplifier 102 of the first stage, which requires a large resistance. (R) and capacitor (C) to extract the DC offset voltage. Thus, in the prior art, two different limiting amplifiers with DC bias configurations as shown in Figures 2A and 2B are produced. As shown in FIG. 2A, this configuration is configured to configure a DC bias circuit 204 that outputs a fixed value to the gain amplifier 202, and a blocking capacitor 206 and 208 are disposed before the positive and negative inputs of the gain amplifier 202. In order to block the DC voltage in the signal from the previous stage, which is an open-circuit differential DC voltage cancellation method, there is another limiting amplifier configured with a DC bias, as shown in FIG. 2B. The self-DC bias and offset cancel circuit 210 for feeding back the DC offset voltage according to the gain amplifier 2〇2 to the DC voltage of the gain amplifier 202 is configured. Similarly, before the positive and negative inputs of the gain amplifier and 202, blocking capacitors 2〇6 and 2〇8 are arranged to block the output signal, which is the DC voltage extraction action. _ Integrally, the configuration of Figures 2A and 2B can be adjusted at each level, that is, the correct signal is output, and thus, the architecture shown in Fig. 3 is developed. Referring to FIG. 3, a five-stage closed-loop limiting amplifier architecture 3A includes five gain amplifiers 302, and each of the gain amplifications 302 is configured with a self-DC bias and offset cancellation circuit. And it can be positive feedback or negative feedback. The positive and negative inputs of each gain amplifier 3〇2 are also provided with blocking capacitors 306 and 3〇8 to block the DC bias. However, each of the gain amplifiers 302 is configured with a DC bias voltage and offset 1253230 | 5197 twf.doc / g cancel circuit 304 results, although the output signal can be made accurate, but will cause a large proportion of the area of the wafer. However, in today's era, any circuit can be designed in the era of a wafer, such a design will not conform to the trend [invention]
本發明的目的就是在提供一種限制放大器架構，其係 可僅於接收輸入訊號Vin的前幾級增益放大器與最後要輸 出訊號的幾級增益放大器配置自直流偏壓及偏移取消電 路，中間級增盈放大器採完全開放式，以達到所要求之輸 出訊號Vout的準確率，與差動直流偏移取消功能。 本發明的再一目的是提供一種限制放大器架構，其係 可大大縮小了佈局的面積。 本發明提出 ‘種限制（limiting)放大器架構，其係適 用於同斯頻移鍵控調變器（Gaussian FrequencyIt is an object of the present invention to provide a limiting amplifier architecture that can be configured from a DC bias and offset cancellation circuit only for the first few stages of the gain amplifier that receives the input signal Vin and the stages of the final gain signal. The gain amplifier is fully open to achieve the required accuracy of the output signal Vout, and the differential DC offset cancellation function. It is still another object of the present invention to provide a limiting amplifier architecture that greatly reduces the area of the layout. The present invention proposes a 'limiting limiting amplifier architecture, which is suitable for a Gaussian Frequency Shifter (Gaussian Frequency)
Keying)中。此限制放大器架構包括輸入級增益放大單元、 至少一中間級增盃放大單元與輸出級增益放大單元。上述 之輸入級增益放大單元包括輸人增益放A||與第 減及偏移取料路，其中，輸人增益放大器具有正輸I &、負輸入端、正輪出端與負輸出端，且第—自直壓 取消電路係轉接至輸入增益放大器之正輸入ς、負 輸入t正輸出端與負輸出端。上述之至少只 放大單元包括中間增益放大器與第 :、、曰: Γ名I山 具有正輸入端、負輸入端、正於㈣ 與負輸出端，且第_古、、幻+ A / 止W出鈿 直Μ偏壓電路係耦接至中間增益放大 7 1253230 ^ 5197twf.doc/e 器之正輸入端、負輸入端。上述之輸出級增益放 括輸出增益放大器與第二自直流偏壓及偏移取消電路，^ T，輸出增妓大器具有正輸人端、負輸人端、正輪出端 〃負輸出端’且第二自直流偏壓及偏移 =增益放大器之正輸入端、負輸入端、正輪 取消所述，上述之自直流偏壓及偏移 ^電路包糾-餘電路、第二餘電路、電容電路 中電路/述之第—電阻電路包括第—電; 心tirt 電晶體之源極端執接至輸入（出） 曰曰Γ放大 輸人端，第—電晶體之_端接地，且第二+ :=源極端_第一電晶體之汲極端，第二電晶體之： 中，ί述電阻電路包括第三電晶體與第四電晶體，其一 入端之源極端輪至輸入（出）增益放大器之負輪 弟一包日日體之閘極端接地，且第 / 至第三電綠找㈣，知t關之極㈣接 第十電ΪΠ電路包括第—電容、第二電容、第九電晶體盘 二:ΐ;二第第：之第-端係她至第二電晶體； 二電容之第一端如1一^係雛至第四電晶體之汲極端；第 端軸至第一電二電容之第曰 至地；第^九電晶體之基底”雜端與汲極端均轉接 第十電晶體之間極端墟至第二電容之第二端，第十ΐ 8 I253230 15i97twf.doc/g 晶體之基底、源極端與汲極端均耦接至地。 々上述之第三電阻電路包括第五電晶體與第六 中，第五電晶體之源極翻接至第二電容之第 曰_ : 體之間極端接地，且第六電晶體之源極端 五I二晶 至輸入（幻增益放大器之負輸出端I、电曰曰體之沒極端轉接 ^述之第四電阻電路包括第七電晶體與第 中，第七電晶體之源極端麵接至第二電容器之第二2第" 晶體之閘極端接地，且第人電晶體之源極端输至第七電 之沒極端’第人電晶體之難端接地，第 曰曰― 接至輸入（出）增益放大器之正輸出^體之沒極端輕 ^發明再提出—種限做Α||架構，其係適用於 斯頻移鍵控調變器中，其特徵在於在輸入級增益放夫印 與輸出級增益放大單元中分麻置第_ ^ 消電路，而在至少-中間級增益放 流偏壓電路。 卞υαϋ置呈 卿、ίί制放大器架構之輸人級與輸出級 二大早70中配置自直流偏壓及偏移取消電路，中間級 =放大單元中賊置直流偏壓電路，因此秘可同樣保 持限制放大器架構輸出之訊號的準確率，而且還可大大縮 減佈局之面積。 、° 為讓本發明之上述和其他目的、特徵和優點能更明顯 明如下y文特舉較佳實施例，並配合所關式，作詳細說 1253230 15197twf.doc/g 【實施方式】 請參照圖4,其係繪示依照本發明一較佳實施例的一 種限制放大器架構之電路圖。在本實施例中，僅以五級的 限制放大器架構400為例作說明，但實際上自當不以此為 限。 在圖4中，此限制放大為架構4〇〇包括兩個輸入級增 益放大單元402與404，兩個中間級增益放大單元4〇6與 φ 408，與輸出級增益放大單元410。而在輸入級增益放大單 元402至輸出級增盈放大單元41〇，在每個單元的正、負 輸入端均配置有阻絕電容412與414，以阻絕直流電壓。 輸入級增益放大單元402、404各自包括輸入增益放大 為422、426與自直流偏壓及偏移取消電路424、428。其 中，輸入增益放大器422、426具有正輸入端、負輸入端、 正輸出端與負輸出端，且由於本實施例係為舉例以負回授 的方式作偏移取消的動作，所以輸入增益放大器422、426 之負輸出端係藉由自直流偏壓及偏移取消電路424、428 籲耦接至輸入增盈放大器422、426之正輸入端，且輸入增益 放大為422、U6之正輸出端係藉由自直流偏壓及偏移取消 電路424、428耦接至輸入增益放大器422、426之負輸入 端。 、 在中間級增盈放大單元4〇6、4〇8方面，其 中間增益放大器430、434與直流偏壓電路4'32、436。1 中，中間增益放大器430、434具有正輸入端、負輸入端 正輸出端與負輸出端，且直流偏壓電路432、436係耦接至 1253230 i 5 197twf.doc/g 中則曾益放大器430、434之正輸入端、負輸入端。且直流 偏壓，路432、436係、為供給固定值之直流偏壓至中間增益 放大态430、434之正、負輸入端。 輸出級增益放大單元410各自包括輸出增益放大器 43 8與自直流偏壓及偏移取消電路44〇。苴 大請具有正輪入端'負輪入端、正輸出端二出輸;;放 且由於本實施例係為舉例以負回授的方式作偏移取消的動 ^，所以輸出增益放大ϋ 438之貞輸出端賴由自直流偏 魘及偏移取消電路440耦接至輸出增益放大器438之正輸 ^端，且輸出增益放大器438之正輸出端係藉由自直流偏 壓及偏移取消電路440耦接至輸出增益放大器438之負輸 入端。 ， 由於在以限制放大器對訊號作處理時，所需要特別注 思的疋先對輸入訊號Vin (差動直流電壓偏移）作調整,，一 以避免讯號偏移過多，而接著則是在要輸出訊號v〇m之 前’對其作調整以得到準確的輸出訊號V〇ut。 请繼續參照圖4’其動作原理為由輸入增益放大器422 之正、負輸入端接收輸入訊號Vin，且阻絕電容412與414 將阻絕輸入訊號Vin中之直流電壓。輸入增益放大器422 在對輸入訊號Vin作放大後輸出，而自直流偏壓及偏移取 消電路424則根據輸入增益放大器422之輸出直流偏壓， Φξ：供一直流偏壓給輸入增益放大器422，並以負回授消去 方式降低輸入增益放大器422所產生之偏移。依此類推， 在此限制器放大器架構400中，自直流偏壓及偏移取消電 11 1253230 15197twf.doc/g 路424、428與440係為分別根據輸入增益放大器422、426 與輸出增益放大器438之正、負輸出端所輸出之直流偏壓 的大小，決定供給至輸入增益放大器422、426與輸出增益 放大器438之正、負輸入端之直流偏壓的大小。而直流偏 壓電路432、436則為供給固定值（在設計時已預設）之直 流偏壓給中間增益放大器43〇、434。 而如表1與表2所示，本發明之限制放大器架構4〇〇Keying). The limiting amplifier architecture includes an input stage gain amplifying unit, at least one intermediate stage booster amplifying unit, and an output stage gain amplifying unit. The input gain amplifying unit comprises an input gain A|| and a minus and offset take-off path, wherein the input gain amplifier has a positive input I & a negative input terminal, a positive wheel output terminal and a negative output terminal And the first-self-direct voltage cancellation circuit is switched to the positive input ς of the input gain amplifier, the negative input t positive output terminal and the negative output terminal. The at least only amplifying unit includes an intermediate gain amplifier and a first:, 曰: ΓI I mountain has a positive input terminal, a negative input terminal, a positive (4) and a negative output terminal, and the first _ ancient, the illusion + A / stop W The output direct-bias bias circuit is coupled to the positive input terminal and the negative input terminal of the intermediate gain amplifier 7 1253230 ^ 5197twf.doc/e. The output stage gain described above includes an output gain amplifier and a second self-DC bias and offset cancel circuit, and the output booster has a positive input terminal, a negative input terminal, and a positive wheel output terminal. 'And the second self-DC bias and offset = the positive input terminal of the gain amplifier, the negative input terminal, the positive wheel cancellation, the above-mentioned self-DC bias voltage and offset ^ circuit package correction-remaining circuit, second residual circuit The circuit in the capacitor circuit / the first circuit - the resistance circuit includes the first - electric; the source of the heart of the fert transistor is connected to the input (out) 曰曰Γ amplifying the input end, the _ terminal of the first transistor is grounded, and Two + : = source terminal _ the first transistor 汲 extreme, the second transistor: in the middle, the ohmic circuit includes a third transistor and a fourth transistor, an input terminal of the input terminal to the input (out The negative pulsator of the gain amplifier is extremely grounded, and the third to the third electric green is found (four), and the fourth pole is connected to the fourth electric circuit, including the first capacitor, the second capacitor, and the first Nine crystal plate two: ΐ; two first: the first end of her to the second transistor; two capacitors The end is from the first to the fourth transistor to the extreme of the fourth transistor; the first end of the first to the first electric capacitance of the first to the ground; the second of the "those of the second crystal" is connected to the tenth The second end of the crystal to the second end of the second capacitor, the tenth I 8 I253230 15i97twf.doc / g crystal base, source and 汲 extreme are coupled to the ground. 々 The third resistor circuit includes the fifth In the crystal and the sixth, the source of the fifth transistor is flipped to the second drain of the second capacitor: the ground is extremely grounded, and the source of the sixth transistor is five I-diode to the input (the negative of the magic gain amplifier) The fourth resistor circuit of the output terminal I and the electric body is not connected to the fourth transistor, and the source of the seventh transistor and the seventh transistor is connected to the second 2nd crystal of the second capacitor. The gate is extremely grounded, and the source of the first transistor is extremely transmitted to the seventh power. The terminal of the first transistor is grounded, and the first output is connected to the positive output of the input (output) gain amplifier. Extremely light ^Invented again - the limit is Α|| architecture, which is suitable for the frequency shift keying modulator The utility model is characterized in that in the input stage gain-fed and output-stage gain amplifying unit, the _ ^ cancellation circuit is divided, and at least the intermediate-stage gain discharge bias circuit is used. The input and output stages are equipped with a DC bias and offset cancellation circuit in the early morning 70, and the middle level = the DC bias circuit in the amplification unit, so the secret can also maintain the accuracy of the signal output of the amplifier structure. The above and other objects, features and advantages of the present invention will become more apparent. The preferred embodiments of the present invention will be apparent from the following description. .doc/g [Embodiment] Please refer to FIG. 4, which is a circuit diagram of a limiting amplifier architecture in accordance with a preferred embodiment of the present invention. In the present embodiment, only the five-stage limiting amplifier architecture 400 is taken as an example, but in practice it is not limited thereto. In Fig. 4, this limitation is amplified to architecture 4, which includes two input stage gain amplification units 402 and 404, two intermediate stage gain amplification units 4〇6 and φ 408, and an output stage gain amplification unit 410. In the input stage gain amplifying unit 402 to the output stage gain amplifying unit 41, blocking capacitors 412 and 414 are disposed at the positive and negative input terminals of each unit to block the DC voltage. The input stage gain amplifying units 402, 404 each include an input gain amplification of 422, 426 and self-DC bias and offset cancellation circuits 424, 428. The input gain amplifiers 422 and 426 have a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. Since the embodiment is an example of a negative feedback method for offset cancellation, the input gain amplifier is used. The negative outputs of 422 and 426 are coupled to the positive input terminals of the input gain amplifiers 422 and 426 by the DC bias and offset cancel circuits 424 and 428, and the input gains are amplified to the positive outputs of 422 and U6. The negative input terminals of the input gain amplifiers 422, 426 are coupled by DC bias and offset cancellation circuits 424, 428. In the intermediate stage gain amplification unit 4〇6, 4〇8, the intermediate gain amplifiers 430, 434 and the DC bias circuits 4'32, 436. 1, the intermediate gain amplifiers 430, 434 have positive inputs, The positive input terminal and the negative output terminal of the negative input terminal, and the DC bias circuits 432, 436 are coupled to the positive input terminal and the negative input terminal of the amplifier 430, 434 in the 1253230 i 5 197twf.doc/g. And the DC bias, the path 432, 436 is the DC bias to supply a fixed value to the positive and negative inputs of the intermediate gain amplification states 430, 434. The output stage gain amplifying units 410 each include an output gain amplifier 43 8 and a self-DC bias and offset cancel circuit 44A.苴大请Please have the positive wheel input 'negative wheel input end, the positive output end two output;; and because this embodiment is an example of negative offset feedback offset cancellation action, so the output gain is amplified ϋ The output terminal of 438 is coupled to the positive output terminal of the output gain amplifier 438 by the DC bias and offset cancellation circuit 440, and the positive output of the output gain amplifier 438 is cancelled by the DC bias and offset. Circuit 440 is coupled to the negative input of output gain amplifier 438. Since the input signal Vin (differential DC voltage offset) is adjusted before the signal is processed by the limiting amplifier, one avoids excessive signal offset, and then To output the signal v〇m before 'adjust it to get the accurate output signal V〇ut. Referring to FIG. 4', the operation principle is that the input signal Vin is received by the positive and negative inputs of the input gain amplifier 422, and the blocking capacitors 412 and 414 block the DC voltage in the input signal Vin. The input gain amplifier 422 is output after amplifying the input signal Vin, and the self-DC bias and offset cancel circuit 424 is based on the output DC bias of the input gain amplifier 422, Φξ: for the DC bias to the input gain amplifier 422, The offset generated by the input gain amplifier 422 is reduced in a negative feedback cancellation mode. And so on, in the limiter amplifier architecture 400, the self-DC bias and offset cancellation power 11 1253230 15197 twf.doc / g channels 424, 428 and 440 are based on the input gain amplifiers 422, 426 and the output gain amplifier 438, respectively. The magnitude of the DC bias output at the positive and negative outputs determines the magnitude of the DC bias applied to the positive and negative inputs of the input gain amplifiers 422, 426 and output gain amplifier 438. The DC bias circuits 432, 436 supply a DC bias to the intermediate gain amplifiers 43A, 434 for a fixed value (preset at design time). As shown in Table 1 and Table 2, the limiting amplifier architecture of the present invention is 4〇〇
可達到與習知技術（如圖3所示之限制放大器架構3〇〇) 同樣的準確率。 表 交流分析 ------- TSMC (習 知） SMCI (習 知） TSMC (本 發明） SMIC (本 發明） 增益（dB) 1———-__ 87.35 ---—-— 87.49 84.06 86.57 f3db lpf (KHz) 75.82 79.725 188.96 246.02 一 f3db hpf (KHz) ——-~_ 14.77 16.3759 14.95 14.89 頻 寬 (MHz) —~~~—— 14.69 16.30 14.76 14.64 整體延遲 (ns) ----— -------- 31.98 30.88 35.76 42.53 —— ----—-_ ’就父流分析而言 可以得到與圖3同樣的增益效果 通過之頻率範圍。 可以看到以圖4之架構 且還可增加放大器所能 1253230 15197twf.doc/g 表2 直流分析 TSMC (習 知） SMCI (習 知） TSMC (本 發明） SMIC (本 發明） 電流（// Α) 597.332 620.516 667.949 663.531 工作電壓 2.75 V 2.75 2.75 2.75 2.75 功 率 (mW) 1.642663 1.706419 1.83685975 1.82471025 V175 1.76053 1.75422 1.7603 1.7542 如表2所示，就直流分析而言，本發明之架構同樣可 達到圖3之功率。The same accuracy can be achieved as the conventional technique (the limiting amplifier architecture shown in Figure 3). Table AC Analysis ------- TSMC (General) SMCI (General) TSMC (Invention) SMIC (Invention) Gain (dB) 1———-__ 87.35 ------ 87.49 84.06 86.57 F3db lpf (KHz) 75.82 79.725 188.96 246.02 A f3db hpf (KHz) ——-~_ 14.77 16.3759 14.95 14.89 Bandwidth (MHz) —~~~—— 14.69 16.30 14.76 14.64 Overall delay (ns) ----- ------- 31.98 30.88 35.76 42.53 —— ------_ 'For the parent flow analysis, the same frequency range as the gain effect of Figure 3 can be obtained. It can be seen that the structure of Figure 4 can also be increased by the amplifier. 1253230 15197twf.doc/g Table 2 DC Analysis TSMC (General) SMCI (General) TSMC (Invention) SMIC (Invention) Current (// Α 597.332 620.516 667.949 663.531 Operating voltage 2.75 V 2.75 2.75 2.75 2.75 Power (mW) 1.642663 1.706419 1.83685975 1.82471025 V175 1.76053 1.75422 1.7603 1.7542 As shown in Table 2, the architecture of the present invention can also achieve the power of Figure 3 for DC analysis.
请接著參照圖5，其係繪示依照本發明一較佳實施例 的一種自直流偏壓之電路示意圖。此自直流偏壓及偏移联 消電路500包括第一電阻電路502、第二電阻電路5〇4、電 谷電路506、第三電阻電路508與第四電阻電路51〇。 此弟一 電阻電路502包括第一電晶體T1與第二冤晶 體=2。其中’第-電晶體T1之源極端係、為耗接至增益故 大器之正輸人端’第-⑼日體T1之閘極端接地，且第二 電晶體T2之源極端祕至第—電晶體T1之没極端一 電晶體T2之閘極端接地。 =二電阻電路5〇4包括第三電晶體了3 T4。其中，第三電晶體T3心原極 曰體 益放大器之負輸入端，第三電 1 =(出）增 曰曰粒13之閘極端接地，且 13 I253230 15 197twf.doc/g ^四電晶體T4之源極端祕至第三電晶體T3之汲極端， 第四電晶體T4之閘極端接地。 電谷電路506包括第一電容α、第二電容C2、 ，晶體T9與第十電晶體T1()。其中，第—電容α之第— ^係耗接至第二電晶體T2之汲極端，第—電容α之第二 、係輕接至第四電晶體T4之汲極端。第二電容C2之第— =雛至第-電容〇之第—端，第二電容〇之第二端 耦】第一電容C1之第二端。第九電晶體τ9之閘極端 梅她d、第—電容C2之第二端，第九電晶體T9之基底、源 :乂、及，端均输至地。第十電晶體tig之閘極端輕接 端谷C2之第一端，第十電晶體T1〇之基底、源極 i^與及極端均輕接至地。Please refer to FIG. 5, which is a schematic diagram of a circuit from a DC bias voltage in accordance with a preferred embodiment of the present invention. The self-DC bias and offset cancellation circuit 500 includes a first resistor circuit 502, a second resistor circuit 5〇4, a valley circuit 506, a third resistor circuit 508, and a fourth resistor circuit 51A. The resistor-resistive circuit 502 includes a first transistor T1 and a second transistor = 2. Among them, the source of the first-transistor T1 is the terminal of the positive-transistor terminal of the gain-to-gain, and the gate of the second-body T1 is extremely grounded, and the source of the second transistor T2 is extremely secretive. The gate of the transistor T1 is not extremely connected to the gate of the transistor T2. The second resistance circuit 5〇4 includes the third transistor 3 T4. Wherein, the third transistor T3 is a negative input terminal of the cardioid pole amplifier, the third electric 1 = (out) is increased by the gate of the thirteenth electrode, and the terminal is grounded, and 13 I253230 15 197twf.doc / g ^ four crystal The source of T4 is extremely secretive to the extreme of the third transistor T3, and the gate of the fourth transistor T4 is extremely grounded. The electric valley circuit 506 includes a first capacitance α, a second capacitance C2, a crystal T9, and a tenth transistor T1(). Wherein, the first portion of the first capacitor α is consumed to the 汲 terminal of the second transistor T2, and the second portion of the first capacitor α is lightly connected to the 汲 terminal of the fourth transistor T4. The second capacitor C2 is - the first end of the first capacitor 耦, and the second end of the second capacitor 耦 is coupled to the second end of the first capacitor C1. The gate terminal of the ninth transistor τ9 is the second end of the first capacitor C2, the base of the ninth transistor T9, and the source: 乂, and, the ends are all sent to the ground. The gate of the tenth transistor tig is extremely lightly connected to the first end of the end valley C2, and the base, the source, and the extreme of the tenth transistor T1 are lightly connected to the ground.
ThU二ί阻電路508包括第五電晶體T5與第六電晶體 二，第五電晶體Τ5之源極端♦馬接至第二電容c2之第二 體Τ5之閘極端接地，且第六電晶體Τ6之源極端 :接^弟五電晶體Τ5之汲極端，第六電晶體Τβ之閘極端接 電晶體Τ6之卿啦輸入(⑽ 盆中第=電阻包路510包括第七電晶體17與第八電晶體Τ8。 二 七電晶體Τ7之源極端轉接至第二電容器C2之第二 叙拉5 =日日體17之閘極端接地，且第人電晶體T8之源極端 地 七電晶體17之汲極端，第八電晶體Τ8之閘極端接 正輸^電晶體Τ8找極端域至輸人⑻增益放大器之 1253230 !5197twf.doc/g 在本發明之較佳實施例中，如熟悉此技藝可以輕易知曉， 如第九電晶體T9與第十電晶體T10的耗接方式，可以讓第九 電晶體T9與第十電晶體T10當作一電容（M0SC)來使用，而 弟一電晶體T1至弟八電晶體T8，則可使其當作一電阻(m〇S R) 來使用。The ThU ohmic resistance circuit 508 includes a fifth transistor T5 and a sixth transistor 2, the source terminal of the fifth transistor Τ5 is connected to the gate terminal of the second body Τ5 of the second capacitor c2, and the sixth transistor is grounded. The source of Τ6 is extreme: the 汲 弟 五 电 电 电 汲 , , , , 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六 第六Eight transistor Τ 8. The source of the Erqi transistor Τ7 is extremely switched to the second capacitor C2, the second Syrah 5 = the gate of the solar body 17 is extremely grounded, and the source of the first transistor T8 is extremely seven transistors 17 At the extreme, the gate of the eighth transistor Τ8 is connected to the positive transistor Τ8 to find the extreme domain to the input (8) gain amplifier 1253230 !5197 twf.doc / g in the preferred embodiment of the invention, as familiar with the art It can be easily known that the ninth transistor T9 and the tenth transistor T10 can be used as a capacitor (M0SC), and the transistor T1 can be used as the capacitor of the ninth transistor T9 and the tenth transistor T10. To the eight transistor T8, it can be used as a resistor (m〇SR).
在本實施例中，由於電晶體之面積很小，故自直流偏壓及 偏移取消電路500以第一電晶體T1至第八電晶體T8來當成電 障使用，以第九電晶體T9與第十電晶體T10當作電容使用的 結果，可以比習知以被動的電阻與電容所形成之電路來的小很 多。 在本發明之較佳實施例中，如熟悉此技藝可以輕易知曉， 第-電晶體T1至第十電晶體T10可以是p型金屬氧化物半導 體但不以此為限。 綜上所述，本發明之限制放大器架構，可僅於接收輸 入訊號Vin的前幾級增益放大器與最後要輸出訊號的幾： 增益放大器配置自直流偏壓及偏移取消電路，以使輸出訊 號Vout的準確率很高，且也同時縮小了佈局的面積。而 且，以购“與驗^。取代了傳統的被動元件，f 大減少佈局的面積。 雖然本發明已以較佳實施例揭露如上，然其 限定本發明，任何熟習此技藝者，在不脫離本發 和範圍内’當可作些許之更動與潤飾，因此本發明之= 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 15 1253230 1 5197twf.doc/g 圖1係習知一種限制放大器架構之電路圖。 圖2A係習知一種配置直流偏壓電路之限制放大器的 電路不意圖。 ^ 圖2B係習知一種配置自直流偏壓及偏移取消電路之 限制放大器的電路示意圖。 圖3係習知一種閉迴路限制放大器架構的電路圖。 圖4繪示依照本發明一較佳實施例的一種限制放大器 架構之電路圖。 圖5繪示依照本發明一較佳實施例的一種自直流偏壓 之電路示意圖。 【主要元件符號說明】 100、400 :限制放大器架構 102、202、302 ··增益放大器 104 :偏移取消電路 ‘ 204、432、436 :直流偏壓電路 206、208、306、308、412、414 :阻絕電容 210、304 :自直流偏壓及偏移取消電路 300 :閉迴路限制放大器架構 402、404 :輸入級增益放大單元 406、408 :中間級增益放大單元 410 :輸出級增益放大單元 422、426 ·•輸入增益放大器 424、428、440、500 :自直流偏壓及偏移取消電路 430、434 :中間增益放大器 16 1253230 15197twf.doc/g 438 ： 502 ： 504 ： 506 ： 508 ： 510 ： 輸出增益放大器 第一電阻電路 第二電阻電路 電容電路 第三電阻電路 第四電阻電路In this embodiment, since the area of the transistor is small, the DC bias and offset cancel circuit 500 is used as the electrical barrier from the first transistor T1 to the eighth transistor T8, and the ninth transistor T9 is used. As a result of the use of the tenth transistor T10 as a capacitor, it can be much smaller than the circuit formed by passive resistors and capacitors. In the preferred embodiment of the present invention, as is well known in the art, the first to tenth transistors T1 to T10 may be p-type metal oxide semiconductors, but not limited thereto. In summary, the limiting amplifier architecture of the present invention can only receive the first few gain amplifiers of the input signal Vin and the last few output signals: the gain amplifier is configured from the DC bias and offset cancellation circuit to make the output signal Vout's accuracy is high, and it also reduces the size of the layout. Moreover, the purchase of "and the test" replaces the conventional passive component, f greatly reduces the area of the layout. Although the invention has been disclosed above in the preferred embodiment, which defines the invention, anyone skilled in the art will not In the context of the present invention, the scope of the invention is defined by the scope of the appended claims. [Illustration of the drawings] 15 1253230 1 5197twf.doc/g 1 is a circuit diagram of a limiting amplifier architecture. Figure 2A is a schematic diagram of a circuit for limiting a limiting amplifier of a DC bias circuit. Figure 2B is a conventional limitation of a configuration of a DC bias and offset cancellation circuit. Figure 3 is a circuit diagram of a closed-loop limiting amplifier architecture. Figure 4 is a circuit diagram of a limiting amplifier architecture in accordance with a preferred embodiment of the present invention. Figure 5 illustrates a preferred embodiment of the present invention. A schematic diagram of a self-DC bias circuit. [Main component symbol description] 100, 400: Limiting amplifier architecture 102, 202, 302 · Gain amplifier 104: Offset Cancellation circuit '204, 432, 436: DC bias circuit 206, 208, 306, 308, 412, 414: blocking capacitance 210, 304: self-DC bias and offset cancellation circuit 300: closed loop limiting amplifier architecture 402, 404: input stage gain amplifying unit 406, 408: intermediate stage gain amplifying unit 410: output stage gain amplifying unit 422, 426 · • input gain amplifier 424, 428, 440, 500: self-DC bias and offset cancel circuit 430, 434: intermediate gain amplifier 16 1253230 15197twf.doc/g 438 : 502 : 504 : 506 : 508 : 510 : output gain amplifier first resistance circuit second resistance circuit capacitance circuit third resistance circuit fourth resistance circuit
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