TWI253146B - Structure of word line in split gate flash memory cell and method for manufacturing the same - Google Patents

Abstract

A structure of a word line in a split gate flash memory cell and a method for manufacturing are disclosed. In the method, a gate structure of a split gate flash memory cell is provided, wherein a material layer of a word line is formed on the gate structure. A cap layer is formed on the material layer of the word line. Then, a portion of the cap layer and a portion of the material layer of the word line are removed by using a chemical mechanical polishing (CMP) technique. After an oxide layer is formed on the exposed material layer of the word line, the remaining cap layer and the material layer of the word line beneath the remaining cap layer are removed, so as to form a box-shape word line in the split gate flash memory cell.

Description

1253146 Case No. 92117328_年月日日 Revision__ V. Description of the Invention (1) Technical Field of the Invention The present invention relates to a character of a split gate flash memory cell (Split Gate Flash Memory Cell) Word Line and its manufacturing method, and in particular, a method for fabricating a box-shaped word line of a split gate flash memory cell using chemical mechanical polishing (CMP) techniques. [Prior Art] In the flash memory device, the split gate flash memory device is smaller in size and more power-saving than the stacked gate flash memory device. Therefore, the current separation of flash memory has become a very popular memory component. In the split gate flash memory, the polysilicon spacer is usually used as a word line to reduce the size of the split gate flash memory. Referring to Figures 1 through 7, the first to seventh drawings illustrate a process cross-section of a conventional word line for separating a gate flash memory cell. First, an oxide layer 1 〇 2, a double-crystallized layer 1 0 4 , and a nitride layer 1 0 6 are sequentially stacked on a substrate 10 of a semiconductor. Among them, the oxide layer 1 〇 2 and the polysilicon layer 1 〇 4 are used to form a material layer of a floating gate. The nitriding layer 1 〇 6 and the polysilicon layer 1 0 4 are defined by a lithography and etching process, and a portion of the nitride layer 1 0 6 and a portion of the eutectic layer 1 〇 4 are removed to form an opening 1 〇 8 And provide an area for making part of the memory gate element. Wherein, the opening 1 〇 8 does not expose the oxide layer 1 〇 2, and the sidewall of the opening 1 0 8 in the region of the polycrystalline germanium layer 104 is inclined to form a groove-like structure, as shown in FIG. 1 . Show. After the opening 108 is formed, a tantalum nitride spacer 1 〇 9 is formed on the sidewall of the opening 1 〇 8 by deposition and etch back. A yttrium oxide gap is also formed on the tantalum nitride spacer 1 〇 9 in the opening 1 0 by means of deposition and etch back.

Page 6 1253146 _ Case No. 92117328_生_^_Θ_Correct_5. Description of the invention (2) Wall 1 1 0, the structure formed is shown in Figure 2. After completing the yttrium oxide spacer 110, the eutectic lanthanum layer 104 exposed in the opening 108 is removed by a lithography and etching process to expose a portion of the oxide layer 102. Next, a yttrium oxide spacer 1 1 4 is formed while removing the exposed oxide layer 10 2 in the opening, thereby exposing a portion of the substrate 100. At this time, the substrate 10 0 ion implantation step exposed in the opening 1 0 8 is performed to form the source 1 1 2 in the substrate 100, as shown in Fig. 3. After the source 1 1 2 is formed, the polycrystalline germanium layer 1 1 6 is filled in the opening 1 0 8 by deposition, wherein the polycrystalline germanium layer 1 16 covers the exposed substrate 100, yttrium oxide. The spacer 1 14 and a portion of the yttrium oxide spacer 1 10 are in contact with the source 1 1 2 . Next, the excess ruthenium layer 161 is removed again by etchback to leave only the ruthenium layer 161 in the opening 108 and a portion of the yttrium oxide spacer 1 1 0 is exposed. At this point, the internal wiring of the source 112 of the flash memory has been completed. Thereafter, the surface of the polycrystalline germanium layer 1 16 is oxidized by thermal oxidation to form an oxide layer 1 18 on the surface of the polycrystalline germanium layer 116. After the oxide layer 1 18 is formed, the remaining nitride layer 106, the portion of the germanium layer 104, the portion of the oxide layer 102, and the tantalum nitride spacer 10, 9 are removed to form a separation. The gate structure of the gate flash memory cell is 20, as shown in Fig. 4. Then, an oxide layer 12 2 is first deposited by deposition to cover the gate structure 1 2 0 and the substrate 1 0 0, and then a polycrystalline germanium layer 12 4 is deposited by deposition to cover the oxide layer 12 2, and A structure as shown in Fig. 5 is formed. Next, the polysilicon layer 1 2 4 is covered with an oxide layer 122, wherein the oxide layer 126 is used as a sacrificial mask for subsequent spacer etching, and the structure is as shown in FIG. .

1253146 __Case No. 92117328_Yearly 曰 _ _ _, invention description (3) At this point, you can start to create the word line of the split gate flash memory component, first carry out the breakthrough (Break Through) #刻 steps A portion of the oxide layer 1 2 6 is removed, but a portion of the oxide layer 1 26 remains in the side of the sidewall of the polysilicon layer 14 . Then, an etch back step is performed to remove a portion of the oxide layer 1 26 and a portion of the germanium layer 1 2 4 to form a polysilicon spacer 1 2 8 adjacent to the gate structure 120. Wherein, the formed polysilicon spacer 1 2 8 is a character line of the separated gate flash memory cell 130. Due to the interaction between the structure of the gate structure 120 and the oxide layer 126 and the etch back, a recessed region 13 2 is formed on the surface of the formed polysilicon spacer 1 28, and further A fence-like structure 1 3 4 is formed on the stone eve spacer 1 2 8 . [Summary of the Invention] Therefore, the word character can be used to make the machine layer of the present invention, and the wire type is another method for forming the line material of the element line of the present invention, and the material layer is mechanically ground, and the structure is further structured. The purpose of the word is to form a layer on the method, the purpose is to adjust the mechanical response, not only beneficial to the yuan line. It is mentioned that the cover layer can be used to provide chemical force, and can be smoothly removed to provide more than one type of character in the word, and then obtained by a kind of mechanical grinding and the word flat material layer formed by the word flattening. This is a word line of a flat structure using chemical mechanical polishing techniques. Deviating the parameters of the process of the gate flash memory cell to enhance the coverage on the 70-line material layer over the word line material layer of the gate structure, thereby fabricating the word line according to the present invention in accordance with the present invention The above-described manufacturing method of the cell word line. In a preferred embodiment of the manufacturing method, an example is provided. The present invention includes at least a step of separating the gates from the gate: the first flash 5 memorabilia cell flash memory crystal

1253146 _ Case No. 92117328_年月日日_ifi_ V. Description of the invention (4) A substrate in which one of the gate structures of the split gate flash memory cell has been formed on a portion of the substrate, and the gate structure is The sidewall of the spacer includes at least a spacer, wherein the material of the spacer may be ruthenium oxide. A dielectric layer is formed on the gate structure and the substrate, and the material of the dielectric layer may be ruthenium oxide. Next, a conductive layer is formed on the dielectric layer, and the material of the conductive layer is preferably a germanium. After the conductive layer is formed, a cover layer is formed on the conductive layer, and the material of the cover layer is preferably tantalum nitride. Then, a planarization step is performed by chemical mechanical polishing until the above-mentioned spacers are exposed. At this time, the cover layer remaining after the planarization step and the conductive layer under the cover layer are removed, that is, the square structure word line separating the gate flash memory cells is completed. According to the above object of the present invention, a word line structure for separating a gate flash memory cell is provided, comprising at least: a gate structure of a split gate flash memory cell is located on a substrate; and a spacer spacer Located on one of the side walls of the gate structure described above. By increasing the mechanical stress of the CMP process and by appropriately adjusting the thickness of the overlay, it is quite easy to obtain a word line structure with vertical sidewalls, and the critical dimensions of the memory elements can be effectively controlled. Furthermore, since the word line material layer is subjected to the planarization step, the remaining word line material layer has a flat surface, so that no barrier-like structure is formed on the word line. In this way, not only can the electrical quality of the memory component be greatly improved, but the process yield can be improved. [Embodiment] In view of the above-described conventional method of manufacturing a word line for separating a gate flash memory cell by etching, it is difficult to effectively control the critical size of the memory cell, and

1253146 _ Case No. 92117328_年月日日__ V. Description of invention (5) As a spacer of the word line, a square structure cannot be formed, and a fence-like structure is often formed on the gap wall, which seriously affects the memory cell. Electrical quality and process reliability. Therefore, the present invention discloses a word line for separating a gate flash memory cell and a manufacturing method thereof. In addition to effectively controlling the critical size of the memory cell, the word line of the square structure can be formed smoothly. In order to make the description of the present invention more detailed and complete, reference is made to the following description in conjunction with the drawings of Figs. 8 to 15. Referring to FIGS. 8 to 15 , FIGS. 8 to 15 are schematic cross-sectional views showing a process of separating a word line of a gate flash memory cell in accordance with a preferred embodiment of the present invention. First, a gate dielectric layer 220 is formed on the substrate of the semiconductor by using, for example, thermal oxidation, wherein the material of the gate dielectric layer 220 can be, for example, hafnium oxide or the like. The conductive layer 204 is formed by, for example, chemical vapor deposition (CVD), wherein the material of the conductive layer 204 is preferably a germanium. The gate dielectric layer 220 and the conductive layer 204 are provided as a material layer for forming a floating gate. Next, a nitride layer 220 is formed on the conductive layer 220 by, for example, chemical vapor deposition. After the formation of the nitride layer 206, the definition step is performed by, for example, lithography and an etching process to remove a portion of the nitride layer 206 and a portion of the conductive layer 204, but does not expose the gate dielectric layer 202. An opening 208 is formed in the nitride layer 206 and the conductive layer 204. Wherein, the opening 208 is used to provide a portion of the memory gate element of the fabrication portion, and the sidewall of the opening 208 in the region of the conductive layer 204 is inclined, as shown in FIG. After the opening 20 8 is formed, a dielectric film (only the spacer 2 1 0 is shown) is conformally deposited over the nitride layer 2 0 6 and the opening 2 0 8

Page 10 Amendment

1253146 A ___ Case No. 92117328 V. Description of the Invention (6) The exposed conductive layer 204, wherein the material of the dielectric film can be, for example, tantalum nitride. A portion of the dielectric film is removed by, for example, etch back, and a spacer 2 1 形成 is formed on the sidewall of the opening 206. Next, another dielectric film (only the spacer 2 1 2 is shown) is deposited in the nitride layer by, for example, chemical vapor deposition and using, for example, tetraethyloxane (TEOS) as a raw material. 2 0 6. The spacer 2 1 〇 and the exposed conductive layer 2 〇 4 . The material of the other dielectric film may be, for example, cerium oxide. A portion of the other dielectric film is removed by etching back, and a spacer 212 is formed on the spacer 210 in the case of 208, as shown in FIG. After the formation of the port spacers 2 1 2, the exposed conductive layer 204 in the opening 20 is removed by, for example, lithography and etching to expose the underlying gate dielectric layer 2 0 2 . Next, the U-shaped dielectric film (only the spacer 214 is shown) is covered by the vapor deposition dielectric film (only the spacer 214 is shown) to be exposed in the nitriding layer, the spacer 2, 2, and the opening 208. Gate dielectric layer 2〇2. The material of the I 铭ί i ? thin ί is preferably yttrium oxide. Re-etching the etchback, the second film, and simultaneously removing the closed 2 1^ exposed in the opening 206, and forming a spacer on the side wall of the portion of the gap 2 2 2 The substrate of the distribution is 2〇〇. The substrate 20 0 is subjected to ion implantation step 2 2 8 8 8 24 24 24 24 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Shown. Then 'using, for example, /f k k Α 、 、 、 、 ; ; ; ; ; ; = = = = 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电The material of the layer is preferably; ===." 'This conductive part of the conductive 厣?! sw reuses, for example, etch back technology, shifts __曰, and only retains the conductive material located in the opening 2 〇8

Page 11 1253146 _ Case No. 92117328_ _ _ _ _ 5, invention description (7) layer, and in the opening 208 form a conductive layer 2 1 8 in contact with the source 2 16 to facilitate rapid planting The internal connection of the source of the flash memory 2 1 6 . Wherein, the conductive layer 2 18 covers the exposed substrate 200, the spacer 2 1 4, and a portion of the gap 2 1 2 . After the formation of the conductive layer 2 18 , the surface of the conductive layer 218 is oxidized by, for example, thermal oxidation, and the oxide layer 220 is formed on the surface of the conductive layer 218. After the oxide layer 220 is formed on the surface of the conductive layer 2 18 , the remaining nitride layer 206, a portion of the conductive layer 204, a portion of the gate dielectric layer 220, and the spacer 2 1 0 are removed. After forming the gate structure 2 2 2 ° as shown in FIG. 1 2, after completing the gate structure 2 2 2, a thin dielectric layer is formed by, for example, chemical vapor deposition, and the gate structure 2 is covered. 2 2 and the substrate 200, wherein the material of the dielectric layer 224 is preferably yttrium oxide. A thick conductive layer 226 is formed on the dielectric layer 224 by, for example, chemical vapor deposition. The material of the conductive layer 226 is preferably a germanium. Then, using a chemical vapor deposition technique or a low pressure chemical vapor deposition (LPC VD) technique, a cap layer 2 2 8 is formed on the conductive layer 2 26 to facilitate the subsequent planarization step, and the formed structure is as follows. Figure 1 2 shows. The material of the cover layer 2 28 is preferably tantalum nitride, and the thickness of the cover layer 2 28 is preferably controlled between 600 and 1800. After the cap layer 2 28 is formed, the structure of Fig. 2 is planarized by, for example, a chemical mechanical polishing process until the spacers 2 1 2 are exposed. In the above planarization step, a portion of the cap layer 228, a portion of the conductive layer 226, a portion of the dielectric layer 2 24, and a portion of the spacer 2 1 2 are removed to form a structure as shown in FIG. . Among them, there may be a part of the dielectric layer 2 2 4 remaining on the oxide layer 220. When performing the above chemical mechanical polishing process, it is preferred to

Page 12 1253146 Case No. 92117328_± Amendment 5, Invention Description (8) Use a hard abrasive pad, and preferably control the downforce between 2 psi and 5 psi, and grind the platform The rotation rate is controlled between 50 rpm and 100 rpm, and the rotation rate of the polishing head is controlled between 50 rpm and 100 rpm. One of the features of the present invention is to increase the mechanical stress of the chemical mechanical polishing by controlling the number of processes of the chemical mechanical polishing process, and to effectively adjust the grinding of the abrasive structure having different patterns (such as the structure shown in FIG. 2). rate. With a suitable thickness of the cover layer 2 2 8, a conductive layer 2 2 6 having a flat surface can be formed smoothly along the gate structure 2 2 2 to facilitate the fabrication of the subsequent square word line. Then, for example, a heat treatment step is performed. Thereby, an oxide layer 230 is formed on the exposed surface of the conductive layer 2 26 to form a structure as shown in FIG. Preferably, the thickness of the oxide layer 230 is controlled to be greater than 2 〇 〇 A. In addition, the cover layer 2 28 material is selected such that its etch rate is different from the oxide layer 2 3 面. Thus, after the oxide layer 2 30 is formed, the residual cap layer 22 8 and the cap layer 22 8 can be removed by using, for example, an etching method and using the difference in etching rate between the oxide layer 230 and the cap layer 2 28 . The conductive layer 226 underneath. Thus, a gap wall 2 3 2 having a square structure can be formed beside the side wall of the gate structure 2 2 2 as a word line for separating the gate flash memory cell 234. The etching technique employed to remove the residual cap layer 22 8 and the underlying cap layer 22 8 is preferably an anisotropic Etching. It will be apparent from the preferred embodiment of the present invention that a character line structure having a flat surface can be provided by regulating the number of slabs of the flattening step and by incorporating an additional cover layer. Therefore, the application of the present invention can avoid the edge of the word line

Page 131253146 _ Case No. 92117328_年月日日__ V. Description of invention (9) Now fence-like structure, which can prevent electrical short circuit and particle pollution caused by the collapse of the fence-like structure on the edge of the word line To achieve the goal of improving process yield and product reliability. It can be seen from the above preferred embodiment of the present invention that, compared with the conventional use of etching technology to form word lines, the present invention can not only easily obtain a character line structure having vertical sidewalls, but also can smoothly obtain a square structure. The word line. Therefore, the critical size of the split gate flash memory cell can be easily controlled, and the process reliability is good.

Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Page 141253146 _ Case No. 92117328_年月日日_«_ Simple description of the drawing [Simple description of the drawing] Figures 1 to 7 show the character line of the conventional separation gate flash memory cell Process profile. 8 through 15 are cross-sectional views showing a process of separating the word lines of the gate flash memory cell in accordance with a preferred embodiment of the present invention. [Simplified description of component symbol]

1 0 0 : substrate 1 0 2 : oxide layer 1 0 4 : polysilicon layer 1 0 6 : nitride layer 1 0 8 ·· opening

1 0 9 : tantalum nitride spacer 1 1 0 : yttrium oxide spacer 1 1 2 : source 1 1 4 : yttrium oxide spacer 1 1 6 : polysilicon layer 1 1 8 : oxide layer 1 2 0 : gate Pole structure 1 2 2 : oxide layer 1 2 4 : polycrystalline germanium layer 1 2 6 : oxide layer 1 2 8 : polycrystalline germanium spacer 1 3 0 : separation gate flash memory cell 1 3 2 : recessed region

Page 151253146 _ Case No. 92117328_ Year and Moon Correction Schematic Brief Description 1 3 4 : Fence-like structure 2 0 0 : Substrate 2 0 2 : Gate dielectric layer 2 0 4 : Conductive layer 2 0 6 : Nitrogen Layer 2 0 8 : opening 2 1 0 : spacer 2 1 2 : spacer 2 1 4 : spacer 2 1 6 : source 218: conductive layer 2 2 0 : oxide layer 2 2 2 : gate structure 2 24 : dielectric layer 2 2 6 : conductive layer 2 2 8 : cover layer 2 3 0 : oxide layer 2 3 2 : spacer 2 3 4 : separation gate flash memory cell

Page 16

Claims (1)

1253146 _ Case No. 92117328_^^_Θ_Correction 6. Applying the scope of the patent to the line of the Yuan Dynasty, the cell crystal recalls the ancient mouth flash fast pole gate 0, the kind of pole seal gate is less to the wall, the side is shaped The structure has a few poles to the gate and the base, and the junction of the structure is divided into a pole, the cell; the material crystal wall: the base space includes a space for the flash to provide a small amount of the base material. ( ; ; The upper layer of the upper layer is electrically shielded to guide the Hai Hai in the bit position ^ The electric cover is used to cover the layered oxygen of the forming shape; the stop is the wall, The electrical layer of the upper layer of the gap exposes the storm to the direct exposure step, and the conductive layer conducts the flattened oxygen into the conductive layer and the layer is covered by the lower layer. And the cover layer covers the cell crystal of the line element which is covered by the same residual rate, and is cut into the special line. In the middle of the item, the first paragraph, the law I · 彳方3 words The crystal of the crystal. The memory of the smashing flash is fast for the layering of the material. The middle of the Μ Μ 第 ί ί ί ί - 方 ί 线 线 线 线 线 线 线 线 线 线 线Please refer to the cell crystal of the line element made by the French side. Recalling the ruin of the crystal, the crystallization of the material is the stratification of the material slab. The middle of the cell is the crystal of the cell. The basics of the pole gates - ▲ Page 17 1253146 _ Case No. 92117328_年月日日__ VI. Patent Application Scope The manufacturing method of the word line, wherein the material of the cover layer is tantalum nitride. 6. The method of fabricating a word line of a split gate flash memory cell according to claim 1, wherein the thickness of the cover layer is between 600 and 180. 7. The method of fabricating a word line of a split gate flash memory cell according to claim 1, wherein the planarizing step is a chemical mechanical polishing step. 8. The method of manufacturing the word line of the split gate flash memory cell according to claim 7, wherein the chemical mechanical polishing step comprises at least: using a hard polishing pad; controlling the pressure to be 2 psi Between 5 psi; controlling the rotation rate of a grinding platform between 50 rpm and 100 rpm; and controlling the rotation rate of a polishing head between 50 rpm and 100 rpm. 9. The method of fabricating a word line of a split gate flash memory cell according to claim 1, wherein the oxide layer has a thickness greater than 200 Å. A method of manufacturing a word line of a split gate flash memory cell according to claim 1, wherein the step of forming the oxide layer is a heat treatment step. Page 18 1253146 _ Case No. 92117328_年月日日__ VI. Patent Application Range 1 1. A method for manufacturing a word line of a split gate flash memory cell as described in claim 1 of the patent application, wherein The remaining cover layer and the step of the conductive layer under the cover layer utilize an anisotropic etch. 1 2. The method for manufacturing a word line of a split gate flash memory cell according to claim 1, wherein the gate structure comprises at least: a source is located in the substrate; The layer is on the substrate, and each of the gate oxide layers is located on a portion of the source; the second conductive film is respectively located on a portion of the gate oxide layers; and the second first oxide spacers are respectively located On the first conductive film; the second yttria spacers are respectively located on the gate oxide layers of the other portion and the sidewalls of the first yttrium oxide spacers; and the second conductive film is located at the source of the other portion And the first yttria spacers and the second yttria spacers; and an oxidized film is disposed on the second conductive film. 1 — A method for fabricating a word line for separating a gate flash memory cell, comprising at least: providing a substrate, wherein a portion of the substrate has at least one of the separated gate flash memory cells formed a gate structure, and a sidewall of the gate structure includes at least a spacer; a first oxide layer is formed on the gate structure and the substrate; 1253146 _ Case No. 92117328_年月日日__ Sixth, the patent application scope forms a polycrystalline spine layer on the oxide layer; a cover layer is formed on the polycrystalline germanium layer; a chemical mechanical polishing step is performed until exposed Forming a second oxide layer on the exposed polysilicon layer, wherein an etching rate of the second oxide layer is different from an etching rate of the cap layer; and removing the remaining cap layer and the capping layer The polycrystalline germanium layer below the layer. 1 . The method of manufacturing a word line of a split gate flash memory cell according to claim 13 wherein the material of the spacer is yttrium oxide. A method of manufacturing a word line of a split gate flash memory cell according to claim 13 wherein the material of the cap layer is tantalum nitride. The method of manufacturing the word line of the split gate flash memory cell according to claim 13 wherein the thickness of the cover layer is between 600 and 180. 1 . The method of manufacturing the word line of the separated gate flash memory cell according to claim 13 , wherein the chemical mechanical polishing step comprises at least: using a hard polishing pad; controlling the pressure between Between 2 psi and 5 psi; controlling the rotation rate of a grinding platform between 50 rp m and 100 rpm; 1253146 _ Case No. 92117328_年月日日__ VI. Patent application scope The rotation rate of a grinding head is controlled between 5 0 r p m and 1 0 0 r p m. A method of manufacturing a word line of a split gate flash memory cell according to claim 13 wherein the thickness of the second oxide layer is greater than 20 〇1. Cellular crystal system recalls flashing fast layer polarization thyristor from the dichotomy of the description of the shape of the item 3 1 its first, the method of the law of the genre. Please take the steps of the line, such as Yuanli • Words 9 1 heat 2 Cell cover Crystal cover Recall this.记和法闪层刻快盖# The extreme cover of the sluice gate is divided into the remaining points, except for the use of the 3XS system, which is the first step, and the method of step-by-step method Please ask the line of the application line such as Yuan Fang • Word ο 层 晶 晶 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The stipulations of the stipulations of the stipulations of the stipulations such as the syllabus of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity The division is in the position •, the upper film is very thin, and the source is divided into the second part of the first layer. The upper part of the oxygen film is thinner, and the first part of the part is the other. Do not divide the wall wall gap between the oxygen Oxide and the second gas. The first part of the wall is on the side of the source wall. Guide the second and the first Page 21 1253146 Case No. 92117328 曰 曰 修正 曰 曰 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请Page 22 1253146 Case No. 921] 7 Milk A Revision 4, Chinese Invention Abstract (Invention Name··Separation Gate Flash Memory Cell Character Line Structure and Manufacturing Method) A Separated Gate Flash Memory Cell (SpUt 忟FUsh Mem〇ry Cell) Word Line structure and its manufacturing method. The method first provides a gate structure for separating a gate flash memory cell, wherein a material layer of a word line is formed on the gate structure. A cover layer is formed on the layer of material of the word line. Next, a portion of the cap layer and a portion of the word line material layer are removed using a chemical mechanical polishing (CMp) technique. After forming an oxide layer on the surface of the exposed word line material layer, removing the remaining cover layer and the word line material layer below it to form a square-shaped flash memory cell shape (Box-shape) Word line. V. (1) The representative figure of this case is ······—_____ (2), the representative figure of the representative figure of this case is a simple description 2 0 0: substrate 2 3 2: spacer 5, English abstract ( STRUCTURE OF WORD LINE IN SPLIT GATE FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME) A structure of a word line in a split gate flash memory cell and a method for manufacturing are disclosed. In the method, a gate structure of a A gate layer is formed on the material layer of the word line. Then, a portion of the cap layer and a portion of the Material Page 21253146 -1~: Face 921173 New York □ lx Four texts ^ month summary (invention name: separate gate flash memory cell word line structure and its manufacturing method) 2 0 2 : gate Pole dielectric layer 2 3 4 · Separation gate flash memory cell 2 0 4 : Conductive layer 2 1 2 : Gap 2 1 4 : Gap 2 1 6 · Source 2 1 8 : Conductive layer 2 2 0 : Oxide layer 2 2 2 : Gate structure 2 2 4 · Dielectric layer 2 3 0 : Oxide layer IN SPLIT GATE FLASH MEMORY V. English invention summary (invention name: STRUCTURE OF WORD LINE CELL AND METHOD FOR MANUFACTURING THE SAME) layer After the word line are removed by using a chemical mechanical polishing (CMP) technique. After an oxide layer is formed on the exposed material layer of the word line, the remaining cap layer and the material layer of the word line beneath the remaining cap layer Are removed, so as to form a box-shape word line in the split gate flash memory cell. 1253146 _ Case No. 92117328_年月日日_ Six, designated representative map Page 4