TWI252569B - Chip package having TIM with reduced bond line thickness - Google Patents

Chip package having TIM with reduced bond line thickness Download PDF

Info

Publication number
TWI252569B
TWI252569B TW093135220A TW93135220A TWI252569B TW I252569 B TWI252569 B TW I252569B TW 093135220 A TW093135220 A TW 093135220A TW 93135220 A TW93135220 A TW 93135220A TW I252569 B TWI252569 B TW I252569B
Authority
TW
Taiwan
Prior art keywords
heat sink
wafer
interface material
heat
thermal conductivity
Prior art date
Application number
TW093135220A
Other languages
Chinese (zh)
Other versions
TW200618226A (en
Inventor
Chun-En Huang
Ching-Hsu Yang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093135220A priority Critical patent/TWI252569B/en
Application granted granted Critical
Publication of TWI252569B publication Critical patent/TWI252569B/en
Publication of TW200618226A publication Critical patent/TW200618226A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A chip package for reducing bond line thickness of TIM mainly includes a substrate, a stiffener, a chip, a TIM (thermal interface material), a heat spreader and a thermal conductive spring. The thermal conductive spring is connected to a bottom surface of the heat spreader. The stiffener and the chip are bonded to the substrate. The TIM is formed on a surface of the chip. When the heat spreader is connected to the stiffener, the TIM at least thermally couples the thermal conductive spring and the chip for reducing the bond line thickness (BLT) of the TIM and increasing heat-dissipating property.

Description

1252569 五、發明說明（2) 1 5 0 ’複數個銲球1 1 4係設於該基板1 1 〇之該下表面丨1 2。在 上述違晶片封裝構造1 〇 〇中，由於設在該基板丨丨〇上之該加 固件1之高度，與該晶片1 30電性連接於該基板11 〇後之 水平问度係難以控制，因此會提供較多之熱導介面物質 14 0以確保該熱導介面物質1 4 0能確實接觸該晶片1 3 0之 該非5動面132與該散熱片150之該底面151，但因此而增 ^ 1衣成本。再者’該熱導介面物質丨4 〇會因材料之熱脹 二縮特1±，而無法控制該熱導介面物質1 4 〇在該晶片1 3 〇與 政熱片150間之鍵結高度（bond line thickness, 曰η私Ξ此在製程上係以一特製之夾具（圖未繪出）夾合該 二二，裝，造100與一輸送載具（圖未緣出），但由於在操 # = = ί蚪，谷易造成該散熱片1 5 0位移或因操作不當而 Ϊ裝構造1〇0脫離該輸送載具，並且夾合與移除 该夾具亦會增加封裝成本。 緣气i = t告第5,909，°56號係揭示-種習知具有凸 ϋ 封裝構造’其係包含-封褒基板、-半導 material)，該半導體 —介面物質（interface 而 ϋ道触θ B日片係具有—非主動面及一主動 接合形成於該主動面之凸塊覆晶 黏結該基板之該上表=以一黏膠（叩啊）分別 具有-凸緣一rusion、) :靡：散熱片之中央處係 介面物質#可A 係對應於該半導體晶片，該 ”面物…為-黏膠(epoxy)或—導熱膠帶(1252569 V. DESCRIPTION OF THE INVENTION (2) 1 5 0 'A plurality of solder balls 1 1 4 are provided on the lower surface 丨 1 2 of the substrate 1 1 . In the above-described chip-wrapping structure 1 , the height of the stiffener 1 provided on the substrate is difficult to control after the wafer 1 30 is electrically connected to the substrate 11 . Therefore, more thermal conductivity interface material 140 is provided to ensure that the thermal interface material 1 40 can positively contact the non-5 moving surface 132 of the wafer 130 and the bottom surface 151 of the heat sink 150, but thus increase ^ 1 clothing cost. Furthermore, the thermal conductivity interface material 丨4 〇 will not be able to control the bonding height of the thermal conductivity interface material 1 4 〇 between the wafer 1 3 〇 and the political heat sheet 150 due to the thermal expansion of the material. (bond line thickness, 曰η私ΞThis is a special fixture (not shown) on the process to clamp the two, two, two, two, two, Fracture # = = ί蚪, Gu Yi caused the heat sink to be displaced by 150° or the armored structure 1〇0 was disengaged from the transporting carrier due to improper operation, and the clamping and removing of the jig also increased the packaging cost. i = t, No. 5, 909, °, 56, revealing that there is a convex structure, a package structure, which includes a sealing substrate, a semi-conductive material, and a semiconductor-interface material. The film has a non-active surface and an active bonding formed on the active surface of the bump, and the upper surface of the substrate is bonded to the substrate by a glue (叩 ) 分别 分别 分别 分别 、 、 ) ) ) ) ) ) ) ) ) ) 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热The central interface of the sheet is the interface material #A, which corresponds to the semiconductor wafer, and the "face material" is - an epoxy or a guide Tape (

第7頁 五、發明說明（3) c ο n d u c t i v e t a p e ) ’该介面物質係介於該半導體晶片之兮 非主動面與該散熱片之該凸緣之間。藉由該凸緣縮短該半" 導體晶片與該加固件之高度差距，以使該介面物質具有— 較薄之厚度，然而，由於該凸緣係屬於該散熱片之一部位 且為硬質，在裝設該散熱片時，該凸緣極容易觸壓到該半 導體晶片’導致該半‘體晶片之才貝壞。 【發明内容】 本發明之主要目的係在於提供一種降低熱導介面物質 鍵結高度之晶片封裝構造，其係包含有一基板、一加固貝. 件、一晶片、一熱導介面物質（thermal interface mat er i a 1，T IΜ )、〆散熱片及一導熱彈片，該加固件係設_> 於該基板，該晶片係没置於該基板，該熱導介面物質係形 成於該晶片與該散熱片之間，該散熱片係具有一底面，^ 導熱彈片係設於該散熱片之該底面，該導熱彈片係具有一 板部’該板部係运離θ亥散熱片之該底面，當該散熱片結合 該加固件，該熱導介面物質係至少熱耦合連接該晶片與該 導熱彈片，以降低該熱導介面物質之鍵結高度（b〇nd fine th i ckness，BLT )且不會損傷该晶片，並增加散熱面積。 本發明之次一目的係在於提供一種降低熱導介面物質 鍵結尚度之晶片封裝構造’ 一散熱片之一底面係設有/導 熱彈片，由於該導熱彈片具有彈性，因此當結合該散熱片 於一加固件時，該導熱彈片係會彈性接觸形^二該晶片之 一表面上之一熱導介面物質’而不會壓傷該晶片；益且， 該導熱彈片係具有至少一開孔’其係可供多餘之該熱導介Page 7 5. Inventive Note (3) c ο n d u c t i v e t a p e ) ' The interface material is interposed between the inactive surface of the semiconductor wafer and the flange of the heat sink. The height difference between the semi-conductor wafer and the reinforcement is shortened by the flange so that the interface material has a thin thickness, however, since the flange belongs to a portion of the heat sink and is rigid, When the heat sink is mounted, the flange is extremely susceptible to being pressed against the semiconductor wafer' resulting in damage to the semiconductor wafer. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wafer package structure for reducing the bonding height of a thermal interface material, which comprises a substrate, a reinforcing shell, a wafer, and a thermal interface mat. Er ia 1, T I Μ ), 〆 heat sink and a thermal conductive elastic piece, the reinforcing device is set to _> on the substrate, the wafer is not placed on the substrate, and the thermal conductive interface material is formed on the wafer and the heat dissipation Between the sheets, the heat sink has a bottom surface, and the heat conducting elastic piece is disposed on the bottom surface of the heat sink. The heat conducting elastic piece has a plate portion that is transported away from the bottom surface of the θHH heat sink. The heat sink is combined with the reinforcing member, and the thermal conductive interface material is at least thermally coupled to the wafer and the thermally conductive elastic sheet to reduce the bonding height of the thermal conductive interface material (BLT) without damage The wafer and increase the heat dissipation area. A second object of the present invention is to provide a chip package structure for reducing the bonding property of a thermal conductive interface material. A bottom surface of a heat sink is provided with a heat conductive elastic piece. Since the heat conductive elastic piece has elasticity, when the heat sink is combined, the heat sink is combined with the heat sink. When the firmware is applied, the thermal conductive elastic sheet elastically contacts a heat conducting interface material on one surface of the wafer without crushing the wafer; and the thermally conductive elastic sheet has at least one opening. The system is available for excess of the thermal conductivity

第8頁 252569 ______ 五、發明說明（4) — — ———^^ 面物質擴散至該導熱彈片與該散熱片之間。 本發明之再一目的係在於提供一種降低熱導介面物質 鍵結咼度之晶片封裝構造，一加固件與一晶片係設置於— 基板之一上表面，該加固件係具有一扣合部，一散熱片係 具有一彈扣部，該散熱片係以該彈扣部彈性扣合於該加固 件之該扣合部，使設在該散熱片之一導熱彈片能更接近該 晶片’且可控制熱耦合連接該晶片與該導熱彈片之一熱導 ”面物質之鍵結高度（bond line thickness，BLT)，並固 疋4散熱片，避免發生分層（del ami nation )。Page 8 252569 ______ V. INSTRUCTION DESCRIPTION (4) — — — — ^^ The surface material diffuses between the thermally conductive elastic sheet and the heat sink. A further object of the present invention is to provide a chip package structure for reducing the bonding strength of a thermal conductive interface material. A reinforcing member and a wafer system are disposed on an upper surface of the substrate, and the reinforcing member has a fastening portion. The heat sink has a latching portion, and the heat sink is elastically fastened to the fastening portion of the reinforcing member, so that the heat conducting elastic piece disposed on the heat sink can be closer to the wafer. Controlling the thermal coupling of the wafer to the thermal conductivity of one of the thermally conductive shrapnel "bond line thickness (BLT), and fixing the 4 heat sink to avoid del ami nation.

、 依本發明之降低熱導介面物質鍵結高度之晶片封裳構 造，其係包含有一基板、一加固件、一晶片、一熱導介面 物質、一散熱片及一導熱彈片，該基板係具有一上表面， 4加固件係設於該基板之該上表面，該晶片係接合於該基 板之違上表面，該熱導介面物質係形成於該晶片之一表 伏罝例如形成於該晶片之一主動面或非主動面，該散熱片 =具有一底面’該導熱彈片係設於該散熱片之該底面，該 …:h ir、具有一板部，該板部係遠離該散熱片之該底 敎 ^ σ亥政熱片結合於該加固件，該熱導介面物質係至少 :，口連接該導熱彈片之該板部與該晶片之該表面。The wafer sealing structure for reducing the bonding height of the thermal interface material according to the present invention comprises a substrate, a reinforcing member, a wafer, a thermal conductive interface material, a heat sink and a thermal conductive elastic sheet, wherein the substrate has An upper surface, 4 reinforcing members are disposed on the upper surface of the substrate, the wafer is bonded to the upper surface of the substrate, and the thermal conductive interface material is formed on one of the wafers, for example, formed on the wafer An active surface or a non-active surface, the heat sink has a bottom surface, the heat-conductive elastic piece is disposed on the bottom surface of the heat sink, the ...:h ir has a plate portion, and the plate portion is away from the heat sink The bottom 敎 ^ σ haizhen heat sheet is coupled to the reinforcing member, the heat conducting interface material is at least: the mouth is connected to the plate portion of the thermally conductive elastic piece and the surface of the wafer.

【實施方式】 茶閱所附圖式，本發明將列舉以下之實施例說明。 埶#，本發明之一具體實施例，請參間第2圖，一種降低 ^ V ;ι面物質鍵結高度之晶片封裝構造2〇〇係主要包含一 土板21 〇、一加固件220、一晶片230、〆熱導介面物質240 1252569__ 五、發明說明⑸ " —— (thermal interface material，TIM)、一 散熱片 250 及 導熱彈片2 6 0，該基板2 1 0係具有一上表面2 1 1、一下表面 2 1 2並包含複數個形成於該上表面2 u之連接墊2丨3。較佳 地’該基板2 1 〇係為一增層電路板n)ui ld—.up wi rin^ substrate)。[Embodiment] The present invention will be described by way of the following examples.埶#, a specific embodiment of the present invention, please refer to FIG. 2, a chip package structure 2 for reducing the bonding height of the ι surface material, mainly comprising a soil plate 21 〇, a reinforcing member 220, a wafer 230, a thermal conductive interface material 240 1252569__5, a description (5) " (thermal interface material, TIM), a heat sink 250 and a thermal conductive elastic piece 260, the substrate 2 1 0 has an upper surface 2 1 1. The lower surface 2 1 2 includes a plurality of connection pads 2丨3 formed on the upper surface 2 u. Preferably, the substrate 2 1 is a build-up circuit board n) ui ld — up wi rin ^ substrate).

該加固件22 0係以一黏膠221黏設於該基板2 l〇之該上 表面2 1 1，該加固件2 2 〇係可為環形體或複數個對稱形成之 條狀體’在本實施例中，該加固件2 2 〇係為一環形體，虬 該加固件220係具有一開口 222、一扣合部223及一外側壁 2 24，該扣合部2 23係可為形成在該外側壁224之凸緣或扣 合槽，較佳地，該凸緣或扣合槽係為對稱形成。在本實施 例中，該開口 22 2係為矩形。 、The reinforcing member 220 is adhered to the upper surface 21 of the substrate 2 by a glue 221, and the reinforcing member 2 2 can be an annular body or a plurality of symmetrically formed strips. In the embodiment, the reinforcing member 22 is an annular body, and the reinforcing member 220 has an opening 222, a fastening portion 223 and an outer side wall 2 24, and the fastening portion 2 23 can be formed therein. The flange or the snap groove of the outer side wall 224, preferably, the flange or the snap groove is symmetrically formed. In the present embodiment, the opening 22 2 is rectangular. ,

該晶片2 3 0係電性連接於該基板21 〇之該上表面2 11， 邊晶片2 3 0係容置於該加固件2 2 〇之該開口 2 2 2内，該晶片 230係具有一主動面231及一對應之非主動面232。在本實 施例中，該晶片230係為一覆晶晶片，該晶片23〇係包含有 複數個在該主動面231之凸塊233，該晶片230係以該主動 面2 3 1朝下之方式，以該些凸塊2 3 3接合至該基板2 1 〇之該 些連接墊213，一底部填充膠234係密封該晶片230之該主 動面2 3 1並填充於該些凸塊2 3 3所形成之間隙。 請參閱第2及3圖，該熱導介面物質2 4 〇係形成於該晶 片230之一表面，例如形成於該晶片“ο之該主動面231或 該非主動面232，在本實施例中，由於該晶片23 0係以該主 動面231朝向該基板21〇，因此該熱導介面物質240係形成The wafer 305 is electrically connected to the upper surface 211 of the substrate 21, and the edge wafer 203 is received in the opening 2 2 2 of the reinforcing member 2 2 , and the wafer 230 has a The active surface 231 and a corresponding non-active surface 232. In this embodiment, the wafer 230 is a flip chip, and the wafer 23 includes a plurality of bumps 233 on the active surface 231. The wafer 230 is in a manner that the active surface 23 31 faces downward. The bumps 233 are bonded to the connection pads 213 of the substrate 2 1 , and an underfill 234 seals the active surface 23 1 of the wafer 230 and fills the bumps 2 3 3 The gap formed. Referring to FIGS. 2 and 3, the thermal interface material 24 is formed on one surface of the wafer 230, for example, on the active surface 231 or the inactive surface 232 of the wafer. In this embodiment, Since the wafer 230 is oriented with the active surface 231 toward the substrate 21, the thermal interface material 240 is formed.

第10頁 1252569___ 一 五、發明說明（7) 增加導熱面積，並且具有避免該熱導介面物質240溢出至 該晶片2 3 0之外之功效，該熱導介面物質2 4 〇係可接觸該散 熱片2 5 0之該底面2 5 1 ;由於該散熱片2 5 0係以該導熱彈片 260接觸該熱導介面物質24〇，因此係可降低該熱導介面物 質2 4 0在該導熱彈片2 6 〇與該晶片2 3 0之該非主動面2 3 2之間 之鍵結南度（bond line thickness, BLT)，且在本實施例 中’該熱導介面物質240係可透過該些開孔264，而局部地 擴散於該導熱彈片26〇之該板部261與該散熱片25〇之該底 面251之間。請參閱第4圖，該導熱彈片260之該些開孔264 係可為矩形或長條狀，該導熱彈片2 6 0之材質係可選自於 銅、铭及其合金之其中之一。在不同實施例中，能以不同 開孔形態導熱彈片置換該導熱彈片26〇。請參閱第5八圖， 一導熱彈片3 1 0之板部3 1 1係具有複數個細條狀之開孔 312 ’該導熱彈片310係可設置於該散熱片250之該底面 Μ〗’或者’睛參閱第5B圖，一導熱彈片410係具有一遠離 该散熱片250之板部411，該板部411係具有複數個圓形之 開孔412 ’該導熱彈片410係可設置於該散熱片2 50之該底 面2 5 1 以組成一種可節省熱導介面物質用量之散熱片結 構。 … 較佳地，一熱固性黏膠270係形成於該加固件2 20之一 頂面22 5與該扣合部223間，以黏著該散熱片25〇於該加固 , = 該熱固性黏膠27〇係可為一種具強黏著力之熱固性 樹脂。在本實施例中，複數個銲球214係設於該基板21〇之 該下表面2 1 2。Page 10 1252569___ 1-5, invention description (7) increase the heat conduction area, and has the effect of avoiding the thermal conductivity interface material 240 spilling out of the wafer 230, the thermal interface material 24 can contact the heat dissipation The bottom surface 2 5 1 of the sheet 2 50; since the heat-dissipating fins 205 contact the thermal conductive interface material 24 〇, the thermal conductive interface material 240 can be lowered in the thermal conductive elastic sheet 2 6 bond a bonding line thickness (BLT) between the inactive surface 2 3 2 of the wafer 203, and in the present embodiment, the thermal conducting interface material 240 is permeable to the openings 264, and partially diffused between the plate portion 261 of the heat conducting elastic piece 26 and the bottom surface 251 of the heat sink 25A. Referring to FIG. 4, the openings 264 of the thermally conductive elastic piece 260 may be rectangular or elongated, and the material of the thermally conductive elastic piece 260 may be selected from one of copper, metal and alloy thereof. In various embodiments, the thermally conductive springs 26 can be replaced by thermally conductive springs in different aperture configurations. Referring to FIG. 5, a plate portion 3 1 1 of a thermally conductive elastic piece 3 1 0 has a plurality of thin strip-shaped openings 312 ′. The thermally conductive elastic piece 310 can be disposed on the bottom surface of the heat sink 250. Referring to FIG. 5B, a thermally conductive elastic piece 410 has a plate portion 411 away from the heat dissipation plate 250. The plate portion 411 has a plurality of circular openings 412. The heat conductive elastic piece 410 can be disposed on the heat dissipation plate 2 The bottom surface 2 5 1 of 50 constitutes a heat sink structure that can save the amount of the thermal conductive interface material. Preferably, a thermosetting adhesive 270 is formed between the top surface 22 5 of the reinforcing member 20 and the fastening portion 223 to adhere the heat sink 25 to the reinforcement, = the thermosetting adhesive 27〇 It can be a thermosetting resin with strong adhesion. In the present embodiment, a plurality of solder balls 214 are disposed on the lower surface 2 1 2 of the substrate 21 .

Ιψ2569 五、發明說明（8)Ιψ 2569 V. Description of invention (8)

在上述之降低熱導介面物質鍵結高度之晶片封裝構造 2〇〇中，該散熱片2 50係結合於該加固件220，該熱導介面 物質24 0係至少熱耦合連接該導熱彈片26〇之該板部26 i與 該晶片230之該非主動面232，該熱導介面物質24〇係不需 要填滿於該導熱弹片2 6 0與該散熱片2 5 0之該底面2 5 1少 間，因此該熱導介面物質24 0可具有較薄之鍵結高度（丨:)〇nd line thickness，BLT)。另外，該導熱彈片26〇係可增加 散熱面積；且因該散熱片2 5 0係以該彈扣部2 5 2彈性扣合於 該加固件220之該扣合部223，以使得該散熱片250能固定 結合於或加固件2 2 0 ’而不會發生分層（de 1 am i n a t ion)， 並且，該具有彈性之導熱彈片2 6 0係不會對該晶片2 3 0造成 損壞。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何热知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。In the above-described chip package structure 2, which reduces the bonding height of the thermal interface material, the heat sink 250 is bonded to the reinforcing member 220, and the thermal conductive interface material 204 is at least thermally coupled to the thermally conductive elastic member 26〇. The plate portion 26 i and the inactive surface 232 of the wafer 230 do not need to be filled between the heat conducting elastic piece 206 and the bottom surface 2 5 1 of the heat sink 2 50 Therefore, the thermal interface material 24 0 can have a relatively thin bond height (丨 line line line line thickness, BLT). In addition, the heat-dissipating elastic piece 26 can increase the heat-dissipating area; and the heat-dissipating piece 205 is elastically fastened to the fastening portion 223 of the reinforcing member 220 by the elastic portion 250, so that the heat-dissipating piece 250 can be fixedly bonded to or stiffener 2 2 0 ' without delining, and the elastic thermally conductive elastic piece 206 will not damage the wafer 230. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are protected by the present invention. range.

1111

I 第13頁 1252569__ 圖式簡單說明 【圖式簡單說明】 第 1 圖：習知晶片封裝構造之截面示意圖； 第 2 圖：依據本發明，一種降低熱導介面物質鍵結高 度之晶片到裝構造之载而示念岡； 第 3 圖：依據本發明，該晶片封裝構造之局部放大截 面示意圖； 第 4 圖：依據本發明，該晶片封裝構造之散熱片之底 面示意圖；及 第5Λ與5B圖：依據本發明，不同型態之導熱彈片裝設於該 散熱片之底面示意圖。 元件符號簡單說明： 1 0 0 晶片封裝構造 1 10 基板 111 上表面 112 下 表 面 1 13 連接塾 114 鲜球 120 加固件 121 黏膠 122 開 π 123 頂面 130 晶片 131 主動面 132 非 主 動面 133 凸塊 134 底部填充膠 140 熱導介面物質 150 散熱片 151 底面 160 熱固性黏膠 200 晶片封裝構造 210 基板 211 上表面 212 下 表 面I Page 13 1252569__ BRIEF DESCRIPTION OF THE DRAWINGS [Simplified Schematic] FIG. 1 is a schematic cross-sectional view of a conventional chip package structure; FIG. 2 is a wafer-to-package structure for reducing the bonding height of a thermally conductive interface material according to the present invention. FIG. 3 is a partially enlarged cross-sectional view of the chip package structure according to the present invention; FIG. 4 is a schematic view showing the bottom surface of the heat sink of the chip package structure according to the present invention; and FIGS. 5 and 5B According to the present invention, different types of thermally conductive elastic sheets are mounted on the bottom surface of the heat sink. Brief description of component symbols: 1 0 0 Chip package structure 1 10 Substrate 111 Upper surface 112 Lower surface 1 13 Connection 塾 114 Fresh ball 120 Reinforcement 121 Adhesive 122 Open π 123 Top surface 130 Wafer 131 Active surface 132 Inactive surface 133 convex Block 134 Underfill 140 Thermal Conductivity Interface Material 150 Heat Sink 151 Bottom Surface 160 Thermoset Adhesive 200 Wafer Package Construction 210 Substrate 211 Upper Surface 212 Lower Surface

第14頁 1252569 圖式簡單說明Page 14 1252569 Schematic description

第15頁Page 15

2 1 3 連接墊 2 1 4 輝球 220 加固件 2 21 黏膠 22 2 開口 223 扣合部 224 外側壁 225 頂面 23 0 晶片 2 3 1 主動面 2 32 非主動面 233 凸塊 234 底部填充膠 240 熱導介面物質 250 散熱片 251 底面 25 2 彈扣部 260 導熱彈片 261 板部 26 2 端部 263 鉚釘 264 開孔 270 熱固性黏膠 310 導熱彈片 311 板部 312 開孔 410 導熱彈片 411 板部 412 開孑L2 1 3 connection pad 2 1 4 glow ball 220 reinforcement 2 21 adhesive 22 2 opening 223 fastening part 224 outer side wall 225 top surface 23 0 wafer 2 3 1 active surface 2 32 inactive surface 233 bump 234 underfill 240 Thermal Interface Material 250 Heat Sink 251 Bottom Surface 25 2 Spring Buckle 260 Thermally Conductive Spring 261 Plate 26 2 End 263 Rivet 264 Opening 270 Thermosetting Adhesive 310 Thermally Conductive Spring 311 Plate 312 Opening 410 Thermally Conductive Spring 411 Plate 412 Open L

Claims (1)

1252569 六、申請專利範圍 【申請專利 1 > —- 含： 種降 基板 力口固 範圍】 低熱導介面物質鍵結南度之晶片封裝構造包 ，其係具有一上表面； 件（s t i f f e n e r )，其係設於該基板之該上表 面； 曰曰 片’其係設置於該基板之該上表面並具有至少 表面； 熱導介面物質（t h e r m a 1 i n t e r f a c e m a t e r i a T I Μ )，其係形成於該晶片之該表面； 散熱 導熱 片，其係具有一底面；及 片係具有 其中， 係至少熱搞 面。 2、 如申請 南度之晶片 少一開孔， 熱片之該底 3、 如申請 南度之晶片 4、 如申請 高度之晶片 彈片，其係設於該散熱片之該底面，該導熱彈 板部，該板部係遠離該散熱片之該底面； 當該散熱片結合於該加固件，該熱導介面物質 合連接該導熱彈片之該板部與該晶片之該表 專利範圍第1項所述之降低熱導介面物質鍵結 封裝構造，其中該導熱彈片之該板部係具有至 以供該熱導介面物質擴散至該導熱彈片與該散 面之間。 專利範圍第2項所述之降低熱導介面物質鍵結 封裝構造，其中該開孔係為矩形。 專利範圍第2項所述之降低熱導介面物質鍵結 封裝構造，其中該開孔係為長條狀。1252569 Sixth, the scope of application for patents [patent 1 > --- Contains: seed drop substrate force port solid range] Low thermal conductivity interface material bonding south degree wafer package construction package, which has an upper surface; The slab is disposed on the upper surface of the substrate and has at least a surface; a thermal interface material (therma 1 interface matrix) formed on the wafer a heat-dissipating heat-dissipating sheet having a bottom surface; and a sheet having therein, at least a heat-generating surface. 2. If there is one opening for the wafer of Nandu, the bottom of the hot sheet 3. If applying for the wafer of Nandu 4, if the wafer shrapnel of the height is applied, it is disposed on the bottom surface of the heat sink, the thermal elastic plate The plate portion is away from the bottom surface of the heat sink; when the heat sink is coupled to the reinforcing member, the heat conductive interface material is coupled to the plate portion of the heat conductive elastic piece and the wafer The reduced thermal conductivity interface material bonding package structure is characterized in that the plate portion of the thermally conductive elastic sheet has a structure for diffusing the thermal conductive interface material between the thermally conductive elastic piece and the scattering surface. The reduced thermal conductivity interface material bonding package structure of claim 2, wherein the opening is rectangular. The reduced thermal conductivity interface material bonding package structure of claim 2, wherein the opening is elongated. 第16頁 1252569 _________—__— 六、申請專利範圍 5、 如申請專利範圍第2項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該開孔係為圓形。 6、 如申請專利範圍第1項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該熱導介面物質係接觸該散熱 片之該底面。 7、 如申請專利範圍第1項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其另包含一熱固性黏膠，以黏著該 加固件與該散熱片。Page 16 1252569 _________—__— VI. Scope of Application Patent 5. The wafer package structure for reducing the bonding height of the thermal interface material as described in claim 2, wherein the opening is circular. 6. The wafer package structure of claim 1, wherein the thermal interface material contacts the bottom surface of the heat sink. 7. A wafer package structure for reducing the bonding height of a thermal interface material according to claim 1 of the patent application, further comprising a thermosetting adhesive for adhering the reinforcement to the heat sink. 8、 如申請專利範圍第1項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該加固件係具有一扣合部，該 散熱片係具有一彈扣部，該散熱片之該彈扣部係扣合於該 加固件之該扣合部。 9、如申請專利範圍第8項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該扣合部係為一凸緣，其係形 成在該加固件之^^外側壁。 1 〇、如申請專利範圍第8項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該扣合部係為一扣合槽，其係 形成在該加固件之一外側壁。8. The chip package structure of claim 1, wherein the reinforcement has a fastening portion, and the heat sink has a latch portion, and the heat sink has a heat sink. The buckle portion is fastened to the fastening portion of the reinforcement. 9. The wafer package structure of claim 8, wherein the fastening portion is a flange formed on an outer side wall of the reinforcing member. 1 . The chip package structure of claim 8, wherein the fastening portion is a fastening groove formed on an outer side wall of the reinforcing member. 1 1、如申請專利範圍第8項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該彈扣部係為複數個卡鉤。 1 2、如申請專利範圍第1 1項所述之降低熱導介面物質鍵結 南度之晶片封裝構造’其中該些卡釣係形成於該散熱片之 周邊。 1 3、如申請專利範圍第1 1項所述之降低熱導介面物質鍵結1 1. The chip package structure for reducing the bonding height of a thermal conductive interface material according to claim 8 of the patent application, wherein the latch portion is a plurality of hooks. 1 2. A wafer package structure for reducing thermal conductivity interface material bonding as described in claim 1 wherein the card fishing systems are formed around the heat sink. 1 3. Reduce the thermal conductivity interface material bonding as described in claim 11 第17頁 T252569 々、申請專利範圍 高度之晶片封 型。 14、如申請專 高度之晶片封 部，該些端部 1 5、如申請專 高度之晶片封 成型。 1 6、如申請專 高度之晶片封 置該晶片。 17、 如申請專 高度之晶片封 18、 如申請專 高度之晶片封 19、 如申請專 高度之晶片封 包含有複數個 2 0、如申請專 高度之晶片封 該基板之一下 21、如申請專 高度之晶片封 銅、鋁及其合 利範圍 裝構造 利範圍 裝構造 利範圍 裝構造 凸塊。 利範圍 裝構造 表面。 利範圍 裝構造 金之其Page 17 T252569 々, patent pending range High wafer seal. 14. If you apply for a special height of the wafer seal, these end parts 15 , such as the application of a special height of the wafer seal molding. 16. If the wafer is applied for a special height, the wafer is sealed. 17. If you apply for a special height of the wafer seal 18, if you apply for a special height of the wafer seal 19, if you apply for a special height of the wafer seal contains a plurality of 20, such as the application of a special height of the wafer seal under one of the substrates 21, such as the application of special height The wafer is sealed with copper, aluminum and its combined range structure and structure. The range of construction is the surface. Advantage range 裝構造，其中該些卡鉤係與該散熱片一體成 利範圍第1項所述之降低熱導介面物質鍵結 裝構造，其中該導熱彈片係另具有複數個端 係鉚接於該散熱片之該底面。 利範圍第1項所述之降低熱導介面物質鍵結 裝構造，其中該導熱彈片係與該散熱片一體 利範圍第i項所述之降低熱導介面物質鍵結 裝構造，其中該加固件係具有一開口，以容 第1項所述之降低熱導介面物質鍵結 ，其中該表面係為一非主動面。 第1項所述之降低熱導介面物質鍵結 ，其中該表面係為一主動面。 第1項所述之降低熱導介面物質鍵結 ，其中該晶片係為一覆晶晶片，其係 第1項所述之降低熱導介面物質鍵結 ，其另包含有複數個銲球，其係設於 第1項所述之降低熱導介面物質鍵結 ，其中該導熱彈片之材質係選自於 中之一。The structure of the hooks is integrated with the heat sink to form the reduced thermal conductivity interface material bonding structure according to the first item, wherein the heat conducting elastic piece has a plurality of end portions riveted to the heat sink. The bottom surface. The reduced thermal conductivity interface material bonding structure according to Item 1, wherein the thermally conductive elastic sheet and the heat sink are integrated with the reduced thermal conductivity interface material bonding structure according to the item i, wherein the reinforcing member The system has an opening to reduce the thermal conductivity interface material bond as described in item 1, wherein the surface is an inactive surface. The thermal conductivity interface material bonding described in Item 1, wherein the surface is an active surface. The thermal conductivity interface material bonding according to Item 1, wherein the wafer is a flip chip, which is a reduced thermal conductivity interface material bond according to Item 1, which further comprises a plurality of solder balls, The material for reducing thermal conductivity interface material according to item 1, wherein the material of the heat conductive elastic piece is selected from one of them. 第18頁 1252569______ 六、申請專利範圍 2 2、如申請專利範圍第1項所述之降低熱導介面物質鍵結 高度之晶片封裝構造，其中該基板係為一增層電路板 2 build-up wiring subs 1r a l e) 用於晶 、一種散熱 一散熱片 係突出於該底 片結構，適 ，其係具有 面，用以固 導熱彈片’其係設 底面 定該散 於該散 片係具有一板部，該板部係遠離 至少一開孔，以供一熱導介面物 利範圍第2 3項所述 2 4、如 孑L係為 2 5、如 孔係為 2 6、如 孑L係為 2 7、如 扣部係 2 8、如 卡鉤係 29、如 卡鉤係 3 0、如 熱彈片 之該底 開孔， 申請專 矩形。 申請專 長條狀 申請專 圓形。 申請專 為複數 申請專 形成於 申請專 與該散 申請專 係另具 面0 片封裝，其係包含： 以及--彈扣部，彈扣部 熱片；及 熱片之該底面，該導熱彈 該散熱片之該底面並具有 質之擴散流通。 之散熱片結構，其中該開 利範圍第2 3項所述之散熱片結構，其中該開 〇 利範圍第2 3項所述之散熱片結構，其中該開 利範圍第2 3項所述之散熱片結構，其中該彈 個卡鉤。 利範圍第2 7 該散熱片之 利範圍第2 8 項所述之散熱片結構，其中該些 周邊。 項所述之散熱片結構，其中該些 熱片一體成型。 項所述 部，該 利範圍第2 3 有複數個端 之散熱片結構’其中該導 些端部係鉚接於該散熱片Page 18 1252569______ VI. Patent Application No. 2 2. The wafer package structure for reducing the bonding height of the thermal interface material as described in claim 1, wherein the substrate is a build-up wiring board 2 build-up wiring Subs 1r ale) for crystal, a heat sink, a heat sink protruding from the structure of the film, suitable for having a surface for solid-state heat-conducting elastic piece 'the bottom surface of the system is fixed to have a plate portion, The plate portion is away from at least one opening for a thermal conductivity interface material range of the second item 23, 4, for example, the 孑L system is 2 5, such as the hole system is 26, and the 孑L system is 2 7 For example, the buckle portion 28, such as the hook system 29, such as the hook system 30, such as the bottom opening of the thermal elastic sheet, apply for a rectangular shape. Apply for a special strip and apply for a special round. The application for the plural application is specially formed in the application and the application for the special application. The system includes: and - the buckle portion, the spring portion of the spring button; and the bottom surface of the heat sheet, the heat transfer bomb The bottom surface of the heat sink has a qualitative diffusion flow. The heat sink structure of the heat sink of the second aspect of the invention, wherein the heat sink structure of the second aspect of the invention, wherein The heat sink structure, wherein the bullet is hooked. The heat sink of the second aspect of the heat sink of the second aspect of the heat sink, wherein the periphery is the same. The heat sink structure of the item, wherein the heat sheets are integrally formed. In the section, the second range has a heat sink structure of a plurality of ends, wherein the ends are riveted to the heat sink 第19頁 1252569_______________ 六、申請專利範圍 3 1、如申請專利範圍第2 3項所述之散熱片結構，其中該導 熱彈片係與該散熱片一體成型。 32、如申請專利範圍第2 3項所述之散熱片結構，其中該導 熱彈片之材質係選自於銅、鋁及其合金之其中之一。Page 19 1252569_______________ VI. Scope of Patent Application 3 1. The heat sink structure of claim 23, wherein the heat transfer elastic piece is integrally formed with the heat sink. 32. The heat sink structure of claim 23, wherein the material of the heat conductive elastic piece is selected from the group consisting of copper, aluminum and alloys thereof. 第20頁Page 20
TW093135220A 2004-11-17 2004-11-17 Chip package having TIM with reduced bond line thickness TWI252569B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093135220A TWI252569B (en) 2004-11-17 2004-11-17 Chip package having TIM with reduced bond line thickness

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093135220A TWI252569B (en) 2004-11-17 2004-11-17 Chip package having TIM with reduced bond line thickness

Publications (2)

Publication Number Publication Date
TWI252569B true TWI252569B (en) 2006-04-01
TW200618226A TW200618226A (en) 2006-06-01

Family

ID=37565457

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093135220A TWI252569B (en) 2004-11-17 2004-11-17 Chip package having TIM with reduced bond line thickness

Country Status (1)

Country Link
TW (1) TWI252569B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8618672B2 (en) 2010-12-31 2013-12-31 Industrial Technology Research Institute Three dimensional stacked chip package structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8618672B2 (en) 2010-12-31 2013-12-31 Industrial Technology Research Institute Three dimensional stacked chip package structure

Also Published As

Publication number Publication date
TW200618226A (en) 2006-06-01

Similar Documents

Publication Publication Date Title
US10236189B2 (en) Adhesive-bonded thermal interface structures for integrated circuit cooling
US5940271A (en) Stiffener with integrated heat sink attachment
US6724080B1 (en) Heat sink with elevated heat spreader lid
TWI267962B (en) Semiconductor packages and methods of manufacturing thereof
CN103117275B (en) A kind of chip-packaging structure and chip packaging method
US7683479B2 (en) Semiconductor package involving a rotary lock that connects a package substrate and a separate component
US7271480B2 (en) Constraint stiffener design
US20060249852A1 (en) Flip-chip semiconductor device
US8703536B2 (en) In-situ foam material as integrated heat spreader (IHS) sealant
US8823164B2 (en) Heatsink attachment module
TW200418159A (en) Semiconductor package with heatsink
US20060043553A1 (en) Chip package having a heat spreader and method for packaging the same
TW200428623A (en) Semiconductor package with heat sink
CN104810335B (en) The manufacturing method of carbon nanotube pieces and semiconductor device, the manufacturing method of carbon nanotube pieces and semiconductor device
TWI242863B (en) Heat dissipating structure and semiconductor package with the heat dissipating structure
JP2007305761A (en) Semiconductor device
US11482470B2 (en) Electronic package and fabrication method thereof
TW200805587A (en) Semiconductor package, method of production of same, printed circuit board, and electronic apparatus
TWI658549B (en) Heat-dissipating packaging structure
TW200810050A (en) Package structure and heat sink module thereof
TWI252569B (en) Chip package having TIM with reduced bond line thickness
US20230069969A1 (en) Package for several integrated circuits
JPH1168360A (en) Cooling structure for semiconductor element
JPH05121603A (en) Hybrid integrated circuit device
TW200423348A (en) Semiconductor package with heatsink