1251986 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種無線傳輸系統，尤其是關於一種用於 植入式微電刺激系統之無線傳輸系統。 【先前技術】 植入式微電刺激系統係使用在醫療工程上，幫助部分器 官失去動作電位之病人作電刺激之復健或醫療。在習知技 術之植入式微電刺激系統架構中，人體内外之傳送器與接 收器乃為使用訊號線硬體連結的方式，而非使用射頻的方 式作溝通，此種做法的缺點為接收器必須依靠穿越生物體 皮膚之訊號線與生物體外之傳送器作溝通，不但造成生物 體之不適’且易造成訊號線穿越生物體傷口之細菌感染。 另種^知之植入式微電刺激系統架構為在接收器使用 晶片組與許多被動元件在微印刷版上作連線，此種做法相 較於在接收器使用系統單晶片（soc)的方式而言，雖不必以 硬體連結方式穿透皮膚，但植入生物體的面積與體積相對 增大許多，並且造成不必要之功率消耗（如美國專利編號： US6,561，970及 US6,402,689)。 因此有必要提供一種創新且具進步性的之無線傳輸系 統，以解決上述問題。 【發明内容】 本發明目的在於提供—㈣於植人式微電刺激系統之無 線傳輸系統，其包括：一傳送器及一接收器。該傳送器係 以射頻傳送控制指令與功率，該傳送器包含：一指令產生 96283.doc 1251986 器、一功率放大器及一傳送線圈。該指令產生器用以產生 控制指令。該功率放大器用以產生所f功率。該傳送線圈 用以產生射頻訊號，傳送該控制指令及功率。該接收器係 以射頻接收控制指令與功率，並產生相對應之電刺激輸出 至泫植入式微電刺激系統之生物性電極。該接收器包含： 一接收線圈、一微印刷電路板及一微電刺激單晶片。該接 收線圈用以接收由該傳送線圈所傳送之該控制指令及功 率，該微印刷電路板用以依據該控制指令及功率，產生相 對應之控制指令及功率至該微電刺激單晶片，該微電刺激 單晶片用以接收該相對應之控制指令及功率，做穩壓、解 該植入式微電刺激系統之生物性電極。 利用本發明之用於植入式微電刺激系統之無線傳輸系 統，可以達成以無線射頻訊號在人體内部與外部進行溝通 資料與傳遞功率。並且本發明之無線傳輸系統可以降低植 入生物體之面積及降低功率消耗，並具有低複雜度及高可 靠度之優點。 【實施方式】 ⑸為本發明用於植入式微電刺激系統之無線傳輸系統 10之架構圖。該無線傳輸系統10包括：一傳送器1〇1及—接 收器105。該傳送器（transmitter) i Q n可產生以編碼為封 包形式之電刺激指令訊息傳送裝置，其係以射頻訊號傳送 控制指令與功率。該傳送器1〇1包含：一指令產生哭 (lnStrUCtl〇n genem〇r)102、一功率放大 ^ (P〇wl 96283.doc 1251986 amplifier) 103及傳送線圈（transmitter c〇u)i〇4。該指令產 生态1 02用以產生控制指令。該功率放大器i 〇3用以產生所 需功率。該傳达線圈1〇4用以產生射頻訊號，傳送該控制指 令及功率。 该接收器105係接收射頻訊號之控制指令與功率，並產生 相對應之電刺激輸出至該植入式微電刺激系統之生物性電 極。該接收器105包含：一接收線圈1〇7、一微印刷電路板 106及一微電刺激單晶片i丨〇。該接收線圈】〇7用以接收由該 傳送線圈104所傳送之該控制指令及功率。該微印刷電路板 1〇7用以依據該控制指令及功率，產生相對應之控制指令及 功率至該微電刺激單晶片11〇。該微電刺激單晶片11〇用以 接收該相對應之控制指令及功率，做穩壓、解調變及該控 制指令之判讀，以產生相對應之電刺激輸出至該植入式微 電刺激系統之生物性電極1 1 6。 該傳送器101包含該指令產生器102、該功率放大器1〇3 及該傳送線圈104，分別詳述其實施方式如下： 該指令產生器102之實施··使用具有RS232介面與控制程 式之计异态，較佳實施方式為使用個人電腦搭配微軟視窗 作業系統與Visual Basic2RS232介面控制程式，產生符合 RS232封包之資料訊號輸出。 /亥功率放大1 〇3之實施··在各種功率放大器的實施上， E類功率放大器相較於a、B、AB功率放大器而言效率較高， 理想上可達到1〇〇%之功率輸出。參考圖2八所示，其顯示本 發明功率放大器之較佳實施電路示意圖。-個基本的E類放 96283.doc 1251986 大杰需包括一個作為開關切換的電晶體M,z2(M，一個RLC的 負載網路來界定工作頻率，一個與電晶體平行的電容‘調 整共振頻率，與一個射頻阻隔（RF choke)的電感、來提供 穩定的電流。而ASK調變的實施方式為在電源與^類功率放 大。口之間加入一個ASK調變器（ASK modulator)201來控制E 類功率放大器的最大電壓供應。 E類功率放大器的電源乃由ASK調變器（ASK modulat〇r)201所控制，根據從指令產生器1〇2所產生之單一 位兀NRZ序列（sequential)資料（NRZ daU)，供給£類放大器 不同的電源；在較佳的實施例中，可設定當NRZ data=i時， ASK調變器輸出5 ¥之電源；當NRZ如匕=〇時，Α§κ調變器 輸出3 V之電源，如此可控制傳送線圈丨〇4之振幅，達到ask 調變的效果。E類功率放大器之工作示意圖如圖2B所示，κ 端電麼變化可切換功率放大器之共振電路於[(;並聯；） 串聯Aw ]或疋[Q串聯]之間，達到此e類功率放大器震蘯 之效果。 一開始K端需有起始電路（Start-up circuit)2〇2給予震 盪，之後傳送線圈1 04兩端會產生約如匕之2〇〇匕交流電 壓。此交流電壓由回授線圈（feedback c〇il)2〇4感應，經過 回授電路（feedback circuit)203將弦波整理為方波，最終回 授至K，形成一個可以自我震盪之E類功率放大器。最後的 輸出可經由傳送線圈以2MHz之射頻訊號供給接收器使 用。圖中之為傳送線圈104所感應到接收線圈與回授線 圈之等效電阻值。 96283.doc 1251986 傳达線圈104之實施：在傳送線圈的實施上，q值越高之 線圈其所傳輸效率越高，在此使用里茲（Litz)線當作傳送線 圈 ’其較佳振輅 士士 所 ~~ --Ί •如下： 何貝 Litz wire, strands 48 AWG? 175 stands of a bundle， — and 8 bundle of a line 14 turns, 8cm inner and 11.2cm outer /φ* rM /j. -- diameter 電感值 28 uH，Q=580 線圈電壓 -----J 200 k，2 MHz之弦波 參考圖1所示，本發明無線傳輸系統10之接收器105為一 可接收以編碼為封包形式之電刺激指令訊息接收裝置，由 接收線圈（receiver c〇il)107接收射頻訊號之控制指令及功 率後’經由該微印刷電路板1〇6上之分壓器（v〇hage dlvlder)108與整流器（voltage rectifier)109，該分壓器 108 用 以依據该控制指令產生相對應之控制指令，該整流器109 用以依據該功率產生相對應之功率。 5亥被電刺激單晶片11 〇係用以做訊號與功率之處理。該微 電刺激單晶片110包含一穩壓電路（Voltage regulator)l 12、 一解調變電路（Demodulator)lll、一數位控制區塊（Digital control)l 13、一 混合訊號模組（Mixed signal module) 11 5與一 數位類比轉換器（DACs)114。 接收線圈（receiver coil)107之較t實施規格如下： 材質 0.3 mm single wire 尺寸 13 turns, 2.8cm inner and 4.1cm outer diameter 電感值 10 uH，Q=30 線圈電壓 30，2 MHz之弦波 該微電刺激單晶片Π 〇之電路說明如下： 96283.doc 1251986 參考圖3A所示，其顯示該接收器105内之穩壓流程示意 圖。接收器1 05的電源先經由微印刷電路板106之整流器 109，該整流器109包括一整流電路301及一降壓電路 (step_down circuit)302。再經由該微電刺激單晶片11〇内之 穩壓器112，以提供該微電刺激單晶片11 〇内其他電路一穩 定電源。 依據本發明之實施例，由該接收線圈所接收之功率為 -25V至+ 25V之弦波訊號（sinusoidal wave)，經由該整流電 路301整流為+ 25V之弦波訊號，再經該降壓電路3〇2之降壓 為帶有漣波（ripple)的+ 5 V電壓，該穩壓器112進行穩壓、 去除雜訊，以提供+ 3 ·3 V之穩定電源至該微電刺激單晶片 110之其他電路。 參考圖3B所示，該穩壓器112包括：啟動電路（Stan_up Circuit)303、一帶差參考電路（Bandgap)3〇4、一錯誤放大器 (Error Amplifier)3 05及一輸出電路（pass eiement)3〇6。該穩 壓态112主要罪帶差參考電路3 〇4提供一個不隨電源和溫度 /示移的穩定電源，送至高放大倍率的單級差動放大器（在線 性穩壓器中一般稱為錯誤放大器3〇5，再送到一個寬長比 (二/L)尺寸非常大的輸出電路取，構成—個快速穩定的鎖 疋迴路。在贡差參考電路3〇4前之該個啟動電路，其目 的是提供帶差參考電路3G4起始的直流偏壓而快速啟動，然 後啟動電路3〇3會因為該帶差參考電路304直流電位的提高 而進入工作區。 /考圖4 A纟顯不接收器解調變之流程示意圖。接收線 96283.doc 1251986 圈107先經由射頻訊號接收到（+17 v，+25 V)與（-17 v， -25 V)之載波為2 MHz之交流電壓，經由該微印刷電路板1〇6 之分壓器108傳送至該微電刺激單晶片11〇之解調變電路 111。經該解調器U1解調變之訊號傳送至其他電路。 參考圖4B，其係該解調變電路之示意圖。本發明之實施 例所使用的為ASK解調器（ASK Demodulator)。該解調變電 路111包含一整流單元（rectifier)4〇i、一包跡線檢測器 (㈣elope detector)·及-電位比較器（p〇tential comparator)403與一負載驅動器（ioa(j driver)404。整流單元 401疋將凋麦成號调整為正半週期訊號，該包跡線檢測器 402用以將訊號的包跡線擷取出來，經過該電位比較器4〇3 來判斷汛旒向電位和低電位後，再經由負載驅動器4〇4以得 到所需之解調訊號。下列詳述各區塊電路之功能： 整流單元401 :本發明實施例所採用的該整流單元實際上 是由一個正擺幅電壓緩衝器（positive swing v〇ltage buffe〇 來構成。一般來說，電壓訊號整流都會採用二極體的檢波 電路，但由於製程中二極體的面積頗大，而且要考慮從整 流早το 401連接至包跡檢測器4〇2的負載效應〇⑽以叩 effect)，所以利用正擺幅電壓緩衝器一方面可把訊號的負 電壓週期去掉，一方面又可以抵抗負載效應。 包跡線檢測為、402 ··此電路由一個電源獨立的偏壓電路 (supply-independent biasing circuit)來組成，當輸入大幅飄 動時，其輸出電流和電壓不會隨之變化，因此即使是前級 的正擺幅訊號進入時，也能把訊號原來的直流準位鎖住， 96283.doc -11 - 1251986 因此達到檢測包跡線的作用。 電位比較裔403 ·其利用一史密特觸發器㈠仏㈤⑴ 來實現，因為從包跡線檢測器出來的訊號之電位會有重疊 的部分，因此利用史密特觸發器的磁滞（hysteresis)現象， 則可以把檢波訊號的高低電位分辨出來，得到我們想要的 解調變訊號。 負載驅動器404:其設置於該解調變電路lu的輸出端， 由兩顆串接的反相器（casca(je inverters)組成。因為在解調 變電路111後面會連接其他電路，因此必須提昇解調變電路 111的推動力，才能避免訊號失真。在本實施例中，負載驅 動器404加上前級史密特觸發器中的反相器，共有三個串接 的反相器，設計它們的尺寸愈來愈大（下一個的尺寸大約是 上一個的2〜3倍），可以增加負載推動力和穩定性。 圖5為該混合訊號模組丨丨5之電路示意圖。該混合訊號模 組115包括一時脈訊號產生器51〇及一電源起始重置訊號產 生器520。該混合訊號模組用以提供數位控制區塊U3之時 脈訊號與電源起始重置訊號。該時脈訊號產生器51〇為一個 五級的環型震盪器（ring oscillator)，經由反相器501至反相 器505的回授電路產生震盪，經由最後一級的反相器5〇6整 波產生5MHz的方波時脈。電晶體Mp5G1為一起始電路裝置， 當電源起始的時候，電晶體义5()1會如同開關斷路，將反相 器501的起始輸入保持在接地狀態，確保此時脈產生電路能 正確產生震盪穩態。 電源起始重置訊號產生器520利用複數個電晶體，其中電 96283.doc 12 1251986 晶體〜〜mp506以其導通t阻與電晶體~〇7之間級電容組 成—個MOS的RC充電系統；在斷電時，電應會經由電晶體 义導通接地；在電源開啟的時候，輪出—開始為低電位； 經過約15US的時間，輸出由低電位轉為高電位，提供一個 起始訊號給其他數位控制電路使用。 圖6為數位類比轉換器114之電路圖，該數位類比轉換器 114包括複數個數位類比轉換區塊。其中數位類比轉換區塊 1為此電路之基本單位區塊，數位類比轉換區塊2至數位類 比轉換區塊η皆與該數位類比轉換區塊丨之電路設計相同。 在該數位類比轉換區塊1中b0〜b4與品〜s為控制電流輸 出的電流式二位元數位類比轉換器（binary_ weightd current DAC)之訊號，b4與印空制MSB，b〇與而控制lsb， 以此設計Μ娜5的寬度為的兩倍，的寬度為％^的 兩倍··以此類推。bO〜Μ為控制電流輸入的NM〇s，亦為電流 式一位兀數位類比轉換器，〜之長寬比照 %6〇5_。中間開關選擇控制訊號D或5將決定電流由正 向或由負向刺激神經，開關的做法為使用互補式金氧半電 晶體（CMOS)的傳輸閘來完成。 該數位類比轉換區塊！之基本操作規則為選擇b〇〜“與 bO〜Μ控制電流大小，1)與δ來控制刺激元件；舉例而言，當 D=1且Channel 1 = 1時，電流會經由乂奶〜％_與Channei工 和D所控制導通之開關，輸出至晶片外之銬形神經電極 1 (Nerve cuff eiectrode υ，同時間从祕〜风祕也會經由 Channel 1和D所控制導通之開關，將電流由晶片外之銬形 96283.doc -13· 1251986 神經電極i吸收回該數位類比轉換區塊丨内，達成控制以電 流控制神經之絲；反之若當㈣時，電流會〜〜〜_ 人<6〇5〜Μ,_所供應之電流路徑來進行刺激，以^位元達到 雙向電流刺激之效果。 而該數位類比轉換區塊丨至該數位類比轉換區塊11的致能 與否可以透過數位控制區塊丨丨3之輸出Channel丨〜Channei η 來進行控制，當Channel 1訊號為^夺，代表該數位類比轉換 區塊1可輸出電流刺激，反之當Channel i訊號為〇時，該數 位類比轉換區塊丨之輸出關閉，因此可藉此控制^個神經的 刺激與否。 圖7A為該數位控制區塊113之電路工作狀態圖，該狀態的 說明如下： S〇 ·閒置狀悲·此時電路之重置訊號（reset)處於〇的狀 態，當接收reset=l時，電路會開始進入S1預備狀態。 51 :預備狀態：一開始傳送器丨〇丨尚未開始傳送訊框的狀 怨’此時系統會等待同步封包並且將電源儲存在電容或電 池中。 52 :同步狀態：此時數位控制區塊113如接收正確之同步 封包（Synchronization packet)，内部接收器1〇5會與外部傳 送器101之時脈訊號同步，以利判別正確之資料傳輸率；此 時如接收到連續之同步封包，系統會持續與時脈訊號同步。 53 :資料讀取狀態：如系統在狀態82接收到起始封包 (start-up packet)，系統會將之後的封包辨識為資料訊框 (data frame)，並依照資料訊框之資訊給予數位類比轉換器 96283.doc -14- 1251986 114電刺激之指令。若在資料封包中判別出連續訊號 (continuous)為1，貝4電路會進入S4連續模式。 S4 :連續模式狀態：在此狀態中如沒有訊框輸入，電路 會依照之前資料訊框所給予的指令作連續刺激之動作，直 到由外部輸入訊框結束連續模式狀態，並進入S2同步狀態 重頭開始做時脈同步之動作。 圖7B為該數位控制區塊113之電路圖，該數位控制區塊113 包括一資料债測器（Data sense)701、一時脈還原器（cl〇ck rec〇Very)702及一封包處理器（Packet pr〇cessing)7〇3。分別說 明如下： 資料偵測器701 ··本電路為擷取^^^^ daU邊緣訊號的方 塊，參考圖7C所示，當資料（NRZdata)的邊緣和時脈（cl〇ck) 的上升緣非常靠近時，該資料偵測器70 1用以在下一個時脈 K號下降緣日守，將一邊緣備測訊號（data—sense)傳給時脈還 原器702做資料的抓取，這樣可以避免違反資料的保存時間 (hold_time violation)。 時脈還原器702 :—開始重置訊號（reset)會提供—i 5則的 reset 0重置汛號’當接收代化问時此區塊開始工作。當電 路接收到同步封包時，會將同步封包的時脈長度以計數方 式、己錄下來，並且在抓取資料封包的時候以訊 號啟動該封包處理器7〇3電路工作，並且以d〇ek——r⑽糟訊 號輸出讓封包處理器703辨認封包資料。 如圖7B所示，該封包處理器—電路迴授⑶此刪喊號 至該時脈還原電路7 〇2 ’此乃當封包處理電路偵測到 96283.doc -15- 1251986 continuous^之資料訊號時，即使在資料輸入（NRZ data)不 輸入的狀態下，該時脈還原器7〇2亦會將之前所同步之時脈 供應封包處理器703做連續刺激的動作。 封包處理器703 :當時脈還原器7〇2接收到資料封包後， 會將reset_behmd的訊號取消，使封包處理器開始工作。封 包處理器703的工作乃辨別資料是否為有效資料，並將資料 儲存在暫存器中供該數位類比轉換器114做電刺激 (stimulation)的輸出，時序如圖7d所示。 本發明之系統架構具有低複雜度與高可靠度之優點，非 常適用於醫療卫業上之植人式微電刺激系統，可望在靡疾 病患與植入式微電刺激研究上有所貢獻，深具實用性。、 惟上述實施例僅為說明本發明之原理及其功效，而非限 制本發明。m於此技術之人士可在不違背本發明^ 精神對上述實施例進行似及變化。本發明之_範圍應 如後述之申請專利範圍所列。 " 【圖式簡單說明】 統之無線傳輪系統 圖1為本發明用於植入式微電刺激系 架構不意圖； 圖2A為本發明功率放大器之電路示意圖； 圖2B為本發明功率放大器之工作示意圖； 圖3 A為本發明接收器内穩壓流程示意圖； 圖3B為本發明穩壓電路之電路示意圖，· 圖4A為本發明接收器内解調變流程示意圖 圖4B為本發明解調變電路之電路示音圖· 96283.doc 1251986 圖5為本發明混合訊號模組之電路示意圖； 圖6為本發明數位類比轉換器之電路示意圖； 圖7A為本發明數位控制區塊之電路工作狀態圖； 圖7B為本發明數位控制區塊之電路示意圖； 圖7C為本發明資料偵測器之時序示意圖； 圖7D為本發明無線傳輸系統之時序示意圖； 【主要元件符號說明】 10 本發明之無線傳輸系統 101 傳送器 102 指令產生器 103 功率放大器 104 傳送線圈 105 接收器 106 微印刷電路板 107 接收線圈 108 分壓器 109 整流裔 110 微電刺激單晶片 111 解調變電路 112 穩壓電路 113 數位控制區塊 114 數位類比轉換器 115 混合訊號模組 116 生物性電極 96283.doc - 17- 1251986 201 ASK調變器 202 起始電路 203 回授電路 l20" l202 電感或線圈之電感值 c20I ’ c202 功率放大器產生震盪所使用之電容 V。 傳送線圈兩端之電壓值 301 整流電路 302 降壓電路 303 啟動電路 304 帶差參考電路 305 錯誤放大器 306 輸出電路 401 整流單元 402 包跡線檢測器 403 電位比較器 404 負載驅動器 501 時脈訊號產生器 502 電源起始重置訊號產生器 501-508 反相器 bO〜b4、b0 〜b4 電流大小控制訊號 D與D 電流方向控制訊號 Channel 1 〜Channel n 頻道控制訊號 701 資料偵測器 702 時脈還原器 96283.doc -18- 1251986 703 NRZ data data—sense clock recover 封包處理器 由解調變電路還原之資料訊號 資料邊緣偵測訊號 資料傳輸時脈還原訊號 96283.doc 19-1251986 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a wireless transmission system, and more particularly to a wireless transmission system for an implantable micro-electric stimulation system. [Prior Art] The implantable micro-electric stimulation system is used in medical engineering to help some patients lose their action potential for electrical stimulation or medical treatment. In the structure of the implanted micro-electric stimulation system of the prior art, the transmitter and the receiver in the body and the outside are communicated by using the signal line hardware connection instead of using the radio frequency. The disadvantage of this method is the receiver. It must rely on the signal line that passes through the skin of the organism to communicate with the transmitter outside the organism, which not only causes the discomfort of the organism, but also causes the bacterial infection of the signal line to pass through the wound of the organism. Another alternative implantable micro-electric stimulation system architecture is to use a chipset at the receiver to interface with a number of passive components on a microlithographic plate, as opposed to using a system single chip (soc) at the receiver. In other words, although it is not necessary to penetrate the skin in a hard-to-tie manner, the area and volume of the implanted organism are relatively large and cause unnecessary power consumption (eg, US Patent Nos.: US 6,561,970 and US 6,402,689). . Therefore, it is necessary to provide an innovative and progressive wireless transmission system to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a wireless transmission system for implanting a micro-electric stimulation system, comprising: a transmitter and a receiver. The transmitter transmits control commands and power by radio frequency. The transmitter includes: an instruction to generate a 96283.doc 1251986 device, a power amplifier, and a transmitting coil. The command generator is used to generate control commands. The power amplifier is used to generate the f power. The transmitting coil is used to generate an RF signal, and the control command and power are transmitted. The receiver receives the control command and power with the radio frequency and generates a corresponding electrical stimulation output to the biological electrode of the implantable micro-electric stimulation system. The receiver comprises: a receiving coil, a micro printed circuit board and a micro-electric stimulation single chip. The receiving coil is configured to receive the control command and power transmitted by the transmitting coil, and the micro printed circuit board is configured to generate a corresponding control command and power to the micro-electric stimulation single chip according to the control command and power, The micro-electric stimulation single chip is used to receive the corresponding control command and power, and to stabilize and solve the biological electrode of the implantable micro-electric stimulation system. By using the wireless transmission system for the implantable micro-electric stimulation system of the present invention, communication and transmission of power between the inside and outside of the human body can be achieved by the wireless radio frequency signal. Moreover, the wireless transmission system of the present invention can reduce the area of implanted organisms and reduce power consumption, and has the advantages of low complexity and high reliability. [Embodiment] (5) is an architectural diagram of a wireless transmission system 10 for an implantable micro-electric stimulation system of the present invention. The wireless transmission system 10 includes a transmitter 1〇1 and a receiver 105. The transmitter i Q n can generate an electrical stimulation command message transmitting device encoded in the form of a packet, which transmits the control command and power with an RF signal. The transmitter 1〇1 includes: an instruction generating a cry (lnStrUCtl〇n genem〇r) 102, a power amplification ^ (P〇wl 96283.doc 1251986 amplifier) 103, and a transmitting coil (transmitter c〇u) i〇4. The instruction produces Ecology 02 to generate control commands. The power amplifier i 〇 3 is used to generate the required power. The communication coil 1〇4 is used to generate an RF signal to transmit the control command and power. The receiver 105 receives the control command and power of the RF signal and generates a corresponding electrical stimulus output to the biological electrode of the implantable micro-electric stimulation system. The receiver 105 includes a receiving coil 1〇7, a micro printed circuit board 106, and a micro-electric stimulation single chip. The receiving coil 〇7 is for receiving the control command and power transmitted by the transmitting coil 104. The micro printed circuit board 1〇7 is configured to generate a corresponding control command and power to the micro-electric stimulation single chip 11 according to the control command and power. The micro-electric stimulation single chip 11 is configured to receive the corresponding control command and power, perform voltage stabilization, demodulation, and interpretation of the control command to generate a corresponding electrical stimulation output to the implanted micro-electric stimulation system. Biological electrode 1 16 . The transmitter 101 includes the command generator 102, the power amplifier 1〇3, and the transmitting coil 104, respectively. The embodiments are as follows: The implementation of the command generator 102 uses the RS232 interface and the control program. Preferably, the preferred embodiment uses a personal computer with a Microsoft Windows operating system and a Visual Basic 2RS232 interface control program to generate a data signal output conforming to the RS232 packet. /Hai power amplification 1 〇3 implementation · In the implementation of various power amplifiers, class E power amplifiers are more efficient than a, B, AB power amplifiers, ideally achieve 1% power output . Referring to Figure 2, there is shown a schematic diagram of a preferred embodiment of the power amplifier of the present invention. - A basic E-class release 96283.doc 1251986 Dajie needs to include a transistor M, z2 (M, a load network of RLC to define the operating frequency, a capacitor parallel to the transistor) to adjust the resonant frequency , with a RF choke inductor to provide a stable current. The ASK modulation is implemented by adding an ASK modulator 201 between the power supply and the power amplifier. The maximum voltage supply for class E power amplifiers. The power supply for class E power amplifiers is controlled by an ASK modulator (ASK modulat〇r) 201, based on a single bit NRZ sequence generated from the command generator 1〇2. The data (NRZ daU) is supplied to a different power source of the class amplifier; in a preferred embodiment, the ASK modulator outputs a power of 5 ¥ when NRZ data=i; when NRZ is 匕=〇, Α § κ modulator output 3 V power supply, so you can control the amplitude of the transmission coil 丨〇 4 to achieve the effect of ask modulation. The working diagram of the class E power amplifier is shown in Figure 2B, the κ terminal power changes the switchable power Amplifier resonant circuit [(; parallel;) between series Aw] or 疋[Q series], the effect of the shock of this class e power amplifier is achieved. At the beginning, the K terminal needs to have a start-up circuit 2〇2 to give oscillation. Then, the two ends of the transmitting coil 104 generate an alternating current voltage of about 〇〇匕. The alternating voltage is induced by a feedback coil 2〇4, and the sine wave is sent through a feedback circuit 203. It is organized into a square wave and finally returned to K to form a self-oscillating Class E power amplifier. The final output can be supplied to the receiver via a transmitting coil with a 2 MHz RF signal. The transmission coil 104 senses the reception. The equivalent resistance value of the coil and the feedback coil. 96283.doc 1251986 The implementation of the transmission coil 104: In the implementation of the transmission coil, the higher the q value, the higher the transmission efficiency of the coil, and the use of Litz here. The line acts as a transmitting coil. It's better to vibrate. ~~ --Ί • As follows: Hebei Litz wire, strands 48 AWG? 175 stands for a bundle, — and 8 bundle of a line 14 turns, 8cm inner and 11.2cm outer /φ* rM /j. -- Diameter inductance value 28 uH, Q=580 coil voltage----J 200 k, 2 MHz sine wave Referring to FIG. 1, the receiver 105 of the wireless transmission system 10 of the present invention is receivable to be encoded into a packet form. The electrical stimulation command message receiving device receives the control command and power of the radio frequency signal by the receiver coil 107, and then passes through the voltage divider (v〇hage dlvlder) 108 on the micro printed circuit board 1 A voltage rectifier 109 is configured to generate a corresponding control command according to the control command, and the rectifier 109 is configured to generate a corresponding power according to the power. 5 Hai is electrically stimulated by a single chip 11 to be used for signal and power processing. The micro-electric stimulation single chip 110 includes a voltage regulator circuit 12, a demodulator circuit 111, a digital control block 13, and a mixed signal module (Mixed signal). Module) 11 5 and a digital analog converter (DACs) 114. The receiver coil 107 has the following specifications: Material 0.3 mm single wire size 13 turns, 2.8cm inner and 4.1cm outer diameter inductance value 10 uH, Q=30 coil voltage 30, 2 MHz sine wave The circuit for electrically stimulating a single chip is described as follows: 96283.doc 1251986 Referring to Figure 3A, a schematic diagram of the voltage regulation process within the receiver 105 is shown. The power of the receiver 105 is first passed through a rectifier 109 of the micro printed circuit board 106. The rectifier 109 includes a rectifier circuit 301 and a step_down circuit 302. The voltage regulator 112 in the single chip 11 is further stimulated via the micro-electricity to provide a stable power supply to the other circuits in the micro-electric stimulation single-chip 11 . According to an embodiment of the present invention, a sinusoidal wave having a power of -25V to +25V received by the receiving coil is rectified into a +25V sine wave signal via the rectifying circuit 301, and then the buck circuit is passed through the rectifying circuit 301. The voltage drop of 3〇2 is a + 5 V voltage with a ripple, and the regulator 112 performs voltage regulation and removes noise to provide a stable power supply of +3·3 V to the micro-electric stimulation single chip. 110 other circuits. Referring to FIG. 3B, the voltage regulator 112 includes: a start circuit (Stan_up Circuit) 303, a band difference reference circuit (Bandgap) 3〇4, an error amplifier (Error Amplifier) 305, and an output circuit (pass eiement). 〇 6. The regulated state 112 main sin-band difference reference circuit 3 〇4 provides a stable power supply that does not follow the power supply and temperature/shift, and is sent to a high-amplitude single-stage differential amplifier (generally referred to as an error amplifier in a linear regulator). 3〇5, and then sent to an output circuit with a very large aspect ratio (two/L), which constitutes a fast and stable lock loop. The start circuit before the tributary reference circuit 3〇4, its purpose It is provided with a DC bias starting from the difference reference circuit 3G4 to start quickly, and then the starting circuit 3〇3 will enter the working area due to the increase of the DC potential of the difference reference circuit 304. Schematic diagram of demodulation process. Receiver line 96283.doc 1251986 Circle 107 receives (+17 v, +25 V) and (-17 v, -25 V) carriers with an AC voltage of 2 MHz via RF signal. The voltage divider 108 of the micro printed circuit board 1〇6 is sent to the demodulation circuit 111 of the micro-electro-stimulation single-chip 11〇. The demodulated signal is transmitted to other circuits via the demodulator U1. Referring to FIG. 4B , which is a schematic diagram of the demodulation circuit. Embodiment of the present invention The ASK Demodulator is used. The demodulation circuit 111 includes a rectifier 4〇i, a pack trace detector ((e) elope detector), and a potential comparator (p〇tential). Comparator 403 and a load driver (ioa (j driver) 404. The rectifying unit 401 调整 adjusts the fading number to a positive half-cycle signal, and the packet trace detector 402 is used to extract the envelope trace of the signal. After the potential comparator 4〇3 determines the zeta potential and the low potential, the load driver 4〇4 is used to obtain the desired demodulation signal. The function of each block circuit is described in detail below: Rectifier unit 401: This The rectifying unit used in the embodiment of the invention is actually constituted by a positive swing voltage buffer (in general, the voltage signal rectification uses a diode detection circuit, but due to the process The size of the middle diode is quite large, and it is necessary to consider the load effect 〇(10) from the rectification early το 401 to the envelope detector 4〇2, so the positive swing voltage buffer can be used to signal the signal. Negative voltage The period is removed, on the one hand, it can resist the load effect. The envelope trace is detected as 402. · This circuit consists of a supply-independent biasing circuit. When the input is greatly fluttered, its output current And the voltage does not change with it, so even if the positive swing signal of the former stage enters, the original DC level of the signal can be locked, so the detection of the envelope trace is achieved. The potential comparator 403 is implemented using a Schmitt trigger (1) 仏 (5) (1) because the potential of the signal from the envelope detector will overlap, so the hysteresis of the Schmitt trigger is utilized. Phenomenon, you can distinguish the high and low potential of the detection signal to get the demodulation signal we want. The load driver 404 is disposed at the output end of the demodulation circuit lu, and is composed of two serially connected inverters (casca(je inverters). Since other circuits are connected behind the demodulation circuit 111, The driving force of the demodulation circuit 111 must be increased to avoid signal distortion. In this embodiment, the load driver 404 is added with an inverter in the front-end Schmitt trigger, and there are three inverters connected in series. They are designed to be larger and larger (the next size is about 2 to 3 times the previous one), which can increase the load driving force and stability. Figure 5 is a schematic circuit diagram of the mixed signal module 丨丨5. The mixed signal module 115 includes a clock signal generator 51 and a power source start reset signal generator 520. The mixed signal module is configured to provide a clock signal and a power start reset signal of the digital control block U3. The clock signal generator 51 is a five-stage ring oscillator, which is oscillated via the feedback circuit of the inverter 501 to the inverter 505, and is passed through the inverter of the last stage. The wave produces a 5MHz square wave clock. The crystal Mp5G1 is an initial circuit device. When the power supply starts, the transistor sense 5()1 will be like the switch open circuit, and the initial input of the inverter 501 will be kept in the ground state, ensuring that the pulse generation circuit can be correctly generated. The oscillating steady state generator 520 uses a plurality of transistors, wherein the electricity 96283.doc 12 1251986 crystal ~ ~ mp506 with its conduction t resistance and the capacitance between the transistor ~ 〇 7 - MOS RC charging system; in the case of power failure, the electricity should be grounded via the transistor sense; when the power is turned on, the turn-off starts to be low; after about 15US, the output turns from low to high, providing a The start signal is used by other digital control circuits. Figure 6 is a circuit diagram of a digital analog converter 114 that includes a plurality of digital analog conversion blocks, wherein the digital analog conversion block 1 is the basic unit area of the circuit. The block, the digital analog conversion block 2 to the digital analog conversion block η are the same as the circuit design of the digital analog conversion block. In the digital analog conversion block 1, b0~b4 and ~s is the signal of the binary-weighted current DAC that controls the current output, b4 and the printed MSB, b〇 and lsb, to design the width of the 55 Double, the width is twice the width of %^ · and so on. bO ~ Μ is the control current input NM 〇 s, also the current type one 兀 digital analog converter, ~ the aspect ratio according to %6 〇 5 _. The intermediate switch selection control signal D or 5 will determine whether the current is stimulating the nerve from the positive or negative direction. The switching is done using a complementary MOS transistor. This digital analog conversion block! The basic operating rule is to select b〇~"with bO~Μ control current magnitude, 1) and δ to control the stimulus element; for example, when D=1 and Channel 1 = 1, the current will pass through the milk ~%_ Switched to the outside of the wafer with the switch controlled by Channei and D, the Nerve cuff eiectrode υ, while the switch from the secret to the wind is also controlled by Channel 1 and D, the current is The outer shape of the wafer is 96283.doc -13· 1251986 The nerve electrode i is absorbed back into the digital analog conversion block, and the control is controlled by the current to control the nerve filament; if the current is (4), the current will be ~~~_ person< The current path provided by 6〇5~Μ,_ is used for stimulation, and the effect of the bidirectional current stimulation is achieved by the ^bit. The enabling of the digital analog conversion block to the digital analog conversion block 11 can be The output of the digital control block 丨丨3, Channel丨~Channei η, is controlled. When the channel 1 signal is ^, it means that the digital analog conversion block 1 can output current stimulation, and when the channel i signal is 〇, the digit Analog conversion block It is closed, so that it can control the stimulation of the nerves. Fig. 7A is a circuit operation state diagram of the digital control block 113, and the state is explained as follows: S〇·idle sorrow·replacement of the circuit at this time The signal is in a squat state. When receiving reset=l, the circuit will start to enter the S1 standby state. 51: Ready state: At first, the transmitter 丨〇丨 has not started to transmit the frame's complaints. Synchronize the packet and store the power in the capacitor or battery. 52: Synchronization state: At this time, if the digital control block 113 receives the correct synchronization packet, the internal receiver 1〇5 and the external transmitter 101 will be synchronized. The signal is synchronized to determine the correct data transmission rate; if the continuous synchronization packet is received, the system will continue to synchronize with the clock signal. 53: Data read status: If the system receives the start packet in status 82 (start -up packet), the system will recognize the subsequent packet as a data frame, and give the digital analog converter according to the information of the data frame 96283.doc -14- 1251986 114 Electrical stimulation If the continuous signal is determined to be 1 in the data packet, the beta 4 circuit will enter the S4 continuous mode. S4: continuous mode state: if there is no frame input in this state, the circuit will follow the previous data frame. The given command is continuously stimulated until the continuous mode state is terminated by the external input frame, and the S2 synchronization state is entered to start the clock synchronization operation. FIG. 7B is a circuit diagram of the digital control block 113. The digital control block 113 includes a data sense 701, a clock restorer (cl〇ck rec〇Very) 702, and a packet processor (Packet). Pr〇cessing) 7〇3. The descriptions are as follows: Data Detector 701 · This circuit is a block for extracting ^^^^ daU edge signals, as shown in Figure 7C, when the edge of the data (NRZdata) and the rising edge of the clock (cl〇ck) When in close proximity, the data detector 70 1 is configured to transmit a data-sense signal to the clock restorer 702 for data capture at the next clock K number. Avoid violations of the data retention time (hold_time violation). Clock Restorer 702: - Start reset signal (reset) will provide - i 5 reset 0 reset apostrophe 'This block starts working when receiving the proxy. When the circuit receives the synchronization packet, the clock length of the synchronization packet is recorded in the manner of counting, and when the data packet is captured, the packet processor 7〇3 circuit is activated by the signal, and d〇ek - r (10) bad signal output allows the packet processor 703 to identify the packet data. As shown in FIG. 7B, the packet processor-circuit returns (3) the spoofing number to the clock recovery circuit 7 〇 2 '. This is when the packet processing circuit detects the data signal of 96283.doc -15- 125 1986 continuous^ At this time, even when the data input (NRZ data) is not input, the clock restorer 7〇2 also performs the continuous stimulation action by the previously synchronized clock supply packet processor 703. The packet processor 703: after receiving the data packet, the clock restorer 7〇2 cancels the signal of the reset_behmd, so that the packet processor starts working. The operation of the packet processor 703 is to determine whether the data is valid and store the data in a scratchpad for the electrical output of the digital analog converter 114, as shown in Figure 7d. The system architecture of the invention has the advantages of low complexity and high reliability, and is very suitable for the implanted micro-electric stimulation system in the medical and health industry, and is expected to contribute to the research of the disease and the implanted micro-electric stimulation. Practical. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. The above embodiments can be modified and changed without departing from the spirit of the invention. The scope of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an implantable micro-electric stimulation system architecture; FIG. 2A is a schematic diagram of a power amplifier of the present invention; FIG. 2B is a schematic diagram of a power amplifier of the present invention; Figure 3A is a schematic diagram of a voltage regulation process in a receiver of the present invention; Figure 3B is a circuit diagram of a voltage regulator circuit of the present invention, and Figure 4A is a schematic diagram of a demodulation process in a receiver of the present invention. Circuit diagram of a variable circuit. 96283.doc 1251986 FIG. 5 is a circuit diagram of a mixed signal module of the present invention; FIG. 6 is a circuit diagram of a digital analog converter of the present invention; FIG. 7A is a circuit diagram of a digital control block of the present invention; Figure 7B is a schematic diagram of the circuit of the digital control block of the present invention; Figure 7C is a timing diagram of the data detector of the present invention; Figure 7D is a timing diagram of the wireless transmission system of the present invention; Inventive Wireless Transmission System 101 Transmitter 102 Command Generator 103 Power Amplifier 104 Transmit Coil 105 Receiver 106 Micro Printed Circuit Board 107 Receive Coil 108 voltage divider 109 rectification 110 micro-electric stimulation single chip 111 demodulation circuit 112 voltage regulator circuit 113 digital control block 114 digital analog converter 115 mixed signal module 116 biological electrode 96283.doc - 17- 1251986 201 ASK modulator 202 Starting circuit 203 Feedback circuit l20" l202 Inductance or coil inductance c20I ' c202 The power amplifier generates a capacitor V for oscillation. Voltage value 301 across the transmitting coil Rectifier circuit 302 Buck circuit 303 Start circuit 304 Band difference reference circuit 305 Error amplifier 306 Output circuit 401 Rectifier unit 402 Packet line detector 403 Potential comparator 404 Load driver 501 Clock signal generator 502 Power Start Reset Signal Generator 501-508 Inverter bO~b4, b0~b4 Current Size Control Signal D and D Current Direction Control Signal Channel 1 ~ Channel n Channel Control Signal 701 Data Detector 702 Clock Restore 96283.doc -18- 1251986 703 NRZ data data-sense clock recover The packet processor is demodulated by the circuit to recover the data signal data edge detection signal data transmission clock recovery signal 96283.doc 19-