TWI251272B - Method of forming self-aligned metal silicide - Google Patents

Abstract

This invention relates to a method of forming self-aligned metal silicide (silicide) and, more especially, to a method of forming self-aligned metal silicide in partial region. The invention uses the silicon layer as a mask layer to form a local self-aligned metal silicide on the logic circuit. A metal silicide is formed on a gate in cell array region while no metal silicide is formed in a diffusion region. The gate and diffusion regions can be formed with metal silicide in periphery circuit regions. The method of this invention is able to obtain lower resistance for the semiconductor device, and the drawback of leakage current is not likely to occur.

Description

1251272

5 - 1 FIELD OF THE INVENTION: 曰 MODIFICATION The present invention is a method of forming a self-aligned metal telluride, and more particularly to a method of forming a self-aligned metal telluride in a partial region, 乂 smoothly in the peripheral circuit region and the unit cell The gate region on the array region and the diffusion region on the peripheral circuit region form a metal germanide so that the semiconductor device obtains a lower resistance and is less likely to cause a leakage current.

5-2 BACKGROUND OF THE INVENTION ▲The degree of integration of the component increases, so that the source/drain resistance of the MOS transistor gradually rises to the channel of the MOS transistor. When the resistance of channe丨 is equivalent, in order to reduce the source/> and the sheet resistance of the pole, and to ensure the shallow junction between the metal and the MOS transistor (shai i〇w junct i〇n) The application of a complete process called "self_aHgned si 1 pesticide" has gradually entered the ultra-large integrated circuit below 5 micrometers (micr〇n; #m) Very iarge scaie a Qin integration; VLSI) process. This process is therefore referred to as the self-aligned metal salicide process. The most commonly used metal halides are the first to promote titanium halides. The formation of titanium telluride generally adopts a two-stage rapid heating process (RTP). First, referring to the first figure,

1251272 — Case No. 90118555 Year Month_Day Revision V. INSTRUCTIONS (2) A stone substrate 10 is provided, and a gold oxide semi-transistor and a shallow trench isolation layer 30 have been formed on the substrate. The MOS transistor has a source/drain region 丨2, a gate, and a spacer 18 formed on a sidewall of the gate, and the gate includes at least a gate oxide layer 14 and a polysilicon layer 16 Then, a layer of titanium metal 20 is deposited on the substrate 1 by chemical vapor deposition (CMP) or direct current magnetron sputtering. The thickness of the titanium layer 2 About ο 埃. Next, a first rapid heating process is performed to react the titanium metal with the ruthenium layer at the contact to form a titanium ruthenium having a thickness of between about 6 7 and 7 〇〇. The structure of the titanium telluride is mainly the structure of the c_49 phase with a relatively high resistance value. Referring to the second figure, the RCA cleaning method is used to remove the titanium metal remaining after the reaction or the reaction, and the titanium germanium compound layer is removed. Leaving on the outermost surface of the gold-oxygen semi-transistor. This is not involved in the reaction or the reverse: the metal is not visible - it will be left in the form of titanium. Finally, the second rapid heating process is performed, and the C-49 phase is titanium. Lower telluride structure conversion value The structure of the C-5 phase is important. In the process of deep submicron components, it is important to treat the source/drain in order to avoid the decay of the transistor drive current caused by the source / :::: resistance. And the widely used process technology. Pure source / bungee deuteration treatment, or by self-satisfaction of the straw field ^. The self-feeding metallization process can be a chemical process and the idle process of the stone. Source/pole

1251272 曰-----SS__90118555_ V. Description of invention (3) In order to reduce the coordination in the formation of gold and the traditional metal stone area, the traditional must be applied to the current logic circuit, the t-resistance of the conduction layer and increase the guidance / need The use of metal lithium logic circuits operates in the quality of Thunder pieces. However, in order to be a telluride, in order to prevent the self-aligned metal telluride in a part of the circuit of the main circuit, the leakage current is defective. The compound must form a metal telluride through a relatively 'different part of the material. In: Qin: The method of the present invention can be used in the more time-consuming steps required to speed up the process of the invention to accelerate the process; the body-process, must be _ 5 - 3 invention purpose and summary: Looking forward to the above invention In the above method, the metal bismuth compound cannot be formed locally on the logic circuit by the method of transmitting the button ΦL ', j, and the first method of the present invention utilizes a mask layer P ' array F Η p ...? t peripheral circuit area and cell: : the idle pole on the domain and the diffusion region on the peripheral circuit region form a metal

Object to reduce the resistance of the cell array region to the peripheral circuit region w〇rd line). - 兀琛C The second object of the present invention is to form a metal smear in the diffusion region of the gate region and the peripheral region on the peripheral circuit region and the cell array region by using the mask sound as a layer of the layer. To avoid the leakage current leakage in the diffusion region on the cell array region. One

1251272

The third object of the present invention is a helmet; the 丨田_μ院丨密利产田心心目 aims to use a layer of the layer as a mask layer, the area = domain and the cell gate array area and the periphery The fourth domain of the present invention is to reduce the thickness of the peripheral circuit region by using a barrier layer, a gate layer on the domain, and a peripheral circuit to improve the semiconductor device. The region and the diffusion region on the region of the cell array region form a metal telluride quality. Now, %% I Dan is intended to utilize a layer of germanium = a diffusion region on the & field in the peripheral circuit region and the cell array region. The formation of metal telluride, peripheral circuit process efficiency. # N + Conductor Element According to the above purpose, the present invention provides a mask layer as a layer of germanium, which is successfully tested in the peripheral circuit region, utilizing the gate on the region and the diffusion region on the peripheral circuit region. ^=cell array to reduce the cell array region and the peripheral circuit region or the metallization and avoid the leakage of the diffusion region on the cell array region. The method of the invention can also reduce the peripheral circuit region. The resistance on the upper side, the defect of L. This method can improve the quality of semiconductor components and improve the efficiency of semiconductors. , the process of the piece of equipment 5 4 invention details:

1251272 Some embodiments of the invention are described in detail below. However, the invention may be broadly defined in other embodiments without limitation. In the following patent scope, the logic circuit is mainly by word line (w〇rd 11〇6) and bit. Line) to connect the semiconductor components on the logic circuit. The word is defined as the position of the signal, and the purpose of the bit line is the decision type, so the word line is connected to the gate of the semiconductor element and to the source/drain on the semiconductor element. For the word line, there is a higher transmission speed transmission data. Therefore, it is necessary to form a metal-deuterated low-word line resistor on the word line and the gate of the semiconductor element to improve the transmission speed of the word line. Except for detailed implementation, and accurate. The bit line (the line of the source line or the like is connected, which requires the method of the method to store the metadata of the function of the logic cell array area, and the components such as the device must be individually unilaterally circuitized by the peripheral power. Therefore, the pole and the diffused circuit are in the other stored data piece of the main domain. By the surrounding power, the required path is led to prevent the components of the domain from being used, and the area must be divided into regions, and the data and peripheral circuit regions are In other areas of the internal processing, the short circuit must be carried out in the vicinity of the metal regions of the present invention. The electrical components of the two regions are carried out by the component materials of the charge path region. Therefore, the mode of interconnection, the compound, the domain, and the mode of the road region are , such as processing, the cell array is used to add one to the periphery at the same time. The unit cell is stored in the flow fast data circuit area of the crystal region for the transfer device to be the crystal array region crystal After the cell array is guided or operated, or after subtraction, the components that are borrowed must be lost.

1251272 Case No. 901185昍5, invention description (6) The formation of the diffusion region force on the metal-parallel region of the gate and the data computing capability of the gate cause the data to flow, and avoid the metal domain to accelerate the peripheral electricity and prevent the crystal The cell array is lost. The leakage current is formed in the data transmission energy region of the cell array region. Referring to the third figure, a wafer containing the substrate 1 is first provided and a substrate 100 is formed. A first oxide layer 12 is formed, a nitride layer 140 is formed on the first oxide layer 120, and a second oxide layer 160 is formed on the nitride layer i4f. Typically, the first oxide layer 丨 2 " 〇 has a thickness of about 70 to 90 angstroms, the nitride layer 140 has a thickness of about 6 〇 to 8 Å, and the second oxide layer 160 has a thickness of about 60 to 80 angstroms. . In the current process, the thickness of the first oxide layer 120 is generally 8 Å, the thickness of the nitride layer 140 is 70 Å, and the thickness of the second oxide layer 160 is Å. However, as the width of the process is gradually reduced, the thicknesses of the first oxide layer, the nitride layer, the layer 110 and the second oxide layer 16 must also be reduced to meet the processing requirements. Referring to the fourth figure, after the cell array region 104 and the peripheral circuit region 1〇2 are defined on the wafer, the peripheral circuit region 102 is removed by a photolithography and an etching method. The first oxide layer 120, the nitride layer 140 and the second oxide layer 160 are disposed to expose the peripheral circuit region 1〇2 to the substrate. Referring to the fifth figure, a third oxide layer 200 is formed on the substrate of the peripheral circuit region 102. The thickness of the third oxide layer 20 is about 40 to 60 angstroms. In the current process, the third The thickness of the oxide layer 200 is typically 50 angstroms. But with

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__ Case No. 90118^ V. Description of the invention (7) The width of the process is gradually reduced. The thickness of the third oxide layer 2 must also be reduced to meet the requirements of the process. Usually, the material of the first oxide layer 丨2〇& ^ oxide layer 160 and the tantalum oxide layer 200 is silicon dioxide, and the material of the nitride layer 140 is usually silicon nitride. In the present embodiment, the cell array region on the wafer and the peripheral circuit region employ different dielectric layers on the substrate. A sandwich type of oxide/nitride/oxide is used as the dielectric layer on the cell array region, and a single layer of oxide is used as the dielectric layer in the peripheral circuit region. Depending on the process requirements, the same form of dielectric layer can be used on the substrate in the cell array region and the peripheral circuit region to achieve the performance of the semiconductor device. The dielectric layer can be an oxide layer.

# Referring to the sixth figure, a germanium layer 3 is formed over the second oxide layer 16? and the second oxide layer 2?, and the germanium layer 3 is a gate layer. Referring to the seventh figure, the position of the gate is defined on the peripheral circuit area 1〇2, and a part of the germanium layer on the peripheral circuit area 1〇2 is removed by a lithography and etching process to be around. A plurality of first gates 400 and a plurality of first diffusion regions 45A are formed on the circuit region 〇2, and the plurality of first diffusion regions 45 〇 are located on both sides of the first plurality of first gates 4 夕. Next, a lightly doped drain (LDD) process is performed to form a lightly doped drain region 3 2 在 in the majority of the first expanded region 450. The purpose of this process is to reduce the defects caused by the h〇t carrier effects.

Page 10 1251272 ____ Case No. 90118555_ Year Month Day Correction V. Invention Description (8) Referring to the eighth figure, after the process of lightly doping the drain, in the second oxide layer 160, crystal a spacer layer 300 is formed on the cell array region 110, a plurality of first gates 400 and a plurality of first diffusion regions 420 are formed on the cell array region by a lithography and etching process. A spacer 500 is formed on the sidewall of the plurality of first gates 40 0 on the cell array region 104. Referring to the ninth figure, after defining the position of the gate/drain on the peripheral circuit region 1 〇 2, the ions required for the process are implanted to form a source in a plurality of first diffusion regions 450 / Nothing 5 5 0. Referring to FIG. 10, a metal layer 600 is formed on the germanium layer 300 on the cell array region 1〇4, the plurality of first gates 40 0 and the plurality of first diffusion regions 450, before depositing the metal layer. First, the wet layer cleaning method is used to remove the oxide layer on the substrate and the oxide on the substrate, so that the metallization is easier to form. Most use chemical vapor deposition or

Magnetron DC plating is used to deposit this metal layer 6 〇 〇. Next, the wafer is sent to the reaction, and the first rapid heating process is performed in the chamber, so that the metal layer 6 反应 reacts with the stone in the contact portion to form a metal siiicide. Or in the array of unit cells after the majority of the first tenth reaction, the structure of C-49 is the only one. The temperature of the first speed of the reheating process is approximately 500 to 7 Torr. The structure at this time is mainly a structure of a c-49 phase having a high resistance value. Referring to the RCA cleaning method, the metal layer 600 not participating in the reaction is removed, and the metal germanium compound layer 62 is disposed on the germanium layer 3 of the germanium region 104, and the plurality of first gates and the bulk region 450. Finally, the second rapid heating process is performed. The metal halide structure is converted into a c 5 4 phase with a low resistance value. The temperature of the idle heating process is about 7 5 .

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V. Description of the Invention (9) The material of the metal layer 600 may be a material of the titanium metal layer 60 0. The titanium is usually used for this purpose. In order to meet the needs of the process, before the 600 layer, most of the first-diffusion regions are removed. To improve the quality of semiconductor components: 1 of the second oxide Titanium is now the best in the self-aligned metal telluride process. At the appropriate temperature, Qin is easy to form with gold - (It is formed by the interdiffusion of Ultanium silicide; TiSi2). y di: In the process of metal lithium, the Γ Γ 6Γ on the array of 9 曰曰 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Self-aligning the metallization of the metallurgical layer, and then removing the gate layer on the array of cell arrays by a lithography and etching process. A plurality of second gates 7A and a plurality of second diffusion regions 75 0 are formed on the second oxide layer 160. The plurality of second diffusion regions 75 are located on either side of the plurality of first gates 70 〇. When the etching process of the germanium layer on the partial cell array is removed, the residual process may stop at the second oxide layer 〇6〇, the nitride layer 丨4〇 or the first oxide layer 120. According to the embodiments described above, the present invention provides a method for smoothly forming a diffusion region on a gate region and a peripheral circuit region on a peripheral circuit region and a cell array region by using a mask layer as a mask layer. Metal telluride to reduce the resistance of the word line of the cell array region and avoid cell arrays

Page 12 1251272 Case No. 90118555 Month 修正 Amendment V. Invention Description (10) Defects in leakage current in the diffusion region of the area. The present invention also reduces the resistance on the peripheral circuit area. The invention can improve the quality of the semiconductor component and improve the process operation efficiency of the semiconductor component, and has the practical effect, and is unprecedented in design, has the improvement of efficacy and progress, and thus has met the requirements of the patent law. Apply in accordance with the law. To this end, I would like to ask the review committee for detailed review, and pray for granting patents as soon as possible. The above is only the preferred embodiment of the present invention, and this embodiment is for illustrative purposes only and is not intended to limit the scope of the invention. It is still possible to carry out the invention without departing from the spirit and scope of the invention, and such variations are still within the scope of the invention. Accordingly, the scope of the invention is defined by the scope of the following claims.

Page 13 SS.^90118555 !251272

i month _itJL diagram simply shows the genus layer = show, ^ using traditional techniques to deposit a titanium on the gold-oxygen semi-transistor π ί two maps using conventional techniques in the gate region and the source / drain region A schematic diagram of forming a titanium telluride; forming a first oxide layer and a nitride layer on the first substrate; a first oxide layer of the layer and the ==== region, a nitride buck; The triple oxide layer is on the substrate of the peripheral circuit region; the upper layer is formed to form a germanium layer on the second oxide layer and the third oxide layer to form a lightly doped drain electrode: in the peripheral circuit The region forms a majority of the first-gate and most of the brother-diffusion zones, and is not intended in the majority of the first diffusion zone; the side layer and the majority of the first gates page 14 1251272 case number 90118555 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 9 is a schematic diagram showing the formation of a source/drain in a plurality of first diffusion regions, and the tenth is a layer in which a metal layer is formed on a cell array region, and a plurality of first gates are formed. Schematic diagram with a plurality of first diffusion regions; eleventh image is at the unit cell A schematic diagram of forming a metal germanium compound layer on the germanium layer, a plurality of first gates, and a plurality of first diffusion regions on the column region; and a twelfth pattern forming a plurality of second gates on the second oxide layer A schematic representation of a plurality of second diffusion regions. Representative symbols for the main parts: 10 Substrate Φ 12 Source/drain region 14 Gate oxide layer 16 Polysilicon layer 18 Gap 2 0 Titanium layer 22 Titanium bismuth compound layer 30 Shallow trench isolation layer 1 0 0 Material 102 Peripheral Circuit Area 1 0 4 Cell Array Area

Page 15 1251272 Case No. 90118555 Corrective Description of Modification 120 140 160 200 300 320 400 450 500 550 600 620 700 750 First oxide layer nitride layer second oxide layer third oxide layer 轻 layer lightly doped a plurality of first gates, a plurality of first diffusion regions, a plurality of first diffusion regions, a source/drain metal layer formed in a plurality of first diffusion regions, and a plurality of second gates Two diffusion region Φ

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Claims (1)

1251272 Ref. No. 90118555. The method for modifying a seed to form a self-aligned metal telluride in a partial region, comprising at least: providing a formation of a first formation of a nitrogen to form a removed portion of the layer to form on the wafer Forming a stone to remove a portion of the gate and a plurality of the plurality of wafers, the crystalline oxide layer comprising at least one substrate in the circle; the layer of the compound on the first dioxide layer a first region of the second oxide is exposed on the oxide layer in the diffusion region, and the first oxide layer is on the first substrate of the first first gate; a nitride layer; a layer, a nitride layer and a first oxide exiting the substrate; a substrate on the first region; a layer on the third oxide layer; and a plurality of layers on the first region a plurality of sidewalls of the plurality of first diffusion regions form a spacer to implant an ion between the plurality of first gates and the germanium layer to form a pole/drain region in the plurality of first diffusion regions; More than * metal An electrode, the most spread joy & domains on the silicon layer; a stem! a rapid heating process to form a metal telluride layer on the plurality of first-interpoles, the majority-diffusion region and the germanium layer; removing the metal layer; and one of the germanium layers: in addition to the rt Part of the metallization layer to form a plurality of second gates on the first region of the wafer and - a plurality of second extensions 1251272 Case No. 90118555 Month 修正 Amendment VI. Patent Application Scope. 2. The method of claim 1, wherein one of the metal layers is titanium. 3. The method of claim 1, wherein the material of one of the metal layers is the beginning. 4. The method of claim 1, wherein one of the metal layers is platinum. 5. The method of claim 1, wherein the first region is a peripheral circuit region. 6. The method of claim 1, wherein the second region is a cell array region. 7. A method of forming a self-aligned metal lithium in a localized region, comprising at least: providing a wafer comprising at least one substrate; forming a first oxide layer on the substrate Forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; removing a portion of the second oxide layer, the nitride layer and the first oxide Page 18 1251272 Case No. 90118555 曰 Amendment 6. Applying a patent range layer to expose the substrate in a first region of the wafer; forming a third oxide layer on the substrate of the first region; forming a a layer of germanium on the second oxide layer and the third oxide layer; removing a portion of the germanium layer to form a plurality of first gates and a plurality of first diffusion regions on the first region a plurality of first diffusion regions are located on one side of the plurality of first gates; forming a lightly doped drain in the plurality of first diffusion regions; forming a spacer on the plurality of first gates One side of the layer is implanted with an ion to form a source/drain region in the plurality of first diffusion regions; a metal layer is formed on the plurality of first gates, and the plurality of first diffusion regions And performing a first rapid heating process to form a metal telluride layer on the plurality of first gates, the plurality of first diffusion regions and the germanium layer; removing the metal layer and performing a Second rapid heating process; and removing part of the Layer and the metal silicide layer to form a portion of the plurality of second gate and a plurality of second diffusion region of the second region on one wafer. 8. The method of claim 7, wherein one of the metal layers is titanium. 9. The method of claim 7, wherein one of the above metal layers Page 19 1251272 ΛΜ 90118555 VI. Scope of Application The material is cobalt. Month 修正 Correction 1 〇 · If the patent application area is 7th, the material is platinum. The method of the member, wherein one of the above metal layers is 11 · as in the patent application range 7 a peripheral circuit area. The method of the present invention, wherein the first region is a partial region forming a self-aligned gold (four) material, the substrate, the substrate is provided with at least one wafer, and the wafer comprises at least one first region and one a second region; forming an oxide layer on the substrate; forming a germanium layer on the oxide layer; removing a portion of the germanium layer to form a plurality of gates and a majority on the first region a first diffusion region, the plurality of first extensions 7 are located on one side of the plurality of first gates; the sidewall of the κ dare region forms a gap wall at a plurality of first gates and a source of the layer Implanting an ion to form a pole/drain region in the plurality of first diffusion regions; Page 20 1251272 amendment -- Case No. 901 彳 Lang [^ Sixth, the scope of application for the patent = metal layer on the majority of the first gate, the majority of the first diffusion region and the layer of 矽; ^ expansion Chu, 仃 a rapid heating process Forming a metal telluride layer on the plurality of first gates, the plurality of diffusion regions and the germanium layer; removing the metal layer; and etching the germanium layer and a portion of the metal germanide layer to The wafer is formed by a plurality of second gates and a plurality of second expanded metal layers. The method of claim 13 wherein the upper material is titanium. 〃 t5·# For example, in the method of claim 13, the material of the above metal layer is Ming·. = The method of claim 13, wherein the material of the above metal layer is platinum. The method of claim 13, wherein the first region is a peripheral circuit region. The method of claim 13, wherein the second region is a unit cell array region. Page 21