1250833 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種整合半導體晶片之電路板製法，尤 指一種藉由相對位標軸定位方式而有效提供半導體晶片位 置，並據以整合於電路板之製法。 【先前技術】 為保護半導體晶片，避免外界環境之影響，同時亦便 於操作、運輸、測試，通常半導體業界所採用之手段係以 封裝件之形式封裝已完成半導體積體電路製程之半導體晶 片。惟於封裝件内，用以承載半導體晶片之ic基板，係 1C基板製造業者依據半導體封裝件製造業者或1C設計者 所提供之設計資料製成，並交付於半導體封裝件製造業者 進行後續封裝，於是半導體封裝件製造業者於該些半導體 晶片之1C基板上進行黏晶、打線、植球等製程。因此，完 成半導體封裝件需涉及1C基板製造業者及半導體封裝件 製造業者，存在界面整合之問題，且耗費大量資金及時間。 為解決界面整合之問題，簡化半導體晶片封裝件製 程，遂發展出一種埋入式晶片之電路板結構，其主要係於 晶片完成半導體積體電路製程之後，嵌埋晶片於電路板 中，在晶片之電性連接墊上形成向外延伸之導電線路。 即如第1A圖至第1 E圖所示，係為埋入式晶片之電 路板製法示意圖。如第1A圖所示，提供一完成積體電路 製程之晶圓10，其包含有複數個晶片100，該些晶片100 上形成有電性連接墊1 03。如第1B圖所示，將晶圓10切 17931 Ϊ250833 割成複數個晶片10〇，之後即可將該晶片1〇〇嵌埋於電路 板105之預設開孔1〇7中，該晶片1〇〇係可以一黏著材暫 日寸固定（圖中未示）。如第lc圖所示，於該整合有晶片1〇〇 之電路板105上形成一絕緣層109，例如熱硬化性樹脂。 如第1D圖所示，以雷射技術於該絕緣層1〇9上形成複數 们開口 111，其中，該等開口 111對應於晶片之電性連接 墊103位置，俾外露出該電性連接墊1〇3。其後進行除膠 渣（De-smear )作業。如第1E圖所示，於該絕緣層及其對 應開口 $表面形成圖案化線路層121，並使該圖案化線路 ^ 得以黾性連接至該晶片1 〇〇之電性連接墊1 〇3。 先惟f上述製程中，所有製程步驟（不論晶片放置或雷射 每技日白以毛路板的對革巴點作為影像基準對位點，但於 片放置過私中，並無法报準確的根據基準點相對位 電：;=:的放置於電路板開孔，其主要原因在於··該 :置於：政片放置孔之精度誤差為土 25μηΐ;且該晶片 放置於電路板時誤差 絕緣層壓5G_;以及該w放置後於 晶片係祐：晶片移動。再者，於後續製程中 辦視。其路板中’其晶片對位點將無法再由影像 之電性製程雷射鑽孔作業無法於“ 衣作出精確的盲孔（士 ip 無法應用在且有古玄疮+t目孔（如弟IF圖所不），進而 板及絕緣層；;；；；Γ輪出入端的產品。甚而該電路 板中之位置發二=冷縮將導致-之晶片在電路 晶片之電性連接塾:Μ热法丰確形成圖案化線路層與該 連接塾之良好電性連接，導致半導體封裳件良 17931 6 1250833 率不佳’嚴重影響半 因而，如何二1¥脸衣置性能’甚至引起失效現象。 並電性連接製程以將半導體晶片整合 時間，同時準確反肖以即’半導體裝置之製程成本與 效於其二:=之電性連ί墊位置’以供後續有 【發明内容】°係為目刖亟待解決之問題。 挺5 X上所述習知技術之缺點，本#明之*至 ^供-種整合半導體晶片之電路板製法：：：主要目的係 片整合並電性連接於 — ’、可將半導體晶 成本與時間。、电路板’错以節省半導體裝置之製程 本發明之另一目的係提供 路板製法，其可準確得知整合於電_^肢晶片之電 電性連接墊位置，以供後浐 之半導體晶片之 為達上述及其他目V本^其上延伸出線路結構。 路板製法’主要係在晶片完 ：：，曰曰月之電 用嵌埋、直接置放等方式將曰片^積狃琶路製程後，採 板可為-"邑緩μ 片整合於承载板中，該承载 板Τ為H緣板或已具線路之電路板·二戟 裝置，確定該承載板之定位點位 心？ ’錯由疋位 載板中之相對座標值，並將爷 °己、彔晶片於該承 以供在該相對座標軸上確定後續 貝科庫， 致的晶片位置偏移量；之後，於該熱脹冷縮所導 形成-絕緣層，該絕緣層為線路增層之承載板上 據該承載板及絕緣層於製程中 θ衣壬而之材料；依 資料輸入至該資料庫中；自將該脹縮 双家日日片於承載板位置 17931 7 1250833 之相對座標值，及録巾承餘及 定晶片實際相對承載板位置，俾”料’以判 應晶片電性連接塾位置之開口以;;準確形成對 淨曰由頰衫，雷射鑽孔，電漿蝕刻等方 " 之開口；其後即可在該絕緣 ^ σ〜二則、 少一圖宰化崎敗恳- 耵4之開口表面形成至 έ1^ " g，错以在晶片之電性連接墊##λ 線路，可供與外界作電性連接。 狀伸出w 亦即，本發明之整合晶片之電路制 晶片埋入或置於-例如為絕緣板或電路::承=、在將 影像辨視系統先將承载板的定位點記錄丄； 點將每個接置於承載板中之晶 2疋位 下來，如此即可明確得知每個晶片相對對t置記錄 相對位署,^ ^ 曰乃祁對衣承载板定位點的 置有半導㈠等座標參數，之後即可將該接 雷射鑽孔板進線路製程，當製程到達 對位點，配人考母個晶片對位點相對於承載板的 鑽孔機中^里 材料脹縮情形，輪人至例如雷射 對w 雷射鑽孔機就能以承載板之對位點精確的 ==孔製程，而排除因一電路板時所造 中4样B本&明之整合晶片之電路板製法係可於資料庫 絕接置於承載板之相對座標資料，配合承載板及 置，二 冷縮情況，準確覆蓋於絕緣層下之晶片位 續延=错由對應晶片連接塾之準確開口，以有效提供後 " 路之製作。亦即，本發明可依據原始承載板位置 17931 8 1250833 及晶片接詈# w 層熱脹冷縮4::s;合後續製程引起之承載板、絕緣 開口之位置，確置偏移’調整形成於絕緣層中 係將半二Γ:能之影響’提升了良率；另本發明 即 省半導俨梦^制％r生運接至书路板結構中，俾可 且衣置之製程成本與時間。 【實施方式】 j 了^藉由4寸（的具體實施例説明本發明之實施 式’熟習此技敲之人本π丄丄、 ^ ^ 可由本δ兑明書所揭示之内容县从 瞭解本發明之其他優 工也 AA曰 與功效。本發明亦可藉由其他不回 的/、體實施例加以施行 ° 可其於T w .. 1應用本§兄明書巾的各項細節亦 土、 5硯點與應用，在不悖離本發 種修飾與變更。 卜進仃各 請參閲第2圖所示，係為本發明之整 電路板製法流程示意圖，同時配合第”3g圖之二， 剖面示意圖，藉以說明本發明之實施態樣。 衣％ 於步驟S1，首先將一半導體晶片21嵌埋入 2〇之預設開孔200 (如第2A圖所示)。該晶片21已 導體積體電路製程，其表面已形成有複數電性連接塾 21〇,該承載板20可為—般絕緣層、金屬板1250833 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board manufacturing method for integrating a semiconductor wafer, and more particularly to an effective position of a semiconductor wafer by relative positioning of a bit axis, and integrated into the circuit The method of making the board. [Prior Art] In order to protect the semiconductor wafer from the influence of the external environment and to facilitate operation, transportation, and testing, the semiconductor industry generally employs a method of packaging a semiconductor wafer in which the semiconductor integrated circuit process is completed in the form of a package. However, in the package, the ic substrate for carrying the semiconductor wafer is manufactured by the manufacturer of the 1C substrate according to the design information provided by the semiconductor package manufacturer or the 1C designer, and delivered to the semiconductor package manufacturer for subsequent packaging. Therefore, the semiconductor package manufacturer performs processes such as die bonding, wire bonding, and ball implantation on the 1C substrate of the semiconductor wafers. Therefore, the completion of semiconductor packages involves 1C substrate manufacturers and semiconductor package manufacturers, which has the problem of interface integration and consumes a lot of money and time. In order to solve the problem of interface integration and simplify the process of semiconductor chip package, a circuit board structure of a buried chip is developed, which is mainly after the wafer is completed by the semiconductor integrated circuit process, and the wafer is embedded in the circuit board. The electrically conductive pad forms an outwardly extending conductive line. That is, as shown in Figs. 1A to 1E, it is a schematic diagram of a circuit board method for a buried wafer. As shown in FIG. 1A, a wafer 10 for completing an integrated circuit process is provided, which includes a plurality of wafers 100 having electrical connection pads 103 formed thereon. As shown in FIG. 1B, the wafer 10 is cut into 17931 Ϊ 250833 and cut into a plurality of wafers 10, and then the wafer 1 is embedded in a predetermined opening 1 〇 7 of the circuit board 105. The tether can be fixed at a fixed time (not shown). As shown in Fig. 1c, an insulating layer 109, such as a thermosetting resin, is formed on the circuit board 105 on which the wafer 1 is integrated. As shown in FIG. 1D, a plurality of openings 111 are formed on the insulating layer 1〇9 by laser technology, wherein the openings 111 correspond to the positions of the electrical connection pads 103 of the wafer, and the electrical connection pads are exposed. 1〇3. Thereafter, a de-smear operation is performed. As shown in FIG. 1E, a patterned wiring layer 121 is formed on the surface of the insulating layer and its corresponding opening, and the patterned wiring is electrically connected to the electrical connection pads 1 〇3 of the wafer 1 . First, in the above process, all the process steps (regardless of the wafer placement or laser every day, the gray point of the hairboard is used as the image reference point, but the film is placed in the private, and can not be accurately reported. According to the reference point relative position electricity:; =: placed in the circuit board opening, the main reason is: · placed: the accuracy error of the political film placement hole is soil 25μηΐ; and the error insulation of the wafer placed on the circuit board Lamination 5G_; and the w is placed on the wafer system: the wafer is moved. Furthermore, in the subsequent process, the wafer alignment point in the circuit board can no longer be laser drilled by the image process. It is impossible to make accurate blind holes in the clothing. (The ip can not be applied and there are ancient sputum + t mesh holes (such as the young IF map), and then the board and the insulation layer;;;;; The position in the board is two = cold shrinking will result in the electrical connection of the wafer to the circuit chip: the thermal method forms a good electrical connection between the patterned circuit layer and the connection, resulting in a semiconductor package Good 17931 6 1250833 Poor rate' serious impact on semi-cause How to set the performance of the 2's face to even cause a failure phenomenon. And electrically connect the process to integrate the semiconductor wafer time, and at the same time accurately reduce the process cost of the semiconductor device and the effect of the second: = electrical connection ί pad position 'for subsequent follow-up [the content] ° is a problem to be solved. The shortcomings of the conventional technology on the 5 X, this #明之* to ^ supply - a circuit board method for integrating semiconductor wafers ::: The main purpose of the film is integrated and electrically connected to - ', the semiconductor crystal cost and time. The circuit board' is wrong to save the semiconductor device process. Another object of the present invention is to provide a road plate method, which can be accurate It is known that the position of the electrical connection pad integrated in the electric-electrode wafer is provided for the semiconductor chip of the latter to extend the circuit structure on the above-mentioned and other objects. The method of the road plate is mainly completed at the wafer: :: After the electric power is embedded, directly placed, etc., the slab can be integrated into the carrier board, and the carrier board is H. Edge board or circuit with circuit · The second device determines the positioning point of the carrier plate? The error is determined by the relative coordinate value in the carrier plate, and the wafer is placed on the substrate to determine the subsequent Beco on the relative coordinate axis. The wafer is offset by the wafer; afterwards, the thermal expansion and contraction leads to the formation of an insulating layer which is a carrier layer of the line buildup layer according to the carrier plate and the insulating layer in the process Material; input into the database according to the data; from the relative coordinate value of the expansion and contraction of the double-day Japanese film on the carrying board position 17931 7 1250833, and the actual bearing position of the recording towel and the fixed wafer, 俾" Material 'to determine the opening of the wafer electrically connected to the position;; accurately form the opening of the cheeks, laser drilling, plasma etching, etc.; then the insulation can be in the insulation ^ σ ~ The second, the less one, the slain, the smashing of the smashing 恳 之 之 之 之 之 之 之 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口 开口Extending the w, that is, the integrated circuit chip of the present invention is embedded or placed in, for example, an insulating plate or a circuit:: in the image recognition system, the positioning point of the carrier plate is first recorded; Each of the crystals placed in the carrier plate is clamped down, so that it is clear that each wafer is relatively positioned relative to the t-position, and ^^ 曰乃祁 has a semi-conducting position on the positioning point of the garment carrying board (1) After the coordinate parameters, the laser drilling plate can be put into the line process. When the process reaches the opposite point, the material of the tester is matched with the wafer. For example, the laser-to-laser laser-drilling machine can accurately define the alignment of the carrier plate with the == hole process, and eliminate the four-piece B & The circuit board system can be placed on the opposite coordinate data of the carrier board in the database, matched with the carrier board and the two cold shrinking conditions, accurately covering the wafer bit renewal under the insulating layer = the accuracy of the corresponding wafer connection Open to effectively provide the post " road production. That is, the present invention can be based on the original carrier plate position 17931 8 1250833 and the wafer interface # w layer thermal expansion and contraction 4:: s; the position of the carrier plate and the insulating opening caused by the subsequent process, the offset is adjusted to form In the insulating layer, the effect of the semi-two enthalpy: the influence of energy can increase the yield; the other invention saves the semi-conducting nightmare and the %r is transported to the book board structure, and the process cost of the clothing can be set. With time. [Embodiment] j by 4 inches (the specific embodiment to illustrate the embodiment of the present invention is familiar with the skill of the person who is π丄丄, ^ ^ can be revealed by the contents of the book Other advantages of the invention are also AA曰 and efficacy. The invention can also be carried out by other non-returning embodiments, and the details of the application of the § brothers can be applied to Tw.. 1 5, points and applications, do not deviate from the modification and change of this type. Bu Jinyi, please refer to Figure 2, which is a schematic diagram of the whole circuit board manufacturing process of the present invention, together with the "3g map" Second, a schematic cross-sectional view for explaining the embodiment of the present invention. In step S1, a semiconductor wafer 21 is first embedded in a predetermined opening 200 (as shown in Fig. 2A). The volumetric body circuit process has a plurality of electrical connections 塾21〇 formed on the surface thereof, and the carrier board 20 can be an ordinary insulating layer or a metal plate.
計之電路板。。 X 於步驟S2,以影像辨視系統先將承載板的定位點記錄 下來’再以此定位點獲得該接置於承載板中之晶片内定位 點’例如包含(x，y』)等座標參數之相對位置記錄下來，並 17931 1250833 秦』入至电恥貝料庫儲存，以進行該相對位置之座標參數資 料收集（如步驟82’），如此即可料得知該晶片相對於承載 板定位點的相對位置。 …於步驟S3’於該嵌埋有晶片21之承載才反2〇表面形成 絕緣層22(如帛3B圖所示），以便後續於該絕緣層u上 形成線路結構。該絕緣層22可採用非纖維之樹脂材料，例 如ABF (Ajlnom〇toBuild_upFilm),亦或纖維含浸樹脂材 料，例如雙順丁浠二酸酿亞胺/三氮拼（βτ、阶㈣心也 tnazine) > BCB ( benzocyclobuthene ) ^ LCP ( liquid crystal polymer)、Pi (polyimide)、ρτρΕ (p卟她__ ethylene)、含玻璃纖維環氧樹脂。 於步驟S4,記錄該承載板漲縮變化偏移量，並存儲於 電腦資料庫，以進行該漲縮變化偏移量之資料收集(如步驟 ⑺。由於形成絕緣層22製程中存在溫度增高、降低之變 化過程’導致承載板2G及絕緣層22發生熱脹冷縮之現象。 、材料之物理f生貝各不相㈤，即承載才反及絕緣層U 的熱膨脹係數不同，相對其漲縮變化致使W承載板 2”之原始位置發生變化，並產生一偏移量，而為準確於 絶緣層中形成對應晶片電性連接墊開口，因此必須考量此 因板材漲縮所造成之偏移量 驟S3,從電腦資料庫中檢索、比對先前存儲之座 ‘，數貝料及由於製程中引起材料偏移量（如步驟Μ，广俾 供電腦依據該資料以判定該晶片21於承載板Μ中實際位 置。將最終處理完成之資料回饋至f射機台，以便於該絕 17931 10 l25〇833 層22上準確敎㈣應該w F以外露出該電性連…•第=之 =保後_程精確於該魏連接㈣G上延伸m 開：=1(De-smear)作業以移除因雷射鑽孔所殘留： 開口 220中之膠渣。去 η夕夂心、 形赤^ 一田：、"，该開口 220以可採用其他技衔 1:成：例如使用曝光、顯影技術，可通過依據最〜：！ =，整_且層(光罩)位置 上準確形成對應於該晶片 I、巴、毒層22 之=生連接墊210之開口 口 220中之膠渣（…聰）作業移除因顯影殘留於開 於步驟S 6，進行綠？々制 斜_日日 、、友路衣程。首先於該絕緣声22万f 程所需之電流傳輪路徑，並中，以U後績電鑛製 相沈積（PVD)、化Μ/、// ¥笔層23可藉由物理氣 中—方式妒成 予*目/L^(CVD)、及無電電錢之其 弋形成。其材料可選自 絡合金或錫，合金所構成之群組之壬―鎳者二^ 導電性高分子材料所 者所、，且成，或可由 電層23上^ (如弟3D圖所示）。接著，於該導 电θ 23上形成—阻層24， 製程時，阻擋I需形点道千圖木化，以於後續電鍍 具有複數個開口 24〇,以々卜山刀韻案化阻層24 該等開口㈣對應㈣日^金屬之導電層23， 第3Ε圖所示）。 曰二之电性連接塾21〇位置（如 外露於該圖案化阻〜二圖所示’進行電鍍製程，在 鍍金屬層25,俾於該 右电層23上形成一琶 層上化成有線路結構，並使該線 1793] 11 I25〇833 路結構電性連接至晶片之電 可由钿入p冰』、 电性連接墊。該電鍍金屬層乃 gp w 4] ^ 斤不，形成電鍍金屬層25後， P 了剝離該圖案化阻層24,计丨、；力 24所费+ 亚以钱刻方式去除先前為阻層 4所復盍之導電層23。 透過上述製程’本發明揭^ ^ ^ ^ ^ 雷改:制L ^ 出種整合半導體晶片之 甩路板製法，其藉由相對座棹 μ夕、， 从知釉疋位覆蓋於絕緣層下之晶 初始位置，依據後續製 變，衣長對電路板及絕緣層之脹縮影 音，於相對座標軸判定晶片 碰彻A、^ 心曰曰月偏移后之位置，在絕緣層上準 確形成對應晶片之電性連接 於今1 墊置之開口，確保後續製程 方、该毛性連接墊上形成延伸線路。 體曰曰整合半導體晶片之電路板製法，係可將半導 二二夕界之電性連接結合於電路板增層製程中，節省 成本J4時間；同時避务了 + m pe . 里入式日日片之電路板製程中絕緣 層開口會偏離晶片 包陡連接墊之現象，提升了半導體製 枉之彳§賴性。 因此，本發明之整合晶片之電路板製法係可於資料庫 r 妾置於承載板之相對座標資料，配合承載板及 、、、巴、、ι之4脹冷縮情況，準確覆蓋於絕緣層下之晶片位 從而藉由對應晶片連接墊之準確開口，以有效提供後 =伸線路之製作。亦即，本發明可依據原始承載板位置 及晶片接置位置’同時配合後續製程引起之承載板、絕緣 層熱脹冷縮所導致的晶片位置偏移，調整形成於絕緣層中 相對應曰曰片電性連接墊之開口位置，確保開口對應晶片之 連接塾’避免製程中晶片偏移料導體裝置性能之影響， 12 17931 ί25〇833 &升了良率，·另本發明係將 電路板結構中，俾可節曰曰片正合亚電性連接至 上、t、~ +導體裝置之製程成本與時間。 效，：：例僅為例示性説明本發明之原理及1功 而非用於限制本發明。任：力 不違背本發明之精神及範田壽下，對上述士均可在 二:::本發明之權利保護範圍，應〜 【圖式簡單説明】 第1八至1E圖係習知之埋入式晶 面示意圖； 々之甩路板製法之剖 弟1F圖係習知之理入式曰η 泰 孔誤差之剖面示意圖；Μ講板製法中形成開 程示=圖=發明之整合半導體晶…― 弟3Α至3(}圖係本發明之整合半導 法之剖面示意圖。 甩格极衣 【主要元件符號說明 10 晶圓 100 晶片 103 電性連接墊 105 電路板 107 電路板開孔 109 絕緣層 111 絕緣層開口 17931 13 1250833 121 圖案化線路層 20 承載板 200 開孔 21 半導體晶片 210 電性連接墊 22 絕緣層 220 絕緣層開口 23 導電層 24 阻層 25 電鍍金屬層 S1，S2，S2, ，S3，S4，S5,S6 步驟 14 17931The circuit board. . X in step S2, the image recognition system first records the positioning point of the carrier board, and then obtains the positioning point in the wafer in the carrier board by using the positioning point, for example, including coordinate parameters such as (x, y) The relative position is recorded, and 17931 1250833 Qin is stored in the electric shame warehouse for the coordinate data collection of the relative position (step 82'), so that the wafer is positioned relative to the carrier plate. The relative position of the point. In step S3', an insulating layer 22 (shown in FIG. 3B) is formed on the surface of the carrier in which the wafer 21 is embedded so as to form a wiring structure on the insulating layer u. The insulating layer 22 may be made of a non-fibrous resin material, such as ABF (Ajlnom〇toBuild_upFilm), or a fiber impregnated resin material, such as a di-n-butyl succinic acid-imide/triazine (βτ, a step (four) heart and a tnazine). > BCB ( benzocyclobuthene ) ^ LCP (liquid crystal polymer), Pi (polyimide), ρτρΕ (p卟 her__ ethylene), glass fiber epoxy resin. In step S4, the offset variation of the carrier board is recorded and stored in the computer database to perform data collection of the offset change offset (such as step (7). Due to the temperature increase in the process of forming the insulating layer 22, The process of reducing the change 'causes the phenomenon of thermal expansion and contraction of the carrier plate 2G and the insulating layer 22. The physical f of the material is different from each other (5), that is, the bearing has the opposite thermal expansion coefficient of the insulating layer U, and the change in its expansion and contraction The original position of the W-bearing plate 2" is changed, and an offset is generated, and the opening of the corresponding wafer electrical connection pad is formed accurately in the insulating layer, so the offset caused by the plate shrinkage must be considered. S3, retrieving from the computer database, comparing the previously stored seats', the number of materials and the material offset caused by the process (such as the step Μ, the computer for the computer based on the data to determine the wafer 21 in the carrier board Actual position. The final processed data is fed back to the f-shooting machine, so that the absolute 17931 10 l25〇833 layer 22 is accurate. (4) The electrical connection should be exposed outside the f F...•第=之=保后_程accurate The Wei connection (4) G extends on m: =1 (De-smear) operation to remove the residue left by the laser drilling: the glue in the opening 220. Go to n 夂 夂 heart, shape 赤 ^ 一田:, " The opening 220 can adopt other technical features: into, for example, using exposure and development techniques, and can accurately form the corresponding wafer I, Ba, and according to the position of the most ~:! =, and the layer (mask). The smear layer 22 of the toxic layer 22 is removed from the opening 220 of the raw connection pad 210, and the residue is removed in the step S6, and the green 々 _ _ 日 日 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 。 。 。 Firstly, the current transmission path required for the insulation sound is 220,000 volts, and in the middle, the post-U phase deposition (PVD), phlegm/, / / / pen layer 23 can be used in the physical gas - The method is formed into a * CVD / L ^ (CVD), and the formation of electricity without electricity and electricity. The material may be selected from the group consisting of a complex alloy or tin, and the alloy is composed of a group of nickel-based two conductive polymer materials. The device can be formed by the electrical layer 23 (as shown in the 3D diagram). Then, the resist layer 24 is formed on the conductive θ 23 , and the process of blocking the I requires a dot pattern. Wooding, so that the subsequent electroplating has a plurality of openings 24〇, so that the openings (4) correspond to the (four) day ^ metal conductive layer 23, as shown in the third figure). Connecting the 塾21〇 position (as shown in the patterning resistor 〜2) to perform an electroplating process, forming a ruthenium layer on the metallization layer 25, forming a layer on the right electric layer 23, and Line 1793] 11 I25〇833 structure electrically connected to the wafer can be electrically connected to p ice, electrical connection pad. The plating metal layer is gp w 4] ^ kg, after forming the electroplated metal layer 25, P The patterned resist layer 24 is stripped, and the conductive layer 23 previously etched by the resist layer 4 is removed by the force 24 in a cost-wise manner. Through the above process, the invention discloses that ^ ^ ^ ^ Lei modified: L ^ to produce a circuit board method for integrating a semiconductor wafer, which covers the insulating layer from the glaze by means of a relative 棹 、 The initial position of the crystal, according to the subsequent change, the length of the film on the circuit board and the insulating layer, the film is folded, and the opposite coordinate axis determines the position of the wafer after the A, ^ heart-moon offset, and the corresponding wafer is accurately formed on the insulating layer. It is electrically connected to the opening of the padding of the present invention to ensure that an extension line is formed on the subsequent process side and the capillary connection pad. The circuit board manufacturing method for integrating semiconductor wafers can combine the electrical connection of the semi-conducting two-second junction into the circuit board build-up process, saving cost J4 time; at the same time avoiding + m pe . In the circuit board process of the film, the opening of the insulating layer deviates from the phenomenon that the wafer package is connected to the pad, which improves the reliability of the semiconductor system. Therefore, the circuit board manufacturing method of the integrated wafer of the present invention can be placed on the opposite coordinate data of the carrier plate in the database r ,, and the expansion and contraction of the carrier plate and the,,,,, and ι can be accurately covered in the insulating layer. The lower wafer level is thereby effectively provided for the fabrication of the post-extension line by the exact opening of the corresponding wafer connection pad. That is, the present invention can be adjusted according to the position of the original carrier plate and the position at which the wafer is placed, and the wafer positional displacement caused by the thermal expansion and contraction of the carrier plate and the insulating layer caused by the subsequent process is adjusted and formed in the insulating layer. The position of the opening of the chip connection pad ensures that the opening corresponds to the connection of the chip 避免 'avoiding the influence of the performance of the wafer offset material conductor device in the process, 12 17931 ί25 〇 833 & the yield is increased, and the other invention is the circuit board In the structure, the crucible sheet is electrically connected to the process cost and time of the upper, t, ~ + conductor device. The examples are merely illustrative of the principles and advantages of the invention and are not intended to limit the invention. Ren: Force does not violate the spirit of the present invention and Fan Tianshou, the above-mentioned can be in the second::: The scope of protection of the present invention should be ~ [Simple description of the diagram] The first eight to 1E diagram is buried Schematic diagram of the input crystal plane; 1F diagram of the method of the 甩 甩 板 1 1 1 习 习 习 泰 泰 泰 泰 误差 误差 误差 泰 泰 泰 泰 泰 剖面 泰 泰 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面—— brother 3Α to 3(} diagram is a schematic cross-sectional view of the integrated semi-conducting method of the present invention. 甩格极衣 [main component symbol description 10 wafer 100 wafer 103 electrical connection pad 105 circuit board 107 circuit board opening 109 insulation layer 111 Insulation opening 17931 13 1250833 121 Patterned wiring layer 20 Carrier board 200 Opening 21 Semiconductor wafer 210 Electrical connection pad 22 Insulation layer 220 Insulation layer opening 23 Conductive layer 24 Resistive layer 25 Electroplated metal layer S1, S2, S2, , S3, S4, S5, S6 Step 14 17931