1250414 年 狄、發明說明： 【發明所屬之技術領域】 本發明係有關於_種省電方法及相關裝置，制地，有關於一種 卞，於運作USB控制晶片之省電方法及相關裝置。 【先前技術】 妓、個人電腦中之通用序列匯流排(universal serial bus，簡稱 USB)琿可 七、連^料種USB裝置，例如USB鍵盤、USB滑ι、USB讀卡機、 =SB k身碟、外接式USB硬碟、USB印表機、以及USB掃描器等等， =仏使用者極為枝之週歧齡面，從早期uSBi」錢讀如之 貝料傳輸，〉寅進到目前USB2 〇支援48〇Mbps之資料傳輸。 ^ USB傳輸規格來分類，USB1.1可支援低速(l〇w speed)週邊裝 置，資料傳輸規袼為速率^聊胸的㈣⑽per sec〇nd)、誤差容忍 f為1·5% ’以及全速_卬^)週邊裝置，資料傳輸速率為12Mbps、 誤差容忍度為G·25% ; USB2.〇可錢冑離_ speed)週邊裝置，資料 傳輸速率則可高達48〇Mbps。低速週邊裝置像是湖鍵盤、聰滑鼠 以及USB搖桿料，全速週邊裝置像是腦隨身碟、聰印表機、 以及USB掃描器等等。一般市面上之聰2 〇可向下相容usbi i之規 格，亦即可支援低速、全速、高速之週邊裝置。 技藝人士可明瞭USB傳輸線中主要包含D+、D-、pWR、GND四 條線’ D+、D-以差動訊號傳輸資料，而pwR、GND提供3·3ν直流電； USB裝置之速度可利用終端(terminati〇n)狀態予以判別，以聰低速裝 置以及USB全速裝置為例，如圖一所示，依照、聰之規格，將主機端 USB控制器(或稱下傳(down stream)USB控制器)11〇之d+、仏腳位經 由拉低電阻Rpd拉低至地(pun down),並將裝置端USB控制器(或稱: 傳㈣Str_)USB控制器）120之D•腳位經由拉升電阻拉高至 v33(v33為3.3V)，其中電阻Rpd為15K歐姆士5%，而電阻咖為1 5Κ 歐姆士5%，主機端便可測知裝置端屬於USB低速傳輸之裝置。若將主 機端USB控制器之D+、D-腳位經由拉低電阻Rpd拉低至地，並將裝 12504141250414 Di, invention description: [Technical Field of the Invention] The present invention relates to a power saving method and related device, a system, and a power saving method and related device for operating a USB control chip. [Prior Art] 通用, Universal Serial Bus (USB) in personal computers can be connected to USB devices such as USB keyboard, USB slider, USB card reader, =SB k body. Discs, external USB hard drives, USB printers, USB scanners, etc., = users are extremely unaware of the age of the face, from the early uSBi "money reading such as the shell material transmission,> into the current USB2 〇 Supports data transmission of 48 Mbps. ^ USB transmission specifications to classify, USB1.1 can support low-speed (l〇w speed) peripheral devices, data transmission rules for speed ^ chat chest (four) (10) per sec 〇 nd), error tolerance f is 1.5% ' and full speed _卬^) Peripheral devices, data transmission rate is 12Mbps, error tolerance is G·25%; USB2. 〇 胄 胄 _ speed) peripheral devices, data transmission rate can be as high as 48 〇 Mbps. The low-speed peripheral devices are like a lake keyboard, a smart mouse, and a USB rocker. The full-speed peripheral devices are like a brain flash drive, a Cong printer, and a USB scanner. In general, Cong 2 on the market can be compatible with the specifications of usbi i, and can support low-speed, full-speed, high-speed peripheral devices. The skilled person can understand that the USB transmission line mainly includes D+, D-, pWR, GND four lines 'D+, D- to transmit data by differential signal, and pwR, GND to provide 3·3ν DC; USB device speed can be used terminal (terminati 〇n) The status is discriminated. Take the Cong low-speed device and the USB full-speed device as an example. As shown in Figure 1, according to the specifications of Cong, the host-side USB controller (or the down-stream USB controller) 11 D's d+, pin position is pulled down to the ground (pull down) via the pull-down resistor Rpd, and the device's USB controller (or: (4) Str_) USB controller) 120 D• pin is pulled through the pull-up resistor Up to v33 (v33 is 3.3V), in which the resistance Rpd is 15K ohms 5%, and the resistance coffee is 1500 ohms 5%, the host side can detect that the device end belongs to the USB low-speed transmission device. If the D+ and D- pins of the host USB controller are pulled down to the ground via the pull-down resistor Rpd, and the 1250414 will be installed.
邮為15K歐姆现，而電jaRpu 裝置端屬於USB全速傳輸之裝置。 r腳位經田拉升電阻Rpu拉高至V33，其中電阻 而電J^Rpii為1·5Κ歐姆:=5%，主機端便可測知 今“=^JSB2.0叩言，主機端USB控制器較佳地應支援低速、全速、 2三種傳魏式，畔控制_至少支援全速以及高速兩 ^輸模式。#兩調連接時，若主機端_聽置端為USB低速傳 輸終端狀祕’便決定傳銳度是錢裝置。如圖二所示，但若 機端偵測到裝置端為USB全速傳輸終端狀態時，會進一步由裝置端 偵測 =、D-傳輪線上是否出現「【战從七,序列持續達ι 〇毫秒以 上β另出現序列達10毫秒以上，可利周GH〇(general 狗脚位210以及開關SW將D增位上之拉升電阻Rpu隔離， 形成所謂USB高速傳翰之終端狀態。 +，習知主機端USB控制器若欲支援低速、全速、高速三種傳輸模式， 工機端USB控制器之硬體對應USB2 〇應實施£11(：1喊讀d匕⑽ control interface之縮寫)介面，而對應聰1;[必須實施而⑼^·公 host control hterface 之縮寫)介面或〇HCI(〇pen h〇st c〇咖i 縮寫)介面，而驅動程式也需要對應支援，因此複雜度甚高。 而〇TG(onthe go之縮寫)則為USB下一代規格之趨勢，具備〇TG 能力者，可以選擇扮演USB裝置或者聰线，以與另-端之主機、 USB裝置或者〇TG進行傳輸連結，其目的在於使裝置端彼此間亦可進 行連結傳輸，以上述方式實施〇TG，例如實施於印表機或者可攜式電 瑙週邊，韌鳢之複雜度甚高，尤其對於〇TG可攜式電臞週邊之耗電亦 著實令人憂慮。 個人電藤中之通闬序列匯流排，簡稱USB)埠可 俣連接許多種USB裝置，例如USB鍵盤、USB滑鼠、USB讀卡機、 USB隨身碟、外接式USB硬碟、USB印表機、以及USB掃描器等等， 提供使用者極為方便之週邊連接介面，從早期uSBU支援12Mb卵之 貢料傳輪，演進到目前USB2.0支援480Mbps之資料傳輸3 1250414【發明内容】 Μ 靠 . 本發明揭示一種遘用於運作USB，封晶片之省電方法，USB主機… 控制晶片包含USB高速主機控制器、USB高速翻譯單元、以及USB 實體衣1，省電方&巴含下列步霉··禁能USB高速翻譯單元；偵側外 部USB裝置之運作模式；判斷转USB裝置是否為高速；以及将外部 USB裝置直接與USB高速主機控制器進行通訊，其當外部USB裝置 係為高速。更進一步地，當該外部USB裝置係為USBU裝置則致能 USB高速翻譯單元，於是USB高速主機控制器連結至USB高速翻譯 單元，且USB高速翻譯單元連結至USB實體裝置，然後重置並規劃外 部USB裝置。 本發明亦揭示一種USB主機控制晶片，其可為〇T(}晶片，USB 主機控制晶片包含USB2.0主機控制器；耦接USB2.〇主機控制器之USB · 南速翻譯單元，其包含交易翻譯器以及UTMI介面；耦接USB高速翻 譯單元及USB2.0主機控制器之埠路甴及實體裝置，其包含UTMI模 '組；以及致能模組’其藉甴第一控制訊號為接埠路由及實體裝置以及 藉由第二控制訊號為接USB高速翻譯單元，其中，致能模組經由第二 控制訊號控制USB τ%、速翻譯單元之致能與否，以回應於第一控制訊 號。當USB主機控制晶片鵜接外部USB高速裝置時，致能模組禁能 USB南速翻譯單元，外部USB高速裝置直接經甴埠路甴及實體裝置與 該USB2.0主機控制器通訊；當USB主機控制晶片鶫接外部USBU裝 置時’致能模組致能USB高速翻譯單元，外部USB1.1裝置經由埠珞® 甴及實體裝置以及USB高速翻譯單元與USB2.〇主機控制器通訊；以 上所提及之UTMT規格亦可為UTMI+、ULPI或其他專屬介面規格》 本發明進一步揭示一種USB主機控制晶片，其可為〇tg晶片， USB主機控制晶片包含USB2.0主機控制器；鹈接USB2.0主機控制器 - 之USB高速翻譯單元，其包含交易翻譯1以及UTMT介面；以及耦接 USB高速翁譯單元及USB2.0主機控制器之埠珞甴及實體裝置，其包含 UTMI模組；其中埠路甴及實禮裝置經甴第一控制訊號輛接USB2.〇主 機控制器，以回報外部USB裝置之連接跃態，而USB2.0主機控制器 1250414 X由第一控帘J訊號控制USB高速翻譯單元之致能與否，以回應於第一 控制訊號；當外部USB裝置係為高速時，則禁能USB高速翻譯單元， 外部USB高速裝置直接經由埠路®及實體裝置與USB2.0主機控制器 通訊；當外部USB裝置係為USB1.1裝置時，則致能USB高速翻譯單 兀，外部USB1.1裝置經由埠路由及實體裝置以及USB高速翻譯單元 與USB2.0主機控制器通訊；以上所提及之規格亦可為 ULPI或其他專屬介面規格。 【實施方式】 圖三顯示USB主機控制晶片300與外部USB裝置360連結之方塊 圖，USB主機控制晶片300包括USB2 〇主機控制器32〇以及USB2 〇 集線控制器340，USB2.0主機控制器320耦接USB2.0集線控制器340; 於主機控制器320部份減少實施有關USB1.1主機控制器之硬體部份， 如此一來，韌體之實施則只要單純支援USB2.〇，使韌體實施單純化， 而為了向下相容USB1.1之裝置，所耦接之USB2.0集線控制器340， 可允許USB主機控制晶片300對外連接所有外部USB裝置360，此架 構整體而言雖然在硬體複雜度上不會較習知技藝具有顯著侵勢，但是 韌體實施之複雜度顯著降低使得此架構特別適合實施於USB内嵌系統 (embedded system)，較佳地，USB主機控制晶片300可以為OTG控制 晶片，適合置放於USB主機端或者是〇tg裝置中，例如多功能事務 機之中，而外部USB裝置360則例如USB滑鼠或數位相機等。 USB2.0集線控制器340較佳地包含中繼器(repeater)341與342、交 易翻譯器(transaction translator)343 與 344、UTMI(USB transceiver macrocell interface)模組346與348，每一個通道對應到一套中繼器與交 易翻譯器，應注意到UTMI模組340與348可以為其他可能標準介面 模組例如UTMI+或者ULPI(USB low pin-count Interface)或者是其他專 屬介面模組’ UTMI模組346與348包含USB傳收器對外以傳收USB 實體層訊號，並對USB數位電路部分溝通UTMI標準訊號；當USB 集線控制器340用以橋接USB2.0外部裝置時，訊號經由中繼器重複加 8 1250414 強即可，而不需經過交易翻譯器β 圖四顯示根據本發明之USB主機控制晶片400與外部USB裝置 460連結之另一具體實施例方塊圖，應注意到USB主機控制晶月4〇〇 較佳地係甩以實施於USB主機之中，USB主機控制晶片400主要包含 USB2.0主機控制器420、致能模組430、USB高速翻譯單元44〇、以及 埠路由及實體裝置45G，USB2.G主機控制器42G經由匯流排401福接 至USB高速翻譯單元440，而USB高速翻譯單元440經由匯流排402 與403促供兩個通道耦接至埠路由及實體裝置45〇，使得USB主機控 制曰曰片400猎由實趙裝置450對外提供兩個USB埠，埠路甴及實體裝 置450經由匯流排404與405直接相接至USB2.0主機控制器420 ,另 一方面，埠路由及實體裝置45〇經由訊號406與407耦接至致能模組參 430 ;應注意到USB2 0主機控制器42〇包含根集線&〇沉單元幻2， 根據USB標準規格，USB本身為集線架構，共可支援127個XJSB裝 置’較佳地，USB主機控制晶片4〇〇可以為otg控制晶片，適合置放 於USB主機端或者是0TG裝置中，例如測内喪系統或多功能事務 機之中’而外部USB裝置460則例如USB滑鼠或數位相機等。 USB向速翻譯單元440較佳地包含交易翻譯器442、UTMI介面 446與448，應注意到UTMI介面_與桃可以為其他可能介面例如 UTMI+或者ULPICUSB I〇wpin-_t匕㈣㈣或者是其他專屬介面，雨 以與USB實體層電路溝通訊號；埠路由及實趙裝置45㈣包含u雙φ 模組452與454 ’其利用第一聰埠47〇及第二腦埠48〇分別對外 連接USB連接器(未示)以供連接之外部腦裝置46〇 ,本具體實施例 方瑰圖僅顯示連接-個外部USB裝置，而第二㈣缂·尚未接 上任何USB裝置；應注意到交易翻譯器糾2主要擔任不同usb速度介 面之翻譯工作，其可由多個通訊埠共享或者是各自獨立擁有，於此實 施例中則由兩個通訊蟑共享單一交易翻譯器Μ2做為實施例說明；另 -方面’應注意到UTMI模組452與454可以為其他可能標準介面模 組例如UTMI+或者ULPI或者是其他專屬介面模組，丽模組松 9 1250414 與454包含USB傳收器對外以傳收USB實體層訊號，並對USB數位 電路部分溝通UTMI標準訊號。 USB南速翻譯單元44〇較佳地負責支援USBU協定運作，其經南 匯流排401輕接USB2.0主機控制器420，而經由匯流排402與403支 援USBU之外部裝置，較佳地，當USB主機控制晶片400橋接USB2.0 外部裝置時，高速資料流直接經由匯流排4〇4舆4〇5與USB主機控制 晶片400之根集線單元422通訊；而當USB2.0主機控制器420橋接 USBU外部裝置時，訊號就必須經由USB高速翻譯單元440之交易翻 譯器442將不同速度之訊號進行翻譯，應注意到，USB2.0主機控制器 420只需支援USB2.0主機之協定運作。 外部USB裝置於剛連接時，會有兩個階段的動作，一為重置與偵· 測速度期(phase)，以決定連接速度，另一為規劃期(c〇nfigurati〇n phase)，以進行適當的規劃。進一步詳細說明此具體實施例之初始運 作’於此具體_實，例之中，只有耦接一個外部USB2.0裝置460，而外 部USB裝置一開始皆預設為經由匯流排4〇4與4〇5與主機控制晶 片400你集線單元422通訊，並由致能模組43〇預設地經南訊號4〇9 將USB高速翻譯單元44〇禁能以進行節電；u模組松於重置鱼 偵測速度期，蚊舆转U脱〇裝置·之運作模式為漏2 ^^ 即480MHz，因此便可正確地藉由匯流排4〇4直接與仍㈣主機控制 器42〇進行通訊，可以完全地讓聰高速翻譯單元_禁能以進行省φ 電較佳地，UTMI模組452與454會將所連接之外部USB裝置之連 線狀態，藉由訊號406與407回報給致能模組430，供致能模組43〇參 考運作。 接續以上圖四之具體實施例，在外部USB2 〇裝置·46〇進入正常運 — 作後，若有另一個外部USB2.0裝置(未示)連接於第二uSB埠480，類 似於外部USB2.G裝置46G，該另-外部USB2 G裝置由模組454 於重置與細速度期，決定其運作模式為USB2 〇，並經由預設匯流排 405直接舆USB2.0主機控制器420進行通訊，完全地讓腦高速翻譯 10 1250414 日修替換頁 單元440禁能以進行ϋ。--………-一- 另一方面’接續以上圖四之具體實施例，若在外部USB2 〇裝置46〇 進入正常運作後，有另-個外部USBU(未示)連接綠二脳蜂48〇， 該另-外部USB1.1裝置由utmI模組454於重置舆積測速度期，決定 其運作模式為USB1.1，則經由訊號406與407回報給致能模組430， 將目前外部USB裝置之連接狀態回報給致能模組430，因此訊號406 與407顯示USB主機控制晶片400經由第一 USB蜂470連接USB2.0 裝置460，而第二USB埠48〇連接USBU裝置(未示），致能模組43〇 藉由訊號409將USB高速翻譯單元440之交易翻譯器442與UTMI介 面448致能，使得USB2.0主機控制器420透過根集線單元422看到 USB高速翻譯單元440 ;然後，埠路由及實體裝置450將UTMI匯流 排訊號405切換路由至匯流排403，並由實體裝置450透過UTMI模組 454與第二USB埠480重新對該外部USB1.1裝置(未示)進行重置與連 ……结—，丛與外部US—B1.1裝置連結運作於USB1.1協定，其中USB實體裝 置㈣可藉由議模組454與第二脳埠對外部的聰絞線對 驅動SE0訊號達-預定時間長度，而引發重置程序；使得外部刪工 裝置可經由實體裝置45〇、USB高速翻譯單元_之交易翻譯器撕 及UTMI介面448，與USB2.0域控制器420進行連結通訊；較佳地， 致能模組430藉由訊號408仍將USB高速翻譯單元44〇之交易翻譯器 442與UTMI介面446維持於禁能，使得原先外部USB2 〇裝置46〇仍 直接地經由USB實體裝置45G、預設匯流排德與聰2 Q主機控制器 420通訊，以進行省電。 圖五顯示根據本發明之再一具體實施例之USB主機控制晶片5〇〇 與外部USB裝置460連結之方塊圖，其相應於圖四之具體實施例，表. 示USB主機控制晶片500之致能模組430之硬體設計亦可由韌體所取 代執行，相應於圖四之控制訊號406、407、408、409，由圖五之控制 訊號506、507、508、509所取代，也就是說，外部USB裝置之連結模 式藉由控制訊號506、507回報给USB2.0主機控制器520，供韌體參考 11The mail is 15K ohms, and the electric jaRpu device is a USB full-speed transmission device. r pin is pulled up to V33 by the field pull-up resistor Rpu, where the resistance and the electric J^Rpii are 1. 5Κ ohm:=5%, the host can detect the current "=^JSB2.0 rumor, host-side USB The controller should preferably support low speed, full speed, 2 three types of transmission type, and the side control _ at least supports full speed and high speed two mode. When the two connections are connected, if the host side _ listening set is the USB low speed transmission terminal type secret 'The decision to pass the sharpness is the money device. As shown in Figure 2, if the device detects that the device is in the state of USB full-speed transmission terminal, it will be further detected by the device side =, and whether the D-transmission line appears." [Battle from seven, the sequence lasts for more than ι 〇 milliseconds. The sequence of β appears for more than 10 milliseconds. The GH 〇 can be isolated. The general dog pin 210 and the switch SW isolate the pull-up resistor Rpu on the D-growth to form a so-called USB. High-speed transmission of the terminal status of the Han. +, the known host side USB controller to support low-speed, full-speed, high-speed three transmission modes, the hardware side of the machine-side USB controller corresponds to USB2 〇 should be implemented £11 (: 1 shouting d匕 (10) control interface abbreviation) interface, and corresponding to Cong 1; [must be implemented and (9) ^ · public host control The hterface abbreviation) interface or 〇HCI (〇pen h〇st c〇咖i abbreviated) interface, and the driver also needs corresponding support, so the complexity is very high. 〇TG (onthe go abbreviation) is the next generation of USB The trend of the specification, those with 〇 TG capability, can choose to play USB device or Cong line to transmit connection with the other end host, USB device or 〇TG. The purpose is to make the device terminals connect and transmit to each other. The implementation of 〇TG in the above-mentioned manner, for example, implemented in a printer or a portable battery, the complexity of the toughness is very high, especially for the power consumption of the 〇 TG portable battery, which is also worrying. The vine's overnight serial bus, referred to as USB), can connect to many kinds of USB devices, such as USB keyboard, USB mouse, USB card reader, USB flash drive, external USB hard disk, USB printer, and USB scanner and the like, providing a user-friendly peripheral connection interface, from the early uSBU support 12Mb egg tribute transfer, to the current USB2.0 support 480Mbps data transmission 3 1250414 [invention] 靠 靠. Reveal a kind遘Used to operate USB, power saving method for sealing chip, USB host... Control chip includes USB high speed host controller, USB high speed translation unit, and USB physical clothing 1. Power saving side & Ba contains the following steps. USB high-speed translation unit; the operation mode of the external USB device of the detection side; determining whether the USB device is high speed; and communicating the external USB device directly with the USB high-speed host controller, which is a high-speed external USB device. Further, when the external USB device is a USBU device, the USB high speed translation unit is enabled, so the USB high speed host controller is connected to the USB high speed translation unit, and the USB high speed translation unit is connected to the USB physical device, and then reset and planned. External USB device. The invention also discloses a USB host control chip, which can be a 〇T (} chip, the USB host control chip comprises a USB2.0 host controller; a USB2. 〇 host controller USB · a south speed translation unit, which includes a transaction Translator and UTMI interface; coupled with USB high-speed translation unit and USB2.0 host controller, including UTMI mode group; and enabling module's The routing and physical device and the second control signal are connected to the USB high speed translation unit, wherein the enabling module controls the enabling of the USB τ% and the fast translation unit via the second control signal in response to the first control signal When the USB host control chip is connected to the external USB high-speed device, the enabling module disables the USB south speed translation unit, and the external USB high-speed device directly communicates with the USB2.0 host controller via the network device and the physical device; When the USB host control chip is connected to the external USBU device, the enable module enables the USB high-speed translation unit, and the external USB1.1 device communicates with the USB2.〇 host controller via the 埠珞® 甴 and the physical device and the USB high-speed translation unit. The UTMT specification mentioned above may also be UTMI+, ULPI or other proprietary interface specifications. The present invention further discloses a USB host control chip, which may be a 〇tg chip, and the USB host control chip includes a USB2.0 host controller; USB2.0 host controller - USB high-speed translation unit, including transaction translation 1 and UTMT interface; and a USB and high-speed translation unit and USB2.0 host controller, including UTMI mode Group; wherein the first control signal is connected to the USB2.〇 host controller via the first control signal to report the connection state of the external USB device, and the USB2.0 host controller 1250414 X is controlled by the first control curtain J. The signal controls whether the USB high-speed translation unit is enabled or not to respond to the first control signal; when the external USB device is high speed, the USB high-speed translation unit is disabled, and the external USB high-speed device directly communicates with the network® and the physical device. USB2.0 host controller communication; when the external USB device is a USB1.1 device, it enables the USB high-speed translation unit, the external USB1.1 device via the routing and physical device and the USB high-speed translation unit USB2.0 host controller communication; the above mentioned specifications can also be ULPI or other proprietary interface specifications. [Embodiment] FIG. 3 shows a block diagram of a USB host control chip 300 connected to an external USB device 360, and a USB host control chip. 300 includes a USB2 〇 host controller 32 〇 and a USB 2 〇 line controller 340, the USB 2.0 host controller 320 is coupled to the USB 2.0 hub controller 340; and the host controller 320 is partially implemented to implement a USB 1.1 host controller The hardware part, as a result, the firmware implementation only supports USB2.〇, so that the firmware is simplistic, and the USB2.0 hub control is coupled for the device compatible with USB1.1. The 340 can allow the USB host control chip 300 to externally connect all external USB devices 360. The overall structure of the device is not significantly more invasive than the prior art, but the complexity of the firmware implementation is significantly reduced. Therefore, the architecture is particularly suitable for implementation in a USB embedded system. Preferably, the USB host control chip 300 can be an OTG control chip, and is suitable for being placed on a USB host or a 〇tg device. For example, in a multifunction printer, the external USB device 360 is, for example, a USB mouse or a digital camera. The USB 2.0 hub controller 340 preferably includes repeaters 341 and 342, transaction translators 343 and 344, and UTMI (USB transceiver macrocell interface) modules 346 and 348, each of which corresponds to A set of repeaters and transaction translators, it should be noted that UTMI modules 340 and 348 can be other possible standard interface modules such as UTMI+ or ULPI (USB low pin-count Interface) or other proprietary interface modules 'UTMI modules The 346 and 348 include a USB transceiver for transmitting the USB physical layer signal and communicating the UTMI standard signal to the USB digital circuit portion; when the USB hub controller 340 is used to bridge the USB 2.0 external device, the signal is repeated via the repeater. 8 1250414 can be used without going through the transaction translator. FIG. 4 shows a block diagram of another embodiment of the USB host control chip 400 and the external USB device 460 according to the present invention. It should be noted that the USB host controls the crystal moon. Preferably, the system is implemented in a USB host. The USB host control chip 400 mainly includes a USB 2.0 host controller 420, an enabling module 430, a USB high speed translation unit 44A, and The routing and physical device 45G, the USB 2.G host controller 42G is connected to the USB high speed translation unit 440 via the bus 401, and the USB high speed translation unit 440 facilitates the coupling of the two channels to the routing and entity via the bus bars 402 and 403. The device 45〇 enables the USB host control chip 400 to be provided by the real device 450 to provide two USB ports, and the circuit device and the physical device 450 directly connect to the USB2.0 host controller 420 via the bus bars 404 and 405. On the other hand, the routing and physical device 45 is coupled to the enabling module reference 430 via signals 406 and 407; it should be noted that the USB 2.0 host controller 42 includes the root set & sinking unit magic 2, according to the USB standard Specifications, USB itself is a hub architecture, can support a total of 127 XJSB devices 'better, USB host control chip 4 can be otg control chip, suitable for placement on the USB host or 0TG device, such as testing Among the systems or MFPs, the external USB device 460 is, for example, a USB mouse or a digital camera. The USB speed translation unit 440 preferably includes a transaction translator 442, UTMI interfaces 446 and 448, and it should be noted that the UTMI interface may be other possible interfaces such as UTMI+ or ULPICUSB I〇wpin-_t(4) (4) or other proprietary interfaces. , rain with the USB physical layer circuit channel communication number; 埠 routing and real Zhao device 45 (four) contains u double φ module 452 and 454 ' it uses the first 埠 47埠 and the second 埠 埠 48 〇 respectively to connect the USB connector ( Not shown) for the external brain device 46 for connection, the embodiment of the present embodiment only shows the connection - an external USB device, and the second (four) 缂 has not been connected to any USB device; it should be noted that the transaction translator corrects 2 Mainly served as translation work of different usb speed interfaces, which can be shared by multiple communication ports or independently owned by each other. In this embodiment, two communication ports share a single transaction translator Μ2 as an embodiment description; It should be noted that the UTMI modules 452 and 454 can be other possible standard interface modules such as UTMI+ or ULPI or other proprietary interface modules, and the Lai modules 9 1250414 and 454 include USB transceivers for external USB transmission. Layer signal, and USB digital circuit section UTMI standard communication signals. The USB south speed translation unit 44 is preferably responsible for supporting the USBU protocol operation, and is connected to the USB 2.0 host controller 420 via the south bus 401, and supports the USBU external device via the bus bars 402 and 403, preferably, when When the USB host control chip 400 bridges the USB 2.0 external device, the high speed data stream directly communicates with the root hub unit 422 of the USB host control chip 400 via the bus bar 4〇4舆4〇5; and when the USB2.0 host controller 420 bridges When the USBU external device is used, the signal must be translated by the transaction translator 442 of the USB high speed translation unit 440 to signal different speeds. It should be noted that the USB 2.0 host controller 420 only needs to support the protocol operation of the USB 2.0 host. When the external USB device is just connected, there will be two phases of action, one for resetting and detecting the phase (phase) to determine the connection speed, and the other for the planning period (c〇nfigurati〇n phase) to Make appropriate planning. The initial operation of this embodiment is further described in detail. In this example, only one external USB 2.0 device 460 is coupled, and the external USB device is initially preset via the bus bars 4〇4 and 4. 〇5 communicates with the host control chip 400, the line unit 422, and the enable module 43 〇 presets the USB high-speed translation unit 44 to save power through the south signal 4〇9; the u module is loosely reset. During the fish detection speed period, the operation mode of the mosquito-repellent-turning U-dislocation device is 2^^ or 480MHz, so that it can communicate directly with the still-(4) host controller 42〇 by the bus bar 4〇4. The UTMI module 452 and 454 will report the connection status of the connected external USB device to the enabling module by signals 406 and 407. 430, for enabling the module 43 〇 reference operation. Following the specific embodiment of Figure 4 above, after the external USB2 device/46〇 enters the normal operation, if another external USB2.0 device (not shown) is connected to the second uSB埠480, it is similar to the external USB2. G device 46G, the external-external USB2 G device is determined by the module 454 during the reset and fine speed period, and its operation mode is USB2, and communicates directly with the USB2.0 host controller 420 via the preset bus 405. Completely let the brain translate at high speed 10 1250414. Replace the page unit 440 to disable it. --.........-一--On the other hand, following the specific embodiment of Figure 4 above, if the external USB2 device 46 is in normal operation, there is another external USBU (not shown) connected to the green bee 48. In other words, the external-external USB 1.1 device is reset by the utmI module 454 to determine the operating mode of the USB 1.1, and the signal is returned to the enabling module 430 via the signals 406 and 407. The connection status of the USB device is reported to the enabling module 430. Therefore, the signals 406 and 407 indicate that the USB host control chip 400 is connected to the USB 2.0 device 460 via the first USB bee 470, and the second USB port 48 is connected to the USBU device (not shown). The enable module 43 enables the transaction translator 442 of the USB high speed translation unit 440 and the UTMI interface 448 by the signal 409, so that the USB 2.0 host controller 420 sees the USB high speed translation unit 440 through the root hub unit 422. Then, the routing and physical device 450 switches the UTMI bus signal 405 to the bus 403, and the physical device 450 re-translies the external USB 1.1 device (not shown) through the UTMI module 454 and the second USB port 480. Reset and connect... knots, bundles with external US-B1.1 units The switch operates in the USB 1.1 protocol, wherein the USB physical device (4) can drive the SE0 signal for a predetermined length of time by the negotiation module 454 and the second pair of external twisted pairs, thereby causing a reset procedure; The device can be connected to the USB 2.0 domain controller 420 via the physical device 45, the USB high speed translation unit, the transaction translator, and the UTMI interface 448. Preferably, the enabling module 430 is still powered by the signal 408. The transaction translator 442 and the UTMI interface 446 of the USB high speed translation unit 44 are maintained in an inactive state, so that the original external USB2 device 46 is still directly connected via the USB physical device 45G, the preset bus and the Cong 2 Q host controller. 420 communication to save power. FIG. 5 is a block diagram showing a connection between a USB host control chip 5 and an external USB device 460 according to another embodiment of the present invention, which corresponds to the specific embodiment of FIG. 4, showing the USB host control chip 500. The hardware design of the energy module 430 can also be replaced by the firmware, and the control signals 406, 407, 408, and 409 corresponding to FIG. 4 are replaced by the control signals 506, 507, 508, and 509 of FIG. The connection mode of the external USB device is returned to the USB2.0 host controller 520 by the control signals 506, 507 for the firmware reference 11
1%月日;1:^七發換頁I 1250414 之 t，_ __ 52〇 根 々动处☆ 24之值經由控制訊號508、509控制USB高速翻譯單元440 器521=、，於^高速翻譯單元物被致能之後，USBZ〇主機控制 璋路由根集線單元522與湖高速翻譯單元連結，類似地， USB·裝置實裝置適當地重置转_裝置，織規劃該外部 例適=::r中具=例之r_ ’此具_ 七· w 碰U巾，該USB主機鋪U包含USB高速 工器USB回速翻譯單元、以及聰實禮裝置，流程自步费咖 :始於步擇610，禁能USB高速翻釋單元，·於步擇㈣，·實體 裝置_物USB裝置之運傾式；於麵⑽ 是否為高速聰裝置，若為高速USB袭置則前進至棘奶， ^别進至步釋638;於步肆635，將外部USB裝置直接與服高速主 機控刮器進行通訊；於步雜638，致能USB冑速翻譯單元；於步辞64〇， USB高速域簡料結至 速翻料元連結至咖實趙裝置;於=二==高 外部聰仏於步物，規 重置該 結束此流程。 ，bi3认置，取後於步驟680 縱上所述，本發明揭示一種適用於運作聰 法侧主機控制晶片包含聰高速主機控制器、us；t速片翻之^電方m 以及USB實體|詈，含啻女义―人 啊裔回連翻譯半兀、鬵 自’ U列物：禁能咖高速翻譯單元； 卿卜部咖__速；以及 τ胃__進_，其當外部-裝置係為4 H步地’ #料部咖 =B =單元，於是USB高速主機控制=== ，謝置並規 .本發明亦揭示-種聰主機控制晶片，其可為〇tg晶片，腦 12 1250414 主機控制晶月包含USB2.0主機控制器；搞接USB2 〇主機控制器之腦 高速翻譯單元’其包含交綠譯㈣及_介面；雜聰高速翻 譯單元及USB2.0主機控制器之埠路由及實體裝置，其包含模 組；以及致能模組，其藉由第一控制訊號耦接埠路由及實韹裝置以及 藉由第二控制訊號為接USB高速翻譯單元，其中，致能模組經由第二 控制訊號控制USB冑速翻譯單元之致能與否，以回應於第_控制訊 號。當該USB主機控制晶片耦接外部USB高速裝置時，致能模組禁能 USB咼速翻譯單元，外部USB高速裝置直接經由埠路由及實體裝置與 USB2.0主機控制器通訊，當USB主機控制晶片輕接外部USB1.1裝置 時，致能模組致能USB高速翻譯單元，外部USB1.1裝置經由埠路由 及實體裝置以及USB高速翻譯單元與USBZ0主機控制器通訊；以上n 所提及之UTMI規格亦可為UTMI+、ULPI或其他專屬介面規格。 本發明進一步揭示一種USB主機控制晶片，其可為〇tg晶片， USB主機控制晶片包含USB2.0主機控制器；耦接USB2.0主機控制器 之USB高速翻譯單元，其包含交易翻譯器以及介面；以及輕接 USB高速翻譯單元及USB2.0主機控制器之埠路由及實體裝置，其包含 UTMI模組，其中埠路由及實體裝置經由第一控制訊號耦接USB2 〇主 機控制器，以回報外部USB裝置之連接狀態，而USB2.0主機控制器 經由第二控制訊號控制USB高速翻譯單元之致能與否，以回應於第一 控制訊號；當外部USB裝置係為高速時，則禁能USB高速翻譯單元，· 外部USB高速裝置直接經由埠路由及實體裝置與USB2.0主機控制器 通訊；當外部USB裝置係為USB1.1裝置時，則致能USB高速翻譯單 元，外部USB1.1裝置經由埠路由及實韹裝置以及USB高速翻譯單元 與USB2.0主機控制器通訊；以上所提及之UTMI規格亦可為UTMI+、 ULPI或其他專屬介面規格。 以上所揭示之具體實施例之說明及圖式，係為便於闡明本發明之 技術内容及技術手段，並不欲拘限本發明之範疇。舉凡一切針對本發 明之結構細部修飾、變更，或者是元件之等效替代、置換，當不脫離 13 1250414 7 以下之申請專利範圍來界定之。 本發明之發明耠神及範疇，其範圍將由 【圖式簡單說明】 圖一顯示USB低速裝置之終端狀態； 圖二顯示支援USB高速裝置之終端狀態； 圖三顯示USB主機控制晶片與外部USB裝置連結之方塊圖； 圖四顯示根據本發明之USB主機控制晶片與外部USB裝置連結之 另一具體實施例方塊圖； 圖五顯不根據本發明之再一具體實施例之USB主機控制晶片與外 部USB裝置連結之方塊圖,·以及 圖六顯示根據本發明之一具體實施例之方法流程圖。1% month day; 1:^ seven-page change page I 1250414 t, _ __ 52 々 々 ☆ 24 24 value control signal 508, 509 control USB high-speed translation unit 440 521 =,, ^ high-speed translation unit After being enabled, the USBZ〇 host control/route rooting line unit 522 is coupled to the lake high-speed translation unit. Similarly, the USB device is properly reset to the device, and the external example is suitable for the =::r = Example r_ 'This tool _ VII w Touch U towel, the USB host shop U contains USB high speed USB USB speed translation unit, and Cong Shili device, the process is self-stepping: starting from step 610, forbidden USB high-speed release unit, · in step selection (four), · physical device _ object USB device operation tilt; on the surface (10) whether it is high-speed Cong device, if it is high-speed USB attack, then advance to the spine, ^ do not enter Step 638; in step 635, the external USB device communicates directly with the high-speed host controller; in step 638, the USB idle translation unit is enabled; in step 64, the USB high-speed domain is connected to The quick-turn material element is connected to the Caishi Zhao device; in the =============================================== The present invention discloses a method for operating a Congfa side host control chip including a Cong high-speed host controller, a us; t-speed chip turn-over ^ electric square m and a USB entity|詈 啻 啻 啻 啻 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U The system is 4 H steps ' #料部咖 = B = unit, so USB high-speed host control ===, thank you and the rules. The invention also discloses - a kind of Cong host control chip, which can be 〇tg wafer, brain 12 1250414 The host control crystal moon contains the USB2.0 host controller; the USB high-speed translation unit of the USB2 〇 host controller is included. It includes the green translation (4) and _ interface; the hybrid video unit and the USB2.0 host controller a routing and physical device, comprising: a module; and an enabling module coupled to the routing and realizing device by the first control signal and the USB high speed translation unit by the second control signal, wherein the enabling module The group controls whether the USB idle translation unit is enabled or not via the second control signal, _ The first hearing shall control number. When the USB host control chip is coupled to the external USB high-speed device, the enabling module disables the USB idle translation unit, and the external USB high-speed device directly communicates with the USB2.0 host controller via the routing and physical device, when the USB host controls When the chip is connected to the external USB 1.1 device, the enabling module enables the USB high-speed translation unit, and the external USB 1.1 device communicates with the USBZ0 host controller via the routing and physical device and the USB high-speed translation unit; The UTMI specification can also be UTMI+, ULPI or other proprietary interface specifications. The invention further discloses a USB host control chip, which can be a 〇tg chip, the USB host control chip comprises a USB2.0 host controller, and a USB high speed translation unit coupled with a USB2.0 host controller, which comprises a transaction translator and an interface. And a USB-based high-speed translation unit and a USB2.0 host controller routing and physical device, including a UTMI module, wherein the routing and physical device are coupled to the USB2 〇 host controller via the first control signal to report the external The connection state of the USB device, and the USB2.0 host controller controls whether the USB high-speed translation unit is enabled or not via the second control signal in response to the first control signal; when the external USB device is high speed, the USB is disabled High-speed translation unit, · External USB high-speed device communicates directly with USB2.0 host controller via 埠 routing and physical device; when external USB device is USB1.1 device, USB high-speed translation unit is enabled, external USB1.1 device Communicate with the USB2.0 host controller via the 埠 routing and implementation device and the USB high-speed translation unit; the UTMI specifications mentioned above can also be UTMI+, ULPI or other It is a interface specification. The description and drawings of the specific embodiments of the invention are intended to be illustrative of the invention. All modifications, alterations, or equivalent substitutions and substitutions of the components of the present invention are defined without departing from the scope of the patent application of 13 1250414 7 below. The invention is in the scope of the invention, and the scope thereof will be described by a simple description of the drawing. Figure 1 shows the terminal state of the USB low-speed device; Figure 2 shows the terminal state of the USB high-speed device; Figure 3 shows the USB host control chip and the external USB device. FIG. 4 is a block diagram showing another embodiment of a USB host control chip and an external USB device according to the present invention; FIG. 5 shows a USB host control chip and an external device according to still another embodiment of the present invention. A block diagram of a USB device connection, and FIG. 6 shows a flow chart of a method in accordance with an embodiment of the present invention.
【元件符號簡單說明】[Simple description of component symbols]
110 主機端USB控制器 120 裝置端USB控制器 210 GPIO腳位 300 USB主機控制晶片 320 USB2.0主機控制器 340 USB2.0集線控制器 341 、342中繼器 343 、344交易翻譯器 346 、348 UTMI 模組 360 外部USB裝置 400 USB主機控制晶片 420 USB2.0主機控制器 422 根集線單元 430 致能模組 440 USB高速翻譯單元 442 交易翻譯器 446 、448 UTMI 介面 450 埠路由及實體裝置 452 、454 UTMI 模組 460 外部USB裝置 470 第一 USB埠 480 第二USB埠 500 USB主機控制晶片 520 USB2.0主機控制器 522 根集線單元 524 暫存器 110 主機端USB控制器 120 裝置端USB控制器 210 GPIO腳位 14 1250414 ；# 正潛摸 i) .. 300 USB主機控制晶片 320 USB2.0主機控制器 ..............… —.一一一..— 340 USB2.0集線控制器 341、342中繼器 343、344 交易翻譯器 346、348 UTMI模組 360 外部USB裝置 400 USB主機控制晶片 420 USB2.0主機控制器 422根集線單元 430致能模組 440 USB高速翻譯單元 442交易翻譯器 446、448 UTMI 介面 450埠路由及實體裝置 460 外部USB裝置 480 第二 USB 埠 500 USB主機|控制晶片 522根集線單元 452、454 UTMI 模組 470 第一 USB 埠 520 USB2.0主機控制器 524暫存器110 host side USB controller 120 device side USB controller 210 GPIO pin 300 USB host control chip 320 USB2.0 host controller 340 USB2.0 hub controller 341, 342 repeater 343, 344 transaction translator 346, 348 UTMI module 360 external USB device 400 USB host control chip 420 USB2.0 host controller 422 root hub unit 430 enable module 440 USB high speed translation unit 442 transaction translator 446, 448 UTMI interface 450 routing and physical device 452, 454 UTMI module 460 external USB device 470 first USB port 480 second USB port 500 USB host control chip 520 USB2.0 host controller 522 root hub unit 524 register 110 host side USB controller 120 device side USB controller 210 GPIO pin 14 1250414; #正潜摸i) .. 300 USB host control chip 320 USB2.0 host controller................. —.11..— 340 USB2.0 hub controller 341, 342 repeater 343, 344 Transaction translator 346, 348 UTMI module 360 External USB device 400 USB host control chip 420 USB2.0 host controller 422 root line unit 430 enable module 440 USB high speed translation unit 442 transaction translator 446, 448 UTMI interface 450 routing and physical device 460 external USB device 480 second USB 埠 500 USB host | control chip 522 root unit 452, 454 UTMI module 470 first USB 埠 520 USB2.0 host controller 524 register
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