1249169 九、發明說明： 【發明所屬之技術領域】 低溫多晶矽(LTPS)製程技術的成熟，使眾多積體電路 實現於玻璃基板上變為可行’在顯示、面板上若可將驅動電 路設計於其中，則可省下周邊1C的成本，簡化面板生產過 程、並提高良率。本發明的設計在於簡化元件的使用數 目’而一樣達成訊號時間位移功能的運作，有別於其他複 雜的電路設計。 【先前技術】 已知，位移暫存器（Shift Register)，在 1971年 Robert、 Stamford等人有相似的設計（如美國專利第361〇951號)如第 8圖所示，此設計有六個元件，分成二級相同的結構，由 不同相位(phase)的二個時脈clkl、clk2將lnput Data作時 間的位移再由Data output端出。第9 一 1、9 — 2圖為此 架構所模擬出之節點電壓波形圖，第1 0圖為原專利所描 述之控制時脈及輸出入關係波形，比較第9 一 1與第1 〇 圖’可發現在相同的控制時脈clkl、Clk2及輸入訊號下， 所得之輸出波形卻與專利所附之輸出波形不同（如第9 一 1圖圈起來之處所示），若使用第9 一 2圖之控制時脈亦僅 月匕得部分相同輸出（Data-out，第9 一 2圖左邊圈起來之處 所不）；根據此一節點模擬，雖然對輸入訊號有位移的作 用仁時脈二(Clk2)在每一次電位變化時’資料輸出端皆 、隻化從實際應用於面板顯不|§而& ’此架構應不能 %為位移暫存器。其中若將元件換NMOS，亦得到同樣的 1249169 結果。 另，於1976又有一相似的設計（如展1249169 Nine, invention description: [Technical field of invention] The mature technology of low temperature polysilicon (LTPS) process technology makes it possible to realize a large number of integrated circuits on a glass substrate. In the display and panel, the driver circuit can be designed in it. , can save the cost of the surrounding 1C, simplify the panel production process, and improve the yield. The design of the present invention simplifies the operation of the number of components and achieves the operation of the signal time shift function, which is different from other complicated circuit designs. [Prior Art] It is known that Shift Register, in 1971, Robert, Stamford et al. have a similar design (such as US Patent No. 361〇951) as shown in Fig. 8, this design has six The component is divided into two equal-sized structures, and the two phases of different phases clkl and clk2 are used to shift the lnput Data for a time and then output by the Data output. The ninth, ninth, and ninth diagrams show the node voltage waveforms simulated by this architecture. The tenth figure shows the control clock and the input-input waveforms described in the original patent. Comparing the ninth and the first 〇 diagrams. 'It can be found that under the same control clock clkl, Clk2 and input signal, the output waveform obtained is different from the output waveform attached to the patent (as shown in Figure 9), if the 9th one is used. 2 The control clock also has only the same output (Data-out, nowhere on the left side of Figure 9-2); according to this node simulation, although the input signal has a displacement effect, Renshi 2 (Clk2) At each potential change, the data output is only applied from the actual application panel. § and & 'This architecture should not be % displacement register. If the component is changed to NMOS, the same 1249169 result is obtained. In addition, in 1976 there was a similar design (such as exhibition
Tl如果國專利第3937984 说），如第1 1圖所不，它的電容C一姑η ^ Μ疋接到輪出點Β 點’且接輸出端的MOS閘~極是接在一個夫考電 參考電位是當輸出端無訊號輸出時，用來維持 ^； 位電壓;以PMOS設計為例’ Vdl須設為低電位 非觸發訊號的狀態時，維持在高準位電壓，因 則… 位若太低，則因PMOS的源極（_ce)端是接Tl If the national patent No. 3937984 says), as shown in Figure 11, its capacitance C 姑 ^ ^ Μ疋 Μ疋 轮 轮 轮 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且The reference potential is used to maintain the ^ bit voltage when the output has no signal output. When the PMOS design is used as an example, the Vdl must be set to a low-level non-trigger signal, and the voltage is maintained at a high level. Too low, because the PMOS source (_ce) is connected
Vdd，會使輸出訊號無法達到理想的低電位，如 ^ 之實線圈所示，若Vdl電位不夠低，則輪 田 〜顆ί出矾號雖可達較 低準位，卻易受控制時脈干擾，如第 一 α + 儍弟12圖之圓圈虛線所 不，所以使用另一個時脈來取代參考電位Vdi， 改 此項缺失。 、 " 【發明内容】 本發明之主要目的，在於解決上述傳統之缺失，避免 缺失存在，本發明在於簡化元件的使用數目，而— 電路功能的運作，有別於其他複雜的電路設計。， .j達上述之目的，本發明之位移暫存器，至少包括有 •ΐ二ΐ、三時脈控制信號所控制各開關，可將輸入的 訊说儲存在電容上並順序地傳遞到下—級，傳遞到下一級 的ί時亦用來啟動面板顯示11巾之每—列像素開關，以接 ，貝：端送出之育訊’顯示在像素上；此控制時脈的特性 疋第一二時脈控制信號不能同時為低電位，以防每 一級電路之開關（第二、三開關）形成直流路徑(DC pa 1249169 th )而燒毁。 【實施方式】 茲有關本發明之詳細内容及技術說明，現配合圖式說 明如下： > 請參閱「第1、2圖所示」，係本發明之第一二級位 移暫存器及第1圖之實際電路線路示意圖，以此設計可組 成任意級數之位移暫存器電路，如圖所示：本發明之位移 暫存器，至少包括有：第一級電路1，承接輸入訊號做時 間位移後送出訊號給下一級，並同時啟動面板顯示器中之 一列像素開關，以接收資料端送出之資訊，顯示在像素上 〇 上述所提之第一級電路1在輸入端上具有一第一開 關1 1，該第一開關1 1之輸出端1 6做為第二開關1 2 之輸入端1 6 a，第一開關1 1之輸出端1 6亦接有第一儲 存元件1 5之一端以儲存第一級電路1之輸入訊號，而第 二開關12之一輸出端18與第三開關13之一輸出端 1 8 a連接，做為本級的訊黎輸出端1 8節點(node);前述 第一開關1 1之輸入端8輸入有一輸入信號1 4，而第一 開關1 1之控制端1 0有一第一時脈控制信號（CLK1) 3 ;另，前述之第二開關1 2之另一控制端1 9有一第二 時脈信號(CLK2)4 ;又，前述之第三開關1 3之控制端6 有一第三時脈控制信號(CLK3)5 ;此第三開關1 3之另一 輸入端17接一固定電源。複製該第一級電路1作為第二 級電路2，唯第一時脈控制訊號(CLK1) 3改接於第五開關 1249169 2 p ^ ώ <一控制端2 6，第二脈控控制訊號(CLK2)4改接於 此級之第四開關2 1之控制端2 〇。 藉由上述之各開關皆以M0S(PM0S、NMOS、CMOS) 70件當開關，配合適當的時脈控制信號，來傳遞位移訊號。 請參閱「第1、2、3 — 1、3 — 2圖所示」，係本 發明之二級輸出位移暫存器及第1圖之實際電路線路，與 輸入信號及第一、二、三時脈控制信號3、4、5示意圖。 如圖所示：上述所提之各開關暫以刚〇8做開關為例，由 第—時脈控制信號(CLK1)3、第二時脈控制信號(CLK2) 4、第三時脈控制信號(CLK3) 5組成有二級輸出的位移暫 存器電路，更後級的電路亦為相同，只是每級相鄰電路第 一時脈控制信號(CLK1)3、第二時脈控制信號(CLK2)4所 控制的控制端1 〇、2 0節點及連接的控制端1 9、2 6 位置要互換，以達成將輸入訊號位移的效果，又，MO S 元件之閘極（Gate)與源極（s〇urce)或汲極（Drain)之間有一 寄生(Parasitic)電容，若此電容值足夠儲存輸入訊號，則可 省略外加之儲存元件1 5、2 4，以第2圖為例即已省略 儲存元件1 5、2 4。 此P MO S位移暫存器電路的操作是，輸入訊號(SJN) 1 4為低電位（LOW )時，控制第一開關1 1的CLK1需 在輸入信號(S_IN)1 4轉為高電位(HIGH)之前，完成低電 位(LOW)、高電位(HIGH)動作，使輸入信號(S_IN)1 4流 經第一開關1 1，儲存於儲存元件1 5中，並致使第二關 關1 2之輸入端1 6 a為低電位，而呈導通狀態。當CLK1 1249169 使第一開關導通前控制端1 〇、2 6節點為高電位 (HIGH)’第三控制時脈（CLK3) 5的低電位$〇界)使第 三開關1 3與第六開關2 3導通，第一級與第二級輸出端 1 8、2 5節點維持在接近輸入端1 7節點的高電位Vdd (HIGH) ’輸出端1 8、2 5、控制端2 6之高電位(HIGH) 使第五開關2 2呈斷路(OFF)狀態，當CLK1訊號為低電位 時’第二級的控制端2 6維持原電位狀態（無訊號輸出）。 第二時脈控制信號(CLK2) 4產生高低高電位（HIGH LOW HIGH)變化時，由於第二開關丄2為導通狀態，而第三時 脈控制信號(CLK3)5為高電位(HIGH)，第一級輸出端工8 隨CLK2同步產生高低高電位變化，完成第一級電路丄訊號 位移的動作。 由於第一級電路1之輸出端1 8節點會隨CLK2同步 產生南低高電位變化，因此當該第一級電路1之輸出端1 8節點為低電位時，CLK2亦控第四開關2 1之輸入端2 〇，使第四開關2 1呈導通狀態，使低電位儲存於該儲存 元件2 4中，並同時致使第五開關元件2 2呈導通狀熊。 此時CLK1使第五開關2 2之控制端2 6為高電位，所以， 第二級電路2之輸出端2 5節點此時會維持在高電位。 後，第三時脈控制信號CLK3會變為低電位，使第三開關1 3與第六開關2 3導通’使第一級電路丄之輪出端“回 到高電位，並使第二級電路2之輪出端2 5維持在 位。而當CLK1變為低電位時，由於儲存於儲存元件2 4 之低電位會使第五關2 2呈導軌態，㈣會使輸 1249169 2 5變為低電位，使該第— CLK1同步產生高低高電位電路2之輸出端2 5會隨 移之動作。CLK1同步產• 完成第二級電路2訊號位 開關1 1導通使輸人信^^高變化的同時，亦控制第一 存元件15中。 ％ ) 14之高電位’儲存於儲 此控制時脈的特性是第_ 二時脈控制信號(CLK2)4、7夺脈控制信號(CLK1)3、第 能同時為低電位，以防第二，時脈控制信號(CLK3)5不 關形成直流路徑(D C p ath ^關1 2及第三開關1 3等開 為高電位(HGH)時，第二^毁。當輸人訊號(S-IN)U 時脈控制信號(CLK2)4不21 2會成0FF狀態，而第二 各級的動作如重複上述之^現在輸出端18節點。以下 請參閱「第4、5圖戶斤- y n唑八 」，係本發明之再一實施例 圖之輸入與第-至第七級輸出波形。如圖所示：本 =施例與上述第^圖相同，所不同之處在於各開關乃 Τ利用NMOS所作成之開關或傳輸閘 。其控制原理與第 1、2圖相同，在此不多言述。 %參閱「第6、7圖所示」，係本發明之又一實施例 及第6圖之輸入與第一至第七級輸出波形。如圖所示：本 例與上述第1、2圖相同，所不同之處在於各開關乃 疋利用CMOS所作成之開關或傳輸閘。其控制原理與第 1、2圖相同，在此不多言述。 進一步’在於可獲得較佳之訊號輸出準位，及較低的 時脈干擾，並正確地將輸入訊號做時間的位移。 1249169 上述僅為本發明之較佳實施例而已，並非用來限定本 =明實施之範圍。即凡依本發明申請專利範圍所做的均等 變化與修飾，皆為本發明專利範圍所涵蓋。 【圖式簡單說明】 第1圖’係本發明位移暫存器之一二級電路示意圖。 第2圖，係為第丄圖之實際電路線路示意圖。 第3〜1圖，係本發明之控制信號與輸入信號示意圖。 第3 2圖，係本發明之輸入信號第一二級輸出信號示意 圖。 第4圖，係本發明之再一實施例示意圖。 第f圖，係為第4圖架構下之輸入與第一至第七級輸出波 形示意圖。 第6圖，係本發明之又一實施仞示意圖。 第I圖，係為第6圖架構下之輸入與第一至第七級輸出波 形示意圖。 第8圖，係為傳統二級位移電路示意圖。 第 Q 一 - 一 丄、9一2圖，係為第8圖所模擬之節點電壓波形 示意圖。 第1 〇圖，係第8圖先前設計(pri〇rart)節點電壓波形示意 圖。 第11圖，係為另一傳統位移電路示意圖。 f1 2圖，係為第丄丄圖之節點電壓波形示意圖。 第一級電路··..... , 1249169 第一開關..................1 第二開關..................1 第三開關..................1 輸入信號....... 1 控制端........./·6、19、20、2 輸入端..........8、10、16a、l 第二級電路.................. 第四開關..................2 第五開關··........ 2 第六開關· · ......... 2 第一時脈控制信號 第二時脈控制信號 第三時脈控制信號 儲存元件...............1 5、2 輸出端..........16、18、18a、2 12Vdd, the output signal can not reach the ideal low potential, as shown by the real coil of the ^, if the Vdl potential is not low enough, the turntable ~ ί 矾 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达 可达For example, the first alpha + silly brother 12 is not dotted with the dotted line, so use another clock to replace the reference potential Vdi, and change the missing. SUMMARY OF THE INVENTION The main object of the present invention is to solve the above-mentioned drawbacks and avoid the absence of the present invention. The present invention simplifies the use of components, and the operation of the circuit functions is different from other complicated circuit designs. For the above purpose, the displacement register of the present invention includes at least a switch controlled by a ?2, three-clock control signal, and the input signal can be stored on the capacitor and sequentially transmitted to the lower - Level, the ί time passed to the next level is also used to start the panel display of each of the 11 rows of pixel switches, to connect, the: the end of the feeding of the 'in the pixel'; the characteristics of this control clock 疋 first The two-clock control signals cannot be low at the same time, in case the switches (second and third switches) of each stage of the circuit form a DC path (DC pa 1249169 th ) and burn out. [Embodiment] The details and technical description of the present invention will now be described with reference to the following figures: > Please refer to "the first and second figures", which is the first two-stage displacement register of the present invention and 1 is a schematic diagram of the actual circuit circuit, so as to design a displacement register circuit which can be composed of any number of stages, as shown in the figure: the displacement register of the present invention includes at least: a first stage circuit 1, which undertakes input signals After the time is shifted, the signal is sent to the next stage, and at the same time, a column of pixel switches in the panel display is activated to receive the information sent by the data terminal, which is displayed on the pixel. The first stage circuit 1 mentioned above has a first input on the input end. The switch 1 1 has an output terminal 16 of the first switch 1 as an input terminal 16 a of the second switch 1 2 , and an output terminal 16 of the first switch 11 is also connected to one end of the first storage element 15 The input signal of the first stage circuit 1 is stored, and the output end 18 of the second switch 12 is connected to the output end 18 8 of the third switch 13 as a level 1 node of the level. The input end 8 of the first switch 1 1 is input with an input signal 1 4, and the control terminal 10 of the first switch 1 has a first clock control signal (CLK1) 3; in addition, the other control terminal 19 of the second switch 12 has a second clock signal (CLK2). Further, the control terminal 6 of the third switch 13 has a third clock control signal (CLK3) 5; the other input terminal 17 of the third switch 13 is connected to a fixed power source. Copying the first stage circuit 1 as the second stage circuit 2, only the first clock control signal (CLK1) 3 is connected to the fifth switch 1249169 2 p ^ ώ < a control terminal 2 6, the second pulse control signal (CLK2) 4 is changed to the control terminal 2 of the fourth switch 2 1 of this stage. Each of the above switches uses a M0S (PM0S, NMOS, CMOS) 70-piece switch to transmit a displacement signal with an appropriate clock control signal. Please refer to "1, 2, 3 - 1, 3 - 2", which is the second-order output displacement register of the present invention and the actual circuit circuit of Figure 1, and the input signals and the first, second, third Schematic diagram of clock control signals 3, 4, 5. As shown in the figure: each of the above mentioned switches temporarily takes the switch as the example, and the first-clock control signal (CLK1) 3, the second clock control signal (CLK2) 4, and the third clock control signal are used as an example. (CLK3) 5 constitutes a displacement register circuit with a secondary output, and the circuit of the latter stage is also the same, except that the first clock control signal (CLK1) 3 and the second clock control signal (CLK2) of each adjacent circuit of each stage The control terminals 1 〇 and 20 nodes controlled by 4 and the connected control terminals 1 9 and 2 6 are interchanged to achieve the effect of shifting the input signal. In addition, the gate and source of the MO S component are connected. There is a parasitic capacitance between (s〇urce) or drain (Drain). If the capacitance is sufficient to store the input signal, the additional storage elements 1 5 and 2 4 may be omitted. The storage elements 1 5, 2 4 are omitted. The operation of the P MO S shift register circuit is such that when the input signal (SJN) 14 is low (LOW), the CLK1 controlling the first switch 11 needs to be turned high at the input signal (S_IN) 14 ( Before HIGH), the low (LOW) and high (HIGH) actions are completed, and the input signal (S_IN) 14 flows through the first switch 1 1 and is stored in the storage element 15 and causes the second switch 1 2 The input terminal 16 a is low and is in a conducting state. When CLK1 1249169 turns on the first switch, the control terminal 1 〇, the 26 node is high (HIGH), the third control clock (CLK3) 5 low potential $〇 boundary makes the third switch 1 3 and the sixth switch 2 3 conduction, the first stage and the second stage output terminal 1 8 and 2 5 nodes are maintained at a high potential Vdd (HIGH) near the input terminal 1 node 7 'output terminal 1 8 , 2 5 , the high end of the control terminal 2 6 (HIGH) The fifth switch 2 2 is in an open (OFF) state, and when the CLK1 signal is low, the second-stage control terminal 26 maintains the original potential state (no signal output). When the second clock control signal (CLK2) 4 generates a high-low (HIGH LOW HIGH) change, since the second switch 丄2 is in an on state, and the third clock control signal (CLK3) 5 is at a high level (HIGH), The first stage output terminal 8 generates high and low high potential changes synchronously with CLK2, and completes the action of the first stage circuit 丄 signal displacement. Since the output terminal of the first-stage circuit 1 has a south-low high-potential change synchronously with CLK2, when the output terminal of the first-stage circuit 1 is low, the CLK2 also controls the fourth switch 2 1 The input terminal 2 〇 causes the fourth switch 21 to be in an on state, so that the low potential is stored in the storage element 24, and at the same time causes the fifth switching element 22 to be a conductive bear. At this time, CLK1 causes the control terminal 26 of the fifth switch 2 to be at a high potential, so that the output terminal 25 of the second-stage circuit 2 is maintained at a high potential at this time. After that, the third clock control signal CLK3 will be turned to a low level, so that the third switch 13 and the sixth switch 23 are turned on 'to make the first-stage circuit turn to the high potential, and to make the second stage The wheel terminal 2 5 of the circuit 2 is maintained in position. When CLK1 goes low, the fifth level 2 2 is in the track state due to the low potential stored in the storage element 24, and (4) the input 1249169 2 5 is changed. For the low potential, the first CLK1 synchronously generates the high and low high potential circuit 2, the output terminal 2 5 will follow the action. CLK1 synchronous production • complete the second level circuit 2 signal bit switch 1 1 turn on to make the input letter ^ ^ high At the same time of change, the first memory element 15 is also controlled. %) The high potential of 14 is stored in the control clock. The characteristic of the clock is the second clock control signal (CLK2) 4, 7 pulse control signal (CLK1). 3. The first energy can be low at the same time, in case the second, the clock control signal (CLK3) 5 does not turn off to form a DC path (DC p ath ^ off 1 2 and the third switch 1 3 is turned into a high potential (HGH) The second ^ is destroyed. When the input signal (S-IN) U clock control signal (CLK2) 4 does not 21 2 will become 0FF state, and the actions of the second level repeat the above The output terminal is 18 nodes. For the following, please refer to "4th, 5th, and 5th," which are input and phase-to-seventh output waveforms of still another embodiment of the present invention. The embodiment is the same as the above figure, except that each switch is a switch or a transfer gate made by an NMOS. The control principle is the same as that of the first and second figures, and is not described here. 6 and 7 are the input and the first to seventh output waveforms of still another embodiment and the sixth embodiment of the present invention. As shown in the figure, this example is the same as the above-mentioned first and second figures, and is different. The reason is that each switch is a switch or transmission gate made by CMOS. The control principle is the same as that of Figures 1 and 2, and is not mentioned here. Further 'is to obtain a better signal output level, and lower The clock interferes with, and correctly shifts the input signal by time. 1249169 The foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Equal variations and modifications are covered by the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a secondary circuit of a displacement register of the present invention. Fig. 2 is a schematic diagram of an actual circuit of the second diagram. Figures 3 to 1 are control signals of the present invention. Figure 3 is a schematic diagram of the first and second output signals of the input signal of the present invention. Figure 4 is a schematic diagram of still another embodiment of the present invention. Figure f is a diagram of Figure 4 The input and the output waveforms of the first to seventh stages are shown in Fig. 6. Fig. 6 is a schematic diagram of another embodiment of the present invention. Fig. 1 is a schematic diagram of the input and the output waveforms of the first to seventh stages in the structure of Fig. 6. Figure 8 is a schematic diagram of a conventional secondary displacement circuit. The Qth - a 丄, 9 2-1 diagram is a schematic diagram of the node voltage waveform simulated in Fig. 8. Figure 1 is a schematic diagram of the voltage waveform of the previous design (pri〇rart) of Figure 8. Figure 11 is a schematic diagram of another conventional displacement circuit. The f1 2 diagram is a schematic diagram of the node voltage waveform of the second diagram. The first level circuit ··..... , 1249169 The first switch..................1 The second switch............ ...1 Third switch..................1 Input signal....... 1 Control terminal......... /·6,19,20,2 Inputs..........8,10,16a,l Second-level circuits.................. The fourth switch..................2 The fifth switch··........ 2 The sixth switch · · ......... 2 First clock control signal Second clock control signal Third clock control signal storage element...............1 5, 2 Output terminal........ ..16,18,18a,2 12