TWI247479B - Motor control circuit for supplying a controllable driving voltage - Google Patents

Motor control circuit for supplying a controllable driving voltage Download PDF

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Publication number
TWI247479B
TWI247479B TW93108187A TW93108187A TWI247479B TW I247479 B TWI247479 B TW I247479B TW 93108187 A TW93108187 A TW 93108187A TW 93108187 A TW93108187 A TW 93108187A TW I247479 B TWI247479 B TW I247479B
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Taiwan
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signal
coupled
circuit
control circuit
gate
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TW93108187A
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Chinese (zh)
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TW200533054A (en
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Chi-Yang Chen
Li-Cheng Chen
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Aimtron Technology Corp
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Abstract

For applying a driving voltage to a motor, an H-bridge circuit is constructed by a first and a second linear unit and a first and a second switching unit. An error amplifier generates an error signal representative of a difference between the driving voltage detected by a voltage detecting circuit and a command voltage signal. A state control circuit synchronously controls the first and second switching units and a feedback circuit. Through the feedback circuit, the error signal is selectively applied to the first or second linear unit such that one is operated in a linear mode and the other is operated in a nonconductive mode, thereby controlling the driving voltage to become proportional to the command voltage signal. The state control circuit further controls a brake circuit for transforming the error signal into a brake signal to operate the first and second linear units simultaneously in a conductive mode.

Description

1247479 玖、發明說明: 【發明所屬之技術領域】 尤其關於一種供應 本發明係關於一種馬達控制電路, 可控制驅動電壓至馬達之控制電路。 【先前技術】 = 而言,由四個開關電晶體所建構成的Η橋式電路 提供驅動電塵至馬達,例如直流馬達(DC 〇=、步進馬達(Stepping M咖Γ)、以及發聲圈馬達(驗 等’藉以控制馬達之轉動方向、轉速、以及 其他#作特徵。 .圖1顯示習知的用於驅動馬達Μ之Η橋式電路1〇之 ,路圖。翏照H1 ’馬達厘經由式電路W輕合於供 L與地面電位間。雖然馬達心際上係由眾多 =性與電路性之幻牛所構成之複㈣統,但是驅動電屡 土本上係施加至馬達M中之線圈,藉以產生磁場。因此, ίI「馬達」一詞主要是指馬達之線圈,1簡化地視 -一电感性負載(Inductive Load),並且圖式也特別 點而以線圈來描繪馬達Μ。 % Η橋式電路1〇包括四個Ν通道M0SFET(金氧 放NM0S)電晶體q〗至Q4。NM〇s電晶體Qi.之沒極轉人 於供應電壓源Vm,且其源極耦合於馬達Μ之端點A。 電晶體Q2之汲極耦合於供應電壓源Vm,且其源極轉合於 馬達Μ之端點^。?^]^(^電晶體(^之汲極耦合 、 a馬建μ 1247479 之端點A,且其源極耦合於地面電位。NM〇s電晶體匕 之汲極耦合於馬達Μ之端點B,且其源極耦合於地面電位。4 由於NMOS電晶體(^至I分別具有寄生二極體 至Ε>4,故Η橋式電路1〇無須額外設置飛輪(Flywh^)二 極體。倘若Η橋式電路10之四個開關電晶體係由雙载子 接面電晶體(Bipolar Juncti〇n Trransist〇r,BJT)所實施,則 如圖1所示的二極體D!至D4必須額外設置。 NMOS電晶體h至I之閘極分別由控制信號h至 G4所控制。當控制信號〇1與&處於邏輯高位準且控制信 號G2與G3處於邏輯低位準時,nm〇S電晶體Qi與q4導 通且NMOS電晶體Ql與A不導通,使得端點八經由^通 的NMOS電晶體Ql耦合於供應電壓源、^,且端點b經= 導通的NMOS電晶體Q4耦合於地面電位。結果,供應電 壓源vm施加一驅動電壓至馬達M,使得驅動電流從 女而點A至端點b之方向流經馬達μ。當控制信號&與g 處於邏輯低位準且控制信號A與Gs處於邏輯高位準/時,4 NM0S電晶體Q1與Q4不導通且舰〇S電晶體I與導 通,使得端點B經由導通的NM0S電晶體h耦合於^應 電壓源Vm,且端點A.經由導通的nm〇S電晶體q3輕二: 地面電位。結果,供應電壓源Vm施加另—驅動電壓 達Μ ’使得驅動電流l2以從端點b至端點 … 馬達M。 , ,, A之方向流經1247479 发明, INSTRUCTION DESCRIPTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a motor control circuit that can control a driving voltage to a control circuit of a motor. [Prior Art] = In other words, a bridge circuit composed of four switching transistors provides driving dust to the motor, such as a DC motor (DC 〇 =, stepping motor, and vocal ring) The motor (testing 'to control the direction of rotation of the motor, the speed of rotation, and other features. Figure 1 shows a conventional bridge circuit for driving the motor 〇1, road map. 翏照H1 'motor PCT The via circuit W is lightly coupled between the supply L and the ground potential. Although the motor is internally composed of a plurality of (four) systems composed of a singularity of circuit and circuit, the drive power is applied to the motor M. The coil is used to generate a magnetic field. Therefore, the word "motor" mainly refers to the coil of the motor, 1 simplifies the view - an inductive load, and the figure also specifically points the coil to describe the motor Μ. The % bridge circuit 1〇 includes four Ν channel MOSFETs (gold oxide NMOS NM0S) transistors q 〗 〖 to Q4. The NM 〇 s transistor Qi. is not transferred to the supply voltage source Vm, and its source is coupled to End point of motor A A. The drain of transistor Q2 is coupled to the supply voltage source Vm, and its source is transferred to the end of the motor ^ ^. ^ ^ ^ ^ ^ transistor (^ 汲 耦合 coupling, a Ma Jian μ 1247479 end A, and its source is coupled to the ground potential. The drain of the NM〇s transistor is coupled to the terminal B of the motor, and its source is coupled to the ground potential. 4 Since the NMOS transistors (^ to I have parasitic diodes to Ε>4, respectively, the bridge The circuit 1 does not need to additionally provide a flywheel (Flywh^) diode. If the four switch cell systems of the bridge circuit 10 are implemented by a bipolar junction transistor (Bipolar Juncti〇n Trransist〇r, BJT) , the diodes D! to D4 shown in Figure 1 must be additionally set. The gates of the NMOS transistors h to I are controlled by the control signals h to G4, respectively. When the control signals 〇1 and & are at a logic high level And when the control signals G2 and G3 are at a logic low level, the nm〇S transistors Qi and q4 are turned on and the NMOS transistors Q1 and A are not turned on, so that the terminal VIII is coupled to the supply voltage source via the NMOS transistor Q1. And the NMOS transistor Q4 whose terminal b is turned on = is coupled to the ground potential. As a result, the supply voltage source vm applies a driving voltage to the motor. M, so that the drive current flows from the female point A to the end point b through the motor μ. When the control signal & and g are at a logic low level and the control signals A and Gs are at a logic high level, 4 NM0S transistor Q1 And Q4 is non-conducting and the ship S transistor I is conducting, such that the end point B is coupled to the voltage source Vm via the turned-on NMOS transistor h, and the terminal end A. is lighter via the turned-on nm〇S transistor q3: Ground potential. As a result, the supply voltage source Vm applies another drive voltage up to Μ 'to drive the current l2 from the end point b to the end point... motor M. , ,, A direction flows through

在使用馬達Μ之廣泛應用中,施加於端點八與B 之驅動電壓決定馬達Μ之實際操作特徵,因〃曰 J、型上需要 1247479 滿足若干應用要求。首先,驅動電壓之極性與絕對值大小 必須為可控制的物理量,因為驅動電壓之極性決定由馬達 Μ之線圈所產生的磁場之方向且驅動電壓之絕對值大小 $定由馬達Μ之線圈所產生的磁場之強度。尤其當馬達Μ 而要操作於定壓驅動之情況下時,驅動電壓之絕對值大小 必須維持固定。 舀知上,脈衝寬度吕周變(pulse Widtli ⑽, 技術Ί $用於控制施加至馬達的驅動電壓之絕對值大 ,、體而吕,在NMOS電晶體Q4導通且NM〇s電晶體 Q2二Q3不‘通之情況下,控制信號Gi得由一 pWM信號 所只靶,使得NM〇s電晶體Qi之導通時間由控制信號& 之作循糸(Duty Cycle)所決定,進而控制驅動電·壓之平 均值。然而’ PWM技術造成供應電壓源%以及施加至馬 達^的㈣電壓之過錢動。對於需要精確控制馬達之應 董用而習知的P W Μ技術可能造成若干不良影響。因而, 期望一種可提供低雜訊的驅動電壓至馬itM的控制電路。 【發明内容】 本發明之-目的在於提供-種馬達控制電路,可控制 用於馬達的驅動電壓之極性與絕對值大小。 、本發明之另一目的在於提供一種馬遠控制電路,可使 用於馬達的驅動電壓之絕對值維持固定。 馬達控制電路,可抑 本發明之又一目的在於提供一種 制用於馬達的驅動電壓之雜訊。 1247479 動命t據本發明,提供—種馬達控制電路,用於供應一驅 _电壓至一馬達。驅動電壓係施加於馬達之第-端點與第 :端點間。該馬達控制電路包括:- Η橋式電路、一電壓 電:電路、一誤差放大器、一回授電路、以及一狀態控制 橋式電路具有弟一與第二線性單元以及第一與第二 :關早兀。第 '線性單元與第一開關單元共同耦合至第一 2點。第二線性單元與第=開關單&共同麵合至第二端 ,。電壓制電路產生至少—電壓偵測信號,其代表馬達 ^驅動電壓。誤差放大器產生至少—誤差信號,其代表至 電壓偵測信號與一命令電壓信號間之差異。至少一誤 化號係電性分離於第—與第二開關_。回授電路輕合 ^差放接收至少-誤差信號,以選擇性施加至少 號至第或第二線性單元。狀態控制電路同步_ !l第一與第二開關單元以及回授電路。 工 在第紅作期間中,第一開關單元操作於一不導通模 ★第严幵1關單元挺作於一導通模式、回授電路允許至少 誤差彳5唬之一個施加至第一線性單元,導致第一線性單In a wide range of applications where motor Μ is used, the drive voltages applied to terminals VIII and B determine the actual operating characteristics of the motor ,, because 247 J, type 1247479 is required to meet several application requirements. First, the polarity and absolute value of the driving voltage must be a controllable physical quantity, because the polarity of the driving voltage determines the direction of the magnetic field generated by the coil of the motor and the absolute value of the driving voltage is determined by the coil of the motor. The strength of the magnetic field. Especially when the motor is operated in a constant voltage drive, the absolute value of the drive voltage must be kept constant. In the know, the pulse width Lu Zhou change (pulse Widtli (10), the technology 用于 $ is used to control the absolute value of the driving voltage applied to the motor, the body is LV, the NMOS transistor Q4 is turned on and the NM 〇s transistor Q2 two In the case where Q3 is not 'passed, the control signal Gi is derived from a target of a pWM signal, so that the on-time of the NM〇s transistor Qi is determined by the control signal & Duty Cycle, thereby controlling the driving power. • The average value of the voltage. However, the 'PWM technology causes the supply voltage source % and the voltage applied to the motor's (4) voltage. The PW technology that is known to require precise control of the motor may have several adverse effects. Therefore, a control circuit capable of providing a low noise driving voltage to the horse itM is desired. SUMMARY OF THE INVENTION The present invention is directed to providing a motor control circuit for controlling the polarity and absolute value of a driving voltage for a motor. Another object of the present invention is to provide a horse far control circuit that can maintain the absolute value of the driving voltage for the motor to be fixed. The motor control circuit can suppress another object of the present invention. It is to provide a noise for driving voltage of a motor. 1247479 According to the present invention, a motor control circuit is provided for supplying a drive voltage to a motor. The drive voltage is applied to the first end of the motor. The motor control circuit includes: - a bridge circuit, a voltage circuit: an error amplifier, a feedback circuit, and a state control bridge circuit having a first and a second linear unit And first and second: off early. The 'linear unit and the first switch unit are coupled together to the first two points. The second linear unit is combined with the first switch & single face to the second end. The circuit generates at least a voltage detection signal representing a motor voltage. The error amplifier generates at least an error signal representing a difference between the voltage detection signal and a command voltage signal. At least one of the error signals is electrically separated from First and second switch _. The feedback circuit is lightly coupled to receive at least an error signal to selectively apply at least a number to the second or second linear unit. The state control circuit synchronizes _1l first and second open Unit and feedback circuit. During the red period, the first switch unit operates in a non-conducting mode. ★ The first unit is in a conduction mode, and the feedback circuit allows at least one of the errors to be applied. To the first linear unit, resulting in the first linear order

=操作於一線性模式、並且回授電路防止至少一誤差信號 施加至第二緩姓留S 木庄早7L。因而,驅動電壓被控制成實質 比於〒7電壓信號。此時,驅動電壓使得一電流以從第一 端點至第二端點之方向流經馬達。 々在第:操作期間中,第一開關單元操作於導通模式、 第^關單元操作於不導通模式、回授電路防止至少一誤 10 1247479 差信號施加至第一線性單元、並且回授電路允許至少一誤 差“號之另個施加至弟一線性單元,導致第二線性單元 操作於線性模式。因而,驅動電壓被控制成實質上正比於 命令電壓信號。此時,驅動電壓使得一電流以從第二端點 至第一端點之方向流經馬達。 電壓偵測電路包含第一與第二分壓器。第一分壓器串 聯於第一端點與地面電位間,用以輪出第一端點分壓信 號,作為至少一電壓偵測信號中之一個。第二分壓器串聯鲁 於第二端點與地面電位間,用以輸出第二端點分壓信號, 作為至少一電壓偵測信號中之另一個。 誤差放大器包含第一至第三NM0S電晶體以及第一 至第三電流鏡。第一 NM0S電晶體之閘極由第一端點分壓 仏號所控制且其源極耦合於一固定電流源。第二NM〇s電 晶體之閘極由第二端點分壓信號所控制且其源極耦合於 口疋電k源。第二N Μ 0 S電晶體之閘極由命令電磨信號所 控制且其源極耦合於固定電流源。第一電流鏡之原始電流 馨 刀支麵s於第一 NMOS電晶體之;及極與第二nm〇s電晶體 之汲極。第二電流鏡之原始電流分支耦合於第三NM〇s電 晶體之汲極。第三電流鏡之原始電流分支耦合於第一電流 鏡之鏡像電流分支。第一輸出端耦合於第二電流鏡之鏡像 電流分支與第三電流鏡之鏡像電流分支,用以供應至少一 誤差信號之一個。 々第二電流鏡更具有一平行鏡像電流分支,並聯耦合於 第二電流鏡之鏡像電流分支。第三電流鏡更具有一平行鏡 11 1247479 像電>7丨L为支’並聯叙人#楚— 羞姑大哭Η人 電流鏡之鏡像電流分支。誤 差放大口0更包含一第—給 鏡像電流分支與第二合於第二電流鏡之平行 應至少-誤差信號I::平行鏡像電流分支,用以供 回授電路包括第一盥第一 继班 合於該第-線性單元,開關裝置輕 並由狀態控制電路所控制。在第 一操作期間中,第_ „ 卜 隻 4關虞置允許至少一誤差信號之一個 :一線性乎70。在第二操作期間中,第一開關裝置 耦八於信號施加至第一線性單元。第二開關裝置 - ^作期^性早元,並且由狀態控制電路所控制。在第 第二綠柹1 —,第二開關裝置防止至少一誤差信號施加至 ,卜一等t。在帛二操作期,巾,第二開關裝置允許至 ^ h〜信號之另一個施加至第二線性單元。 狀態控制電路孫n丰^ ^ ,、冋步輸出第一至第四狀態控制信 二雷:分別控制回授電路之第-與第二開關裝置以及Η ^ . ^ ^苐—開關單元。第一至第四狀態控制信 ί低IS個係一數位邏輯信號,具有-邏輯高位準與-邏 料低位準。Α筮一 · 處於邏輯低位準^ 中’第―與第三狀1控制信號 位準 - 苐一與第四狀態控制信號處於邏輯高 邊鳋:^第二操作期間中’第一與第三狀態控制信號處於 遴軏向位準而漁结 、 一 ^第四狀態控制信號處於邏輯低位準。 所> 2達控制電路更包括一煞車電路,由該狀態控制電路 乂卢^炎。在第三操作期間中,煞車電路轉換至少一誤差信 ^ :’、至/ —煞車信號,並且經由回授電路同時施加至少 12 1247479 #、》、 了 信號至第-與第二線性單元 單元同 電路控 狀 輯信號 號輸入 號成為 四狀態 邏輯高 時操切導通Μ。纟¥—與第二線性 制第一與第二開『二-麵作期間中,狀態控制 態控制電路更於:導通模式。 ,具有-邏輯高位準金一其係-數位邏 ::車電路,使得該煞車電路轉換:至煞 :至少一煞車信號。在第三操作期間中,第;:: 工制仏號處於瀑輯低位準並 = 位準。 干I工剌化號處於 【實施方式】 下文甲之說明與附圖將使本發明之甘 的、特徵、與優點更明顯。— 、’处,、八他目 發明之較佳實施例。、、> ^圖式詳細說明依據本 圖2顯示依據本發明之馬達路夕 電路圖。參照圖2,焉这裇生丨杂 峪20之一例子之 91 φ r 馬達控制電路20包括一 Η橋式♦啟 、:,測電路22、一誤差放大器23、二: 24、以及一狀態控制電路乃。 口杈電路 Η橋式電路2 1包括兩個線故 個開關單元处與SQ2。線 Qb、吨以及兩 應電㈣vm與馬達M s :_Qb、.LQ2用以福合供 合馬達Μ與地面電 ::早7° SQl與%則用以耦 括線性模式、導通模式:LQI與LQ2之操作狀態包 與SQ2之操作狀能則包括、;^通模式,而開關單元% 〜、則包括導通模式與不導通模式。「線性 13 1247479 化:r司係•曰等效電阻值隨著控制信號實質上線性地變 料雷ρ、、路之㈣狀態。「不導通模式」-詞係指 阻值甚高而視為f質上開路之操作狀離。= operating in a linear mode, and the feedback circuit prevents at least one error signal from being applied to the second slower S. Thus, the drive voltage is controlled to be substantially proportional to the 〒7 voltage signal. At this time, the driving voltage causes a current to flow through the motor in a direction from the first end point to the second end point.第In the first: operation period, the first switching unit operates in the conduction mode, the first switching unit operates in the non-conduction mode, the feedback circuit prevents at least one error 10 1247479 difference signal is applied to the first linear unit, and the feedback circuit Allowing at least one error "the other one is applied to the linear unit, causing the second linear unit to operate in the linear mode. Thus, the driving voltage is controlled to be substantially proportional to the command voltage signal. At this time, the driving voltage causes a current to The motor flows from the second end to the first end. The voltage detecting circuit includes first and second voltage dividers. The first voltage divider is connected in series between the first end point and the ground potential for rotation The first end dividing signal is used as one of the at least one voltage detecting signal. The second voltage divider is connected in series between the second end point and the ground potential for outputting the second end point dividing signal as at least one The other of the voltage detection signals. The error amplifier includes first to third NMOS transistors and first to third current mirrors. The gate of the first NMOS transistor is controlled by the first terminal voltage division nickname and The pole is coupled to a fixed current source. The gate of the second NM〇s transistor is controlled by the second terminal voltage dividing signal and its source is coupled to the port source. The second N Μ 0 S transistor gate The pole is controlled by the command electric grind signal and its source is coupled to the fixed current source. The original current of the first current mirror is singular to the first NMOS transistor; and the pole is connected to the second nm 电s transistor. The primary current branch of the second current mirror is coupled to the drain of the third NM〇s transistor. The original current branch of the third current mirror is coupled to the mirror current branch of the first current mirror. The first output is coupled to the second The mirror current branch of the current mirror and the mirror current branch of the third current mirror are used to supply at least one of the error signals. The second current mirror further has a parallel mirror current branch coupled in parallel to the mirror current branch of the second current mirror. The third current mirror has a parallel mirror 11 1247479 image electric > 7 丨 L for the branch 'parallel narrator # Chu — shy aunt crying the current mirror mirror current branch. Error amplification port 0 contains a first - Giving the mirror current branch with the second The parallel of the two current mirrors should be at least - error signal I:: parallel mirror current branch for the feedback circuit including the first first step and the first linear unit, the switching device is light and controlled by the state control circuit During the first operation period, the _ _ _ only 4 虞 setting allows at least one of the error signals: a linear 70. During the second operation, the first switching device is coupled to the signal applied to the first linear unit. The second switching device - is a period of time and is controlled by the state control circuit. In the second green 柹1, the second switching means prevents at least one error signal from being applied to, i. In the second operation period, the second switching device allows the application of the other of the ^h~ signals to the second linear unit. The state control circuit Sun n Feng ^ ^ , , step output first to fourth state control signals two Lei: respectively control the feedback circuit of the first and second switching device and Η ^ . ^ ^ 苐 - switching unit. The first to fourth state control signals are low IS one-bit digital logic signals having a logic high level and a logic low level. Α筮一· is in the logic low level ^ 'the first and third shape 1 control signal level - the first and fourth state control signals are at the logic high side ^: ^ during the second operation period 'first and third state The control signal is in the horizontal direction and the fishing knot, and the fourth state control signal is at the logic low level. The > 2 control circuit further includes a brake circuit, and the state control circuit is ^ Lu ^ Yan. During the third operation period, the braking circuit converts at least one error signal: ', to / - braking signal, and simultaneously applies at least 12 1247479 #, ", a signal to the first and second linear unit units via the feedback circuit When the circuit control number signal input number becomes four-state logic high, the operation is turned on.纟¥—and the second linear system first and second open “two-plane period, the state control state control circuit is more: conduction mode. , with a logic high level of gold - a system - digital logic :: car circuit, the brake circuit conversion: to 煞: at least one brake signal. During the third operation period, the ::: system nickname is at the lower level of the waterfall and = level. The following description and the accompanying drawings will make the advantages, features, and advantages of the present invention more obvious. —, ‘处,八八目 The preferred embodiment of the invention. And, FIG. 2 shows a circuit diagram of a motor circuit according to the present invention. Referring to FIG. 2, the 91 φ r motor control circuit 20 of an example of the twin 峪 20 includes a 式 bridge type, a circuit 22, an error amplifier 23, two: 24, and a state control. The circuit is. Port circuit The bridge circuit 2 1 consists of two lines, the switch unit and SQ2. Line Qb, ton and two electric (4) vm and motor M s : _Qb, .LQ2 for the integration of the motor Μ and ground power:: 7 ° early SQl and % are used to couple linear mode, conduction mode: LQI and The operating state package of LQ2 and the operational state of SQ2 include, and the switching mode %~, includes the conduction mode and the non-conduction mode. "Linear 13 1247479: R system / 曰 equivalent resistance value with the control signal substantially linearly variable material ρ, road (four) state. "non-conduction mode" - word means that the resistance is very high and is considered f quality open circuit operation.

電壓偵測電路22係用以㈣馬達M之驅動電壓,亦 =加於馬達Μ之端點A與端點^之電壓,並且輸出 哭二代表馬達驅動電壓之電㈣測信號%至誤差放大 :之反相輪入端㈠。誤差放大器23之非反相輸入端 )接收有一命令電遷(c〇mmand v〇hage)信號,用 以指不依據本發明之馬達控制料2G產生所期望的馬達 ,動電壓°命令電M信號U由使用者決依據應用 而f而肩整、或者由其他電路依據馬達之操作特徵而回授 jt誤差放大器23中,至少一電壓偵測信號Vd與命 令電壓信號ve()m相互比較’因而產生至少—代表兩者差值 的誤差信號Ve。The voltage detecting circuit 22 is used for (4) the driving voltage of the motor M, and is also applied to the voltage of the terminal A and the terminal ^ of the motor, and the output of the crying represents the motor driving voltage (four) measuring signal % to error amplification: Inverted wheel end (1). The non-inverting input terminal of the error amplifier 23 receives a command electromigration (c〇mmand v〇hage) signal for indicating that the motor control material 2G not according to the present invention generates a desired motor, the dynamic voltage ° command electric M signal U is returned by the user according to the application, or is returned to the jt error amplifier 23 according to the operating characteristics of the motor by other circuits, and at least one voltage detection signal Vd is compared with the command voltage signal ve()m. At least - an error signal Ve representing the difference between the two is generated.

基於狀態控制電路25所產生之狀態控制信號心與 S2,回授電路24使由誤差放大器23所產生的至少一誤差 信號Ve選擇性施加至線性單元%或LQ2。具體而言,當 狀態控制信號~與S2指示回授電路24 :線性單元[仏操 作於線性模式且線性單元LQ2操作於不導通模式時,回授 電路24允許至少一誤差信號Ve施加於線性單元lq 1但防 止至少一誤差信號Ve施加於線性單元乙匕。在此情況下, 線性單元LQl之等效電阻值隨著至少一誤差信號Ve實質 上線性地變化。當狀態控制信號心與h指示回授電路24·· 14 1247479 操作於不導通模式且線性單元LQ2操作於線 =式時,回授電路24防止至少—誤差信號I施加於線 兀lQi但允許至少一誤差信號Ve施加於線性單元 一在此情況下’線性單A Lq2之等效電阻值隨著至少 誤差k號V e實質上線性地變化。 狀態控制電路25更產生另外兩個狀態控制信號 :,用以控制Η橋式電路21之開關單元吩與叫2,使: 操作於導通模式或不導通模式。狀態控制電路&所同^ ^ ^狀恕控制信號Si至&係相互配合,以達成依據本 " 馬達控制電路20之操作狀態控制。 體而曰,當狀態控制信號&使回授電路Μ選擇性 地施加至少—誤荽作缺 χ 、。Ve至線性單元LQi時,狀態控制 # 5虎S4使開關單元叫摔作 信號τ¥通挺式。此時,狀態控制 '、、早70 LQ2與開關單元SQi操作於 不導通%式。社要,民、去Λ 、° 馬達Μ之端點八經由操作於線性模 ^ 叫1麵合於供應電職Vm,而馬達Μ之端 點Β則短路於地面雷你。 * 電位由於端點Β之電壓實質上為零, 故如點Α之電壓即為^圭 「為馬達驅動電壓。在此情況下,驅動電 L二 至端點^之方向流經馬達Μ。如前所述, 馬達lw動電堡之變動經 23、以及回授電路24所構貞測電路22、誤差放大器 _ ^ 斤構成之迴路回授至線性單元LQ!, 籍而利用線性單元LQi之箄 勒雷壓實併卜 寺效電阻值的變化而控制馬達驅. 另二 命令電屋信號V。一 W狀悲控制信號S2使回授電路24選擇性 15 1247479 地施加至少一莩 信號1使開關差至線性單元吨時,狀態控制 信號S4 s八早^ Ql#作於導通模式。此時,狀態控制 不導通模式二果Λ t 了L Q1與開關單元s Q 2操作於 式的線性單元L0無二之端點b經由操作於線性模 Q2耦合於供應電壓源Vm而馬達M之端$ A則短路於地 皿心鲕點 由於蝠點A之電壓實質上為零,故 ”’、t壓即為馬達驅動電壓。在此情 :以:端點B至端點A之方向流經馬⑽。如前所:: 達驅動電壓之變動經由電㈣測電路22、誤差放大器23、 以及回授電路24所構成之迴路回授至線性單it LQ2,藉而 =性單元Lq2之等效電阻值的變化而控制馬達驅“ 壓貫質上正比於命令電壓信號。 因此,依據本發明之馬達控制電路2〇可控制用於馬 達的驅動電壓之極性與絕對值大小。倘若命令電壓信號 Vc〇m設定為一固定值,則依據本發明之馬達控制電路^ 可使用於馬達的驅動電壓之絕對值維持固定。由於依據本 發明之馬達控制電路20係利用線性單元LQi與LQ2之線 性模式而獲得所期望的馬達驅動電壓,故有效地抑^驅動 電壓之雜訊。 應注意在依據本發明之馬達控制電路2〇中,開關單 元SQ!與SQ2係由狀態控制電路25所產生的狀態控制传 號S3與S4控制,而非至少一誤差信號Ve。尤其,至少一 誤差信號Ve係電性分離於開關單元與Sq2。至w、一 、 ^ 一誤 差“號Ve主要係經由回授電路24選擇性回授控制線性單 16 1247479 元LQ!或LQ2,使其操作於線性模式。 在圖2所示的實施例中, 、、裏广生早儿L Q1 > NM〇S電晶體所實施。線 Vb、LQ2传由 r、 早70 LQi之汲極耦合於佴雍蕾 壓源vm,且其源極耦合於馬達 ' ^适Μ之端點A。線性單 之沒極耦合於供應電壓源V 且 Q2Based on the state control signal generated by the state control circuit 25 and S2, the feedback circuit 24 selectively applies at least one error signal Ve generated by the error amplifier 23 to the linear unit % or LQ2. Specifically, when the state control signals ~ and S2 indicate the feedback circuit 24: the linear unit [仏 operates in the linear mode and the linear unit LQ2 operates in the non-conduction mode, the feedback circuit 24 allows at least one error signal Ve to be applied to the linear unit Lq 1 but prevents at least one error signal Ve from being applied to the linear unit. In this case, the equivalent resistance value of the linear unit LQ1 varies substantially linearly with at least one error signal Ve. When the state control signal heart and h indicate that the feedback circuit 24·· 14 1247479 operates in the non-conduction mode and the linear unit LQ2 operates in the line=式, the feedback circuit 24 prevents at least the error signal I from being applied to the line lQi but allows at least An error signal Ve is applied to the linear unit - in this case the equivalent resistance value of the linear single A Lq2 varies substantially linearly with at least the error k number Ve. The state control circuit 25 further generates two other state control signals: for controlling the switching unit of the bridge circuit 21 to be called 2, such that: operating in a conduction mode or a non-conduction mode. The state control circuit & the same control signal Si to & cooperate with each other to achieve control according to the operation state of the motor control circuit 20. In other words, when the state control signal & enables the feedback circuit to selectively apply at least - an error occurs. When Ve reaches the linear unit LQi, the state control #5虎S4 causes the switch unit to be called the signal τ¥. At this time, the state control ',, early 70 LQ2 and the switching unit SQi operate in the non-conducting % mode. The society wants, the people, the Λ, the end point of the motor 八 eight through the operation of the linear mode ^ 1 side in the supply of electricity Vm, and the end of the motor Β is short-circuited to the ground. * The potential is essentially zero due to the voltage at the end point. Therefore, if the voltage is Α, it is the motor drive voltage. In this case, the direction of the drive power L to the end point ^ flows through the motor. As described above, the motor lw is changed by the 23, and the feedback circuit 22 constructed by the feedback circuit 24 and the error amplifier _ ^ kg are looped back to the linear unit LQ!, and the linear unit LQi is used. The Lele compacts and controls the motor drive to change the resistance value. The other command the electric house signal V. The W-shaped sad control signal S2 causes the feedback circuit 24 to selectively apply at least one signal 1 to the switch circuit 24 to make the switch When the difference is linear to the unit ton, the state control signal S4 s is eight early and Ql# is in the conduction mode. At this time, the state control is not conducting mode. The L Q1 and the switching unit s Q 2 operate in the linear unit L0. The end point b of the second is coupled to the supply voltage source Vm via the linear mode Q2, and the end $A of the motor M is short-circuited to the heart point of the cell. Since the voltage of the bat point A is substantially zero, "', t pressure This is the motor drive voltage. In this case: the horse (10) flows in the direction from the end point B to the end point A. As before:: The fluctuation of the driving voltage is fed back to the linear single it LQ2 via the circuit formed by the electric (four) measuring circuit 22, the error amplifier 23, and the feedback circuit 24, whereby the equivalent resistance value of the sex unit Lq2 is The control is controlled to be proportional to the command voltage signal. Therefore, the motor control circuit 2 according to the present invention can control the polarity and absolute value of the driving voltage for the motor. If the command voltage signal Vc〇m is set For a fixed value, the motor control circuit according to the present invention can maintain the absolute value of the driving voltage for the motor constant. Since the motor control circuit 20 according to the present invention utilizes the linear mode of the linear units LQi and LQ2 to obtain the desired The motor drives the voltage, so the noise of the driving voltage is effectively suppressed. It should be noted that in the motor control circuit 2 according to the present invention, the switching units SQ! and SQ2 are controlled by the state control circuit 25 to control the signal S3. And S4 control, rather than at least one error signal Ve. In particular, at least one error signal Ve is electrically separated from the switching unit and Sq2. To w, one, ^ an error " Ve mainly linear feedback control membered mono 161247479 LQ via a feedback circuit 24 selectively! Or LQ2, so that it operates in linear mode. In the embodiment shown in Fig. 2, Li, Shousheng, L Q1 > NM〇S transistor were implemented. Lines Vb and LQ2 are coupled by r, early 70 LQi's drain is coupled to the bud source vm, and its source is coupled to the motor's end point A. Linear single pole is coupled to supply voltage source V and Q2

m且其源極輕合於馬達M ‘點Β。開關單元sQi與SO f山\Τ1ν>ΓΑm and its source is lightly coupled to the motor M ‘point Β. Switch unit sQi and SO f mountain \Τ1ν> ΓΑ

Wh、侍由NM〇S電晶體所 開關單元S(^之汲極耦合於馬達M 、 δ於地面電位。開關單元SQ2之沒極輕合於馬達…: B ’且其源極輕合於地面電位。 … 應注意由於NMOS電晶體具有寄生二極體…至d 故圖2所示的Η橋式電路21無須額外設置飛輪 4, 偏若Η橋式電路21之線性單元叫與LQ2以及開 SQ^ SQ2係由雙載子接面電晶體所實施,則如圖2所示 的二極體D!至D4必須額外設置。 ,、 電壓偵測電路22得由兩個分壓器22ι與222所構成, 刀別偵測馬達Μ之端點A處的電壓與端點B處的電壓。 刀壓态22丨係由串聯於端.點a與地面電位間之電阻反與 I所實施。電壓偵測信號Vdl係從電阻心與h之耦合點 取出,其與端點A處的電壓間之分壓比為R3/(Ri + R3)。^ 壓器222得由串聯於端點B與地面電位間之電阻R2與^ 所實施。電壓偵測信號Vu係從電阻h與I之耦合點取4 出’其與端點B.處的電壓間之分壓比為r4/(R2 + R4)。泰 心至R4得設計成使得R3/(R1 + R3)等於R4/(R2 + R4)。在圖2 所示的實施例中,電壓偵測信號Vdl與Vu係構成前文所 17 1247479 述的至少一電壓偵測信號Vd,用以代表馬達驅動電壓。 —應注意雖然在圖2所示的實施例中,電壓偵測電路22 輪出兩個電㈣測㈣Vdi肖Vd2,但本發明不限於此而 2應用至電壓偵測電路22更包括一類比比較器,用以獲 =端點A與端點B處的電壓間之差值而產生單—電壓债測 信號vd,代表馬達驅動電壓。 、 誤差放大器23具有兩個反相輸入端,用以分別接收 電壓偵測^號Vdl與Vd2。如前所述,當馬達M操作於驅 流,端點Α流向端點β之情況下時,馬達驅動電壓係 貫質上等於端點A之電壓且端點B短路於地面電位,所以 $壓偵測信號vdl代表馬達驅動電壓且電壓偵測信號vWh, the switch unit S of the NM〇S transistor is connected (the drain of the ^ is coupled to the motor M, δ to the ground potential. The switch unit SQ2 is not lightly coupled to the motor...: B ' and its source is lightly coupled to the ground Potential. ... It should be noted that since the NMOS transistor has a parasitic diode ... to d, the bridge circuit 21 shown in Fig. 2 does not need to additionally provide the flywheel 4, and the linear unit of the bridge circuit 21 is called LQ2 and SQ. ^ SQ2 is implemented by a bipolar junction transistor, and the diodes D! to D4 shown in Fig. 2 must be additionally provided. The voltage detection circuit 22 is composed of two voltage dividers 22 and 222. The knives detect the voltage at the end point A of the motor 与 and the voltage at the end point B. The squeezing state 22 实施 is implemented by a series connection between the end point a and the ground potential. The measured signal Vdl is taken out from the coupling point of the resistance core and h, and the voltage division ratio between the voltage and the voltage at the terminal A is R3/(Ri + R3). The voltage regulator 222 is connected in series to the terminal B and the ground potential. The resistors R2 and ^ are implemented. The voltage detection signal Vu is taken from the coupling point of the resistors h and I. The voltage division ratio between the voltage and the voltage at the terminal B. is r4/(R2 + R4). The core to R4 is designed such that R3/(R1 + R3) is equal to R4/(R2 + R4). In the embodiment shown in Fig. 2, the voltage detection signals Vd1 and Vu constitute the former 17 1247479 The at least one voltage detecting signal Vd is used to represent the motor driving voltage. - It should be noted that although in the embodiment shown in FIG. 2, the voltage detecting circuit 22 rotates two electric (four) measuring (four) Vdi Xiao Vd2, the present invention The second application to the voltage detecting circuit 22 further includes an analog comparator for obtaining the difference between the voltages at the terminal A and the terminal B to generate a single-voltage debt signal vd representing the motor drive. The error amplifier 23 has two inverting input terminals for respectively receiving the voltage detection signals Vdl and Vd2. As described above, when the motor M operates in the driving flow, the end point Α flows to the end point β. When the motor driving voltage is substantially equal to the voltage of the terminal A and the terminal B is short-circuited to the ground potential, the voltage detection signal vdl represents the motor driving voltage and the voltage detecting signal v

it =零二果,誤差放大器23 Μ上僅比較電㈣ 測^唬乂心與命令電壓信號义㈣間之差異。另一方面,合 馬達Μ操作於驅動電流從端點3流向端點A之情況下時田, 馬達驅動電壓係實質上等於端點B之電壓且端點A短路於 地面電位,所以電壓她言號Vd2代表馬達驅動電壓且 壓積測《Vdl實質上為零。結果,誤差放大器^實質上 僅比較電壓偵測信號VU與命令電壓信號Ye·間之差異。 誤差放大器23具有兩個彼此相同的輪 ^ 】於產生彼此相同的誤差信號 '鳥作為前文;斤:2的 至> 一誤差信號Ve。輪出端〇1耦合於線性單元LQ ==2則叙合於線性單元LQ2。回授電路24設有兩個 :關波置SWl與SW”開關裝置SWi受到狀 h之控制。當開關裝置SW1導通時,輪出端01短路= 18 1247479 面電位,導致誤差信號Vel無法施加至線性單元%並且 線性單元LQl操作於不導通模式。#開關裝置^不導通 時,誤差信號vel施加至線性單元吨使之操作於線性模 式。開關裝置sw2受到狀態控制信號S2之控制。當開關 裝置sw2導通時’輸㈣〇2短路於地面電位,導致誤差 信號Ve2無法施加至線性單A LQ2並且線性單元叫操作 於不導通模^當開關裝置SW2不導通時,誤差信號Ve2 施加至線性單元LQ2使之操作於線性模式。 /應注意雖然在圖2所示的實施例中,回授電路24係 ,在狀態控制€路25之控制下,獨立地決定誤差信號Vel 疋否把加至線性早凡LQi並且獨立地定誤差信號L是否 施加至線性單元LO,# 士 &。 _ Q2仁本發明不限於此而得應用於誤差 放大器23僅設有單一輪+ σ ^ 輪出端,用以產生早一誤差信號Ve。 在此障況下’回授電路24係在狀態控制電路之 下,使誤差放大器^ ^ 0 一 " 早一輸出糕選擇性地耦合於線性 早兀LQ!.或LQ。藉以執行單一 至線性單元吨或lq2。、…擇性地施加 線性==橋式電路21之線性單元LQl與叫係操作於 、工.而非如同習知技藝以PWM方式高頻率地 於導通與不導诵壯处M 门两手地切換 20不合因此依據本發明之馬達控制電路 « k又擾動供應電壓源Vm並且有效 電懕之雜邙 Λ, 介丨市』馬違驅動 ^ V右期望更大程度地抑制馬達驅動電麗 訊’則回授電路24得更設有電容c 知 合於線性單元Tn 2冤谷Ci係耦 之閘極與地面電位間,使得誤差信號 19 1247479It = zero two, the error amplifier 23 Μ only compares the electric (four) measured the difference between the heart and the command voltage signal meaning (four). On the other hand, when the motor is operated to drive the current from the end point 3 to the end point A, the motor drive voltage is substantially equal to the voltage of the end point B and the end point A is short-circuited to the ground potential, so the voltage is her Vd2 represents the motor drive voltage and the pressure measurement "Vdl is substantially zero. As a result, the error amplifier ^ substantially only compares the difference between the voltage detection signal VU and the command voltage signal Ye. The error amplifier 23 has two wheels which are identical to each other to generate the same error signal as each other 'bird as the former; jin: 2 to > an error signal Ve. The wheel terminal 〇1 is coupled to the linear unit LQ ==2 to be combined with the linear unit LQ2. The feedback circuit 24 is provided with two: the OFF-wave SW1 and the SW" switching device SWi are controlled by the shape h. When the switching device SW1 is turned on, the wheel-out terminal 01 is short-circuited = 18 1247479 surface potential, so that the error signal Vel cannot be applied to The linear unit % and the linear unit LQ1 operate in the non-conduction mode. When the switching device is not turned on, the error signal vel is applied to the linear unit to operate in the linear mode. The switching device sw2 is controlled by the state control signal S2. When sw2 is turned on, 'transmission (4) 〇 2 is short-circuited to the ground potential, causing the error signal Ve2 to be applied to the linear single A LQ2 and the linear unit is called to operate in the non-conduction mode. When the switching device SW2 is not conducting, the error signal Ve2 is applied to the linear unit LQ2. Let it operate in linear mode. / It should be noted that although in the embodiment shown in Fig. 2, the feedback circuit 24 is independent of the state control road 25, the error signal Vel is independently determined to be added to the linear early. Where LQi and independently determines whether the error signal L is applied to the linear unit LO, #士& _ Q2 仁 The present invention is not limited thereto and is applied to the error amplifier 23 with only a single wheel + σ ^ round-out, used to generate the early error signal Ve. In this case, the feedback circuit 24 is under the state control circuit, so that the error amplifier ^ ^ 0 a " early output cake selectively Coupling linear early LQ!. or LQ. To perform a single to linear unit ton or lq2.,...optically apply linear == bridge unit 21 linear unit LQl and call system operation, work. The technology is switched in a high-frequency manner by the PWM method, and the M-gate is switched between the two doors. Therefore, the motor control circuit «k according to the present invention disturbs the supply voltage source Vm and effectively chokes the entanglement. The city's horse violates the drive ^V right expects to suppress the motor drive electric sensation to a greater extent. Then the feedback circuit 24 has a capacitance c. It is known that the linear unit Tn 2 冤谷Ci coupling is between the gate and the ground potential. To make the error signal 19 1247479

Vel相對緩和地施加至線性 人 早凡LQi之閘極。電宠Γ焱知Vel is applied relatively gently to the linear person's gate of the LQi. Electric pet know

5於線性單元LQ2之閑極與地面,差: ve2相對緩和地施加至線性單元吻之_使❹差W 依據本發明之馬達控制電路20 26’用以使線性單元 …、皁電路 ^ ^ ± v,、同Λ刼作於導通模式。罝 體而吕,當馬達控制電路2〇鈾/一从土 ,、 電路鈐 仃…、車控制時,狀態控制 電路25輸出一煞車控制传声 处由w 彳。唬BRK至煞車電路26。回岸於 煞車控制信號BRK,敎車雷败γw於 沾“、。、 皁電路26使誤差放大器23所產生 的至父一誤差信號Ve轉換虚$ W、 ^ .T ^ W換成至J 一煞車信號。在狀熊柝 制電路25之控制下,_ 〜工 H # 開關早凡叫與%操作於不導通 杈式,並且回授電路24同睥 ^ 抑一 U 加至少一煞車信號至線性 早7G Q4LQ2,使其料操作於導通模式。 ^體而言’在圖2所示的實施例中’回應於煞車控制 化號BRK,煞車電路26使誤 ^ ^ 便&差放大斋23之兩個反相輸入 知短路於地面電位或虛於 .^田 次處於低於命令電壓信號vcom之狀 悲。結果,誤'差作辨· λ, Λτ ” " el /、Ve2轉變成具有邏輯高位準的 煞車信號,而不再暑箭味M m > 、 丹疋則述的用於回授控制的線性信號。在 此情況下’狀態控制電路25兹士社处^心5 in the linear unit LQ2 idle pole and the ground, the difference: ve2 is relatively gently applied to the linear unit kiss _ ❹ W 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据v, and the same as in the conduction mode.罝 Body and Lu, when the motor control circuit 2 〇 uranium / a slave earth, circuit 仃 、, car control, the state control circuit 25 outputs a brake control sound by w 彳.唬BRK to brake circuit 26. Returning to the brake control signal BRK, the brakes are defeated by the gamma, and the soap circuit 26 converts the error-to-parent error signal Ve generated by the error amplifier 23 into virtual $W, ^.T^W to J. Brake signal. Under the control of the bear-bearing circuit 25, the _~工H# switch is called the % operation and the non-conduction type, and the feedback circuit 24 is the same as the 睥^ 一一U plus at least one brake signal to the linear 7G Q4LQ2, the material is operated in the conduction mode. ^ In the embodiment shown in Fig. 2, in response to the brake control number BRK, the brake circuit 26 makes the error and the difference is amplified. The two inverting inputs are known to be short-circuited to the ground potential or false. The field is at a lower level than the command voltage signal vcom. As a result, the error is poorly identified λ, Λτ ” " el /, Ve2 is transformed into logic The high-level brake signal, instead of the summer arrow M m >, Tanjong describes the linear signal used for feedback control. In this case, the state control circuit 25

电塔25精由狀怨控制信號&與L 開關裝置SWi與SW。III r士 π it β 不導通.’使得具有邏輯高位準的 煞車4吕5虎V e 1與V 合兄丨|於 备 口〇 e2刀別輪入線性早元LQi與LQ2之閘極。 具有邏輯高位準的敔鱼户缺v . Tr 干』“、、皁佗號Vel與Yd使線性單元lq〗與 LQ2操作於導通模式,;查如Μ 、 供忒達成所期望的煞車控制。 在煞車控制中,兔Υ /由i & 為了使系差仏唬Vel與Ve2更迅速地 轉變成具有邏輯高 旱的…、車仏说,煞車電路26可額外 20 1247479 設有直接控制誤差放大器23之輸出級之裝置,強迫兩個 輸出端〇1與〇2迅速輸出具有邏輯高位準的煞車信號 與 Ve2 0 圖3顯示依據本發明之誤差放大器23與煞車電路% 之一例子之詳細電路圖。首先說明依據本發明之誤差放大 器23之一例子之詳細電路。NMOS電晶體Nl之閘極用以 接收電壓偵測信號Vdl,NMOS電晶體n2之閘極用以接收 電壓偵測信號Vu,而NMOS電晶體%之閘極用以接收命 令電壓信號Vcom。NMOS電晶體川至N3之源極皆輕合於 一固疋電流源Iea。當電壓偵測信號Vd2為零時,NMOS電 晶體N2不導通。在此情況下,電壓偵測信號vdl與命令電 t k號VC()m決定固定電流源iea分配於NMOS電晶體Νι 與A之電流比例。當電壓彳貞測信號vd2為零時,nm〇S電 晶體A不導通。在此情況下,電壓偵測信號Vd2.與命令電 壓^號VCQm決定固定電流源Iea分配於]STMOS電晶體 與N3之電流比例。 PMOS電晶體?1與P3構成一電流鏡,其中pjy^os電 曰曰曰體Pi作為原始電流分支且PMOS電晶體P3作為鏡像電 6丨匕刀支。PMOS電晶體Pi輕合於NMOS電晶體队與, 使得流經PMOS電晶體P3之電流藉由鏡像效應而對應於 流經NMOS電晶體N!(或NO之電流,用以代表電壓铺測 信號Vdl(或Vd2)。PMOS電晶體P2與P4構成另一電流鏡, 其中PMOS電晶體P2作為原始電流分支且PMOS電晶體 P4作為鏡像電流分支。PMOS電晶體P2耦合於NMOS電晶 21 1247479 體N3,使得流經PMOS電晶體P4之電流經由鏡像效應而 對應於流經NMOS電晶體N3之電流,用以代表命令電壓 信號Vec)m 〇 NMOS電晶體N4與N5構成一電流鏡,其中NMOS電 晶體N4作為原始電流分支且NMOS電晶體N5作為鏡像電 流分支。NMOS電晶體N4耦合於PMOS電晶體P3,使得 流經NMOS電晶體N5之電流藉由鏡像效應而對應於流經 NMOS電晶體Ni(或N2)之電流,用以代表電壓偵測信號 Vdl(或 Vd2)。 誤差放大器23之輸出端h耦合於PMOS電晶體P4 與NMOS電晶體N5。當電壓偵測信號Vdl(或Vd2)小於命 令電壓信號VCQm時,流經PMOS電晶體P4之電流大於 NMOS電晶體N5之電流,導致一差動電流從輸出端山流 出。當電壓偵測信號Vdl(或Vd2)大於命令電壓信號VCC)m 時,流經PMOS電晶體P4之電流小於NMOS電晶體N5之 電流,導致一差動電流流入輪出端〇i。因此,誤差信號Iel 得由此差動電流所實施。 PMOS電晶體P5係並聯耦合於PMOS電晶體P4,作為 平行鏡像電流分支,使得流經PMOS電晶體P5之電流亦代 表命令電壓信號V。·。NMOS電晶體N6隹並聯耦合於 NMOS電晶體N5,作為平行鏡像電流分支,使得流經NMOS 電晶體N6之電流亦代表電壓偵測信號Vdl(或Vd2)。 誤差放大器23之輸出端02耦合於PMOS電晶體P5 與NMOS電晶體N6。當電壓偵測信號Vdl(或Vd2)小於命 22 1247479 令電壓信號vCC)m時,流經PM〇s電晶體之電流大於 NMOS電晶體N6之電流,導致一差動電流從輸出端…流 出。當電壓偵測信號Vdl(或yd大於命令電壓信號 時,流經PMOS電晶體I之電流小於NM〇s電晶體N6: 電流,導致一差動電流流入輸出端〇2。因此,誤差信號込2 得由此差動電流所實施。 煞車電路26包括NMOS電晶體小與Νδ,其汲極分 別耦合於NMOS電晶體%與Ν2之閘極且其源極皆耦合於 _ 地面電位。NMOS電晶體%與Ns之閘極皆由煞車控制信 號BRK所控制。當煞車控制信號BRK處於邏輯高位準時, NMOS電晶體N?與Ns導通,分別使NM〇s電晶體Νι與 N2之閘極短路於地面電位。結果,誤差放大器23所產生 的誤差信號乂^與Ve轉換成具有邏輯高位準的煞車信 號。為了使誤差信號Vel與Vd更迅速地轉態成具有邏輯 回位準的煞車信號,煞車電路26更設有NM〇s電晶體N9, 其汲極耦合於第一輸出級之NMOS電晶體Ns之閘極與^ 二輪出級之NMOS電晶體Νό之閘極且其源極耦合於地面 電位。NMOS電晶體A之閘極由煞車控制信號brk所控 制。當煞車控制信號BRK處於邏輯高位準時,NM〇s = -V 包日日 體N9導通,使NM〇s電晶體比與队之閘極短路於地面 電位而立即不導通,結果,誤差放大器23,所產生的誤差 信號Vel與Vel迅速地轉換成具有邏輯高位準的煞車作號。 為了更清楚瞭解依據本發明之馬達控制電路2 Q之找 作’茲將參照圖4舉例說明依據本發明之馬達控制電路^ 23 1247479 之(-冰電流從端點A至端點3流經馬達M之定麼驅動操 =狀態、(二)煞車操作狀態、以及(三)使電流從端點B至 端點A流經馬達M之定壓驅動操作狀態。 如圖4所示’在操作期間1中,狀態控制信號、與 3為邏輯低位準、狀態控制信號、與§4為邏輯高位準、 sw * "t控制仏虎BRK為邏輯低位準。因此,開關裝置 關單元SQl皆不導通、開關裝置sw_M單元 Q2白¥通、並且煞車電路26處於不賦能⑼灿⑷狀態。 所M之端點B因為短路於地面電位所以其電壓實 貞測信〜為零。誤差信… 區域;處於邏輯高位準11與邏輯低位準L間之線性 誤差M v回料㈣性單元LQl使之操作於線性模式。 位2 Γ·因開關裝置SW2之導通而被拉低至地面電 H、; ’ :壓偵測信號V d 1維持成實質上等於命令電壓 ::比二Γ:之,馬達M之端點A之電㈣持成實質 係—固定信拉 D#u Vcom。因而,當命令電壓信號Vcom 成你^ 依據本發明之馬達控制電路2〇有效地達 ^電流從端點A至…流經馬達M之定壓驅動操^ 在紅作期間T2中狀態控制信 位準,並且煞車抑 S4白為璉輯低 關裝置SW1盘^ 為邏輯高位準。因此,開 車電路26使誤 的煞車信號。具有邏輯 輯冋位準H的煞車信號vel與ve2使 24 1247479 元吨與lq2同時進人導通模式1而,依據本發 提,,、、卜1控制電路20有效地達成煞車操作狀態。附帶一 庫雷茂時馬達M之端點A與端點B之電壓實質上等於供The electric tower 25 is finely controlled by the control signal & and the L switching devices SWi and SW. III r士 π it β non-conducting.' Makes the brakes with logic high level 4 Lu 5 Tiger V e 1 and V 丨 丨 于 于 于 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 The squid with a high logic level lacks v. Tr dry, ", saponin Vel and Yd make the linear unit lq and LQ2 operate in conduction mode; check the 、, supply to achieve the desired brake control. In the brake control, the rabbit / by i & In order to make the differentials Vel and Ve2 more quickly into a logically high drought ..., the car said that the brake circuit 26 can be equipped with a direct control error amplifier 23 The output stage device forcing the two output terminals 〇1 and 〇2 to rapidly output the brake signal with the logic high level and Ve2 0. Figure 3 shows a detailed circuit diagram of an example of the error amplifier 23 and the brake circuit % according to the present invention. A detailed circuit of an example of the error amplifier 23 according to the present invention is shown. The gate of the NMOS transistor N1 is used to receive the voltage detection signal Vdl, and the gate of the NMOS transistor n2 is used to receive the voltage detection signal Vu, and the NMOS is The gate of the crystal % is used to receive the command voltage signal Vcom. The source of the NMOS transistor to N3 is lightly coupled to a solid current source Iea. When the voltage detection signal Vd2 is zero, the NMOS transistor N2 is not turned on. here In the case, the voltage detection signal vdl and the command electric tk number VC()m determine the current ratio of the fixed current source iea to the NMOS transistors Νι and A. When the voltage measurement signal vd2 is zero, the nm〇S transistor In this case, the voltage detection signal Vd2. and the command voltage ^VQm determine the ratio of the current of the fixed current source Iea to the STMOS transistor and N3. The PMOS transistors ?1 and P3 form a current mirror, The pjy^os electric body Pi is used as the original current branch and the PMOS transistor P3 is used as the mirror electrode. The PMOS transistor Pi is lightly coupled to the NMOS transistor team, so that the current flowing through the PMOS transistor P3 Corresponding to the current flowing through the NMOS transistor N! (or NO for representing the voltage spreading signal Vdl (or Vd2) by the mirror effect. The PMOS transistors P2 and P4 constitute another current mirror, wherein the PMOS transistor P2 As the original current branch and the PMOS transistor P4 as a mirror current branch. The PMOS transistor P2 is coupled to the NMOS transistor 21 1247479 body N3 such that the current flowing through the PMOS transistor P4 corresponds to the flow through the NMOS transistor N3 via the mirror effect. Current to represent the command voltage signal V Ec)m 〇 NMOS transistors N4 and N5 form a current mirror, wherein NMOS transistor N4 acts as a raw current branch and NMOS transistor N5 acts as a mirror current branch. NMOS transistor N4 is coupled to PMOS transistor P3 so that it flows through NMOS The current of the crystal N5 corresponds to the current flowing through the NMOS transistor Ni (or N2) by the mirror effect to represent the voltage detection signal Vd1 (or Vd2). The output terminal h of the error amplifier 23 is coupled to the PMOS transistor P4 and the NMOS transistor N5. When the voltage detection signal Vdl (or Vd2) is smaller than the command voltage signal VCQm, the current flowing through the PMOS transistor P4 is greater than the current of the NMOS transistor N5, causing a differential current to flow out from the output terminal. When the voltage detection signal Vdl (or Vd2) is greater than the command voltage signal VCC)m, the current flowing through the PMOS transistor P4 is smaller than the current of the NMOS transistor N5, causing a differential current to flow into the wheel terminal 〇i. Therefore, the error signal Iel is implemented by this differential current. The PMOS transistor P5 is coupled in parallel to the PMOS transistor P4 as a parallel mirror current branch such that the current flowing through the PMOS transistor P5 also represents the command voltage signal V. ·. The NMOS transistor N6 is coupled in parallel to the NMOS transistor N5 as a parallel mirror current branch such that the current flowing through the NMOS transistor N6 also represents the voltage detection signal Vd1 (or Vd2). The output terminal 02 of the error amplifier 23 is coupled to the PMOS transistor P5 and the NMOS transistor N6. When the voltage detection signal Vdl (or Vd2) is less than the voltage signal vCC)m, the current flowing through the PM〇s transistor is greater than the current of the NMOS transistor N6, resulting in a differential current flowing from the output terminal. When the voltage detection signal Vdl (or yd is greater than the command voltage signal, the current flowing through the PMOS transistor I is less than the NM〇s transistor N6: current, causing a differential current to flow into the output terminal 〇2. Therefore, the error signal 込2 The braking circuit 26 includes an NMOS transistor small and Νδ, the drain of which is coupled to the gates of the NMOS transistors % and Ν2, respectively, and the sources of which are coupled to the ground potential. NMOS transistor % The gates of the Ns are controlled by the brake control signal BRK. When the brake control signal BRK is at the logic high level, the NMOS transistors N? and Ns are turned on, respectively, and the gates of the NM〇s transistors Νι and N2 are short-circuited to the ground potential, respectively. As a result, the error signals 乂^ and Ve generated by the error amplifier 23 are converted into a braking signal having a logic high level. In order to make the error signals Vel and Vd transition more rapidly into a braking signal having a logical return level, the braking circuit 26 Further, an NM〇s transistor N9 is provided, the drain of which is coupled to the gate of the NMOS transistor Ns of the first output stage and the gate of the NMOS transistor of the second stage and whose source is coupled to the ground potential. Gate of transistor A The brake control signal brk is controlled. When the brake control signal BRK is at the logic high level, NM〇s = -V, the day body N9 is turned on, so that the NM〇s transistor ratio and the gate of the team are short-circuited to the ground potential and immediately do not conduct. As a result, the error amplifiers 23, the generated error signals Vel and Vel are rapidly converted into the brakes having the logic high level. For a clearer understanding of the motor control circuit 2 Q according to the present invention, reference will be made to FIG. By way of example, the motor control circuit according to the present invention (23-247479) (the ice current flows from the end point A to the end point 3 through the motor M, the drive operation state = (2) the brake operation state, and (3) the current From the end point B to the end point A, the constant pressure driving operation state of the motor M flows through. As shown in Fig. 4, in the operation period 1, the state control signal, and 3 are logic low level, state control signals, and § 4 The logic high level, sw * "t control 仏虎 BRK is logic low level. Therefore, the switch device off unit SQl is not turned on, the switch device sw_M unit Q2 is white, and the brake circuit 26 is not energized (9) can (4) state The end of M Point B is short-circuited to the ground potential, so its voltage is measured to zero. Error signal... Area; linear error between logic high level 11 and logic low level M v. (4) The unit LQl is operated in linear Mode 2. Bit 2 Γ· is pulled down to ground power H due to the conduction of the switching device SW2; ' : The voltage detection signal V d 1 is maintained to be substantially equal to the command voltage:: ratio Γ:, the end of the motor M The power of point A (4) is held in a substantial system - fixed signal pull D#u Vcom. Thus, when the command voltage signal Vcom is made to you ^ according to the motor control circuit 2 of the present invention, the current flows from the end point A to ... The constant pressure drive operation of the motor M is in the state control signal level during the red period T2, and the brake control device S4 white is the logic low level device SW1 disk ^ is the logic high level. Therefore, the driving circuit 26 causes an erroneous braking signal. The braking signals vel and ve2 having the logical position H make 24 1247479 yuan tons and lq2 enter the conduction mode 1 at the same time. According to the present invention, the control circuit 20 effectively achieves the braking operation state. With a library, the voltage at terminal A and terminal B of motor M is substantially equal to

Vm’因此電壓偵測信號〜與Vd2分別為 3 ( l+R3)*Vm 與 R4/(R2 + R4)*Vm。 準壯,作期間T3中’狀態控制信號與s3為邏輯高位 ,二控制信號82與%為邏輯低位準、並且煞車控制 首為邏輯低位準。因此,開關裝置^與開關單 Q二:通、開關裝置SW2與開關單元SQ2皆不導通、 並且煞車電路26處於 ^ ^ 、不賦此狀態。由於馬達Μ之端點Λ 口為短路於地面電位每 信號〜也為零。誤差貝上為零’故電㈣測 被拉w el因開關裝置SWl之導通而 輯古位s w面電位。誤差㈣Ve2為—線性信號,處於邏 輯同位準η與邏輯 绐『一 τ 位旱L間之線性區域,並且回授控制 線性早7G LQ2使之操作於線 V % i# ^ ^ …U生模式。結果,電壓偵測信號Vm' therefore voltage detection signals ~ and Vd2 are 3 (l+R3)*Vm and R4/(R2 + R4)*Vm, respectively. During the period of T3, the state control signal and s3 are logic high, the second control signal 82 and % are logic low, and the brake control is logic low. Therefore, the switching device ^ and the switch unit Q 2: the switch, the switch device SW2 and the switch unit SQ2 are not turned on, and the brake circuit 26 is in the ^ ^ state. Since the end of the motor port is short-circuited to the ground potential, the signal is also zero. The error is zero on the 'below' power (four) measurement. The pull w el is due to the conduction of the switching device SW1 and the ancient potential s w surface potential. The error (4) Ve2 is a linear signal, which is in the linear region between the logical parity η and the logic 绐 "a τ position drought L", and the feedback control linearity is 7G LQ2 to operate in the line V % i# ^ ^ ... U mode. Result, voltage detection signal

Vu維持成貫質上等於命令電壓 Μ之端點B之電壓維持 二。「二“之,馬達 ㈣,當命令電壓作成二…比於命令電麼信號 發明之馬達控制電路 係―㈣值時,依據本 點八流經馬達Μ之定壓達成使電流從端點B至端 思Μ之疋壓驅動操作狀態。 應注意雖然在圖2所+ ^ r η紅入认糾 斤的貫施例中,線性單元LQ!盥 LQ2_ 5於供應電壓源ν /、 SQ2麵合於馬達Μ與地面電位二且開關早-抑與 應用於線性單元LQlMQ^ ’但本發明不限於此而得 Q2耦合於馬達Μ與地面電位間且 25 1247479 開關單tg SQi與SQ2 _合於供應電壓源%與馬達μ間。 在此情況下’開關單元SQi與Sq2之導通分別決定馬達Μ 之知點Α與Β疋否短路於供應電壓源〜而線性單元叫 與LQ』分別提供受到回授控制的等纟電阻值於馬達以之 端點A與B以及地面電位間。 的各種修改與相似配詈。μ . ^ 置 口此’申清專利範圍之範圍應根 據最廣的言全釋,以包定所古卩 匕谷所有此類修改與相似配置。 雖^本發明業已藉由較佳實施例作為例示加以說 明’應瞭解者為:本發明不限於此被揭露的實施例。相反 地,本發明意欲涵蓋對於熟習此項技藝之人士而言係明顯 [圖式簡單說明】 圖1顯不習知的用於酿私民 用於|£動馬達之Η橋式電路之電路 圖。 圖2顯示依據本於明 ^月之馬達控制電路之一例子之電路 圖。 圖3顯示依據本發明口 73之&差放大态與煞車電路之—例 子之坪細電路圖。 列 圖4顯示依據本發 時序圖 馬達控制電路之三種操作狀! 元件符號說明: 1 〇 習知Η橋式電路 2〇 馬達控制電路 26 1247479 21 H 橋式電路 22 電 壓偵測電路 22l9 222 分壓器 23 誤 差放大器 24 回 授電路 25 狀 態控制電路 26 車電路 A, B 馬達之端點 BRK 煞 車控制信號 Ci? c2 電容 D! 〜D 4 二極體 〇! 〜g4 習知控制信號 Ii, 12 驅 動電流 lea 固 定電流源 LQi? LQ2 線性單元 M 馬邊 N! 〜Ν 9 NMOS電晶體 〇 1 ,〇2 輸出端 Pi 〜Ρ5 PMOS電晶體 Qi 〜q4 NMOS電晶體 Ri 〜R4 電阻 Si 〜S 4 狀態控制信號 SQi? SQ2 開關單元 swl5 sw: 1 開關裝置 1247479 h〜τ3 操作期間 vcom 命令電壓信號 vd,vdl,vd2 電壓偵測信號Vu is maintained to be consistently equal to the voltage of terminal B of the command voltage 维持. "Two", the motor (four), when the command voltage is made to two... Compared to the command motor, the invention of the motor control circuit system - (four) value, according to the point eight flow through the motor Μ constant pressure to achieve the current from the end point B The state of the drive is driven by the pressure. It should be noted that although in the example of Fig. 2, the linear unit LQ!盥LQ2_5 is applied to the supply voltage source ν /, SQ2 to the motor Μ and the ground potential 2 and the switch is early - It is applied to the linear unit LQ1MQ^', but the invention is not limited thereto, and Q2 is coupled between the motor Μ and the ground potential and the 25 1247479 switch single tg SQi and SQ2 _ are combined between the supply voltage source % and the motor μ. In this case, 'the conduction of the switching units SQi and Sq2 respectively determines whether the motor Μ knows the point Β疋 and Β疋 whether it is short-circuited to the supply voltage source ~ and the linear unit 叫 and LQ 』 respectively provides the equivalent 纟 resistance value of the feedback control to the motor Between the endpoints A and B and the ground potential. Various modifications and similar arrangements. μ . ^ The scope of this patent application should be based on the broadest interpretation of all such modifications and similar configurations. The present invention has been described by way of illustration of preferred embodiments. It is understood that the invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover a person skilled in the art. [Simplified illustration of the drawings] Fig. 1 is a circuit diagram of a bridge circuit for brewing a private motor. Fig. 2 is a circuit diagram showing an example of a motor control circuit according to the present invention. Fig. 3 is a view showing a fine circuit diagram of the & differential amplification state and the brake circuit of the port 73 according to the present invention. Figure 4 shows the three operation modes of the motor control circuit according to the timing diagram of the present invention! Symbol description of the components: 1 〇 Η Η bridge circuit 2 〇 motor control circuit 26 1247479 21 H bridge circuit 22 voltage detection circuit 2219 222 partial pressure 23 Error amplifier 24 Feedback circuit 25 State control circuit 26 Vehicle circuit A, B Motor terminal BRK Brake control signal Ci? c2 Capacitance D! ~ D 4 Diode 〇! ~ g4 Conventional control signal Ii, 12 drive Current lea Fixed current source LQi? LQ2 Linear unit M Horse side N! ~Ν 9 NMOS transistor 〇1, 〇2 Output terminal Pi~Ρ5 PMOS transistor Qi~q4 NMOS transistor Ri~R4 Resistance Si~S 4 State control Signal SQi? SQ2 Switch unit swl5 sw: 1 Switching device 1247479 h~τ3 During operation vcom command voltage signal vd, vdl, vd2 voltage detection signal

Vea 固定電壓源 ve, vel,ve2 誤差信號 vm 供應電壓源Vea fixed voltage source ve, vel, ve2 error signal vm supply voltage source

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Claims (1)

1247479 拾、申請專利範圍: 1 · 一種馬達控制電路,用於一 驅動電壓至-馬達,該 号達具有一第一端點與一第— _ ^ 乐一鳊點該驅動電壓係施加於 “弟端點與該第二端點間,該馬達控制電路包含: -- Η橋式電路’具有—第—線性單元、_第二線性單 兀、一第一開關單元、與一篦一 一 弟一開關早兀,該第一線性單 凡與該第一開關單元共同耦 极w Λ — 褐口至該弟一端點且該第二線1247479 Pickup, patent application scope: 1 · A motor control circuit for a driving voltage to - motor, the number has a first end point and a first - _ ^ Le 鳊 point the driving voltage is applied to the "di Between the end point and the second end point, the motor control circuit comprises: - a bridge type circuit having - a - linear unit, a second linear unit, a first switching unit, and a one-and-one brother Switching early, the first linear unit is coupled with the first switching unit to w Λ — the brown mouth to the one end of the brother and the second line 早兀/、該第二開關單元〜共同耦合至該第二端點; 一電壓偵測電路,用以產生至少一 φ 座生主^ 電壓偵測信號,其 代表該馬達之該驅動電壓; 一誤差放大器,用以產生至少一亨 甘l 士 土王少 W差^旎,其代表該 >'一電壓偵測信號與一命令電壓信號間之差異,其中該 至少-誤差信號係電性分離於該第—與該第二開關單元; 」一回授電路,輕合於該誤差放A器以接收該至少一誤 差信號,以選擇性施加該至少一誤差信號至該第一或該 二線性單元;以及The second switching unit is coupled to the second terminal; a voltage detecting circuit is configured to generate at least one φ generating main voltage detecting signal, which represents the driving voltage of the motor; An error amplifier for generating at least one Henggan L Shi Shi Wang Shao W difference, which represents a difference between the voltage detection signal and a command voltage signal, wherein the at least-error signal is electrically separated And the feedback circuit is coupled to the error amplifier to receive the at least one error signal to selectively apply the at least one error signal to the first or second linearity Unit; 仰一狀態控制電路,用以同步控制該第一與該第二開關 單元以及該回授電路,使得在一第一操作期間中,該第一 ,關單元操作於-不導通模式、該第二開關單元㈣於一 導通模式、該回授電路允許該至少一誤差信號之一個施加 至該第一線性單元,導致該第一線性單元操作於一線性模 式、並且该回授電路防止該至少一誤差信號施加至該第二 線性單元,藉而控制該驅動電壓實質上正比於該命令電壓 信號。 29 1247479 2 ·如申请專利範圍第 項之馬達控制電路,其中: 在該弟一知作期 向流經該馬達 第-端點至該第二端點:方該驅動電壓使得-電流以從該 3 ·如申請專利範圍第 該第一與該第二線性 項之馬達控制電路,其中: 且 單元更耦合至一供應電壓源,並 該第一與該第 開關 單元更辆合至一地面電位 4·如申請專利範圍第1 ‘ 項之馬達控制電路,其中: 該電壓偵測電路包含·· 電壓偵 間,用以輸出二該第-端點與-地面電位 測信號中之-個,以Γ 號,作為該至少一 聯於該第二端點與該地面電位 一第二分壓器,串 點分壓信號,作為該至少一 電壓偵 間,用以輸出一第 測信號中之另一個 5.如申請專利範圍第4項之馬達控制電路,其中: 該誤差放大器包含: -源極一第—NM〇S電晶體,具有一閉極、-沒極、盘 伟輕人/閘極係由該第—端點分壓信號所控制且該源極 係稱合於一固定電流.源; 30 1247479 一第二NMOS電晶體,具有一閘極、一汲極、與 一源極,該閘極係由該第二端點分壓信號所控制且該源極 係耦合於該固定電流源; 一第三NMOS電晶體,具有一閘極、一没極、與 一源極,該閘極係由該命令電壓信號所控制且該源極係耦 合於該固定電流源; 一第一電流鏡,具有一原始電流分支與一鏡像電 流分支,該原始電流分支係耦合於該第一 NMQS電晶體之 該汲極與該第二NMOS電晶體之該汲極; 一第二電流鏡,具有一原始電流分支與一鏡像電 流分支,該原始電流.分支係耦合於該第三NMOS電晶體之 該汲極; 一第三電流鏡,具有一原始電流分支與一鏡像電 流分支,該原始電流分支係耦合於該第一電流鏡之該鏡像 電流分支;以及 一第一輸出端,耦合於該第二電流鏡之該鏡像電 流分支與該第三電流鏡之該鏡像電流分支,用以供應該至 少一誤差信號之該一個。 6.如申請專利範圍第5項之馬達控制電路,其中: 該第 > 電流鏡之該原始電流分支係由一第一 PMOS電 晶體所實施,該第一 PMOS電晶體具有一閘極、一汲極、 與一源極,該閘極係耦合於該汲極、該汲極係耦合於該第 一 NMOS電晶體之該汲極與該第二NMOS電晶體之該汲 31 1247479 極、且該源極係耦合於一固定電壓源; 該第二電流鏡之該原始電流分支係由一第二PMOS電 晶體所實施,該第二PMOS電晶體具有一閘極、一汲極、 與一源極,該閘極係耦合於該汲極、該汲極係耦合於該第 三NMOS電晶體之該汲極、且該源極係耦合於該固定電壓 源; 該第一電流鏡之該鏡像電流分支係由一第三PMOS電 晶體所貫施’該第三PMOS電晶體具有一閘極、一沒極、 與一源極,該閘極係耦合於該第一電流鏡之該原始電流分 支之該閘極、該汲極係耦合於該第三電流鏡之該原始電流 分支、且該·源極係耦合於該固定電壓源;並且 該第二電流鏡之該鏡像電流分支係由一第四PMOS電 晶體所實施,該第四PMOS電晶體具有一閘極、一汲極、 與一源極,該閘極係耦合於該第二電流鏡之該原始電流分 支之該閘極、該汲極係耦合於該誤差放大器之該第一輸出 端、且該源極係耦合於該固定電壓源。 7.如申請專利範圍第5項之馬達控制電路,其中: 該第三電流鏡之該原始電流分支係由一第四NMOS 電晶體所實施,該第四NMOS電晶體具有一閘極、一汲 極、與一源極,該閘極係麵合於該沒極、該没極係_合於 該第一電流鏡之該鏡像電流分支、且該源極係耦合於一地 面電位,並且 該第三電流鏡之該鏡像電流分支係由一第五NMOS 32 1247479 電晶體所實施’該第五NMQS I晶體具有一閘極、一汲 極、與一源極,該閘極係耦合於該第四NM〇s電晶體之該 閘極、該汲極係耦合於該第二電流鏡之該鏡像電流分支、 且該源極係耦合於該地面電位。 8.如申請專利範圍第i項之馬達控制電路,其中: 該回授電路包含: 一第一開關裝置,耦合於該第一線性單元,並且 由該狀態控制電路所控制,用以在該第一操作期間中允許 該至少一誤差信號之該一個施加至該第一線性單元,以及 一第二開關裝置,耦合於該第二線性單元,並且 由該狀態控制電路所控制,用以在該第一操作期間中防止 該至少一誤差信號施加至該第二線性單元。 9·如申請專利範圍帛!項之馬達控制電路,其中·· 該回授電路包含: -帛-電容,耦合於該第一線性單元,用以在該 第一操作期間中,使該至少—誤差信號之該_個相對和緩 地施加至該第一線性單元。 10.如申請專利旄圍第i項之馬達控制電路,其中: 該狀態控制電路係同步輸出第—至第四狀態控制产 號,用以分別控制該回授電路之該第一與該第二開關裝; 以及該Η橋式電路之該第—與該第二_單元,其中 33 1247479 一至該第四狀態控制信號之每一個係一 有一邏輯高位準與—邏輯低位準,並且 數位邏輯信號,具 在該第一操作期間中 處於該邏輯低位準而該第 該邏輯高位準。 該第 與該第三狀態控制信號 二與該第四狀態控制信號處於 η.如申請專利範圍第!項之馬達控制電路,盆中: 元以::態電路更同步控制該第-與該第二開關單 :: 使得在一第二操作期間中,該第-開 2病作於料通模式作於該不導 u莫^、該回授電路防止該至少—誤差”施加至該第一 線性早兀、並且該回授電路允許該至少一誤差信號之另一 個施加至該第二線性單元,導致該第二線性單元操作於該 線性模式’藉而控制該驅動電壓實f上正比於該命令電壓 信號。 12·如申請專利範圍第n項之馬達控制電路,其中: 在該第二操作期間中,該驅動電壓使得一電流以從該 第二端點至該第一端點之方向流經該馬達。 13 ·如申請專利範圍第11項之馬達控制電路,其中: 該第二電流鏡更具有一平行鏡像電流分支,並聯耦合 於該第二電流鏡之該鏡像電流分支; 該第三電流鏡更具有一平行鏡像電流分支,並聯耦合 34 1247479 於該第三電流鏡之該鏡像電流分支;並且 該誤差放大器更包含一第二輸出端,耦合於該第二電 流鏡之該平行鏡像電流分支與該第三電流鏡之該平行鏡 像電流分支’用以供應該至少一誤差信號之另一個。 1 4 ·如申明專利乾圍弟11項之馬達控制電路,其中· 該回授電路包含: 一第一開關裝置,耦合於該第一線性單元,並且 由該狀態控制電路所控制,用以在該第一操作期間中允許 該至少一誤差信號之該一個施加至該第一線性單元,並且 在該第二操作期間中防止該至少一誤差信號施 , 一線性單元,以及 以弟 、X不一冰怔早兀,並 由該狀態控制電路所控制,用以在該第一操作期 該至少一誤差信號施加至該第二線性單元,並且在 操作期間中允許該至 弟 第二線性單元。 、差u之該另一個施加至. 15.如申請專利範圍第u項之馬達控制電路,其中 該回授電路包含: ,用以在該 個相對和緩 用以在該 一第一電容,耦合於該第一線性單元 第一操作期間中’使該至少一誤差信號之該一 地施加至該第一線性單元,以及 第二電容,耦合於該第二線性單元 35 1247479 第二操作期間中,使該至少一 緩地施加至該第二線性單元。 誤差信號之該另一個相對和 16.如申請專利範圍第11項之馬達控制電路’盆中. =狀態控制電路係同步輸出第一至第四狀態控制信 :及控制該回授電路之該第—與該第二開關裝置 及該Η橋式電路之該第一與該第二開關單元,其中 一至該第四狀離#告1产味 — / 狀〜、控制彳5唬之母一個係一數位邏輯信號,直 有一邏輯高位準與一邏輯低位準,使得: 八 户於㈣期間中’該第—與該第三狀態控制信號 低位準而該第二與該第四狀態控制信號處於 該邏輯南位準,並且 處於操作期間中,該第一與該第三狀態控制信號 ΐ二位準而該第二與該第四狀態控制信號處於 該邏輯低位準。 如申'專利範圍第1項之馬達控制電路,更包含: 一'一煞車電路,由該狀態控制電路所控制,使得在一 ,1、操:' t間中’該煞車電路轉換該至少-誤差信號成為至 =一‘、,、車信號,並且經由該回授電路同時施加該至少一敔 信號至該第—與該第二線性單元,導致該第一與該第二 線性單元同時操作於該導通模式,並1 在該第三操作期間中,該狀態控制電路控制該第—盘 該第二開關單元操作於該不導通模式。 /、 36 1247479 18. 如申請專利範圍第17項之馬達控制電路,其中: 該誤差放大器具右5/卜 有至》一反相輸入端,用以分別接收 該至少-電壓债測信號’以及一非反相輸入端,用以接收 該命令電壓信號,並且 在該第三操作期間中,該煞車電路使該誤差放大器之 該士二&相輸入端短路於該地面電位,使得該至少一誤 差信號轉換成為該至少一煞車作费。 19. 如申請專利範圍第18項之馬達控制電路,其中: 該誤差放大器f 至少一誤差信號,並i 卜輸出端,用以分別輸出該 在該第三操作期問φ 該至少-輸出端相對迅逹:棘拖車電路使該誤差放大器之 該至少-煞車信號。轉換該至少—誤差信號成為 20. 如申請匕專利範圍第17項之馬達控制電路,其中: 該狀恶控制電路係輪一 八 及一煞車控制信號,該第_ 4四狀g控制信號以 別控制該回授電路之^ ^㈣四狀態控制信號用以分 式電路之該第—_^;;與該第二開關裝置以及該Η橋 入該煞車電路,使、關單元,該煞車控制信號係輸 為該至少-敦車产,二、車電路轉換該至少-誤差信號成 以及該煞車控制信號之每—個H該第四狀態控制信號 個係一數位邏輯信號,具有一 37 1247479 趣輯高位準與一邏輯低位準,使得: 處於^Γ &作期間中,該第—與該第三狀態控制信號 孩邏輯低位準、兮— 邏輯言你、、隹_ dx弟—與該第四狀態控制信號處於該 冋、’二且該煞車控制信號處於該邏輯低位準,並且 在該第三操作期間中,該第一至該第四狀態控制信號 處於該邏輯低位準並且該煞車控制信號處於該邏輯高位 準。a first state control circuit for synchronously controlling the first and second switching units and the feedback circuit, such that in a first operation period, the first, off unit operates in a non-conduction mode, the second The switching unit (4) is in a conducting mode, the feedback circuit allowing one of the at least one error signal to be applied to the first linear unit, causing the first linear unit to operate in a linear mode, and the feedback circuit prevents the at least An error signal is applied to the second linear unit, whereby the drive voltage is controlled to be substantially proportional to the command voltage signal. 29 1247479 2 - The motor control circuit of claim 2, wherein: the first phase of the motor flows through the first end of the motor to the second end point: the driving voltage is such that the current is from 3. The motor control circuit of the first and second linear items of the patent application, wherein: the unit is further coupled to a supply voltage source, and the first and the first switch unit are further coupled to a ground potential 4 · For example, in the motor control circuit of claim 1 ', the voltage detection circuit includes a voltage detection circuit for outputting two of the first-end and the ground potential measurement signals. No. as the at least one second terminal and the ground potential-second voltage divider, the serial point voltage dividing signal is used as the at least one voltage detector to output another one of the first measured signals. The motor control circuit of claim 4, wherein: the error amplifier comprises: - a source-first NM 〇S transistor, having a closed-pole, - immersed, Pan Wei light person / gate system The first end point partial pressure Controlled by a source and coupled to a fixed current source; 30 1247479 a second NMOS transistor having a gate, a drain, and a source, the gate being terminated by the second terminal a voltage dividing signal is controlled and the source is coupled to the fixed current source; a third NMOS transistor having a gate, a gate, and a source, the gate being controlled by the command voltage signal and The source is coupled to the fixed current source; a first current mirror having an original current branch and a mirror current branch coupled to the drain of the first NMQS transistor and the second NMOS a second current mirror having a raw current branch and a mirror current branch, the original current branch being coupled to the drain of the third NMOS transistor; a third current mirror having An original current branch and a mirror current branch coupled to the mirror current branch of the first current mirror; and a first output coupled to the mirror current branch of the second current mirror Three current The mirror current branch of the mirror is used to supply the one of the at least one error signal. 6. The motor control circuit of claim 5, wherein: the first current branch of the current mirror is implemented by a first PMOS transistor having a gate and a gate a drain and a source, the gate is coupled to the drain, the drain is coupled to the drain of the first NMOS transistor and the gate of the second NMOS transistor 31 1247479 The source is coupled to a fixed voltage source; the original current branch of the second current mirror is implemented by a second PMOS transistor having a gate, a drain, and a source The gate is coupled to the drain, the drain is coupled to the drain of the third NMOS transistor, and the source is coupled to the fixed voltage source; the mirror current branch of the first current mirror Passing through a third PMOS transistor, the third PMOS transistor has a gate, a gate, and a source, and the gate is coupled to the original current branch of the first current mirror. a gate, the drain is coupled to the original current branch of the third current mirror And the source is coupled to the fixed voltage source; and the mirror current branch of the second current mirror is implemented by a fourth PMOS transistor having a gate and a drain. And a gate coupled to the gate of the original current branch of the second current mirror, the gate is coupled to the first output of the error amplifier, and the source is coupled to the gate Fixed voltage source. 7. The motor control circuit of claim 5, wherein: the original current branch of the third current mirror is implemented by a fourth NMOS transistor having a gate and a 汲a pole, a source, the gate is coupled to the gate, the gate current is coupled to the mirror current branch of the first current mirror, and the source is coupled to a ground potential, and the gate The mirror current branch of the three current mirror is implemented by a fifth NMOS 32 1247479 transistor. The fifth NMQS I crystal has a gate, a drain, and a source, and the gate is coupled to the fourth The gate of the NM〇s transistor is coupled to the mirror current branch of the second current mirror, and the source is coupled to the ground potential. 8. The motor control circuit of claim i, wherein: the feedback circuit comprises: a first switching device coupled to the first linear unit and controlled by the state control circuit for The first operation period allows the one of the at least one error signal to be applied to the first linear unit, and a second switching device coupled to the second linear unit and controlled by the state control circuit for The at least one error signal is prevented from being applied to the second linear unit during the first operation. 9. If you apply for a patent range 帛! a motor control circuit, wherein: the feedback circuit comprises: - a 帛-capacitor coupled to the first linear unit for causing the at least one of the at least - error signals to be relative during the first operation period Apply to the first linear unit gently. 10. The motor control circuit of claim i, wherein: the state control circuit synchronously outputs the first to fourth state control codes for respectively controlling the first and second of the feedback circuit a switch device; and the first and the second unit of the bridge circuit, wherein each of the 33 1247479 to the fourth state control signal has a logic high level and a logic low level, and the digital logic signal, At the logic low level during the first operation period and the first logic high level. The third state control signal 2 and the fourth state control signal are at η. As claimed in the patent scope! The motor control circuit of the item, in the basin: the:: state circuit controls the first-and the second switch more synchronously:: in a second operation period, the first-on-two disease is made in the material pass mode The feedback circuit prevents the at least-error from being applied to the first linear early 兀, and the feedback circuit allows the other of the at least one error signal to be applied to the second linear unit, Causing the second linear unit to operate in the linear mode to thereby control the driving voltage to be proportional to the command voltage signal. 12. The motor control circuit of claim n, wherein: during the second operation The driving voltage causes a current to flow through the motor in a direction from the second end to the first end point. 13. The motor control circuit of claim 11, wherein: the second current mirror is further Having a parallel mirror current branch coupled in parallel to the mirror current branch of the second current mirror; the third current mirror further having a parallel mirror current branch coupled in parallel with the first current mirror 34 1247479 And the error amplifier further includes a second output end coupled to the parallel mirror current branch of the second current mirror and the parallel mirror current branch of the third current mirror to supply the at least one error signal The other is the motor control circuit of claim 11 , wherein the feedback circuit comprises: a first switching device coupled to the first linear unit, and the state control circuit is Controlling to allow the one of the at least one error signal to be applied to the first linear unit during the first operation period, and preventing the at least one error signal, a linear unit during the second operation period, and The younger brother, X is not hail, and is controlled by the state control circuit for applying the at least one error signal to the second linear unit during the first operation period, and allowing the younger brother during the operation period. The second linear unit, the other of the difference u is applied to. 15. The motor control circuit of claim 5, wherein the feedback circuit comprises: Applying the one of the at least one error signal to the first linear unit during the first operation of the first linear unit during the first operation of the first and second capacitors, and a second capacitor coupled to the second linear unit 35 1247479 during the second operation period to cause the at least one to be slowly applied to the second linear unit. The other relative of the error signal and 16. The scope of claim 11 a motor control circuit 'in the basin. The state control circuit synchronously outputs the first to fourth state control signals: and controls the first of the feedback circuit and the first of the second switching device and the bridge circuit The second switch unit, wherein the one to the fourth shape is different from the first one, the control unit is a digital logic signal, and has a logic high level and a logic low level, so that: In the (four) period, the 'the first-lower level with the third state control signal and the second and the fourth state control signal are at the logic south level, and during the operation period, the first and the third state Ϊ́ two quasi control signal and the second control signal is the fourth state of the logic low level. For example, the motor control circuit of claim 1 of the patent scope further includes: a 'one brake circuit, which is controlled by the state control circuit, so that the brake circuit converts the at least one in one, one: The error signal becomes to = a ',, a vehicle signal, and the at least one signal is simultaneously applied to the first and the second linear unit via the feedback circuit, causing the first and second linear units to operate simultaneously The conduction mode, and 1 during the third operation period, the state control circuit controls the second switch unit to operate in the non-conduction mode. /, 36 1247479 18. The motor control circuit of claim 17, wherein: the error amplifier has a right 5/b to an inverting input for receiving the at least-voltage debt signal respectively a non-inverting input terminal for receiving the command voltage signal, and during the third operation period, the braking circuit short-circuits the second and the phase inputs of the error amplifier to the ground potential, such that the at least one The error signal is converted into the at least one vehicle fee. 19. The motor control circuit of claim 18, wherein: the error amplifier f has at least one error signal, and the output terminal is configured to respectively output the φ at the third operation period. Xunyi: The spine trailer circuit makes this error amplifier at least the brake signal. Converting the at least-error signal to 20. For example, the motor control circuit of claim 17 of the patent scope, wherein: the evil control circuit is a wheel and a brake control signal, and the fourth _4 g control signal is different Controlling the feedback circuit of the ^^(four) four-state control signal for the first portion of the fractional circuit; and the second switching device and the bridge into the braking circuit, the enabling and closing unit, the braking control signal The system converts the at least-error signal into the at least-error signal and the brake control signal for each H-the fourth state control signal is a digital logic signal having a 37 1247479 The high level and the low level of logic make: in the period of ^Γ &, the first - and the third state control signal have a low logic level, 兮 - logic words you, 隹 _ dx brother - and the fourth The state control signal is at the 冋, '2 and the brake control signal is at the logic low level, and during the third operation period, the first to the fourth state control signals are at the logic low level and the 煞The control signal is at a logic high level. 3838
TW93108187A 2004-03-25 2004-03-25 Motor control circuit for supplying a controllable driving voltage TWI247479B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI766768B (en) * 2021-07-21 2022-06-01 茂達電子股份有限公司 Motor controlling circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI398090B (en) * 2009-11-11 2013-06-01 Princeton Technology Corp Motor controlling circuit for multiple control modes
TWI790862B (en) 2021-12-17 2023-01-21 茂達電子股份有限公司 Braking control system of motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI766768B (en) * 2021-07-21 2022-06-01 茂達電子股份有限公司 Motor controlling circuit

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