TWI247413B - Electrostatic discharge protection circuit and semiconductor circuit having the same - Google Patents

Abstract

An ESD protection circuit and a semiconductor circuit using the same are provided. The ESD protection circuit is connected between a first and a second power source lines, and comprises a first silicon controlled rectifier (SCR), a second silicon controlled rectifier, and a parasitic diode. The gate of the first silicon controlled rectifier is connected to a first power source line, and the gate of the second silicon controlled rectifier is also connected to the first power source line.

Description

And especially about one kind

1247413 14327twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a protection circuit for protecting an electrostatic discharge of a circuit. [Prior Art] Today's integrated circuits are becoming more and more power-saving because of the innovation of the process and technology, and thus more power-saving. However, the voltage of the body circuit is not an ideal standard value. Occasionally, there is an electric voltage noise generated by == and the electric power is too large. If this phenomenon is not prevented, the noise is too large and the integrated circuit in operation is burned. All are. Therefore, it is necessary to prevent sudden voltage noise from causing damage to the internal circuit, which is the responsibility of the protection circuit. Figure 1 is a block diagram showing the protection circuit architecture for electrostatic discharge. As shown in the figure, the circuit of the electrostatic discharge has two clamp circuit 13〇 and 135, and the electrostatic discharge protection circuit just and = stay, the circuit to be protected is the integrated circuit 1GS, integrated circuit ιι〇 = is located between the integrated circuit 105 and the integrated body 110 as the data transfer/1-plane circuit 120. The electrostatic discharge protection circuit 14A and the electrostatic discharge protection circuit 145 serve the same function. The integrated circuit 105 is connected to the first voltage source vddl and the ground terminal GND integrated circuit 11 is connected to the second voltage source v and the second ground GND2' and the interface circuit 12 is connected to the first voltage source side. Bu = ground G brain, second voltage source Vdd2, and the second dirty are electrically connected. 5 1247413 14327twf.doc/006 Therefore, if the electrostatic voltage noise occurs in the first voltage source Vddl, the electrostatic discharge powder level circuit 130 and the electrostatic discharge connection circuit 14 are theoretically turned on immediately, so that the electrostatic voltage noise is generated. The current flows through the electrostatic discharge I-growth circuit 130 and the electrostatic discharge connection circuit 14 to GNm and Vdd2, and does not cause the noise current to flow through the integrated circuit 1〇5 and the interface circuit 120 to cause burnout. Conversely, if the second voltage source Vdd2 generates an electrostatic voltage hysteresis, the 'electrostatic discharge clamp circuit 135 and the electrostatic discharge connection circuit 14〇φ will immediately V-pass, and the noise current generated by the electrostatic voltage noise is discharged through the electrostatic discharge. The clamp circuit 130 and the electrostatic discharge connection circuit 14 are turned to GND2 and Vddl', and the noise current does not flow through the integrated circuit 11 and the interface circuit 120 to cause burnout. In the prior art, the electrostatic discharge connection circuits 140 and 145 are mostly made of a diode or a semiconductor controlled rectifier (SCR), which is characterized by a diode or a semiconductor. The controlled rectifier has a low holding voltage and therefore low power. Among them, the semiconductor controlled rectifier can be divided into a lateral semiconductor controlled rectifier (lateral > SCR, LSCR for short) and a low voltage triggered semiconductor controlled rectifier (i〇w). Voltage trigger SCR, referred to as LVTSCR). Please refer to Figure 2. Figure 2 is a block diagram and block diagram of a conventional electrostatic discharge connection circuit 140, 145 of Figure 1. The semiconductor-controlled rectifier used here is a semiconductor-controlled rectifier, which is similar to a PM〇S (positive_channel metal oxide semiconductor) transistor plus an N+ pole region due to the lateral semiconductor-controlled rectification. Here, it is called a P-type semiconductor-controlled rectifier (P-type SCR, PSCR for short), or 6 1247413 14327twf.doc/006 is similar to an NMOS (negative-channel metal oxide semiconductor) transistor plus A p+ pole region, which is referred to herein as an N-type semiconductor rock-controlled rectifier (10) ype SCR, referred to as psc illusion, 'so for the convenience of viewing Figure 2, the left diagram of Figure 2 plus the equivalent 1> The illustration is shown in the right diagram of Figure 2 with an equivalent NM〇s diagram to facilitate understanding of the original A. The functions of the left and right diagrams of Figure 2 are the same. The left diagram of Figure 2 is composed of two pscr I4la and 143a. The control gate of the PMOS in PSCR 141a is connected to Vddl in Φ, and the control gate of PMOS in PSCR M3a is connected to Vdd2. Research (4) 2. Therefore, when the Vddl generates a large positive electrostatic voltage noise, the voltage difference between the anode of the PSCR 143a (ie, the source end of the pM〇s) and the control gate of the PMOS may be greater than the pM in this instantaneous time. The threshold voltage of s generates a current path, so that Vddl and Vdd2 are turned on via PSCR 143a. Usually, the threshold voltage is 〇·4~2 volts. To simplify the description, the following threshold voltages are 丨VV. Similarly, when Vdd2 generates a large positive electrostatic voltage noise, the voltage difference between the anode of the PSCR 14la (ie, the end of the PM0S) and the control gate of the PMOS is greater than this in the #1 instantaneous time. The threshold voltage of pM〇s (about 1 volt) generates a current path, so that vddl and Vdd2 are turned on via PSCR 141a, so that the noise current generated by the electrostatic voltage noise does not harm the internal circuit. The electrostatic discharge connection circuit 14 of the right diagram of FIG. 2 is composed of two nscr 141b and 143b, wherein the control gate of the NMOS in the NSCR 141b is connected to Vss2, and the control gate of the NMOS in the NSCR 143b is 1247413 14327twf. Doc/006

Vss 1 is connected to the rest of the relationship. Here, the Vss 1 disk Yg § 2 is the same as Vddl and Vdd2, and its name is changed for convenience of explanation. Therefore, when Vssl generates a large positive electrostatic voltage noise, the control gate of the NMOS in the NSCR 143b and the NSCR 141b are in this instantaneous time.

The voltage difference between the cathode (ie, the source end of the NMOS) is greater than the threshold voltage of this nm〇s (also about 1 volt) to generate a current path, so that Vssl and Vss2 are turned on via the NSCR 143b, so that the noise generated by the electrostatic voltage noise is generated. The current does not hurt the internal circuitry. The operation principle of NSCR 141b is the same as that of NSCR 143b, and will not be described here. As described above, the electrostatic discharge connection circuit in the protection circuit structure of the white pen is used as the first voltage source Vddl and the second voltage source -

When Vdd2 differs by more than 1 volt, the above-mentioned electrostatic discharge connecting circuit will =' such that the integrated circuits 1〇5 and 110* can receive the input from the outside. Therefore, the difference between the first voltage source Vddl and the second voltage source Vdd2 must be less than 1 volt to use the circuit, or a plurality of static J-connected circuits must be connected in series to allow the first source Vddl and the second voltage source Vdd. 】 / Tian 1 volt difference 'so that the limitations here lead to the circuit design (four) link circuit ' must be seen from the structure diagram below Figure 2, because PSCR 141a phase i, ^ ^ lVddl meet, PSCR 143a The control gate and her must be on the PSCR 141a and PSCR 143a N well area Γ placed in the same N N well area, job 141b and, the same situation, resulting in circuit wiring area will increase 1247413 14327twf.doc/006 Large, it will also increase costs. SUMMARY OF THE INVENTION The object of the present invention is to use a circuit in which the circuit can be designed without the electrostatic discharge of the electrostatic discharge, and the present invention can be used with the voltage source and the second voltage source of the present invention. Providing an electrostatic discharge road can reduce the cost of the circuit and protect the electric wiring area and reduce the cost. x, the purpose is to provide a two-way structure for electrostatic discharge, which can be used to design the circuit without paying attention to the difference between the first voltage source and the first: the cost can be reduced and the area can be reduced. 1 way wiring The present invention proposes an electrostatic discharge protection circuit, the first-integrated circuit, including the first-phase control positive-, first-semiconductor-controlled rectifier, and parasitic two-semiconductor rectifying ϋ including the first-metal oxide The cathode of the semi-conductive-medium-semiconducting financial control rectifier and the first voltage source phase: the anode of the semiconductor hybrid rectifier is connected to the second voltage source. The second MOS rectifier transistor includes a second metal oxide semiconductor transistor, the anode of the second semiconductor thyristor is connected to the first voltage source, and the second cathode of the second rectifier is connected to the second voltage source, wherein The gate of the first and the first metal oxide semiconductor transistor is connected to the -voltage source and the voltage source. The cathode of the parasitic diode and the anode of the first voltage source are connected to the second voltage source. According to an embodiment of the invention, the first and second voltage sources are relatively high voltage sources (Vdd) of the system 9 1247413 14327 twf.doc/006, and the first and the second metal oxide semiconductor transistors are P And the gate is connected to the first voltage source. The ESD protection circuit may further include a signal delay single S, between the electrical_to-first voltage source and the gate of the second metal oxide semiconductor transistor. According to an embodiment of the invention, the first and second voltages are relatively low voltage sources (Vss), and the first and second metal oxide semiconductor transistors are N-type and the gates are connected to the second voltage source. In this case, the signal delay unit may be further coupled between the second voltage source and the gate of the N-type first metal oxide semiconductor transistor. The signal delay unit is a circuit composed of a resistor, a circuit composed of a resistor and a capacitor, or a transmission gate. The invention further proposes an electrostatic discharge circuit suitable for use in an integrated circuit having a first electric waste source and a second electric ink source, including a first semiconductor hybrid rectification||, a second conversion financial control rectification series Parasitic diode. The first half of the body-rock control rectifier includes a first metal oxide semiconductor transistor, wherein the cathode of the first-semiconductor financial rectifier is connected to the first voltage source, and the anode and the second of the semiconductor-controlled rectifier The voltage sources are connected. The first-half V body 11-controlled rectification includes a second metal oxide semiconductor transistor, wherein an anode of the second semiconductor-controlled rectifier is connected to the first voltage source, and a cathode of the first-semiconductor controlled rectification crucible and the second (four) The source is connected, wherein the closed end of the second metal oxide semiconductor transistor is connected to the first voltage source and the second voltage source via the signal delay unit. The parasitic ^' where the cathode is connected to the first voltage source and the second voltage source of the parasitic diode is connected. 1247413 14327twf.doc/006 According to an embodiment of the invention, the first and second voltage sources are relatively high voltage sources of the system, and the first and second metal oxide semiconductor transistors are P-type and the gates are signaled The delay unit is connected to the first voltage source. The first and second voltage sources are relatively low voltage sources of the system, and the first and second metal oxide semiconductor transistor types are coupled to the second voltage source via the signal delay unit.

The aforementioned signal delay unit is a circuit composed of a resistor, a circuit composed of a resistor and a capacitor, or a transmission gate. According to an embodiment of the present invention, an electrostatic discharge protection semiconductor circuit is further provided in an integrated circuit having a first voltage source and a second voltage source. The electrostatic discharge/protective semiconductor circuit comprises: a substrate; a well region, located in the substrate; a first first type (eg N-type) doped region and a second first type doped region, located in the substrate and outside the well region The second first type doped region is switched to the second voltage source; the first and second second type (eg, p-type) doped regions are adjacent to the m-type doped region, respectively, and are located at the substrate and the well In the region, the second and fourth second type doping regions are respectively adjacent to the first and second second type impurity regions, and are located in the well region, wherein the third second cutting region _ to the ^ voltage source a first gate structure, located on the substrate and in the first and third regions, wherein the first-type doped region and the first-gate structure are engaged, the younger-voltage source; the third- a doped region located in the well region between the third and fourth second doped regions; and a second gate structure on the substrate and between the second and fourth second doped regions , the = impurity region, the fourth second type doping region and the second gate junction are connected to the first voltage source. In the above structure, the third second division d and the third first type 11 1247413 14327twf.doc/006 doped regions constitute a parasitic diode. The first first type doping region, the substrate, the t»海井£ and the second two-type doping region constitute a first semiconductor cut-controlled rectification, and in addition, the brother-in-four second-type doping region, the The well region, the substrate and the second first type doped region constitute a second semiconductor controlled rectifier. According to an embodiment of the invention, an electrostatic discharge protection semiconductor circuit is further provided for use in an integrated circuit having a first voltage source and a second voltage source. The static and discharge protection semiconductor circuit comprises: a substrate; a well region, located in the substrate; the first first type doping region and the second first type doping region are located outside the junction region of the substrate, wherein the first first type is doped The doped region is reduced to the first voltage source and the second first doped region is coupled to the second voltage source; the third and fourth first doped regions are adjacent to the first and second first doped regions, respectively And in the substrate, in the region, the first gate structure is located on the substrate and between the first fish "type doped regions, wherein the first-interpole junction __ a private source, the second a gate structure, located on the substrate and between the second and fourth inter-cells, wherein the second interpole structure _ is connected to the second voltage, the dice, the first second type doped region, and the third disc respectively a fourth first = : a burn tree, wherein the first second type doped region · and the second: the second source and the second second type doped region are coupled to the first voltage source; , located in the well zone and located between the first and the first -the ===, wherein the fifth first type doped region is coupled to the third region. 'The third, the doping region and the fifth first type are mixed. Area And the first second type doped type II, the substrate, the well, η Chu-constituting the first abundance conductor stone-controlled rectifier; another χ-31 doped region, the well region, the substrate and the first The first 12 1247413 14327twf.doc/006 type doped region constitutes the second semiconductor controlled rectifier. The present invention (4) connects the control side poles of the metal oxide body of the two financial control rectifiers (10) to the same On the electrical surface, therefore, the conduction of the two semiconductor-controlled rectifiers is based on the above-mentioned voltage source:: control, 'if one is, it is not necessary to connect multiple semiconductors to control the rectifier string=卩The voltage difference between the voltage source and the second voltage source is large. And the cuff is connected to the same-/voltage source due to the control of the metal oxide semiconductor transistor, so the N well region can be used in the circuit wiring. The area of the circuit wiring is thus reduced, and the cost of the production is reduced. The above-mentioned and other objects, features and advantages of the present invention are described in detail with reference to the accompanying drawings. The invention is to put a static electricity of a conventional technology into a semiconductor The control pole of the device is connected to the same two ========================================================================================== : Source === Control of the flow device • Do not cover the area of the wiring to save the cost. Reduce the electrical protection according to the frustration - the circuit block of the electrostatic discharge protection circuit of the electrostatic discharge ± of the preferred embodiment Figure should be surnamed = time reference picture] Lang 3, electrostatic discharge t in Figure 3,: composition. The sub-electrode protection circuit 140 of Figure 1. For the sake of = road 340 j to see Figure 13 1247413 14327twf. Doc/006 3, especially on the left diagram of Figure 3 plus the equivalent PM 〇 s diagram, the right diagram of Figure 3 plus the equivalent NMOS diagram to facilitate understanding of the principle. The operation principle of the left and right diagrams of FIG. 3 is the same. Therefore, in the following embodiments, only the left half of the diagram is an electrostatic discharge protection circuit 34 designed by a P-type semiconductor controlled rectifier (p_type SCR, PSCR for short). 〇 The electrostatic discharge protection circuit 34 designed by N-type semiconductor controlled rectifier (NSCR) in the right half of the figure refers to the operating principle of psCR. • In the left half of Figure 3, the circuit is framed on a substrate, such as a P-type substrate. There is a well region in the substrate, such as an N-doped well region. As shown, a plurality of doped regions are formed in the substrate and the well region, respectively, to form the electrostatic, electrical protection circuit 340 of the present invention. The first-type (eg, N-type) doped region and the first first-type doped region are located in the substrate and outside the well region, wherein the second first-type doped region is coupled to the second voltage source Vdd2. The first and second second type (e.g., P-type) doped regions are adjacent to the first and second first type doped regions, respectively, and are located in the base and ί regions. The third and fourth second type doping regions are adjacent to the first and second second type doping regions, respectively, and are located in the well region, wherein the third second type impurity changing region is lightly connected to the second voltage source Vdd2. The first gate structure G is located on the substrate and between the first and third second type doping regions, wherein the first first type, the impurity region and the first gate structure G1 are connected to the first voltage source vddl . The first doped region of the first type is located in the well region and between the third and fourth doped regions. And the second gate structure G2 is located on the substrate and between the second and fourth second type doping regions, wherein the third first type doping region, the fourth second type doping region and the second gate structure G2 side is connected to the first voltage source

Vddl. In the above structure, the third second type doping region and the third first type doping region constitute a 14 1247413 14327 twf.doc/006 parasitic diode (shown by a broken line). First first type doped region, substrate, well region

The first semiconductor-type doped region (e.g., P-type SCR 'PSCR) 341a is formed with the second first-type doped region. In addition, the fourth second type doping region, the well region, the substrate and the second first type doping region constitute a second semiconductor rock-controlled rectifier 343a. The electrostatic discharge protection circuit 340 has two PSCRs 341a, 343a, PSCR 341a. The cathode is connected to the first voltage source Vddl, and the anode is connected to the second voltage source Vdd2, and the control gate of the PMOS in the PSCR 341a is coupled to Vddl. The anode of the PSCR 343a is connected to the first voltage source, and the control terminal of the PMOS of the cathode connected to the voltage source Vdd2' PSCR 343a is also coupled to Vddl.

Therefore, whether or not the PSCRs 341a and 343a are turned on or not is determined based on the first voltage source Vddl. If the first voltage source vddl generates a positive electrostatic voltage noise greater than the PMOS breakdown voltage in the pscR 343a, then at this instant, the PSCR 343a will be generated by the KpM〇s collapse current, and the PSCR The 343a is turned on, so that the noise current generated by the electrostatic voltage noise passes through the electrostatic discharge protection circuit 14A to reach the first voltage source Vdd2 to accomplish the object of the present invention. In this embodiment, the threshold voltages of the PSCR and the NSCR are both taken as i volts. If the second voltage source Vdd2 has a large positive static voltage noise, then at this instant, the parasitic diode 344a located between the two PSCRs 341a, 343a may be greater than the first voltage source vddl due to the second voltage source vdd2. Turning on, the PSCR 341a is connected to a different level/stage, a well area, and a p-type substrate to become a bi-carrier junction transistor similar to pNp 15 1247413 14327twf.doc/006 junction ( Bip〇iar juncti〇n transistor (BJT for short) conducts current into the P-type substrate to turn on PSCR 341a; in addition, if the voltage difference of Vdd2 with respect to vddl is greater than the threshold voltage of PMOS in PSCR 341a, PSCR 341a is also turned on; Finally, the noise current generated by the electrostatic voltage noise is caused to reach the first voltage source vddl from the electrostatic discharge protection circuit 340 for the purpose of the present invention. In addition, as shown in the structural diagram at the lower left of Fig. 3, since the control gates of pm〇S in PSCr 341a and 343a are both connected to the first voltage source Vddl, the two n well regions can be placed in the same n well region. This greatly reduces the area of the circuit wiring. The dotted diode shown in the figure is the position of the parasitic diode 344a.

Another embodiment is shown in the lower right of Fig. 3, and its structure is similar to that of the pscR type, and its detailed structure is not redundant. Similarly, the structure diagram at the lower right of Fig. 3 is because the control gates of the NSCRs 341b and 343b are both connected to the first voltage source Vss2, so that the two n well regions can be placed in the same N well region. The dotted diode shown in the figure is the position of the parasitic diode 344b. 4 is a circuit block diagram of an ESD connection circuit in a protection circuit for electrostatic discharge according to another preferred embodiment of the present invention. The block diagram of the upper half of Figure 3 is roughly the same, with only a signal delay unit (soft_pull_up circuit unit, SPU) 450a between the control gate of the pscR 343a and the first voltage source Vddl. The signal delay units 450a and 450b are the same device, and are mainly used to transmit and delay the electrostatic noise generated by the first voltage source Vddl 16 1247413 14327twf.doc/006. The electrostatic voltage noise is delayed by between about a few nanoseconds and a few microseconds, so that the voltage of the PMOS control terminal in the PSCR 343a is maintained during the occurrence of electrostatic voltage noise. The low voltage state maintains the first voltage source vddl and the first voltage source Vdd2 in an on state. The control gate of the NMOS in NSCR 343b is also the same principle. When the electrostatic voltage noise occurs, it is maintained at a high voltage state. The rest of the process will not be described here. • Since the duration of the electrostatic voltage noise is only a few hundred nanoseconds, the function of the signal delay units 450a and 450b is to turn on the first voltage source and the second voltage source Vdd2 once the electrostatic voltage noise is generated. - For a period of time, the electrostatic voltage noise is passed, so that the electrostatic discharge protection circuit can quickly eliminate the electrostatic voltage noise. FIG. 5 is a circuit diagram of a signal delay unit 45A in an electrostatic discharge connection circuit according to another preferred embodiment of the present invention. FIG. 6 is a circuit diagram of a signal delay unit 450b in an electrostatic discharge connection circuit according to another preferred embodiment of the present invention. Referring to FIG. 5 and FIG. 6, at the same time, since the delay time is short, the circuit (8) only needs one resistor to delay the signal. Circuit (b) uses a resistor-capacitor circuit (RC drcuit) to adjust the delay time depending on the size of the capacitor. The circuit (4) uses the transmission gate as the signal delay unit, and uses the resistance in the transmission gate and its parasitic capacitance to delay the electrostatic voltage noise to achieve the above-mentioned transmission to maintain the electrostatic voltage noise. Figure 7 is a block diagram showing the circuit of an electrostatic discharge connection circuit in an electrostatic discharge protection circuit according to still another preferred embodiment of the present invention. Figure 7 17 1247413 14327twf.doc/006

The left half is substantially the same as the circuit block diagram of the left half of Figure 3, only between the control gate of PSCR 343a to the first voltage source vd (n, and the control gate of psCR 3jla to the first voltage source vddl, Both are connected to the signal delay τ 550a. Since the control gates of the two semiconductor step-controlled rectifiers pscR 341a, 343 & are driven by the first voltage source vddl, in this embodiment, the first voltage source vddl has In the case of positive electrostatic voltage noise, the delay unit will delay the electrostatic voltage noise to the control gates of the two semiconductors 矽 整流 PS PS PS PS PS PS 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并The pscR 341a, 343a is turned on to continuously turn on the first voltage source Vddl and Vdd2. The signal delay unit 550a of Fig. 7 is identical to the signal delay unit 45 of Fig. 4. The right half of Fig. 7 is similar to the left half, only The control gate of the NSCR 343b is connected to the second voltage source Vss2, and the control terminal of the NSCR 341b to the second voltage source Vss2 is connected to the signal delay unit 5. The signal delay unit 550b of FIG. 7 and the signal of FIG. 4 are delayed. Unit overview is phase In addition, according to the voltage difference between the first voltage source Vddl and the second voltage source Vdd2, a plurality of pcSR connections (not shown) may be disposed in the first voltage source Vddl and the second in the electrostatic discharge protection circuit. The voltage source Vdd2 does not describe the principle here. According to the voltage difference between the voltage source Vssl and the voltage source Vss2, a plurality of NCSRs can be connected in series (not shown) to the voltage source vssl in the ESD protection circuit. And the voltage source vssd2. As described above, the present invention connects the control gates of the metal oxide semiconductor transistors in the two semiconductor-controlled rectifiers to the same voltage 1247413 14327twf.doc/006 source. The conduction and non-conduction of the two semiconductor controlled rectifiers are controlled by the above voltage source, so that the plurality of semiconductor step-controlled rectifiers are not required to be connected in series, so that the first voltage source and the second power source can be used. The difference between the electro-inks is large. Moreover, since the control electrodes of the MOS transistors are all connected to the same voltage source, the well regions can be made together during the circuit wiring, so that the area of the circuit wiring is reduced. , While reducing the cost of production.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the invention, and it is possible to make some modifications and retouchings without departing from the spirit of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 depicts a block diagram of a protection circuit architecture that is not an electrostatic discharge. 2 is a circuit block diagram and a structural diagram of a conventional electrostatic discharge connection circuit 140 of FIG. 3 is a circuit block diagram and a structure of an electrostatic discharge connection circuit in an electrostatic discharge=protection circuit according to a preferred embodiment of the present invention, which is a preferred embodiment of the present invention. ...^ The circuit block diagram of the ESD connection circuit in the protection circuit. Figure 5 is a circuit diagram showing the addition of a signal delay unit 45 in a static electrical connection circuit in accordance with another embodiment of the present invention. Figure 6 is a circuit diagram of a signal delay unit 45% in a static and electrical connection circuit in accordance with another embodiment of the present invention. Figure 7 is a block diagram of an electrostatic discharge connection circuit in an electrical protection circuit in accordance with a repetitive embodiment of the present invention. 1247413 14327twf.doc/006. [Description of main component symbols] 105, 110: integrated circuit 120 · interface circuit 130, 135: electrostatic discharge clamp circuit 140, 145: electrostatic discharge connection circuit 141a, 143a, 341a, 343a: P-type semiconductor controlled rectifier ( P_type SCR) 141b, 143b, 341b, 343b · N-type semiconductor controlled rectifier (N-type SCR) 344a, 344b · Parasitic diodes 450a, 450b, 550a, 550b ··Signal delay unit

20

Claims (1)

1247413 14327twf.doc/006 X. Application for Patent Park: 1. An electrostatic discharge protection circuit, 褕 and m original - integrated 3 / = with - first - electricity 1 original including one; 3? Shi Xidou control machine The first semiconductor-controlled rectifier includes a metal-oxide semiconductor transistor, wherein a cathode of the first controlled rectifier is connected to the first electrical surface, and an anode of the first controlled rectifier and the second The voltage source is connected; _ a cup of a cup I" semiconductor stone-controlled rectifier 'the second semiconductor-stone rectifier rectifier = metal oxide semiconductor transistor, wherein the anode of the second semiconductor second-controlled rectifier and the first fg The source of the control of the whole production test is connected to the 'the second semiconductor stone Xi 2: the two voltage sources are connected', wherein the first and the second transistor are connected to the first voltage source and the first One of the electric dust sources, and a parasitic diode, wherein the parasitic diode source is connected, the parasitic diode is _"= a circuit, wherein the brother and the second power source, and the First - opposite to the second metal oxygen and the gate is connected The first voltage source. The body transistor is a Ρ-type and 3· as in the scope of the patent application scope, wherein the first-and second-source power source protects the power source, and the first and the first The second metal oxide semiconductor has a voltage and the gate is connected to the second voltage source. The body electrical body is N-type and 4. The electrostatic discharge protection power according to the second item of claim 2 21474413 14327twf The .doc/006 circuit further includes a signal delay unit electrically coupled between the first voltage source and the gate of the P-type second metal oxide semiconductor transistor. The protection circuit for electrostatic discharge of the present invention further includes a signal delay unit electrically coupled between the second voltage source and the gate of the N-type second metal oxide semiconductor transistor. The anti-shake circuit for electrostatic discharge according to the fourth or fifth aspect of the invention, wherein the signal delay unit is a circuit composed of a resistor. 7. The protection circuit for electrostatic discharge according to claim 4 or 5, wherein the signal delay unit is a circuit composed of a resistor and a capacitor. 8. 8. As described in claim 4 or 5. The protection circuit for electrostatic discharge, wherein the signal delay unit is _. =-Transfer to protect the circuit, suitable for having a first-in-one source and a second voltage source, including a financial rectifier, the first-semiconductor-controlled rectifier includes -苐- a metal oxide semiconductor transistor, wherein a cathode of the current device is connected to the first electrical source, and an anode of the first semiconductor controlled rectifier is connected to the second voltage source. An H-conductor-controlled rectifier oxide semiconductor transistor, wherein an anode of the second semiconductor device is connected to the first-electro-electric source, and the cathode of the second semiconductor-controlled cathode is connected to the second-electrode The closed pole of the semiconductor transistor, via the signal delay = connected to the turn-voltage source and the second source - to = 22 1247413 14327twf.doc / 006 - parasitic one body 'the parasitic pole The cathode of the body is connected to the first voltage source, and the anode of the parasitic diode is connected to the second voltage source. 10. 10. For the protection of the electrostatic discharge according to Item 9 of the full-time application, the first section is And the second voltage source is a relatively high voltage source of the system, and the first and the second metal oxide are half • crystals and electrically connected to the first gate voltage source through the signal delay unit. I亚. As claimed in the patent application, the φ path of the electrostatic discharge described in the ninth item, the second voltage source is the relatively low source of the system and the 5th - and the - metal oxide The semiconductor transistor is and the gate is connected to the second voltage source via the signal delay unit. , ' 12. If you apply for the full-scale circumstance of the 9th rhyme, the signal delay unit is a circuit composed of resistors. 13. The protection circuit for electrostatic discharge according to claim 9, wherein the signal delay unit is a circuit composed of a resistor and a capacitor. 14. The protection circuit for electrostatic discharge according to claim 9, wherein the signal delay unit is a transmission gate. • A semiconductor circuit having an electrostatic discharge protection circuit, comprising: - a first-integrated circuit, an electrical-to-high voltage source and a first low-voltage source; - a second integrated circuit, an electrical secret And a second high voltage source and a second low voltage source; a first electrostatic discharge protection circuit coupled between the first and the second high voltage source, further comprising: ^ -Ρ type - semiconductor second a controlled rectifier comprising: -p type 23 1247413 14327 twf.doc/006 a metal oxide semiconductor transistor, wherein a cathode of the p-type first semiconductor controlled rectifier is connected to the first high voltage source, the p type first An anode of the semiconductor-controlled rectifier is connected to the second high-voltage source, and a P-type second semiconductor-controlled rectifier includes a p-type second oxide semiconductor transistor, wherein the p-type second semiconductor is controlled And an anode of the flow device is connected to the first high voltage source, and a cathode of the p-type second semiconductor rock-controlled rectifier is connected to the second high voltage source, wherein the p-type first and the p-type Gate connection of two metal oxide semiconductor transistors The first high voltage source, and a parasitic diode, wherein the cathode of the parasitic diode is connected to the first high voltage source, and the anode of the parasitic diode is connected to the second high voltage source; a second electrostatic discharge protection circuit coupled between the first and the second low voltage source, further comprising: an N-type first semiconductor controlled rectifier, comprising an N-type first metal oxide semiconductor a transistor, wherein a cathode of the first semiconductor controlled rectifier is connected to the first low voltage source, and an anode of the N-type first semiconductor controlled rectifier is connected to the second low voltage source, N type a semiconductor magnet synchronous rectifier comprising an N-type oxide semiconductor transistor, wherein an anode of the N-type second semiconductor controlled rectifier is connected to the first low voltage source, the N-type second semiconductor controlled rectifier a cathode connected to the second low voltage source, wherein a gate of the N-type *Nth and N-type second metal oxide semiconductor transistors is connected to the second low voltage source, and 24 1247413 14327twf.doc/006 a viable dipole, of which The cathode of the parasitic diode and the second - the low voltage source in contact with the anode of the parasitic diode of the second low electrical contact. "' 16. If you apply for a home circuit _ 15 semiconductor circuits with electrostatic discharge circuits, including n delay, electricity =, to the first high voltage source and the p-type second metal oxide semiconductor Between the gates of the transistor. The circuit 15 has an electrostatic discharge protection connection 3' and further includes a second signal delay unit 71, which is electrically lighter and has static electricity as described in Item 16 or Item 17 of the second metal oxide semiconductor The circuit consisting of a resistor, wherein the signal delay unit is an electric discharge material, and the circuit has a static resistance and a capacitance circuit, wherein the signal delay unit is electrically discharged according to item 16 or item t7. brake. And a v-body circuit, wherein the 戎峨 delay unit is a circuit of a semi-conducting ^ ^ 帛 帛 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电 静电Connected between the first high voltage and low voltage source; and 25 1247413 14327twf.doc/006 voltage-second electrostatic discharge clamp circuit between the electrical source and the second low voltage source. The electric circuit of the circuit of claim 15, wherein the semiconductor circuit of the circuit of claim 15 further comprises: a 〃-interface circuit electrically connected to the first integrated circuit and the second integrated body First - with the second source and the first 23·- a semiconductor circuit having an electrostatic discharge protection circuit, comprising: a first integrated circuit electrically coupled to the first high voltage source 盥 a first low voltage source; 'a second integrated circuit, Is coupled to a second high voltage source and a second low voltage source; ^ a first electrostatic discharge protection circuit coupled between the first and the second high voltage source, further comprising: a p type A semiconductor controlled rectifier comprising: a _-type first metal oxide semiconductor transistor, wherein a cathode of the p-type first semiconductor-controlled rectifier is connected to the first high-voltage source, the p-type first semiconductor is controlled The anode of the rectifier is connected to the second high voltage source, and the second semiconductor controlled rectifier of the second type includes a p-type second metal oxide semiconductor transistor, wherein the anode of the second semiconductor magnet controlled rectifier of the second type The first high voltage source is connected, the cathode of the second semiconductor magnetron rectifier is connected to the second high voltage source, wherein the p-type first and the second metal oxide semiconductor transistor of the second type The gate is via a first message The delay unit is connected to the first high voltage source, and 26 1247413 14327 twf.doc/006 a parasitic diode, wherein the cathode of the parasitic diode is connected to the first high voltage source, and the anode of the parasitic diode Connected to the second high voltage source; and a second electrostatic discharge protection circuit coupled between the first and the second low voltage source, further comprising: an N-type first semiconductor controlled rectifier, including a An N-type first metal oxide semiconductor transistor, wherein a cathode of the N-type first semiconductor controlled rectifier is connected to the first low voltage source, and the N-type first semiconductor is shredded to an anode and the second low An N-type second semiconductor step-controlled rectifier includes an N-type first metal-oxide-semiconductor transistor, wherein the N-type second semiconductor is controlled and rectified to be an anode and the first low-voltage source Connected to the cathode of the N-type second semiconductor-controlled rectifying yoke and the second low-voltage source, the interpole of the towel-type and the N-type second MOS transistor is delayed via a second signal The unit is connected to the second low battery Source, and - a parasitic diode, wherein a cathode of the parasitic diode of the second voltage source in contact with the anode of the parasitic diode of the low voltage source and the second contact. The semiconductor circuit of the circuit described in claim 23, which has the electrostatic discharge protection as the first component and the second signal delay unit, as described in claim 23, wherein the circuit is as described in claim 23, wherein the first: Guaranteed, a circuit composed of a resistor and a capacitor. The semiconductor circuit having an electrostatic discharge protection circuit according to claim 23, wherein the signal delay unit is a transfer brake. The semiconductor circuit having the electrostatic discharge protection circuit of claim 23, further comprising: a first electrostatic discharge clamp circuit electrically coupled to the first high voltage source and the first low voltage Between the sources; and a younger-electrostatic discharge clamp circuit electrically connected between the second high voltage source and the second low voltage source. The semiconductor circuit having the electrostatic discharge protection circuit of claim 23, further comprising: an interface circuit electrically coupled between the first integrated circuit and the second integrated circuit, and And coupled between the first and the second high voltage source and the first and second low voltage sources. An electrostatic discharge protection semiconductor circuit is suitable for use in an integrated circuit having a first voltage source and a second voltage source, the electrostatic discharge protection semiconductor circuit comprising: a substrate; a well region located on the substrate The first first type doping region and the second first type doping region are located in the substrate and outside the well region, wherein the second first type doping region is coupled to the second voltage source a younger and a younger brother-type doping area adjacent to the first and the second first type doped regions, respectively, and located in the base and the well region; a second and a fourth second type a doped region adjacent to the first and the 28 1247413 14327 twf.doc/006 second second type doped region, and located in the well region, wherein the third second type doped region is coupled to the second a voltage source; a first gate structure on the substrate and between the first and the third second type doping regions, wherein the first first type doping region is coupled to the first gate structure Receiving the first voltage source; a third first type doping region located in the well region and located in the third and the younger brother Di-type titanium heteroaryl between multicast areas; and a second gate structure on the substrate between the second and the fourth second type doped regions, wherein the third first type doping region, the fourth first good region 4 region And the first voltage source is connected to the gate structure, wherein the second second type doping region and the third first type doping region constitute the first-type doping region, the substrate The well region and the f-th-type doped region constitute a first-semi-conducting financial control rectifier, the first::: type ΐ region, the well region, the substrate and the second first-type doped region form a brother A semiconductor controlled rectifier. The electrostatic discharge canister semiconductor circuit of claim 29, wherein the first-type doped region is doped-type doped: ; = : the impurity region is a germanium-type doped region. The younger brother, the 6th body, the 29th, the second, the second, the second is the P-shaped base, and the well is the N-type well. The discharge protects the relatively high power ii of the semiconductor circuit. Item 4, and the electrostatic discharge 33.-type electrostatic discharge protection semiconductor circuit, suitable for having a first 29 1247413 14327twf.doc/006 voltage source and a second voltage source integrated circuit, the electrostatic discharge semiconductor circuit a substrate comprising: a well region located in the substrate; a first first type doped region and a second first type doped region located in the read substrate and outside the substrate, wherein the first —Type doping _ connected to ^ a second source and a second first type doping _ connected to the second voltage source, a third and a fourth first type doped region, respectively adjacent to the first and second type a doped region, located in the substrate and the well region; 3 a first gate structure on the substrate and between the first and second type of doping regions, wherein the first gate The pole junction_ receives the second; source, flute-: Ι 秘 secret structure, recorded on the bottom of the weaving and between the second and the fourth 'the towel, the second chorus, the second electric source, See the first-and second-type doped regions, the third is adjacent to the four-type doped region, and is located in the doped region coupled to the first, the second of which is the brother- Dimensions to the first - voltage source, · = γ phase two second type doped region lightly connected to the fifth type-type doped region, located in the well zone and located between the first disk-changing region 'its (four) The fifth-type is connected to the fourth:: the first radix: the first type doping region and the fifth first-type doping region, the doping region, the substrate, the well region 30 1247413 14327twf .doc/006 and the first second type doped region constitute the first Conductor silicon controlled rectifier, the second second-type doping region, the well region, the first substrate and the second semiconductor-type doped region forming the second silicon-controlled rectifiers. 34. The ESD protection semiconductor circuit of claim 33, wherein the first type doped region is an N-type doped region and the second type doped region is a P-type doped region. 35. The electrostatic discharge protection semiconductor circuit of claim 33, wherein the substrate is a P-type substrate and the well region is an N-type well. 36. The ESD protection semiconductor circuit of claim 33, wherein the first and the second voltage source are unequal and are a relatively low voltage source of the electrostatic discharge protection semiconductor circuit. 31