1246744 玖、發明說明： 發明所屬之技術領域 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種金氧半導體電晶體的製造方法。 先前技術 金屬氧化半導體（Metal-Oxide-Semiconductor，MOS) 電晶體是現在半導體元件中最重要的一種基本電子元件。 在MOS電晶體的製程中，通常是以介電材質來形成閘極 結構的間隙壁。其中，利用氮化矽作爲間隙壁的製程是將 矽烷或是二氯矽烷導入反應爐內，並以高溫使其與氨氣產 生化學反應，而在欲形成間隙壁的基底上沈積一層氮化矽 覆蓋MOS電晶體的閘極結構，其後再回蝕此氮化矽以於 閘極結構的兩側形成間隙壁。但是此種氮化矽層的形成方 法熱預算較高，並不適用於下一世代（45/65nm的線寬）之 MOS電晶體的氮化矽間隙壁製程。因此，習知發展出一種 以六氯矽烷（HCD)作爲前驅物來進行氮化矽層的沈積製 程。此種方法不但可以降低製程之熱預算，且含氫量較低’ 其更有較佳的階梯覆蓋（step coverage)能力，並且負載效 應（Loading Effect)低。 然而，以六氯矽烷作爲前驅物經由沈積、回鈾所形成 的氮化矽材質間隙壁，在後續利用稀釋之氫氟酸溶液(0·01 % )所進行之金屬矽化物製程的預淸洗(Pre-clean)步驟中’ 其濕蝕刻速率卻是由快速熱化學氣相沈積（Rapid Thermal CVD，RTCVD)法使矽烷與氨氣產生反應而生成的氮化矽 12461twf.doc 5 1246744 層之蝕刻速率的3倍，且其甚至是由二氯矽烷與氨氣反應 而生成的氮化矽層之蝕刻速率的6倍。所以使得上述預淸 洗步驟或是其他的溼式蝕刻製程難以控制，甚至可能對氮 化矽間隙壁造成過度蝕刻，進而對元件的效能造成不良的 影響，並降低生產良率。 發明內容 因此，本發明的目的就是提供一種金氧半導體電晶體 的製造方法，其能夠提高金氧半導體電晶體之間隙壁的抗 濕蝕刻能力，並維持其在乾式蝕刻中與其他膜層的蝕刻選 擇比。 本發明的另一目的就是提供一種金氧半導體電晶體的 製造方法，能夠降低此金氧半導體電晶體之源極/汲極延 伸區的片電阻値，並使源極/汲極延伸區具有陡峭的輪廓。 本發明的再一目的就是提供一種金氧半導體電晶體的 製造方法，能夠減經源極/汲極區延伸區以及源極/汲極區 中的摻質向外擴散的現象，以減少暫態加速效應(Transient Enhanced Diffusion Effect)現象的產生。 本發明提出一種金氧半導體電晶體的製造方法，此方 法係先提供一已形成有閘極結構的基底’接著在閘極結構 兩側的基底中形成源極/汲極延伸區，然後在基底上形成 含碳之材料層，再回蝕此含碳之材料層以於閘極結構的側 壁上形成間隙壁，然後於間隙壁兩側的基底中形成源極/ 汲極區，即完成一金氧半導體電晶體。 依照本發明之一實施例所述，含碳之材料層的形成方 12461twf.doc 6 1246744 法爲一沈積製程。且此沈積製程是以六氯矽烷（HCD)以及 乙烯（c2H4)作爲前驅物，以使材料層含碳。而在本發明之 另一實施例中，含碳之材料層的沈積製程還可以是以雙(特 -丁基氨基）砂院（Bis(tert-butylamino)silane，BTBAS)作爲前 驅物。 依照本發明之再一實施例所述，含碳之材料層的形成 方法可以是先在基底上沈積一層材料層，再將碳離子摻雜 於其中，以形成含碳之材料層。 本發明之金氧半導體電晶體的製造方法可以使金氧半 電晶體之間隙壁中含有碳，以提高此間隙壁在後續金屬矽 化物製程之預淸洗製程或是其他溼式蝕刻製程中的抗蝕刻 能力，且並不影響其在乾式蝕刻製程中與其他膜層之間的 蝕刻選擇比。 此外，本發明金氧半導體電晶體的製造方法還可以使 材料層與後續形成之間隙壁中含有碳，其中碳會於基底表 面形成源極/汲極的阻障層，進而減輕源極/汲極區延伸區 以及源極/汲極區中的摻質向外擴散的現象。 再者，由於金氧半電晶體之間隙壁中含有碳，因此可 以降低源極/汲極延伸區之片電阻，並使其具有較陡峭的 輪廓。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下。 實施方式 12461twf.doc 7 1246744 第一實施例 第1A圖至第1C圖係繪示本發明一較佳實施例的一 種金氧半導體電晶體之製造方法的流程剖面圖。請參照第 1A圖，基底100上已形成有閘極結構102，且基底1〇〇例 如是一矽基底。首先，在閘極結構1〇2兩側的基底1〇〇中 形成源極/汲極延伸區106，接著在基底100上形成共形之 襯層104。其中，襯層104的材質例如是氧化矽，其形成 的方法例如是熱氧化法或是化學氣相沈積法，而用以形成 源極/汲極延伸區106的摻質，依元件形態的不同而可以 是N型或P型離子，當植入離子爲N型時，其例如是砷 離子，另外，植入的離子爲P型時，其例如是氟化硼離子’ 其形成的方法例如是以閘極結構1〇2爲罩幕，使用離子植 入法將摻質植入閘極結構102兩側的基底中。 請參照第1B圖，於襯層104上形成含碳之材料層108。 其中，含碳之材料層108的材質例如是氮化矽。而沈積此 含碳之材料層108的方法例如是進行化學氣相沈積製程， 並且此化學氣相沈積製程例如是將基底1〇〇置於一反應爐 管（未繪示）中，然後分別將氨氣、氮氣、乙烯以及六氯矽 烷(HCD)導入反應爐管內，使其相互反應而於基底100上 形成含碳之氮化矽層(即材料層1〇8)。其中，乙烯與HCD 係作爲沈積氮化矽層的前驅物。 在此化學氣相沈積製程中，反應爐管內的壓力値例如 是介於0.2 ton*至2.5 torr之間，而其反應溫度例如是介於 攝氏450度至攝氏600度之間。此外，HCD之體積相對於 12461twf.doc 8 1246744 氨氣之體積的比値例如是介於2.5%至8%之間。乙烯的流 速例如是介於lOOsccm至1200sccm之間’氮氣的流速例 如是介於300sccm至1800sccm之間，氨氣的較佳流速例 如是180sccm。而HCD的流速例如是介於12sccm至20sccm 之間，較佳的流速爲15sccm。 請參照第1C圖，將含碳之材料層108沈積於基底100 上之後，移除部分之含碳之材料層108以於閘極結構102 的側壁上形成間隙壁108a，其中移除部分之含碳之材料層 108的方法例如是進行一非等向性蝕刻製程以回蝕含碳的 材料層108。接著，於間隙壁108a兩側之基底100中形成 源極/汲極（S/D)區106a，其中形成源極/汲極區l〇6a的方 法例如是以閘極結構102以及間隙壁l〇8a爲罩幕來進行 離子植入製程，以於基底1〇〇中摻入濃度較濃的摻質以形 成源極/汲極區l〇6a，其中植入的摻質依元件形態的不同 而可以是N型或P型離子，其中植入離子爲N型時，其 例如是磷或砷離子，而植入離子爲P型時，其例如是硼或 氟化硼離子。依上述第1A圖至第1C圖的製程，即可以 完成一金氧半導體電晶體。 第二實施例 値得注意的是，第一^實施例的第1 B圖所繪75之含碳 之材料層108，還可以藉由其他的方法以形成，於本實施 例中是形成含碳之氮化矽及氧化矽所組成的氮化矽/氧化 矽複合層（未繪示）。而形成前述含碳之氮化矽/氧化矽複合 12461twf.doc 9 1246744 層的方法，係在化學氣相沈積製程中將氧氣、氮氣、氨氣 以及雙（特-丁基氨基）砍院（Bis(tert-butylamino)silane， BTBAS)導入反應爐管內，並使其相互反應而形成氮化矽/ 氧化矽複合層，且此氮化矽/氧化矽複合層含有碳。其中， BTBAS係用以作爲沈積氮化矽/氧化矽複合層的前驅物。 在本實施例的化學氣相沈積製程中，反應爐管內的壓 力値例如是介於0.5 ton*至2.5 ton·之間，而其溫度例如是 介於攝氏550度至攝氏600度之間。此外，BTBAS之體 積相對於氨氣之體積的比値例如是介於15%至25%之間， BTBAS之體積相對於氧氣之體積的比値例如是介於10% 至30%之間。而氮氣的流速例如是介於11〇8(：(：111至200sccm 之間’ BTBAS的流速例如是介於75sccm至llOsccm之間。 在上述二實施例中，形成材料層之化學氣相沈積製程 所使用的則驅物皆具有較局的含碳量，因此可在基底上形 成含碳的材料層。然而，除了上述兩種沈積製程之外，本 發明更提出另一種金氧半導體電晶體的製造方法，同樣可 以形成含碳之材料層，以使後續形成之間隙壁含碳。以下 將舉第三實施例來說明此方法。 第三實施例 請參照第2A圖，以第一實施例所述之方法形成襯層 104之後，接著在基底10〇上形成材料層1〇7。其中，材 料層107的形成方法例如是先將基底1〇〇放置在反應爐管 內，接著將HCD、氮氣以及氨氣導入反應爐管內，使其相 12461twf.doc 10 1246744 上以形成材料層 互反應而生成氮化矽，並沈積在基底100 107。 請參照第2B圖，於本實施例中，係藉由在材料層1 摻雜碳的方式以使材料層1〇7含碳，其例如是對材料層=7 進行一離子植入製程101，以將碳離子植入材料層1〇7中7 進而形成第1B圖所示之含碳之材料層108。 而形成含碳之材料層108之後的後續製程即如同第_ 實施例之第1C圖的說明，此處將不再贅述。 本發明之第一實施例係在習知以HCD作爲前驅物的 製程中，加入乙烯而與HCD —同作爲沈積材料層的前驅 物，因此仍可保有習知利用HCD作爲前驅物來降低熱預 算的優點。而且，同時以HCD及乙嫌做爲沈積氮化砂間 隙壁的前驅物，還可以提高此間隙壁在後續之金屬@化 製程的預情洗步驟或是溼式蝕刻製程中的抗蝕刻能为，且 並不影響其在乾式蝕刻製程中與其他膜層之間的蝕刻選擇 比。 ' 第3圖係繪示在本發明之第一實施例中所形成之氮化 矽間隙壁的特性曲線圖。請參照第3圖，圖中之橫座標爲 第一實施例所使用之乙烯流速，左縱座標爲氮化矽間隙壁 的含碳濃度，而右縱座標則爲氮化砂間隙壁在以氫氟酸爲 蝕刻液之溼式蝕刻製程中的蝕刻速率。而圖中以·表示的 曲線即是乙烯流速與含碳濃度間的關係曲線，由此曲線可 看出，在本發明之第一實施例中所選用的乙烯流速係與所 形成之氮化矽間隙壁的含碳濃度成正比。 12461twf.doc 11 1246744 此外，圖中以♦表示的曲線是乙烯流速與氮化矽間隙 壁之蝕刻速率間的關係曲線，由此曲線可看出，在本發明 之第一實施例中所選用的乙烯流速係所形成之氮化矽間隙 壁的蝕刻速率成反比。由此二曲線即可得知，氮化矽間隙 壁中的含碳量愈高，則其在溼式蝕刻中的蝕刻速率愈小。 因此，本發明能夠有效地降低氮化矽間隙壁在溼式蝕刻中 的蝕刻速率。 第4圖係繪示在本發明之第一實施例中所形成之氮化 矽間隙壁以及習知製程所形成之氮化矽間隙壁與四乙烷基 氧矽甲烷（Tetra-Ethyl-ortho-Silicate，TEOS)層在乾式蝕刻 製程中的蝕刻選擇比間之差異比較的直條圖。請參照第4 圖，由圖中可看出，在本發明之第一實施例中，無論選用 的乙烯流速是300sccm或是900sccm，其所形成之氮化矽 間隙壁在乾式蝕刻製程中與TEOS的蝕刻選擇比，係相當 近似於習知利用二氯矽烷所形成之氮化矽間隙壁的蝕刻選 擇比。由此可證實，本發明在沈積氮化矽間隙壁的製程中 以乙烯及HCD作爲前驅物，不但可以降低氮化矽間隙壁 在溼式蝕刻中的蝕刻速率，也能維持氮化矽間隙壁在乾式 蝕刻中與其他膜層的蝕刻選擇比。 此外，在間隙壁的沈積製程加入乙烯而使此製程所生 成的間隙壁含碳，此些存在間隙壁中的碳原子可由間隙壁 中擴散至襯層與基底的界面（即氧化矽/矽之界面）而作爲源 極/汲極區的阻障層，以減少源極/汲極區中之摻質例如是 硼離子向基底深處擴散，並能夠降低源極/汲極延伸區的 12461twf.doc 12 1246744 片電阻’且使源極/汲極延伸區具有較陡峭的輪廓。特別 的7H ’ 材料層之含碳量亦可以降低其介電常數，從而 使得此材料層亦能夠應用於後段製程（Backend Process)所 使用的介電材料。 而本發明在第二實施例中以BTBAS爲沈積材料層的 前驅物’在第三實施例以離子植入法將碳離子植入材料 層’皆是爲了讓本發明的金氧半導體電晶體所形成之間隙 壁中含碳，以達成上述之優點。 以下所繪示之表1係依照本發明之第一實施例所得之 實驗數據’用以說明利用本發明所揭露之製程而形成的金 氧半電晶體與利用習知製程所形成的金氧半導體電晶體之 源極/汲極延伸區在基底中的深度及其片電阻値。 表1 摻質參數 間隙壁參數 回火溫度 (°C) 接合界面 深度(nm) 片電阻値 (ohm/sq) 條件（1) BF2，IKeV SiH4+NH3 1075 24 5050 ^ 條件（2) BF2，IKeV HCD 1075 24 4168 條件（3) BF2，IKeV HCD+乙烯 (300sccm) 1075 25 1836 條件（4) BF2，IKeV HCD+乙烯 (900sccm) 1075 25 1772 請參照表1，條件（1)至條件(4)皆係在形成金氧半導體 12461twf.doc 13 1246744 電晶體之源極/汲極延伸區的製程中以濃度爲1·5χ 1015atom/cm3的BF2作爲摻質，並以IKeV的能量將其植 入金氧半導體電晶體的基底中。其中’條件（1)中的間隙壁 係由矽烷與氨氣在習知之製程中相互反應而生成，條件(2) 係以HCD做爲沈積間隙壁的前驅物，而條件(3)條件(4)則 是以HCD及乙烯做爲沈積間隙壁的前驅物。其中，條件（3) 所選用的乙烯流速爲300sccm，條件(4)所選用的乙烯流速 爲90〇Sccm。表1中的實驗數據顯示，金氧半導體電晶體 之源極/汲極延伸區的片電阻値會隨著乙烯流速的提高而 下降。由此可知，本發明在金氧半導體電晶體之間隙壁的 沈積製程中加入乙烯作爲前驅物可有效地降低源極/汲極 延伸區的片電阻値，進而提高元件的效能。 於上述較佳實施例中，本發明係以典型的金氧半導體 電晶體製程進行說明，然而本發明並不限定於此，本發明 亦可以應用於其他型態之金氧半導體電晶體的製程。舉例 來說，本發明係'可以應用於使用預非晶矽化植入法（Pre-amorphization implantation)的金氧半導體電晶體製程，其 步驟如下：對形成有閘極結構的基底進行一預非晶矽化植 入製程，以於基底中形成非晶矽化區域，接著於閘極兩側 之非晶矽化區域中形成源極/汲極延伸區，再於閘極側壁 形成本發明之含碳的間隙壁，然後於間隙壁兩側之非晶矽 化區域中形成源極/汲極區，接著進行一固相磊晶（Solid phase epitaxial)製程，使非晶矽化的區域再結晶，並使源極/ 汲極延伸區與源極/汲極區的摻質活化以形成源極/汲極。 12461twf.doc 14 1246744 綜上所述，本發明之金氧半導體電晶體的製造方法具 有下列優點： L提高金氧半導體電晶體之間隙壁在金屬矽化物製程 之預淸洗步驟或是其他溼式蝕刻中的抗蝕刻能力，並維持 其在乾式蝕刻中與其他膜層的蝕刻選擇比。 2·在金氧半導體電晶體之源極/汲極延伸區中，係能夠 使源極/汲極延伸區的片電阻値降低並得到較陡峭的輪 廓，以提高元件的效能。 3·在金氧半導體電晶體中，材料層以及後續形成之間 隙壁中的碳原子，會在基底表面形成阻障層，因此能夠減 少源極/汲極區延伸區以及源極/汲極區中之摻質向外擴散 的現象。 4·本發明之形成含碳之間隙壁的製程，與習知使用 HCD爲驅質形成間隙壁的製程同樣具有低熱預算，因此本 發明能夠維持在低熱預算的條件下形成間隙壁的優點。 5·由於增加材料層中碳含量能夠降低其介電常數，因 此本發明之材料層亦能夠應用於後段製程(Backend Pr〇cess) 所使用的介電材料。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和I範圍內’當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1A圖至第1C圖係繪示本發明一較佳實施例的一 12461twf.doc 15 1246744 種金氧半導體電晶體之製造方法的流程剖面圖。 第2A圖至第2B圖係繪示本發明另一較佳實施例的 一種金氧半導體電晶體之製造方法的部分流程剖面圖。 第3圖係繪示在本發明之第一實施例中所形成之氮化 矽間隙壁的特性曲線圖。 第4圖係繪示在本發明之第一實施例中所形成之氮化 矽間隙壁以及習知製程所形成之氮化矽間隙壁與TEOS層 在乾式蝕刻製程中的蝕刻選擇比間之差異比較的直條圖。 【圖式標示說明】 100 :基底 101 :離子植入製程 102 :閘極結構 104 :襯層 106 :源極/汲極延伸區 106a :源極/汲極區 107 :材料層 108 ··含碳之材料層 108a :間隙壁 12461twf.doc 16BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a MOS transistor. Prior Art Metal-Oxide-Semiconductor (MOS) transistors are the most important basic electronic components in semiconductor devices today. In the process of MOS transistors, the spacers of the gate structure are usually formed by a dielectric material. Among them, the process of using tantalum nitride as a spacer is to introduce decane or dichloromethane into the reaction furnace, and to chemically react with ammonia gas at a high temperature, and deposit a layer of tantalum nitride on the substrate on which the spacer is to be formed. The gate structure of the MOS transistor is covered, and then the tantalum nitride is etched back to form spacers on both sides of the gate structure. However, the formation method of such a tantalum nitride layer has a high thermal budget and is not suitable for the tantalum nitride spacer process of the next generation (45/65 nm line width) MOS transistor. Therefore, it has been conventionally practiced to develop a deposition process for a tantalum nitride layer using hexachlorodecane (HCD) as a precursor. This method not only reduces the thermal budget of the process, but also has a lower hydrogen content, which has better step coverage and a lower loading effect. However, the pre-washing of the metal telluride process by the dilute hydrofluoric acid solution (0.101%) is carried out by using hexachlorodecane as a precursor through the deposition of the yttrium nitride barrier formed by the uranium. In the (Pre-clean) step, the wet etching rate is the etching of the tantalum nitride 12461twf.doc 5 1246744 layer formed by the reaction of decane with ammonia by rapid thermal chemical vapor deposition (RTCVD). It is 3 times the rate, and it is even 6 times the etching rate of the tantalum nitride layer formed by the reaction of dichlorosilane with ammonia. Therefore, the above pre-washing step or other wet etching process is difficult to control, and may even cause excessive etching of the niobium nitride spacer, thereby adversely affecting the performance of the device and reducing the production yield. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a MOS transistor capable of improving the wet etching resistance of a spacer of a MOS transistor and maintaining etching thereof with other layers in dry etching. Choose ratio. Another object of the present invention is to provide a method for fabricating a MOS transistor capable of reducing sheet resistance 源 of a source/drain extension of the MOS transistor and making the source/drain extension region steep Outline. A further object of the present invention is to provide a method for fabricating a MOS transistor capable of reducing the out-diffusion of dopants in a source/drain region extension region and a source/drain region to reduce transients. The generation of the phenomenon of the Transient Enhanced Diffusion Effect. The invention provides a method for fabricating a MOS transistor, which first provides a substrate having a gate structure formed, and then forms a source/drain extension in a substrate on both sides of the gate structure, and then on the substrate Forming a carbon-containing material layer, and etching back the carbon-containing material layer to form a spacer on the sidewall of the gate structure, and then forming a source/drain region in the substrate on both sides of the spacer, that is, completing a gold Oxygen semiconductor transistor. According to an embodiment of the present invention, the formation of the carbon-containing material layer is a deposition process 12461 twf.doc 6 1246744. The deposition process is based on hexachlorodecane (HCD) and ethylene (c2H4) as precursors to make the material layer carbonaceous. In another embodiment of the present invention, the deposition process of the carbon-containing material layer may also be a precursor of Bis (tert-butylamino) silane (BTBAS). In accordance with still another embodiment of the present invention, the carbon-containing material layer may be formed by depositing a layer of material on the substrate and then doping carbon ions therein to form a layer of carbon-containing material. The method for fabricating the MOS transistor of the present invention can include carbon in the spacer of the MOS transistor to improve the gap in the pre-wash process or other wet etch process of the subsequent metal telluride process. It is resistant to etching and does not affect its etching selectivity ratio with other film layers in the dry etching process. In addition, the method for fabricating the MOS transistor of the present invention can further include carbon in the material layer and the subsequently formed spacer, wherein the carbon forms a source/drain barrier layer on the surface of the substrate, thereby reducing the source/汲The phenomenon of out-diffusion of dopants in the polar region extension and source/drain regions. Furthermore, since the spacer of the MOS transistor contains carbon, the sheet resistance of the source/drain extension region can be lowered and a steep profile can be obtained. The above and other objects, features, and advantages of the present invention will become more apparent from the understanding of the appended claims. Embodiments 12461 twf.doc 7 1246744 First Embodiment FIGS. 1A to 1C are cross-sectional views showing the flow of a method of manufacturing a MOS transistor according to a preferred embodiment of the present invention. Referring to Figure 1A, a gate structure 102 has been formed on the substrate 100, and the substrate 1 is, for example, a substrate. First, a source/drain extension 106 is formed in the substrate 1 两侧 on both sides of the gate structure 1 , 2, and then a conformal lining 104 is formed on the substrate 100. The material of the lining layer 104 is, for example, cerium oxide, and the method of forming the lining is, for example, thermal oxidation or chemical vapor deposition, and the dopant used to form the source/drain extension 106 varies depending on the form of the element. It may be an N-type or a P-type ion, and when the implanted ion is an N-type, it is, for example, an arsenic ion. Further, when the implanted ion is a P-type, it is, for example, a boron fluoride ion. The dopant is implanted into the substrate on both sides of the gate structure 102 by ion implantation using the gate structure 1〇2 as a mask. Referring to FIG. 1B, a carbon-containing material layer 108 is formed on the liner 104. The material of the carbon-containing material layer 108 is, for example, tantalum nitride. The method for depositing the carbon-containing material layer 108 is, for example, performing a chemical vapor deposition process, and the chemical vapor deposition process is, for example, placing the substrate 1 in a reactor tube (not shown), and then separately Ammonia gas, nitrogen gas, ethylene, and hexachlorosilane (HCD) are introduced into the reaction tube to react with each other to form a carbon-containing tantalum nitride layer (i.e., material layer 1〇8) on the substrate 100. Among them, ethylene and HCD are used as precursors for depositing a tantalum nitride layer. In this chemical vapor deposition process, the pressure 値 in the reactor tube is, for example, between 0.2 ton* and 2.5 torr, and the reaction temperature is, for example, between 450 ° C and 600 ° C. Further, the ratio of the volume of the HCD to the volume of the ammonia gas of 12461 twf.doc 8 1246744 is, for example, between 2.5% and 8%. The flow rate of ethylene is, for example, between 100 sccm and 1200 sccm. The flow rate of nitrogen gas is, for example, between 300 sccm and 1800 sccm, and the preferred flow rate of ammonia gas is, for example, 180 sccm. The flow rate of the HCD is, for example, between 12 sccm and 20 sccm, and a preferred flow rate is 15 sccm. Referring to FIG. 1C, after the carbonaceous material layer 108 is deposited on the substrate 100, a portion of the carbonaceous material layer 108 is removed to form a spacer 108a on the sidewall of the gate structure 102, wherein the removed portion is included. The carbon material layer 108 is, for example, an anisotropic etch process to etch back the carbon-containing material layer 108. Next, a source/drain (S/D) region 106a is formed in the substrate 100 on both sides of the spacer 108a, wherein the method of forming the source/drain region 16a is, for example, the gate structure 102 and the spacer l 〇8a is a mask for the ion implantation process to dope the dense dopant in the substrate 1 to form the source/drain region l〇6a, wherein the implanted dopants are different in shape of the device. Instead, it may be an N-type or P-type ion, wherein when the implanted ion is an N-type, it is, for example, a phosphorus or arsenic ion, and when the implanted ion is a P-type, it is, for example, boron or a boron fluoride ion. According to the processes of Figs. 1A to 1C described above, a MOS transistor can be completed. The second embodiment is noted that the carbon-containing material layer 108 of the first embodiment shown in FIG. 1B can also be formed by other methods, in this embodiment, carbon-forming. A tantalum nitride/yttria composite layer (not shown) composed of tantalum nitride and hafnium oxide. The method for forming the above-mentioned carbon-containing tantalum nitride/yttria composite 12461twf.doc 9 1246744 layer is to chop oxygen, nitrogen, ammonia and bis(tert-butylamino) in a chemical vapor deposition process (Bis (tert-butylamino)silane, BTBAS) is introduced into the reaction tube and reacted with each other to form a tantalum nitride/yttria composite layer, and the tantalum nitride/yttria composite layer contains carbon. Among them, BTBAS is used as a precursor for depositing a tantalum nitride/yttria composite layer. In the chemical vapor deposition process of the present embodiment, the pressure 値 in the reactor tube is, for example, between 0.5 ton* and 2.5 ton·, and the temperature thereof is, for example, between 550 ° C and 600 ° C. Further, the ratio of the volume of the BTBAS to the volume of the ammonia gas is, for example, between 15% and 25%, and the ratio of the volume of the BTBAS to the volume of the oxygen is, for example, between 10% and 30%. The flow rate of nitrogen gas is, for example, between 11〇8 (: (: 111 to 200 sccm). The flow rate of BTBAS is, for example, between 75 sccm and 11 Osccm. In the above two embodiments, the chemical vapor deposition process for forming a material layer The precursors used have a relatively high carbon content, so that a carbon-containing material layer can be formed on the substrate. However, in addition to the above two deposition processes, the present invention further proposes another metal oxide semiconductor transistor. In the manufacturing method, a carbon-containing material layer can also be formed so that the subsequently formed spacers contain carbon. The third embodiment will be described below. The third embodiment is described with reference to FIG. 2A, in the first embodiment. After the method of forming the liner 104, a material layer 1〇7 is formed on the substrate 10〇. The material layer 107 is formed by, for example, placing the substrate 1 in the reaction tube, followed by HCD and nitrogen. And the ammonia gas is introduced into the reaction tube, and the phase of the material layer is mutually reacted to form a tantalum nitride on the substrate 12461twf.doc 10 1246744, and deposited on the substrate 100 107. Referring to FIG. 2B, in this embodiment, By The material layer 1 is doped with carbon such that the material layer 1〇7 contains carbon, for example, an ion implantation process 101 is performed on the material layer=7 to implant the carbon ions into the material layer 1〇7 to form the first The carbon-containing material layer 108 shown in Fig. 1B. The subsequent process after forming the carbon-containing material layer 108 is as described in the first embodiment of the first embodiment, and will not be described again here. In the conventional process of using HCD as a precursor, ethylene is added to be the precursor of the deposition material layer with HCD, so that the advantage of using HCD as a precursor to reduce the thermal budget can still be preserved. Using HCD and B as precursors for depositing nitride sand spacers, it is also possible to improve the etching resistance of the spacers in the subsequent metal-chemical process, or in the wet etching process, and The etching selectivity ratio between the other layers in the dry etching process is not affected. 'Fig. 3 is a characteristic diagram of the tantalum nitride spacer formed in the first embodiment of the present invention. Figure 3, the abscissa in the figure is the first embodiment The ethylene flow rate used, the left ordinate is the carbon concentration of the tantalum nitride spacer, and the right ordinate is the etch rate of the nitride sand spacer in the wet etching process using hydrofluoric acid as the etching solution. The curve indicated by the middle is the relationship between the ethylene flow rate and the carbon concentration. From this curve, it can be seen that the ethylene flow rate selected in the first embodiment of the present invention and the formed tantalum nitride spacer are The carbon concentration is proportional to. 12461twf.doc 11 1246744 In addition, the curve indicated by ♦ in the figure is a relationship between the ethylene flow rate and the etching rate of the tantalum nitride spacer, and thus the curve can be seen in the present invention. The ethylene flow rate selected in one embodiment is inversely proportional to the etch rate of the tantalum nitride spacer formed. From this two curves, it can be known that the higher the carbon content in the tantalum nitride spacer wall, the smaller the etching rate in wet etching. Therefore, the present invention can effectively reduce the etching rate of the tantalum nitride spacer in wet etching. Fig. 4 is a view showing a tantalum nitride spacer formed in the first embodiment of the present invention and a tantalum nitride spacer formed by a known process and Tetra-Ethyl-ortho- Silicate, TEOS) A bar graph comparing the difference in etch selectivity between layers in a dry etch process. Referring to FIG. 4, it can be seen from the figure that in the first embodiment of the present invention, regardless of the selected ethylene flow rate of 300 sccm or 900 sccm, the formed tantalum nitride spacer is in the dry etching process and TEOS. The etching selectivity ratio is quite similar to the etching selectivity ratio of the conventional tantalum nitride spacer formed by using dichlorosilane. It can be confirmed that the invention uses ethylene and HCD as precursors in the process of depositing the tantalum nitride spacer, not only can reduce the etching rate of the tantalum nitride spacer in the wet etching, but also maintain the tantalum nitride spacer. The etching selectivity ratio of other film layers in dry etching. In addition, ethylene is added in the deposition process of the spacer to make the spacer formed by the process contain carbon, and the carbon atoms in the spacer may be diffused from the spacer to the interface between the liner and the substrate (ie, yttrium oxide/矽Interface) as a barrier layer of the source/drain region to reduce the dopant in the source/drain region, for example, boron ions diffuse deep into the substrate, and can reduce the source/drain extension of 12461 twf. Doc 12 1246744 Chip resistance 'and makes the source/drain extension have a steeper profile. The carbon content of the special 7H' material layer also reduces its dielectric constant, allowing the material layer to be applied to the dielectric materials used in the Backend Process. In the second embodiment, the precursor of the BTBAS as a deposition material layer is implanted into the material layer by ion implantation in the third embodiment, in order to make the MOS transistor of the present invention. The formed spacers contain carbon to achieve the above advantages. Table 1 below is the experimental data obtained in accordance with the first embodiment of the present invention' to illustrate the MOS semi-transistor formed by the process disclosed in the present invention and the MOS formed by the conventional process. The depth of the source/drain extension of the transistor in the substrate and its sheet resistance. Table 1 Adhesion parameters Gap parameters Tempering temperature (°C) Joint depth (nm) Sheet resistance 値 (ohm/sq) Condition (1) BF2, IKeV SiH4+NH3 1075 24 5050 ^ Condition (2) BF2, IKeV HCD 1075 24 4168 Condition (3) BF2, IKeV HCD + ethylene (300sccm) 1075 25 1836 Condition (4) BF2, IKeV HCD + ethylene (900sccm) 1075 25 1772 Please refer to Table 1, conditions (1) to (4) are In the process of forming the source/drain extension of the MOS semiconductor 12461twf.doc 13 1246744 transistor, BF2 with a concentration of 1.5 χ 1015 atom/cm 3 is used as a dopant, and it is implanted into the MOS semiconductor with the energy of IKeV. In the base of the transistor. Wherein the spacer in the condition (1) is formed by the reaction of decane and ammonia in a conventional process, and the condition (2) is based on HCD as a precursor of the deposition spacer, and the condition (3) condition (4) ) HCD and ethylene are used as precursors for the deposition of spacers. Among them, the ethylene flow rate selected for the condition (3) is 300 sccm, and the ethylene flow rate selected for the condition (4) is 90 〇 Sccm. The experimental data in Table 1 shows that the sheet resistance 源 of the source/drain extension of the MOS transistor decreases as the ethylene flow rate increases. It can be seen that the addition of ethylene as a precursor in the deposition process of the spacer of the MOS transistor can effectively reduce the sheet resistance of the source/drain extension region, thereby improving the performance of the device. In the above preferred embodiment, the present invention is described in a typical MOS transistor process. However, the present invention is not limited thereto, and the present invention is also applicable to processes of other types of MOS transistors. For example, the present invention can be applied to a MOS transistor process using pre-amorphization implantation by the following steps: pre-amorphously forming a substrate having a gate structure The implantation process is performed to form an amorphous germanium region in the substrate, then a source/drain extension region is formed in the amorphous germanium region on both sides of the gate electrode, and the carbon-containing spacer of the present invention is formed on the gate sidewall And then forming a source/drain region in the amorphous deuterated region on both sides of the spacer, followed by a solid phase epitaxial process to recrystallize the amorphous deuterated region and source/deuterium The dopants of the polar extension region and the source/drain regions are activated to form source/drain electrodes. 12461twf.doc 14 1246744 In summary, the method for fabricating the MOS transistor of the present invention has the following advantages: L improves the gap of the MOS transistor in the pre-washing step of the metal telluride process or other wet type The etching resistance in etching is maintained and the etching selectivity ratio to other film layers in dry etching is maintained. 2. In the source/drain extension of the MOS transistor, the sheet resistance of the source/drain extension can be reduced and a steeper profile can be obtained to improve the performance of the device. 3. In a MOS transistor, the material layer and the carbon atoms in the subsequently formed spacers form a barrier layer on the surface of the substrate, thereby reducing the source/drain region extension and the source/drain regions. The phenomenon of the outward diffusion of the dopant in the medium. 4. The process for forming a carbon-containing spacer of the present invention has a low thermal budget as well as the conventional process of forming a spacer by using HCD as a flooding material. Therefore, the present invention can maintain the advantage of forming a spacer under a low thermal budget. 5. Since the carbon content in the material layer can reduce the dielectric constant, the material layer of the present invention can also be applied to the dielectric material used in the back end process. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention to those skilled in the art, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1C are cross-sectional views showing a process of manufacturing a oxymetal oxide transistor of 12461 twf.doc 15 1246744 according to a preferred embodiment of the present invention. 2A to 2B are partial cross-sectional views showing a method of manufacturing a MOS transistor according to another preferred embodiment of the present invention. Fig. 3 is a graph showing the characteristics of a tantalum nitride spacer formed in the first embodiment of the present invention. Figure 4 is a diagram showing the difference between the etching selectivity ratio of the tantalum nitride spacer formed in the first embodiment of the present invention and the tantalum nitride spacer formed by the conventional process and the TEOS layer in the dry etching process. Comparison of straight bars. [Illustration Description] 100: Substrate 101: Ion implantation process 102: Gate structure 104: Liner 106: Source/drain extension 106a: Source/drain region 107: Material layer 108 ··Carbon Material layer 108a: spacer 12461twf.doc 16