1245487 14772twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是關於-種可變增益放大器，且特別是關於 流匹配式可變增益放大器。 裡兒 【先前技術】 •隨著無線通訊領域的快速成長，其中的可變增益擴大器 (variable gam amplifier)也有彳艮多人研究。到目前為止，雖然 經有不少解決方案，還是有改進的空間。 •、，圖」為美國專利申請案2003/0181181號所提出的可變增 益放大器的電路圖。其中Input為輸入端，〇utput為輸出端，曰 而電感器202為此放大器電路的負載。這個放大器是利用控制 . 訊號201分別開啟或關閉N通道金氧半場效電晶體（n_channd • metal oxide semiconductor field effect transistor NMOSFET，以下簡稱為NMOS電晶體）211與212，藉以改 k通過電感裔202的電流，在兩種增益之間切換。在高增益模 式下，控制訊號201會關閉NMOS電晶體211，打開NMOS 電晶體212，使所有電流都通過電感器202，達成高增益。在 低增益模式下，控制訊號201則打開NMOS電晶體211，並且 關閉NMOS電晶體212，只讓部分電流通過電感器202，達成 i 低增益。這個放大器的電路比上一個放大器簡單，問題是為了 達到準確的增益值，NMOS電晶體211和213的大小必須有適 當的匹配，而因為受限於半導體製程，這個問題並不容易解 決。為了使電流大部分流入NMOS電晶體211達成低增益模 式，此電晶體大小必須使用較大的，造成在高增益操作時功率 損耗較大，使得雜訊特性較為差。 圖2為美國專利6211737號所提出的可變增益放大器的電 6 1245487 14772twf.doc/g 路圖。這個放大态的輸入端為I叩ut，輸出端為Output，和上 一個放大器一樣採用分流技術。也就是利用控制訊號301至 303分別打開或關閉雙極接面電晶體（bip〇lar juncti〇n transistor，以下簡稱BJT電晶體）311至313，使分支電路321 至323各自分擔或不分擔電流，藉以改變流經BjT電晶體31〇 的電流大小，在多種不同的增益之間切換。這個放大器和上一 個放大器有相同的缺點，也就是電晶體的大小不易匹配，以及 在高增益操作時的功率損耗較大。 由以上說明可知，我們仍然需要更好更容易設計的放大器 電路，以進一步改善先前技術的許多問題。 【發明内容】 本發明的目的是在提供一種電流匹配式可變增益放大 器，其優點為電路比較簡單，不需要複雜的阻抗匹配，而且在 高增益操作時的功率損耗比較低，足以解決先前技術的問題。 為達成上述及其他目的，本發明提出一種電流匹配式 增益放大器，包括-參考電流源、至少—個串接放大器(咖_ _)、-匹配電路、一控制電路、以及至少一個第一 2，+參考電_提供參考電流。串接放大器各自根據: 考電&接收-輸入訊號，然後輸出—輸出訊號，其中輸出訊於 為輸入訊號放大後之結果。B電路祕於上狀串接放^ 減大ϋ之第-接點之電壓特匹 壓’並且使各串接放大器之 ::； 流等於匹配電路之第-金氧半場效電晶^ ，於匹配電路’控制匹配電路之第—金氧半場效“體^ = 大小。第一阻擋電路與上述之串接放大哭—一 電冰 於參考電流源麟應之串接放大㈣I 輕接 1245487 M772twf.d〇c/g 上逑之電流匹配式可變增益放大器，徐 之電流匹配式可變增益放 =财，上述 放大器構成-單邊串接放大器:僅"括個串接放大器，此串接 之電流^器，在—實施例中，上述 些串接放大器構成；二：個大大 出端為兩個串接放大哭於 U接放大益之輸 之輪入端為兩個串接放大“輸入此差異串接放大器 接放益放大器’在—實施例中，各串 金氧半場效電晶體之大小=^^之大小細配電路之第一 電路可變增益放大器，在一實施例中，匹配 器、至少-個第二金氧4效;二=;曰曰體、-做 電路。其中開關元件_於_ “ 弟二阻擔 金氧半場效接點。第二 ::弟二阻擋電路與串接放大器一一 = ::輸入端與對應之串接放大器之第-接點之間「： 配式可變增益放大器’在一實施例中，控制 p更匕括至^個第二金氧半場效電晶體，這些第三金^ 每效電晶體各自祕於匹配電路、參考電流源、盘平 ^ mir；or) 1245487 14772twf.doc/g ==心_體，則控制電路更包括多 雁，m 關7"件與第三金氧半場效電晶體--對 ^。σ自祕於匹配電路與對應之第三金氧半場效電晶體之 電路之可變增益放大器，在-實施例中，控制 於匹配電路钤出又咸"^源以及一輪出感應器。可變電流源耦接 出之輸出電壓，調整可變電流源所輸 接放變增第益放^ 氧丰揚对雷= 弟四金氧半場效電晶體、主要金 四全氧^二負載電路。電感器_於-地線。第 第一接點、Γ 7汛唬。主要金氧半場效電晶體耦接於 昂接點、一電壓源、與串接放 耦接於電壓源與串接放大器°端二端^；負載電路 流。 勒】之間，自電壓源接收電 電路式:變增益放大器，在-實施例中，負載 电峪马至）一個負載兀件所組成， 器、電感n、與電阻其巾之―。貞载轉之種類為笔容 上述之電流匹配式可變增益放大哭，—奋 個次要金氧半場效電晶體。這些:二 :主要金氧半場效電晶體並聯，各自根據 口饋控峰edbaek叫順制，使第—金氧半場效電晶體的 9 1245487 14772twf.doc/g 電流與主要金氧半場效電晶體的電流相同，因此可達到電路比 較簡單，不需要複雜的阻抗匹配的優點。另外，因為第二金气 半場效電晶體的尺寸較小，因此可達到在高增益操作時 耗比較低的優點。如此即足以解決先前技術的問題。 、 為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂，下文特舉本發明之較佳實施例，並配合所附圖式， 說明如下。 【實施方式】 圖3為根據於本發明一實施例的電流匹配式可變增益放 大斋的電路圖。圖3的放大器包括參考電流源41〇、串接放大 器440、匹配電路430、控制電路42〇、以及阻擋電路幻。 參考電流源410的作用是以電流源灶#提供參考電流， 於是電流鏡的左半邊。 、 串接放大器44〇會根據來自參考電流源41〇的參考電流， 從輸入端Input接收輸入訊號，加以放大後，做為輸出訊號在 輸出端Output輸出。圖3的實施例當中只有一個串接放大器 440構成一個單邊串接放大器（singie-sided casc〇de 然而本發明並不僅限於一個串接放大器。在其他實施例中，可 以包括兩個或更多串接放大器。 串接放大杰440包括電感器li、NM0S電晶體FET1、電 晶體模組450、以及負載電路u，詳細說明如下。 兒 電感器L1耗接於地線GND與nm〇S電晶體FET1之間， 作用是匹配輸入阻抗。NM〇s電晶體FET1耦接於電感器Li、 輸广端Input、與接點VA之間，負責自輸入端〗叩泔接收輸入 汛唬’並且自參考電流源41〇的NM〇s電晶體FET7鏡射袁 電流。 1245487 14772twf.doc/g 電晶體模組450耦接於接點VA、電壓源VDD、與輸出端 Output之間。本實施例的電晶體模組45〇包括並聯的主要金氧 半場效電晶體FET2以及次要金氧半場效電晶體FET3。其中 小尺寸=次要金氧半場效電晶體FET3是用於維持放大器在低 電流狀態下的線性度(linearity)，會根據控制訊號A1導通或關 斷。FET2與FEI3在本實施例中都是刪〇8電晶體，而本發 明也涵蓋了 PM0S電晶體（P通道金氧半場效電晶體，即 p-channel metal oxide semiconduct〇r fldd effect •為PMOSFET)。電晶體模組45〇的作用在後面有詳細說明。 ，然圖3的貫施例只包括—個次要金氧半場效電晶體阳）， 實際上，本發明可以包含任意數量的次要金氧半場效電晶體， 也可以不包含次要金氧半場效電晶體。 負載電路L2麵接於電顧VDD與串接放大器物的輸 出端0呻Ut之間，做為輸出負載(output loading)，並且自電壓 ，VDD接收電流。本實_的負載電路L2僅包括一個電感 裔’但疋在本發明的範圍内，負載電路L2可以是由任意數^ 的負載70件，例如電容器、電感器與電阻所組成的電路。 圖3的實_中，匹配電路·包括關元件挪、刪㈨ 電晶體附5、運算放大器（〇P-amP) A、PM0S電晶體酣4、 R2。其中開關元件SW1耗接於電愿源vdd與 電晶體FET5之間，控制有無電流通過N ^ NM〇S FET5 輸入鳊耦接於阻擋電路R2，而輸出 PM0S電晶體FET4〇PM〇S雷日㈣拉出^輕接於 運算放大器A的輸出端、馬接於電壓源侧、 Μ及串接放大器44〇的接點¥八之 11 1245487 14772twf.doc/g 間。阻擒電路R2 _接於運算放λ|§ A的第 點VA之間，作用為阻撞射頻訊號。 以而與接 規mm1在本實施射可用金氧半場效電晶體來實 見f卜在本兔明的範圍内，阻撞電路R1與幻是由至 二個高阻抗元件所組成’如可阻擋射頻（radi。㈣u 稱為RF)訊號的電阻及電感。本實施例的阻擒電路則與… 是由二個電阻串聯組成。至於匹配電路43〇的作用， 詳細說明。 另 圖3當中的控制電路42〇耦接於匹配電路43〇，作用是控 制通過NMOS電晶體fET5的電流大小。本實施例的控制電路 420只包含一個NM0S電晶體FET6，FET6與參考電流源· 的NMOS冑晶體FET7組成一個電流鏡，將參考電流鏡射到 FET6與FET5。本發明所包含的控制電路不只是控制電路42〇 這麼簡單，在後面的其他實施例中，會有更複雜的控制電路， 也會說明控制電路如何控制1^]4〇8電晶體即丁5的電流大小。 阻檔電路R1耦接於參考電流源41〇的NM〇s電晶體 FET7與串接放大器440的輸入端input之間，作用是阻擋射頻 訊號。在本發明的範圍内，阻擋電路R1是由至少一個高阻抗 元件所組成。而本實施例的阻擋電路R1是由三個電阻串聯組 成0 圖3的電流匹配式可變增益放大器有兩種增益可供切 換。在高增益模式下，開關元件SW1會關斷，使匹配電路430 失去作用，而控制訊號A1會使NMOS電晶體FET3導通。此 時NMOS電晶體FET2與FET3同時導通，串接式放大器440 處於正常運作而達到高增益。 在低增益模式下，控制訊號A1會使NMOS電晶體FET3 12 1245487 14772twf.doc/g 關斷，而開關元件SW1會導通。匹配電路包含一個以運 异放大ϋ A為中心'的_控制機制，當關科剛導通 時’回饋機制就會啟動。此時NM〇s電晶體FET6血阳7合 構成電流鏡，將FET7的參考電流鏡射到航6與服5。做二 極體連接的FET5會提供位於接點VB的參考電麼給運曾放大 器A阻檔電路Μ會將接點VA❾電壓傳達給運^大器 A。運异放大器A比較兩個接點的電壓之後，其輸出會控制 ^ PM〇S電晶體FET4的閘極(_)，使FET4產生電流。FET4 ❿的電流會使通過FET2的電流減少，進而減少航2的閉源極 電壓(gate-to-source voltage)，也就是減少接點va的電壓。之 後，接點VA白勺電壓會繼續影響運算放大器a的輸出。 &配電路430會透過以上的回饋機制，使得接點va與接 點VB的電壓相等，而NM〇s電晶體航5與ρΕτ2的大小完 全一致，加上一致的閘源極電壓，等於1^丁2與17^15也構成 個電流鏡’因此通過FET2的電流會等於通過FET5的電流。 圖3的可變增益放大器就是藉由阳2的電流隨著ρΕτ5改變 而切換不同的增益。 驗 圖4是根據於本發明另—實施儀電流匹配式可變增益 放^器的電路圖。圖4是圖3的延伸，將圖3的放大器的兩段 增盃延伸為多段增益。圖3的控制電路42〇換成了圖4 電路520,圖3的電晶體模組450換成了圖4的電晶體模組 550，圖4的其餘構件與圖3相同。 圖4的控制電路520包含四個分支，每個分支各自耦接於 匹配電路430、參考電流源410、與地線GND之間。每個分支 各包含串聯的一個開關元件（標示為SW2至SW5)以及一個 NMOS電晶體（標示為FET6a至FET6d>NMOS電晶體FET6a 13 1245487 14772twf.doc/g 顺NMQS電晶體FET7構成電流鏡，將參考電 ;ί是否分i ’而開關元件SW2至SW5是為了控制各個 的iC由圖4不難看出，通過觸S電晶體FET5 至SW5 ^ it過所有分支的總電流’因此透過開關元件SW2 FET5的開啟與關閉組合，就能控制通過應⑽電晶體 器的增/。 而改變圖4的電流匹配式可變增益放大 本實施例的控制電路52〇包含四個分支，然而本發明並不 ，限於四個分支，也不於NMGS電晶體。在本發明的範 =士控㈣路可包含任意數量的分支，由對應數量的 %效電晶體與開關元件所組成。 千 、圖4的電晶體模組55〇包括主要金氧半場效電晶體FET2 以及次要金氧半場效電晶體FET3a與FET3b。這三個金 場效電晶體並聯於輸出端0utput與接點VA之間。其中，次 要金氧半場效電晶體FET3a與FET3b各根據控制訊號Ala與1245487 14772twf.doc / g IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a variable gain amplifier, and particularly to a current-matching variable gain amplifier. Lier [Previous Technology] • With the rapid growth of the wireless communication field, many people have studied the variable gam amplifier. So far, although there are many solutions, there is still room for improvement. ",," is a circuit diagram of a variable gain amplifier proposed in US Patent Application No. 2003/0181181. Among them, Input is the input terminal and OUTput is the output terminal, and the inductor 202 is the load of the amplifier circuit. This amplifier is controlled. Signal 201 turns on or off the N-channel metal-oxide-semiconductor field-effect transistor (n_channd • metal oxide semiconductor field effect transistor NMOSFET, hereinafter referred to as NMOS transistor) 211 and 212 respectively, so as to change k through inductor 202. Current, switching between two gains. In the high gain mode, the control signal 201 will turn off the NMOS transistor 211 and turn on the NMOS transistor 212, so that all currents pass through the inductor 202 to achieve high gain. In the low gain mode, the control signal 201 turns on the NMOS transistor 211 and turns off the NMOS transistor 212, so that only part of the current is passed through the inductor 202 to achieve a low gain i. The circuit of this amplifier is simpler than the previous one. The problem is that in order to achieve accurate gain values, the sizes of the NMOS transistors 211 and 213 must be properly matched. However, this problem is not easy to solve because of the limited semiconductor process. In order to make most of the current flow into the NMOS transistor 211 to achieve a low gain mode, the size of this transistor must be larger, resulting in larger power loss during high gain operation, making the noise characteristics worse. FIG. 2 is a circuit diagram of the variable gain amplifier proposed by US Patent No. 6211737. 1245487 14772twf.doc / g. The input terminal of this amplified state is I 叩 ut, and the output terminal is Output. It uses the shunting technique like the previous amplifier. That is, the control signals 301 to 303 are used to open or close the bipolar junction transistor (hereinafter referred to as BJT transistor) 311 to 313, respectively, so that the branch circuits 321 to 323 share or not share the current, respectively. By changing the magnitude of the current flowing through the BjT transistor 31, it is possible to switch between different gains. This amplifier has the same disadvantages as the previous amplifier, that is, the size of the transistor is not easy to match, and the power loss is large during high gain operation. As can be seen from the above description, we still need better and easier to design amplifier circuits to further improve many problems of the prior art. SUMMARY OF THE INVENTION The object of the present invention is to provide a current-matching variable gain amplifier, which has the advantages of relatively simple circuits, does not require complicated impedance matching, and has relatively low power loss during high-gain operation, which is sufficient to solve the prior art. The problem. In order to achieve the above and other objectives, the present invention proposes a current-matching gain amplifier, which includes a reference current source, at least one series amplifier (Ca__), a matching circuit, a control circuit, and at least one first 2, + Reference_to provide a reference current. The serial amplifiers are based on: test & receive-input signal, and then output-output signal, where the output signal is the result of amplification of the input signal. The B circuit is secretly connected in series. ^ Decrease the voltage of the-contact of the large-amplifier, and make each series amplifier ::; the current is equal to the-metal-oxide half field effect transistor of the matching circuit. The "matching circuit" controls the first of the metal-oxygen half-field effect "body ^ = size. The first blocking circuit is connected in series with the above amplifier to cry-an electric ice is connected in series with the reference current source Lin Ying. I lightly connect 1245487 M772twf. Doc / g current-matching variable gain amplifier on the top, Xu's current-matching variable gain amplifier = the above amplifier configuration-single-side series amplifier: only " include a series amplifier, this series connection In the embodiment, the above-mentioned series-connected amplifiers are constituted; two: a large output terminal is two series-connected amplifiers, and a wheel input terminal of the U-connected amplifier is two series-connected amplifiers. This difference in series amplifier is connected to a gain amplifier. In the embodiment, the size of each string of metal-oxygen half-field-effect transistors is equal to the size of the first circuit variable gain amplifier with a fine-grained circuit. In one embodiment, Device, at least-a second metal oxide 4 effect; two =; said body,-do electricity . Among them, the switching element _ 于 _ "Di Er obstructs the metal-oxygen half field effect contact. Second :: Di Er blocking circuit and the series amplifier one by one = :: between the input terminal and the corresponding-contact of the series amplifier ": Matching variable gain amplifier 'In an embodiment, the control p is further extended to ^ second metal-oxide half-field effect transistors, and each of the third gold ^ each effect transistor is secreted in the matching circuit and reference current source , Pan Ping ^ mir; or) 1245487 14772twf.doc / g == heart_body, the control circuit further includes multiple geese, m related 7 " pieces and the third metal-oxide half field effect transistor-pair ^ .σ self-confidence The variable gain amplifier in the matching circuit and the circuit of the corresponding third metal-oxide-semiconductor half-effect transistor is, in the embodiment, controlled by the matching circuit and the source and a round-out inductor. The variable current source Coupling the output voltage, adjusting the output of the variable current source to increase the gain of the first gain ^ Oxygen Yang = Lei Si metal oxide half field effect transistor, the main gold four total oxygen ^ two load circuit. Inductor_ Yu-Ground. The first contact, Γ 7 flood. The main metal-oxygen half field effect transistor is coupled to the Ang contact, one The voltage source and the series connection are coupled between the voltage source and the series amplifier. The two ends of the load circuit are connected to the load circuit. The voltage is received from the voltage source. Circuit type: variable gain amplifier. In the embodiment, the load It is composed of a load element, a device, an inductor n, and a resistor. The type of the carrier load is the above-mentioned current-matching variable gain amplifier, which is crying out. —A second major oxygen Half field effect transistors. These: two: the main metal oxide half field effect transistors are connected in parallel, and they are controlled according to the mouth feed peak edbaek, which makes the 9-1245487 14772twf.doc / g current of the first metal oxide half field effect transistor and the main metal The oxygen half field effect transistor has the same current, so it can achieve a relatively simple circuit without the need for complicated impedance matching. In addition, because the size of the second gold gas half field effect transistor is small, it can achieve high power consumption during high gain operation. Relatively low advantages. This is enough to solve the problems of the prior art. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes preferred embodiments of the present invention and cooperates with the accompanying drawings The description is as follows. [Embodiment] FIG. 3 is a circuit diagram of a current matching variable gain amplifier according to an embodiment of the present invention. The amplifier of FIG. 3 includes a reference current source 410, a series amplifier 440, a matching circuit 430, The control circuit 42 and the blocking circuit are magic. The role of the reference current source 410 is to provide the reference current to the current source stove #, so the left half of the current mirror. The series amplifier 44o will be based on the reference current from the reference current source 41o. The input signal is received from the input terminal Input, amplified, and then output as an output signal at the output terminal Output. In the embodiment of FIG. 3, only one serial amplifier 440 constitutes a single-sided serial amplifier (singie-sided casc). The invention is not limited to a series amplifier. In other embodiments, two or more series amplifiers may be included. The series connection amplifier 440 includes an inductor li, a NMOS transistor FET1, a transistor module 450, and a load circuit u, as described in detail below. The inductor L1 is connected between the ground GND and the nm transistor FET1, and its role is to match the input impedance. NM〇s transistor FET1 is coupled between inductor Li, input terminal, and contact VA. It is responsible for receiving the input from the input terminal, and from the reference current source 41. NMOS transistor. FET7 mirrors Yuan current. 1245487 14772twf.doc / g The transistor module 450 is coupled between the contact VA, the voltage source VDD, and the output terminal Output. The transistor module 45 of this embodiment includes a primary metal-oxide-semiconductor FET2 and a secondary metal-oxide-semiconductor FET3 connected in parallel. Among them, small size = secondary metal-oxide-semiconductor field-effect transistor FET3 is used to maintain the linearity of the amplifier in a low current state, and will be turned on or off according to the control signal A1. Both FET2 and FEI3 are deleted in this embodiment, and the present invention also covers PMOS transistors (P-channel metal oxide semi-conductor transistors, which are PMOSFETs). . The function of the transistor module 45 will be described in detail later. However, the embodiment shown in FIG. 3 only includes one secondary metal-oxide half-field effect transistor. In fact, the present invention may include any number of secondary metal-oxide half-field effect transistors, or may not include secondary metal-oxide. Half field effect transistor. The load circuit L2 is connected between the power supply VDD and the output terminal 0 呻 Ut of the amplifier in series, as an output loading, and receives the current from the voltage VDD. The actual load circuit L2 includes only one inductor. However, within the scope of the present invention, the load circuit L2 may be an arbitrary number of 70 loads, such as a circuit composed of a capacitor, an inductor, and a resistor. In FIG. 3, the matching circuit includes switching of the element, deletion of the transistor, operation amplifier (0P-amP) A, PMOS transistor 4 and R2. The switching element SW1 is connected between the electric source vdd and the transistor FET5, and controls whether or not a current is coupled to the blocking circuit R2 through the N ^ NMMOS FET5 input 5, and the output PM0S transistor FET4 〇PM〇S 雷 日 ㈣ Pull out ^ lightly connected to the output terminal of the operational amplifier A, connected to the voltage source side, Μ and the connection point of the serial amplifier 44. ¥ 11 of 1245487 14772twf.doc / g. The blocking circuit R2 _ is connected between the point VA of the operational amplifier λ | § A and functions to block the RF signal. Therefore, with the connection of mm1 in this implementation, a gold-oxygen half-field effect transistor can be used to see that in the scope of this rabbit, the collision circuit R1 and the magic are composed of two high-impedance components. Radio frequency (radi.㈣u is called RF) signal resistance and inductance. The blocking circuit of this embodiment is composed of two resistors in series with ... The function of the matching circuit 43 will be described in detail. In addition, the control circuit 42 in FIG. 3 is coupled to the matching circuit 43 and controls the current flowing through the NMOS transistor fET5. The control circuit 420 of this embodiment only includes one NMOS transistor FET6, and the FET6 and the reference current source NMOS 胄 crystal FET7 form a current mirror, and the reference current mirror is irradiated to the FET6 and the FET5. The control circuit included in the present invention is not just as simple as the control circuit 42. In other embodiments described later, there will be more complicated control circuits. It will also explain how the control circuit controls 1 ^] 408. The amount of current. The blocking circuit R1 is coupled between the NMOS transistor FET7 of the reference current source 41 and the input terminal input of the series amplifier 440, and is used to block the radio frequency signal. Within the scope of the present invention, the blocking circuit R1 is composed of at least one high-impedance element. The blocking circuit R1 of this embodiment is composed of three resistors in series to form 0. The current-matching variable gain amplifier of FIG. 3 has two kinds of gains for switching. In the high gain mode, the switching element SW1 is turned off, making the matching circuit 430 ineffective, and the control signal A1 will turn on the NMOS transistor FET3. At this time, the NMOS transistor FET2 and FET3 are turned on at the same time, and the series-connected amplifier 440 is in normal operation to achieve high gain. In the low gain mode, the control signal A1 turns off the NMOS transistor FET3 12 1245487 14772twf.doc / g, and the switching element SW1 turns on. The matching circuit contains a _ control mechanism centered on the operational amplifier ϋ A as the center. When the Guanke just turns on, the feedback mechanism will start. At this time, the NM6 transistor FET6 and the blood yang7 are combined to form a current mirror, and the reference current mirror of the FET7 is shot to the navigation 6 and the service 5. The diode-connected FET5 will provide the reference voltage at the contact VB to the blocking circuit A of the amplifier A, and will transmit the voltage of the contact VA to the amplifier A. After the amplifier A compares the voltage of the two contacts, its output will control the gate (_) of the transistor FET4, so that the FET4 generates a current. The current flowing through FET4 will reduce the current flowing through FET2, which will reduce the gate-to-source voltage of Hang2, that is, reduce the voltage of contact va. After that, the voltage at the contact VA will continue to affect the output of the operational amplifier a. & The distribution circuit 430 will make the voltage of the contact va and the contact VB equal through the above feedback mechanism, and the size of the NMOS transistor 5 and ρΕτ2 is exactly the same, plus a consistent gate-source voltage, equal to 1 Ding 2 and 17 15 also form a current mirror, so the current through FET2 will be equal to the current through FET5. The variable gain amplifier in Fig. 3 is to switch different gains by changing the current of yang 2 with ρEτ5. Fig. 4 is a circuit diagram of a current-matching variable gain amplifier according to another embodiment of the present invention. Fig. 4 is an extension of Fig. 3, which extends the two-stage booster of the amplifier of Fig. 3 into a multi-stage gain. The control circuit 42 of FIG. 3 is replaced by the circuit 520 of FIG. 4, and the transistor module 450 of FIG. 3 is replaced by the transistor module 550 of FIG. 4. The remaining components of FIG. 4 are the same as those of FIG. 3. The control circuit 520 of FIG. 4 includes four branches, and each branch is respectively coupled between the matching circuit 430, the reference current source 410, and the ground GND. Each branch contains a switching element (labeled SW2 to SW5) in series and an NMOS transistor (labeled FET6a to FET6d). The NMOS transistor FET6a 13 1245487 14772twf.doc / g cis-NMQS transistor FET7 constitutes a current mirror. Reference electric; whether or not i 'is divided and the switching elements SW2 to SW5 are for controlling the respective iC. It is not difficult to see from Figure 4. By touching the S transistors FET5 to SW5 ^ it passes the total current of all branches' so through the switching element SW2 FET5 The combination of on and off can control the gain of the transistor. In addition, the current-matching variable gain amplifier of FIG. 4 is changed. The control circuit 52 of this embodiment includes four branches, but the present invention does not, It is limited to four branches and not to NMGS transistors. In the present invention, the fan control circuit can include any number of branches, which are composed of a corresponding number of% efficiency transistors and switching elements. Thousands of transistors in Fig. 4 Module 55 includes the main metal-oxide-semiconductor FET2 and the secondary metal-oxide-semiconductor FET3a and FET3b. These three gold-effect transistors are connected in parallel between the output terminal OUTPUT and the contact VA. Oxide-semiconductor field effect transistor with FET3b FET3a each control signal according to Ala
Alb導通或關斷，FET3a# FET3b的作用與圖3的次要金 半場效電晶體FET3相同。 圖4的電流匹配式可變增益放大器，在最高增益時，開關 兀件SW1至SW5全部關斷，而控制訊號AU與鳩會使次 要金氧半場效電晶體FET3a與FET3b全部導通。如果想到較 低的增益，可分批導通開關元件SW1以及SW2至sw5；；啟動 匹配電路430 ’使PMOS電晶體FET4產生電流。此時次要金 氧半場效電晶體FET3a與FET3b會依次關斷，以降低電晶體 杈組550之内的電晶體有效大小，確保導通的電晶體在飽和區 (saturation region)内操作。由於通過電晶體模組55()的電流降 低，圖4的電流匹配式可變增益放大器可達成較低的增益。在 14 1245487 14772twf.doc/g 最低增益時，開關元件SW1與撕 处 件SW3至SW5 、， 处於^通狀恶，而開關元 都處於關斷狀態。a Μ杨效電晶體FET3a與FE!3b 放大H疋根據於本發明另一實施例的電流匹配式可變辦兴 H的電路圖。圖5朗3的 ^: 450換成了不含戈|j疋口 J的私日日體杈組 且圖3的加引+ 、，乳丰琢效电晶體的電晶體模組650，而 出;庫哭:闰路420換成了圖5的可變電流源Iref2以及輸 出感應叩OS。圖5的其餘構件與圖3相同。 、圖f的電流匹配式可變增益放大器的目的，是自動修正周 化、電壓源VDD的電麗變化、以及製程等因素對^ 盈的影響。輸出感應器os會感應輸出端〇傘t的輸 出電堡的變化’藉以調整可變電流源Iref2所輸出的電流大 小。因為Iref2耦接於匹配電路43〇的NM〇s電晶體fet5 士 的輸出電流大小就是通過NMOS電晶體FET5以及FET2的電 流大小，會改變輸出端〇utput的增益，所以圖5的電流匹配 式可變增益放大器能自動修正上述因素對於增益的影響。 舉例而言，下面的表1是電壓與溫度變化對於放大器增益 的影響。由表1的數據可知，實際的差距有將近ldB的誤差。 如果有圖5的自動修正，可以做到幾乎沒有誤差。 表1，溫度與電壓變化對於增益聚響 VDD 溫度變化 溫度變化 的電壓 -40°C 25〇C 85〇C -40°C 25〇C 85〇C 變化 高低增益差距(dB) 向低增益差距的Ί 吳差(dB) 1.7V 14.12 15.21 15.93 -0.9 —0·21 0.93 1.8V 13.18 15.33 15.96 -0·8 0.33 0.96 1.9V 14.18 15.32 16.00 -0.8 0.32 0.99 15 1245487 14772twf.doc/g ，6為根據於本發明另一實施例的電流匹配式可變增益 放大器的電路圖。圖6的實施例除了串接放大器44〇之外，還 有】個串接放大器740。這兩個並聯的串接放大器構成一個 差異串接放大器（differentiai casc〇deampHfier)，其輸入端是由 串接放大态440的輸入端i^ut與串接放大器74〇的輸入端 P 、、且成’其輸出端是由串接放大器440的輸出端Output 與串接放大器740的輸出端0utputn組成。 一為了配合新增的串接放大器740，圖6的實施例增加了阻 撞笔路Rln在NM0S電晶體FETln與FET7之間阻擔射頻訊 號。與圖3的匹配電路430相比，圖6的匹配電路730也增加 了 PM0S電晶體FET4n與阻擋電路R2i^PM0S電晶體FET4n 耦接於運算放大器A的輸出端、電壓源VDD、以及串接放大 杰740的接點VAn之間，而阻擋電路R2n耦接於運算放大器 A的第一個輸入端與接點VAn之間。匹配電路會以回饋 機制使VB、VA、與VAn這三個接點的電壓一致，並且使通 過NM0S電晶體FET2與FET2n的電流和通過FET5的電流一 致。圖6的其餘構件與圖3相同。 圖4的控制電路520可用來取代圖6的控制電路420。圖 4的電晶體模組550可用來取代圖6的電晶體模組450與750。 圖5的可變電流源iref2與輸出感應器〇s也可以用來取代圖6 的控制電路420。另外，圖6的實施例只包括兩個並聯的串接 放大态440與740 ’而本發明亦涵蓋了使用更多個串接放大器 的實施例。看過前面的說明之後，在本發明相關技術領域具備 通常知識者應該不難實現上述的變化與延伸。 如以上的實施例所述，本發明以回饋控制機制達成電流匹 配效果，因此電路比較簡單，不需要複雜的阻抗匹配，也不需 16 1245487 14772twf.doc/g 要匹配電晶體大小。另外，因為匹配電路的pM〇s電晶體（如 圖3的]^MOS電晶體FET4)的尺寸較小，因此可達到在高增 益操作時功率損耗比較低的優點。如此即足以解決先前技術的 問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 .【圖式簡單說明】 圖1至圖2為先前技術的可變增益放大器。 圖3至圖6為根據於本發明不同實施例的電流匹配式可綠 增益放大器。 & 【主要元件符號說明】 201 :控制訊號 202 :電感器 211〜213 ·金氧半場效電晶體 301〜303 :控制訊號 > 310〜313 :雙極接面電晶體 320 :跨導電路 321〜323 :分支電路 410 :參考電流源 420、520 ··控制電路 430、730 ··匹配電路 440、740 ··串接放大器 450、550、650、750 :電晶體模組 A:運算放大器 1245487 14772twf.doc/g A1、Ala、Alb :控制訊號 Bias :電壓訊號 FET1 〜FET7 、 FETln 〜FET4n 、 FET3a 〜FET3b 、 FET6a〜FET6d :金氧半場效電晶體 GND :地線 Input、Inputn :輸入端 Iref:電流源 Iref2 :可變電流源 _ LI、Lin :電感器 L2、L2n ·•負載電路 OS :輸出感應器Alb is turned on or off, and the function of FET3a # FET3b is the same as that of the secondary gold half field effect transistor FET3 of FIG. 3. In the current-matching variable gain amplifier of FIG. 4, at the highest gain, all of the switching elements SW1 to SW5 are turned off, and the control signals AU and dove all turn on the secondary MOSFETs FET3a and FET3b. If a lower gain is desired, the switching elements SW1 and SW2 to sw5 can be turned on in batches; the matching circuit 430 'is activated to cause the PMOS transistor FET4 to generate a current. At this time, the secondary metal-oxide-semiconductor half-effect transistors FET3a and FET3b are turned off in order to reduce the effective size of the transistors within the transistor group 550 and to ensure that the turned-on transistors operate in the saturation region. Because the current through the transistor module 55 () is reduced, the current matching variable gain amplifier of Fig. 4 can achieve a lower gain. At the lowest gain of 14 1245487 14772twf.doc / g, the switching element SW1 and the tearing elements SW3 to SW5 are in the same state, and the switching elements are in the off state. a MH Yang transistor FET3a and FE! 3b magnify the circuit diagram of a current-matching variable circuit H according to another embodiment of the present invention. Figure 5: ^ 3: 450 is replaced by a private day and day body group without Ge | jJ 口 J and the transistor module 650 of Figure 3 is added. Ku cry: Kushiro 420 has been replaced with the variable current source Iref2 and the output induction 叩 OS shown in Figure 5. The remaining components of FIG. 5 are the same as those of FIG. 3. The purpose of the current-matching variable gain amplifier shown in Figure f is to automatically correct the effects of factors such as aging, changes in the voltage of the voltage source VDD, and the manufacturing process. The output sensor os will sense the change in the output power of the output terminal 0 ′ to adjust the current output by the variable current source Iref2. Because Iref2 is coupled to the matching circuit 43, the output current of the NMOS transistor fet5 is the current through the NMOS transistor FET5 and FET2, which will change the gain of the output terminal. Therefore, the current matching formula in Figure 5 can be The variable gain amplifier can automatically correct the influence of the above factors on the gain. For example, Table 1 below shows the effect of voltage and temperature changes on amplifier gain. It can be known from the data in Table 1 that the actual gap has an error close to ldB. If there is an automatic correction in Fig. 5, almost no error can be achieved. Table 1. Changes in temperature and voltage for gain VDD. Temperature change. Voltage for temperature change. -40 ° C 25 ° C 85 ° C -40 ° C 25 ° C 85 ° C Change in Gain Gain (dB) Ί Wu difference (dB) 1.7V 14.12 15.21 15.93 -0.9 —0 · 21 0.93 1.8V 13.18 15.33 15.96 -0 · 8 0.33 0.96 1.9V 14.18 15.32 16.00 -0.8 0.32 0.99 15 1245487 14772twf.doc / g, 6 is based on A circuit diagram of a current-matching variable gain amplifier according to another embodiment of the present invention. The embodiment of FIG. 6 includes a serial amplifier 740 in addition to the serial amplifier 44o. The two parallel-connected series amplifiers constitute a differential series amplifier (differentiai casc deamp Hfier), whose input terminal is an input terminal i ^ ut of the serial amplifier state 440 and an input terminal P of the serial amplifier 74, and The output terminal is composed of the output terminal Output of the serial connection amplifier 440 and the output terminal Outputn of the serial connection amplifier 740. First, in order to cooperate with the newly added serial amplifier 740, the embodiment of FIG. 6 adds a blocking pen circuit Rln to block the RF signal between the NMOS transistor FETln and the FET7. Compared with the matching circuit 430 of FIG. 3, the matching circuit 730 of FIG. 6 also adds a PM0S transistor FET4n and a blocking circuit R2i ^ PM0S transistor FET4n which are coupled to the output terminal of the operational amplifier A, the voltage source VDD, and a series amplifier. Jie 740 is connected between the contact VAn, and the blocking circuit R2n is coupled between the first input terminal of the operational amplifier A and the contact VAn. The matching circuit will use the feedback mechanism to make the voltages at the three contacts VB, VA, and VAn the same, and make the current through the NMOS transistor FET2 and FET2n consistent with the current through FET5. The remaining components of FIG. 6 are the same as those of FIG. 3. The control circuit 520 of FIG. 4 may be used instead of the control circuit 420 of FIG. 6. The transistor module 550 of FIG. 4 may be used instead of the transistor modules 450 and 750 of FIG. 6. The variable current source iref2 and the output inductor 0s of FIG. 5 can also be used instead of the control circuit 420 of FIG. 6. In addition, the embodiment of Fig. 6 includes only two parallel-connected amplifier states 440 and 740 ', and the present invention also covers an embodiment using more series-connected amplifiers. After reading the foregoing description, it should not be difficult for those with ordinary knowledge in the technical field related to the present invention to implement the above-mentioned changes and extensions. As described in the above embodiments, the present invention uses a feedback control mechanism to achieve the current matching effect. Therefore, the circuit is relatively simple, does not require complicated impedance matching, and does not require 16 1245487 14772twf.doc / g to match the size of the transistor. In addition, because the size of the pMOS transistor (as shown in Figure 3) of the matching circuit is smaller, the advantage of lower power loss during high gain operation can be achieved. This is sufficient to solve the problems of the prior art. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. [Brief Description of the Drawings] Figures 1 to 2 show the prior art variable gain amplifiers. 3 to 6 are current-matching green gain amplifiers according to different embodiments of the present invention. & [Description of Symbols of Main Components] 201: Control signal 202: Inductor 211 ~ 213 · Metal oxide half field effect transistor 301 ~ 303: Control signal > 310 ~ 313: Bipolar junction transistor 320: Transconductance circuit 321 ~ 323: Branch circuit 410: Reference current source 420, 520 ... Control circuit 430, 730 ... Matching circuit 440, 740 ... Series amplifier 450, 550, 650, 750: Transistor module A: Operational amplifier 1245487 14772twf .doc / g A1, Ala, Alb: Control signals Bias: Voltage signals FET1 to FET7, FETln to FET4n, FET3a to FET3b, FET6a to FET6d: Metal Oxide MOSFETs GND: Ground Input, Inputn: Input Iref: Current source Iref2: Variable current source_ LI, Lin: Inductors L2, L2n • Load circuit OS: Output inductor
Output、Outputn :輸出端 R1、R2、Rln、R2n :阻擋電路 SW1〜SW5 :開關元件 VA、VAn、VB :電路的接點 VDD :電壓源Output, Outputn: Output terminals R1, R2, Rln, R2n: Blocking circuits SW1 to SW5: Switching elements VA, VAn, VB: Contacts of the circuit VDD: Voltage source
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