TWI244277B - Method for WCDMA frame synchronization and related device - Google Patents

Abstract

A method for performing frame synchronization in a WCDMA system includes first, correlating a received signal with a plurality of predetermined correlators to obtain a plurality of frame synchronization correlation results, then, coherently combining frame synchronization correlation results with a slot synchronization phase when a test phase difference is less than a threshold phase difference, or, coherently combining frame synchronization correlation results with a linear combination of slot synchronization phases when the test phase difference is greater than or equal to the threshold phase difference. The slot synchronization phase is determined by correlating the received signal with a slot synchronization sequence. Lastly, the method determines a frame boundary of the received signal based on the coherent combination results. The method accommodates for a changing signal to noise ratio to improve frame synchronization speed and accuracy.

Description

I 94. 7 ″ 5 — 1

j 12442, or two-sided I ~-__year month day_correction__ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for wideband code division multiple access (Wideband Code Division Multiple Access? WCDMA) search method for communication area (C e 1 1) system, especially a method for frame synchronization in a wideband code division multiple access system. [Previous technology] The importance and spread of spread-spectrum communication systems in cellular network systems is increasing, especially when the wideband code division multiple access system is gradually commercialized, and the system has a market that significantly improves performance and reliability. potential. In order to establish a network connection in a wideband CDMA multiple access system, a user equipment (UE) must first perform a communication area search procedure. The communication area search program enables the user equipment to achieve timing and coding synchronization with the Downlink Channel. There are many different methods known in the art for performing communication area search procedures. Known technologies have been revealed, such as published in the International Journal of Electrical and Electronic Engineering, Vol. 18, No. 8 (August 2000 Edition) (Vo 1 · 18, No. 8 (August 2000 edition) of (IEEE Journal on Selected Areas in Communications) by Yi-Pin Eric

"RCell Search in W-CDMA" by Wang and Tony Ottosson is described and cited in this case.

Page 8

Modified ϋ〇ΙΏΠ1 () η Pilot Channel (CPICH) 20 and shared control band 10: block diagram of the same propagation. The code used in the common pilot band 20 is dedicated to the base station. In a wideband CDMA multiple access system, a fixed platform can choose one of the 512 different main scrambling codes for shared guidance. The 20 and 2 main scrambling codes are composed of 6 4 It consists of a code group and 8 independent codes in each code group 2. The synchronization code in the main synchronization frequency band 6 p is shared by all base stations, so it can also be used for $ synchronization in the time slot. Although the secondary synchronization code of the secondary synchronization band 1 6 s is in the time slot 1 4 code, it changes with the base of the time slot 1 4 ', but the sequence pattern of the secondary synchronization band 1 6 s is used and refined (pat ter η) still depends on the coding used in the code group for the common code 1 pilot band 20. That is, there are 64 sequences in the 'secondary synchronization band 16 s. The sequence mode can be adopted.' One coding sequence mode corresponds to a specific code group combined with the codes used in the ^ guide 20 channel 20. The shared control channel signal 1 received by / by waiting and all possible minor steps =, 16S encoding sequence are crosslinked (correlating) to find the maximum crosslink value (Maximum Correlation Value), then It is possible to synchronize with the code group of the guide channel 2 0 and achieve the frame 2. Since the secondary synchronization frequency band 16s is changed according to a pre-defined sequence, the sequence of opening J is known and placed at the beginning of each frame 12. I = therefore frame synchronization can be achieved. When the code group code f of the common pilot frequency band 20 is shared, the main channel used in the communication area can be obtained by calculating the correlation between every 8 signals in the group used to identify the common pilot frequency band 20. code. And when the main scrambling code used by the base station is confirmed, the specific propagation frequency band between the system area and the signal area can be read.

Page 9 —— ^^ _— mJi842_ 年月 日 _Ifi_ V. Description of the invention (4) According to the above, the search method of the communication area is generally divided into the following three steps: Step 1: Time slot synchronization

Time slot synchronization is performed using the main synchronization band 16p. Matching between the main synchronization codes shared by all base stations is usually achieved by a matched filter or similar device. Generally speaking, a useful time slot in a frame is a non-coherently combination after the output of the matched filter. After finding a maximum peak value, the time slot length range is obtained according to the maximum peak value. . Step 2: Frame synchronization and code group identification

The time slot length obtained in step 1 is used to perform a cross-link operation on the secondary synchronization band 16 s and all possible secondary synchronization codes. From the secondary synchronization code 1 to the secondary synchronization code 16 constitute a code sequence having 16 secondary synchronization codes. These secondary synchronization codes are cross-linked with the values of all time slots in a frame and accumulated over all possible frame ranges to produce a table of values. Each value in the table represents the range of the scrambling code group and the frame slot with its rank in the table. The largest value in the table is selected as a candidate value that can determine the frame range and code group group. Step 3: Identification of scrambling code Perform a cross-link operation between the signal and the signal in the shared pilot frequency band 20 to achieve the confirmation of the scrambling code and code group in step 2. The maximum cross-linking value is selected

Page 10 f (Chu) is replacing the page Amendment 15842 ^ V. Description of the invention (5) is the main scrambling code of the base station. And only when the maximum cross-linking value is greater than the critical value will the maximum cross-linking value be accepted. Please refer to FIG. 4. FIG. 4 is a block diagram of a conventional user equipment 30 used for communication area synchronization. To facilitate the explanation, the actual components of the user equipment 30 of the present invention are not fully shown in FIG. Necessary components. The user equipment 30 includes a transceiver 39 and a synchronizer 38. The transceiver 39 receives the propagation signal from the base station (not shown) and transmits the propagation data to the synchronizer 38 using a technique similar to a conventional wireless component. The synchronizer 38 includes a first stage 31, a second stage 32, and a third stage 33. The first stage 31 is used to perform slot synchronization in step 1 above. The results from the first stage 31 are transmitted to the second stage 32 to perform frame 12 synchronization and code group identification in dream step 2. The result produced by the second stage 32 is then transmitted to the third stage 33 to perform the scrambling code recognition of step 3. The peak value must be combined with the number of slots. In the medium, 16 p. The first stage 31 includes a peak recorder (peak Pr0f}) 34. The recorder 34 contains the same main synchronization code 35 as all base stations. The main step code 35 is compared with the main synchronization frequency band 16p received by the transceiver 39 to generate peak record data 36. The peak is discontinuously: ϊ Ϊ1 : Ϊ́ Ϊ 12 peak record data 36 will retain the preset soil film and when the main synchronization frequency band 16 卩 at each time = 2 m is sufficient to cover a complete time slot 14 of the value of the substrate recording the peak record data 36 The substrate with the shortest peak is used to mark the master and is therefore used as the time slot range offset 37. As shown in Figure 5

Page 11 94. Ί. Lb ί

12 孑 2 孑 hair replacement page I… a _ year month day _ correction _ 5. Description of the invention (6), Figure 5 is an example of peak record data 36 6 (scale is not shown). The first level 31 marks the maximum peak value appearing on the substrate No. 16 58 in the peak record data 36. The time slot range offset 37 thus has a value for indicating the peak path on the substrate No. 168. The time slot range offset 3 7 is sent to the second stage 3 2 as the time slot 1 4 synchronization point. Utilizing the position of the time slot 14 marked by the time slot range offset 37, the second stage 32 performs the above step 2 to generate a code group 32g and a time slot number 32s.

The second stage 32 has a cross-link operation unit 32c to generate a cross-link value table 32t according to the cross-link value obtained from the offset of the time slot range 37 and the secondary synchronization band 16 s and the secondary synchronization code. The cross-link arithmetic unit 32c includes 16 cross-link arithmetic units for the secondary synchronization codes. It is assumed that α 0 to α 1 5 are 16 secondary synchronization frequency bands. The output value (time slot ratio) of the cross-linking calculator. Table c in the lower part of FIG. 6 is a configuration table of the secondary synchronization code in the secondary synchronization frequency band, which can be used to look up the table. The table w on the right is used to record the cumulative results of 15 time slots. The following steps will clearly describe how to determine the frame range and code group: for slot = 0:14 for group = 0:63

for shift 2 0:14 w (group, shift) + = (c (group, (shift + slot) mod 15)) next shift next group

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€ 4 ^ 2 5 f (All oxygen daggers are replaced by I * m · »«. »* .Γϊ-.: · ^ · ί.Λ- · ^^ tvvti ^ .T-« r-.r »« r < »I.-f. ^ · Eight, ... -m-a case jj _ case number 93115842_ year month day _iMz_ V. description of the invention (7) next slot The maximum value corresponds to a code group and a time slot number. The corresponding time slot number 32s is the difference between the number of time slots and the current time slot boundary, and the boundary of the frame can also be obtained. The corresponding code group 3 2 g is used for the current communication area. The group number third stage 33 of the scrambling code also includes a cross-link arithmetic unit 33c, which is used to perform a cross-link operation on all possible main scrambling codes included in the common pilot frequency band 20 and the code group 3 2g. In this method, the cross-linking operation result 3 3r can be obtained from the main scrambling code separately. Only the main scrambling code whose corresponding cross-linking value exceeds the critical value 3 3 X and has the largest cross-linking value will be selected as the main scrambling code 3 3 p. For example, if each code group contains 8 main scrambling codes SO-S7, the main cross-link value 33r is: CO, Cl, C2, C3, C4, C5, C6, C7, respectively. Code group indicated by code group 3 2 g The main cross-linking values of the eight main scrambling codes S 0 to S7 in the group. Assuming that C 6 has the highest main cross-linking value and exceeds the threshold 33x, the third level 33 will set the value of the main scrambling code number 3 3p Is, f 6 ▼ 丨. Conventionally, the phase estimation values of the main synchronization frequency bands in the second stage 3 2 are compared with the cross-linking calculation unit 3 2 c when performing a continuous combination operation. That is, the phase correction value for the 16 s signal of the secondary synchronization frequency band is based on the phase difference of the corresponding 16 p signal of the primary synchronization frequency band, because the secondary synchronization frequency band is It is transmitted in parallel with the main sync band, and so is the main sync band. This is why we can use the phase reference value estimated from the main sync band. This method can be applied to high signal-to-noise ratio (Signal to

P. 13 h Λ ^ ΙΪ4421Ψ: \; 乂 — Ί.案 Case No. 93115842 _η Amendment V. Description of the invention (8) In the case of the lower situation, the lower energy efficiency will be C 2 3 yuan, which will be calculated separately. The slower and slower lead in the newsletter will change. The search area of the variable search area is miscellaneous. The slow and relatively slow time-to-frequency interval is similar. The video message is clearly displayed. On the low-level question and the first statement, the decisive solution is related to the main picture and the originator of the Ming Fa: \ The scope of the patent application for the invention due to the frame is to provide a right A method for synchronizing a received signal. The received signal has a plurality of frames, and each frame includes a plurality of time slots. The method includes cross-linking the received signals with a plurality of preset cross-linking operators to obtain a plurality of signals. Frame synchronization cross-link value; when a test phase difference is less than a critical phase difference, the frame sync cross-link value and a time slot sync phase are combined into a coherent combination value, and the time slot sync phase is obtained by combining the received signal with A time slot synchronization sequence is determined by a cross-linking operation; when the test phase difference is greater than or equal to the critical phase difference, a linear combination of the frame synchronization cross-link value and the time slot synchronization phase is combined into a continuous combined value; And determining a frame boundary of the accepted signal according to the coherent combination value. Another object of the present invention is to reduce the effect of high signal noise by coherently combining the calculation frame synchronization with the linear combination of the cross-linked value and the time slot synchronization.

Learning on page 14, (¾ is replacing one ------ ~ 111311 square 842 朁 turning 丨 correction V. description of the invention (9) Another object of the present invention is to select a critical value to make the frame synchronization and corresponding Code group selection is optimized. [Embodiment] Please refer to FIG. 7. FIG. 7 is a block diagram of the user equipment 100 of the present invention. Although detailed constituent elements are not shown in FIG. These different component functions can use a Central Processing Unit (CPU) to execute appropriate code to implement the method of the present invention. The detailed implementation method will be described below. There is already a central processing unit in the conventional technology. The processing unit and the corresponding code execute the search procedure of the communication area. In the preferred embodiments detailed below, the present invention can be achieved by a suitable technique. In addition, some specific hardware can also be used to implement the present invention. Part or all of the functions. In addition, these different functional units and data structures do not necessarily need to be arranged according to the parts described in Figure 7. The user equipment of the present invention 1 0 0 The user equipment 30 of the conventional technology has many similarities. In particular, both the user equipment 100 and the user equipment 30 have a transceiver 1 0 1, a first stage 1 1 0 and a third stage 1 3 0 The user equipment 100 also includes a second stage 120 to perform the method of frame synchronization and communication area search of the present invention. Please refer to FIG. 8, which is a block diagram of the second stage 120. second level

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Year, month, and year_ 5. The invention description (10) 120 includes a plurality of cross-linking operators (coorlator) 131, a combiner (140), and a selection unit (15). The plurality of cross-linking operators 1 3 1 includes a cross-linking operator 1 3 2 corresponding to the time slot synchronization signal of the main synchronization band and a cross-linking operator 1 3 4 corresponding to 16 secondary (frame) synchronization codes. a-p. The output signals of the first stage 1 10 are input to the cross-linking operators 132, 134a-p, and each of the cross-linking operators 132, i34a-p outputs a cross-linking value to the combiner 140. The combiner 140 includes a simple average (SA) processor 142 for calculating the average value of the output of the cross-linking calculator 132, a judgment logic 1 4 5 and a conjugate complex number processor 1 4 4 for obtaining judgments. The conjugate complex number of the output values of the logic unit 1 4 and the multipliers 4 6 are used to synchronize the frame obtained by the cross-linking operator 1 3 4 a-p with the estimated phase obtained by the cross-linking operator 1 3 2 The cross-linked calculation values are continuously combined. In particular, the simple average processor 142 and the conjugate complex processor 144 receive and process the output generated by the cross-link nose device 1 3 2 according to the limit of the judgment logic 1 4 5 and output the processed value to Each multiplier is 1 4 6. The processing by the judgment logic Ϊ45 includes determining whether the main (time slot) synchronization phase or the linearity of the main (time slot) synchronization phase is linear or cooperative based on the critical value of the root mean square error. This section will be described later. More details. In addition, the simple average processor 142, the judgment logic 145, and the conjugate complex number processor 144 can be rearranged, combined, or separated according to the design requirements of a professional designer. Each secondary cross-linking operator 1 3 4 a-p outputs a cross-linking value to the corresponding multiplier 1 4 6, and then the multiplier 1 4 6 synchronizes the frame cross-linking value with the conjugate complex number processor 1 4 The output values of 4 are continuously combined. Multiplier 1 4 6

V. Invention description (11) The output value is linked to the selection unit 1 50. The selection unit 150 includes a plurality of accumulators (Accumuiat〇r) 1 5 2 'wherein the female accumulators 1 5 2 are connected to a corresponding multiplier 1 4 6, a controller 1 5 4, and a non-interval coder. A Comma-Free Reed-Solomon Unit (CFRS Unit) 156, a memory 158, and a selector 160. The totalizer i 5 2, the controller 1 5 4, the C F R S unit 1 5 6 and the memory 1 5 8 generate a cross-linked value table 3 2 t as shown in FIG. 6. In particular, these components accumulate and list the cross-linking values of the code group sequence representing the secondary synchronization band of 16 s (as shown in Figure 2). When the table 32t is generated, the selector 16 then selects the maximum value from it to determine the frame boundary and code group. The selection unit 5 is actually a selection circuit for a frame boundary and a code group, which can determine and output the code group 1 2 4 of the received signal 122. In general, the operation of the second-stage circuit 120 is as follows. Primary = joint operator 132 and secondary cross-link operator 13 "—p outputs multiple synchronizing parent-link values to the combiner 1 4 0. The decision logic 丨 4 5 will determine the secondary cross-link, and the calculator 134a- The frame cross-linking value of p output should be combined with the time-slot synchronization phase output value of the main cross-link = calculator 1 3 2 or be synchronized with the current time-slot synchronization phase value and the time slot received before. The linear groups of synchronizing phase values are coherently combined. In order to increase the possibility of obtaining the correct code group 1 24, the criterion of judgment is based on the time slot synchronization phase value received at the time and before and a specially selected critical value To decide.

Page 17 1244211 Case No. 93115842 Revision V. Description of the invention (12) The operation performed by the simple average processor 1 4 2 is based on the following equation (1), equation (2) and equation (3): Equation (1 ΔP ( η) -P (η) -P (η ~ 1) where A P (η) is the phase difference P (η) obtained after a time slot operation is the synchronous phase of the time slot at that time, and P (η-1) is the previous time The synchronization phase of the slot. 14Σ ΑΡ (η) 14 Equation (2) Root mean square error (MS Ε) is calculated as follows: 14Σ (户 ⑻- 岣 显) 2 14 Equation (3) Equation (1), Equation (2) ) And equation (3) are executed by the judgment logic 145. After performing these calculations, the judgment logic 1 45 takes the calculated Δ pMSE value as a critical value, which is based on the signal of the received signal Clutter ratio. The critical value can be set at any time to any value that can optimize the operation of the present invention. For example, the

C74: .6412 Arm: Page 5842. Revision V. Invention Description (13) For the first mobile phone, the threshold value can be set to a fixed value according to the experimental value or classification method at the factory. However, for the second mobile phone, its critical value can be constantly changed by the phone's system based on the instantaneous signal-to-noise ratio measurement operation. Of course, you can also use a combination of the above two methods, or other methods with the same effect. Please refer to FIG. 9. FIG. 9 is a flowchart of determining an average value and a root mean square error (MSE) in the first embodiment. The calculation of the average and root-mean-square difference is detailed as follows: Step 3 0 0: Start; Step 3 2 2: Perform cross-linking operation between the received signal and the signal of the main synchronization frequency band to obtain the current received time. Slot synchronization phase P (η). This operation is performed by the cross-linking operator 1 32 shown in FIG. 8; Step 3 0 4: Calculate the synchronization phase P (η) of the current time slot and the previously received time slot synchronization phase P according to equation (1). (nl) The phase difference between the two. This step and subsequent steps are performed by the judgment logic 1 45 shown in Fig. 8; ❿ Step 3 06: It is judged whether the current time slot is the 14th time (the last time operation slot). If necessary, continue to judge the next time slot; Step 308: Select the next time slot; Step 3 1 0: Calculate the values of △ Pmean and Δ PMSir according to equation (2) and equation (3);

Page 19 / .ίο 12 ^ 447 ^ 1.; X y < \ Case No. 93115fc42 Month of the year _ V. Description of the invention (14) Step 3 1 2: At the end of the above procedure, the calculation of Δρμεαν and. △ pMSE values It may be repeated between alternate time slots. In particular, this series of values can be used to find the mean and root mean square difference. Please refer to the flowchart shown in FIG. 10, and the following will describe in detail all the operation processes of the second-stage circuit 120 of the present invention in FIG. 8: Step 4 0 0: Start; Step 4 2 2: Level 1 1 0 performs time slot synchronization; Step 4 0 4: The signals received by the cross-linking operators 1 32 and 1 34a-p are used for cross-linking operations. The main cross-linking calculator 1 3 2 is used to cross-link the received signal and the main synchronization frequency band signal to obtain the time slot synchronization phase P (η). Use 16 secondary cross-linking operators 1 3 4 a-ρ to cross-link the received signal with the signal of the secondary sync band; Step 4 0 6: Determine the average time slot synchronization phase difference Δ of the primary sync band Phase difference between Pmean and the time slot of the previous frame (15) △ Pmse root mean square difference. This step can be achieved by the procedure shown in Figure 9. Next, it is checked whether the root mean square difference of these phase differences ΔPμξε is greater than or equal to the critical value Pτ. If yes, go to step 408; if not, go to step 410. As shown in Figure 8, this step is performed by the judgment logic 1 4 5 according to the equation (1), equation (2) and equation (3).

Page 20 ϊ ^ ύτ% V. Explanation of the invention Step 4 0 8 931 Rev. Step 4 1 0 Step 4 1 2 Step 4 1 4 Step 4 1 6 Step 4 1 8 (15) Perform the operation; Use multiplication The device 1 4 6 continuously combines the frame synchronization cross-linking value obtained by the secondary cross-linking operator 1 3 4 a-ρ and the average time slot synchronization phase difference Δρμελν value generated by the conjugate complex processor 144; The multiplier 1 4 6 is used to synchronize the frame cross-linking value obtained by the secondary cross-linking operator 1 3 4 a-ρ and the time-slot synchronization phase P (η) value generated by the conjugate complex processor 1 4 4 Coherently combine: use the accumulator 1 5 2 to accumulate the cross-linked value, and use the controller 1 5 4, CFRS unit 1 5 6 and memory 1 5 8 to represent the secondary synchronization frequency band 16 s (such as (Shown in Figure 2) The secondary cross-linking value Wx, x of the code group sequence;: The selector 160 selects the largest list value Wx, x to determine the frame boundary; The stage 130 determines the code group of the received signal according to the determined frame boundary;: End. For the purposes of the present invention, steps 406 to 410 are the most important of all the steps of the above method. In addition, the comparison result in step 406 depends on the definition of the critical value and how to execute the storage and comparison procedure on a device. That is, the comparison will be less than or similar to the estimate. FIG. 11 is a flowchart of a method for determining a mean value and a root mean square difference according to a second embodiment of the present invention. The method of the second embodiment uses the time slot 槽

Page 21 Revision V. Description of the invention (16) The phase difference is adjusted to two ranges and the average and root mean square difference are calculated respectively. These two ranges are shown in Figure 12 and Figure 13. Select the average corresponding to the smaller root mean square error and repeat the calculation of the average and root mean square error further to improve the accuracy. The determination method of the average value and the root mean square difference in the second embodiment will be described in detail below: Step 5 0 0 ·· Start; Step 5 0 2: Calculate according to equation (1), equation (2), and equation (3) In the two different ranges of -7Γ ~ 7Γ and 0-27Γ, the average value of the phase difference of the time slot and the root mean square difference; Step 5 0 4: Select the lower root mean square error value in Step 5 0 2 and The mean corresponding to the root mean square error. Set the average value corresponding to the lower root mean square difference in step 502 as an initial average value ΔP, mean (O). In addition, the number of repeated operations m is set to 0; Step 5 0 6 Step 5 0 8 Use Equation (4) to calculate the repeated average; Use Equation (2), Equation (3), and Equation (5) to calculate at -7Γ The average and root mean square difference of the time slot phase difference in the range of ~ 7Γ; Step 5 1 0 Check whether the limit of repeated operations is reached, that is, check whether the current number of repeated operations m is equal to the preset number of repeated operations N, If yes, go to step 5 1 4; otherwise, go to step 5 1 2; step 5 1 2: perform the next repeated operation, and set the value of the repeated operation m to m + 1; step 5 1 4: end.

Page 22 1244221 Case No. 93115842 V. Explanation of the invention (17) d4 7 Mou · Yue > Revised (see) Turning page I Amendment

MEAN

MEA n (w) Equation (4) ΔP, (η) = ΔP (η)-ΔP;

The MEAN equation (5 as shown in Figure 12 and Figure 13) may have the same time slot synchronization phase value in different phase ranges. For example, in Figure 12 & I ~ 2 7Γ and Figure 13-7 The same time slot synchronization phase value appears in the phase range of Γ ~ 0. The method shown in Figure 11 above can offset the uncertainty of the actual phase range of the synchronization phase in the time slot and make the output The correctness of the value is improved. Compared with the conventional technology, the present invention regards the root mean square difference values of a plurality of time slot phases as a critical value, and then selects a corresponding time slot phase average value or obtains it based on a comparison operation. A single time slot phase value. The setting of the critical value is based on an estimated value of the signal to noise ratio or its measured value. Therefore, in an environment where the signal to noise ratio is constantly changing, accurate time slot synchronization and Corresponding code group and search confirmation to achieve communication area0

1244277 Case No. 93115842 1 Xiu (body) is replacing the year ^ Gan ...

—Jf Amendment 5. Explanation of the invention (18) The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the invention patent.

imii page 24 1244277

-f r. 15 I

Year, month, and month of repair (Qi anti-replacement page I Case No. 93115842 Ping-Wan-...-Gan Yiyi "Amendment _ Simple illustration of the drawing Simple illustration of the drawing Figure 1 is a wide-band code division multiple access system Block diagram of the shared control frequency band. Figure 2 is a time slot block diagram of the shared control frequency band shown in Figure 1. Figure 3 is a block diagram of a common pilot frequency band and the shared control frequency band shown in Figure 1. Fig. 4 is a block diagram of a conventional user equipment used for communication area synchronization. Fig. 5 is an example diagram of user equipment peak record data shown in Fig. 4. Fig. 6 is a cross-linked value diagram shown in Fig. 4.

FIG. 7 is a block diagram of a user equipment according to the present invention. FIG. 8 is a block diagram of the second-stage circuit in FIG. 7. FIG. 9 is a flowchart of deciding an average value and a root mean square error (MSE) in the first embodiment. FIG. 10 is a flowchart of a communication area searching method in the present invention. Fig. 11 is a flowchart of a second embodiment of the present invention for determining an average value and a root mean square difference. Figures 12 and 13 are phase distribution range diagrams for the method shown in Figure 11.

Symbols of the drawings 14 Symbols of the main shared control entity 16 Symbols

Page 25, Rev. 1244277 (C, page I on the first floor, case number 93115842 ^ a --- Ping ~ ~ month --- day ...) A simple explanation of the revised diagram 1 6 p Primary synchronization frequency band 16s Secondary synchronization frequency band 18 Symbol 20 Common pilot frequency band 30 User equipment 31 First stage 32 Second stage 32c Crosslink operation unit 32g Code group 32s Time slot number 32t Crosslink value table 33 First stage 33c Crosslink operation unit 33p Main scrambling code 33r Crosslink Value 33x critical value 34 peak recorder 34m matched filter, wave filter 34s SRRC 35 main sync code 36 peak record data 37 path position of main sync band (time slot range offset 38 synchronizer 39 transceiver

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1244277

Case No. 93115842 one-by-one · a-one "amendment diagram simple explanation 100 users δ and 10 10 transceivers 110 first level 120 second level 122 receiving signals 124 code group 130 second level 131 plural Linker 132 Main crosslinker 134a Secondary crosslinker 134b Secondary crosslinker 134k Secondary crosslinker 140 Combiner 142 Simple average processor 144 Total number of processors 145 Decision logic 150 Select Unit 152 Accumulator 154 Controller 156 CFRS Unit 158 Memory 160 Selector

Page 27

Claims (1)

1244277 6. Scope of patent application 1. A method of receiving a frame by receiving a plurality of numbers, each preset number of signals when a test phase cross-linked value is synchronized with a time slot synchronization operation when the test phase frame is synchronized Cross-linking is a coherent method of synchronizing signals based on the coherent connection. The received signal has a plurality of frames including a plurality of time slots. The method includes: When the difference is less than a critical phase difference, the frame synchronization time slot synchronization phase is combined into a coherent combination value; the bit is determined by combining the received signal with a time slot synchronization sequence; when the difference is greater than or equal to the critical phase difference , Combining the signal value with a linear combination of one of the time slot synchronization phases and a combined value; and the combined value to determine the frame boundary of the accepted signal. 2. The method as described in item 1 of the scope of patent application, wherein the linear combination is obtained by the following steps: calculating a phase difference between the current time slot synchronization phase and at least one previous time slot synchronization phase; and obtaining the time The average of the slot phase differences. Contains the continuation of the items mentioned in the French box in the newsletter 1. Each of the 15 levels should be based on the difference. The phase value is the same as that of the flat slot at that time and the first, 4 11 The calculation of the profit of the surrounding slot is continued. Please try the 15 slots in the application. Assessed by the French side of the 11th paragraph Fan Li specifically invited the Chinese as 4 I Page 28 1244277 6. Scope of patent application The difference is the root mean square difference of the synchronization phase of a preset number of time slots. 5. The method as described in item 1 of the patent application range, wherein the critical phase difference is determined according to a range of expected signal-to-noise ratios of the received signal, so that when the signal-to-noise ratio is in a high range, the frame is synchronized The joint value is coherently combined with the time slot synchronization phase, and when the signal-to-noise ratio is in a low range, the frame cross-linking value is coherently combined with the linear combination. 6. The method as described in item 1 of the scope of patent application, wherein the frame border It is obtained by the following steps: accumulating a coherent combination value of a preset number of time slots; and selecting the maximum value of the coherent combination value to determine a frame group corresponding to a code group. 7. The method according to item 1 of the scope of patent application, wherein there are 16 preset cross-linking calculators, and the received signal includes 16 preset cross-linking calculators to obtain 64 of the combined values. One, calculated from a set of 15 symbols for each time slot in the message frame. 8. A wireless device capable of receiving signals synchronously, comprising: a receiver for receiving a signal, the signal having a plurality of frames, wherein each frame has a plurality of time slots; a first stage for Time slot synchronization phase for receiving the received signal; 1244277 VI. Patent application range: A plurality of cross-linking calculators for outputting a plurality of frame synchronization cross-linking values of the received signal; a combiner for testing a signal when a test phase difference is less than a critical phase difference; The frame sync cross-linking value is coherently combined with a time slot sync phase, and when the test phase difference is greater than or equal to the critical phase difference, the frame sync cross-link value is linearly combined with one of the time slot sync phases. Consecutively combining; and a selecting unit for selecting a frame boundary value according to the output of the combiner. 9. The wireless device according to item 8 of the scope of patent application, wherein the selection unit includes a simple average processor to calculate the linear combination in the following steps: Calculate a time slot synchronization phase between at least one previous time slot synchronization phase and at least one previous time slot synchronization phase. The phase difference; and find the average of the phase difference in the time slot. 10. The wireless device as described in item 9 of the scope of patent application, wherein the frame includes 15 consecutive time slots, and the average value obtained by the simple average processor is based on the 15 consecutive time slots. The fourteen time slot synchronization phase differences calculated in the slot are averaged. 11. The wireless device as described in claim 8 in the patent application range, wherein the combiner includes a simple average processor to calculate the test phase difference, the Page 30 1244277 6. Scope of patent application The test phase difference is regarded as the root mean square difference of the synchronization phase of a preset number of time slots. 12. The wireless device according to item 8 of the scope of patent application, wherein the combiner can be used to set the critical phase difference, the critical phase difference is determined according to a range of expected signal-to-noise ratio of the received signal. In the high range, the frame sync cross-linking value is coherently combined with the time slot sync phase, and when the signal-to-noise ratio is in the low range, the frame sync cross-linking value is coherently combined with the linear combination. Combined. 13. The wireless device according to item 8 of the scope of patent application, wherein the selection unit includes a plurality of accumulators for accumulating output values of the combiner according to a preset number of time slots. 14. The wireless device according to item 8 of the scope of patent application, wherein the combiner includes 16 cross-linking calculators, wherein each cross-linking calculator has a preset cross-linking value, and the received signal includes One preset cross-linking operator is used to obtain one of the 64 combined values, which is calculated by a set of 15 symbols in each time slot in the frame. Page 31