TWI243467B - Protective device of two-way electrostatic discharge - Google Patents

Abstract

The invention provides a two-way electrostatic discharge protective device suitable for a bonding pad. A first the second type well area and a second the second type well area are formed separately on a first type semiconductor substrate. A first the first type doped area and a first the second type doped area are formed on the first the second type well area and are coupling to the bonding pad. A third the first type doped area is formed on the first type semiconductor substrate. The triggering network is coupling between the third the first type doped area and the reference level.

Description

1243467 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an electrostatic discharge protection device, and more particularly to an electrostatic discharge protection device of a silicon controlled rectifier with two-way electrostatic discharge protection capability. [Previous Technology] Electrostatic discharge (hereinafter referred to as ESD) is commonly used in the measurement, assembly, installation and use of integrated circuits. It may damage the integrated circuit and indirectly affect the function of the electronic system. Of course, the causes of ESD stress are most commonly based on three models

To explain. (1) Human body model: This is a model defined by US military standard No. 883 method 3〇15.6 (MIL-STD-883, Met hod 3015.6), which refers to the electrostatic contact of the human body. ESD stress caused by the pins of the integrated circuit; (2) machine model ·· means the ESD stress caused by the static electricity of the machine when it contacts the pins of the integrated circuit. The current industry standard EIAJ-IC- 121 method 20 defined measurement method; (3) Electric = model device model (Charge device model): refers to an integrated circuit that has been charged with electricity in the subsequent process, contact conductive material to ground, so the product The body circuit forms an ESD pulse path.

In the current general technology, many methods for solving the problem of electrostatic discharge are provided. U.S. Patent No. US 50 1 2 3 1 7 discloses an electrostatic discharge protection circuit. U.S. Patent No. US54 6 5 1 8 9 discloses another electrostatic discharge circuit. The first picture of Lingying's picture 1 is a cross-sectional view of a conventional antistatic semi-conductor device. The P-type doped region 15, the N-type well region 12 and the P-type substrate 1 1 ′ constitute an emitter, a base, and a collector of a PNP bipolar transistor q 1.

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pole. N-type well area 12, P-type substrate " and N-NPN bipolar transistor Q2's collector pole temple type constitutes a coffee-type hybrid area 15 series is electrically connected to the junction U pole; area 14 is connected with P The type doped region 13 is electrically connected to a potential ~ 18. The above-mentioned p = bipolar transistor and NPN bipolar transistor system constitute a silicon control device. Figure 2 shows the equivalent circuit diagram of the semiconductor device in Figure 丨. In the figure, the resistance Rsub represents the impedance of the p-type substrate 11 and the resistance represents the impedance of the N-type well region 12 ^ When the potential difference between the bonding pad 19 and V ss is a certain degree due to the accumulation of a single electrical charge, the P-type substrate The potential difference caused by the leakage current of 11 will cause the NPN bipolar transistor Q2 to be turned on. When the NPN bipolar electricity is on. When the crystal Q2 is turned on, the current flowing through the resistor Rnw will cause the pNp bipolar electricity transistor Q1 to be turned on. As a result, under the positive feedback effect of the PNP bipolar transistor qi and the npn bipolar transistor Q2, a large amount of ESD current appearing in the bonding pad 9 can be released, thereby protecting the internal components of the semiconductor device Damaged by electrostatic stress. Figure 3 shows the I-v curve of a conventional silicon-controlled rectifier. When the silicon-controlled rectifier is in a closed state before the latch-up occurs, when the applied voltage exceeds the triggering voltage Vt (triggering voltage), the silicon-controlled rectifier will conduct the above-mentioned blocking effect and turn on, so the voltage will drop to a holding voltage Vh 4 ). Then, most of the current will be quickly eliminated by the conducting silicon control rectifier. However, it can be seen from FIG. 3 that the signal of the conventional silicon-controlled rectifier at the bonding pad 19 can only be a positive voltage (greater than 0). Once you need to send two-way

1243467 V. Description of the invention (3) When the signal (can be larger or smaller than 0), it must be able to prevent excessive ESD current of μ negative polarity from damaging the components in IC. In the transmission circuit and protection circuit, there is no such function. In view of this, in order to solve the above problems, the present invention mainly provides a two-way E S D protection circuit, which is not only to prevent the main purpose of ESD impact on I c damage, but also. The impact of the block voltage on ESD shock. Stop negative polarity electricity. Also according to the bi-directional ES provided by the present invention]) The anti-tank includes a trigger network to accelerate the bi-directional ESD protection circuit. A protective device is proposed for bonding 塾 1—type 2 well area ^ f electric discharge prevention semiconductor substrate. The first ~ the second ~ type-doping π at the reference level. The second and first type wells, the '' region, the jade doped region, and the second and second sub-coupling hetero regions are formed in the first type semiconductor and the bonding pad. The first-type doped region and the above reference: ". Trigger network system handle: Yu r reference [Embodiment] / Example: Well regions are formed in the first and second-type doped regions respectively ：： ； ： 第 ： At the reference level. The second first brother is formed between the second and second wells.

II Refer to FIG. 4, which is a cross-section toward the ESD protection device. The ESD protection device includes a double-sided view according to an embodiment of the present invention. According to the embodiment of the present invention—P-type semiconductor substrate 40, N-type well region

1243467 V. Description of the invention (4) 4 = and 42B are formed on the surface of the p-type semiconductor substrate 40. 't'? 44A ^ McCall level Vref-type doped region 46β, and N ^ 42B-type semiconductor substrate 40. Here, the p-type doped region 46β, N ['-type semiconductor substrate 40, and N-type well region 42A constitute a positive mp device. In addition, the P-type doped region 46A and N-type well region 42A are az-type semiconducting bodies. The bottom 40 and the N-well area 4 2B constitute a reverse silicon controlled rectifier. In addition, the trigger network is coupled between the P-type doped region 48 and the reference bit V r e f 'to accelerate the on-time of one of the positively controlled rectifiers. Figure 5A and Figure 5D describe the possible circuits for triggering the network 49 respectively. As shown in the figure, the node “plane is connected to the p-type doped region 48, and the node: ΐΓ to the reference level Vref. As shown in FIG. 5A, the trigger network 49 may be an electrical valley C, or as shown in FIG. The resistor r and the capacitor c are connected in series as shown in Figure 5B. In addition, the trigger network 49 may be composed of _S transistors and s, as shown in the figure. NM0S transistor_ has a coupling to p The source / inverter and the gate between the “type doped region” and the “level” ref are connected, and the electric handle is connected between the armour and the McCaw level Vref. In addition, in the gate of the transistor and the p-type doped region 48 f, it is possible to add a capacitor, as shown in 5d1. 'Further' in the NMMOS transistor MOS shown in Figure 5 (: and Figure 5D) 'The substrate of the semiconductor structure is electrically floating. By setting the trigger network 49, a p-type semiconductor substrate can be provided. 4〇 Internal current-a temporary current path, making the ESD protection device positive

1243467 V. Description of the invention (5) Xiang Shixi control rectifier and reverse silicon control rectifier can be turned on earlier. Therefore, the electrostatic discharge protection device can be turned on early to reduce the chance of the internal circuit being damaged by electrostatic stress. Fig. 6 is an equivalent circuit diagram of the two-way electrostatic discharge protection device shown in Fig. 4 according to the embodiment of the present invention. The resistance Rsub in the figure represents the impedance of the p-type bottom 40, the resistance I "represents the impedance of the N-type well region 42B, and the electric soil ^ indicates the impedance of the N-type well region 42A. When a potential difference occurs between the bonding pad 47 and Vref due to the accumulation of positive charges, the potential difference caused by the leakage current of the P-type substrate 40 will cause the NPN bipolar transistor to conduct. When the NPN bipolar transistor is turned on, the electric current Pn flowing through the resistor will cause the Tian MP bipolar transistor Qpnpl to be turned on. As a result, under the positive feedback effect of the PNP bipolar transistor Qpnpi and the NPN bipolar transistor Qnpni, a large amount of positive ESD currents appearing in the bonding pad 47 can be released. Similarly, when the potential difference between the 塾 47 V ^ e f and the negative electric street is accumulated, the potential difference caused by the leakage current of the P-type substrate 40 will cause the NpN double carrier ^ 2 to conduct. When the NPN bipolar transistor Q_2 is turned on, the current flowing through the 卩 Rnw2 will cause the PNP bipolar to be turned on. Society, in the PNP double-carrier thunder, said n t electric day 脰% np2 V 逋. As a result, ^ m τ ,; N ^ PN ^ ^ ^ ^ stream. Therefore, according to the present invention, a large amount of negative ESD that occurs at 47 ° can protect semiconductors. Only the electrostatic discharge protection device described in the example is damaged by stress. ′, The internal σ 卩 components are not subject to positive and negative static electricity. Figure 7 shows the two-way electrostatic discharge described in the example of I-V Qu Lu Wen Tu Ming of the protective device ... When Shi Xi controls the rectifier before blocking occurs,

Page 9 1243467 V. Description of the invention (6) is in the closed state. When the applied positive voltage exceeds the positive trigger voltage (+ V t) (trigger ing vo 1 t age), the silicon-controlled rectifier will conduct the above-mentioned blocking effect and turn on. Therefore, the above voltage will drop to a holding voltage V h) (holding voltage), and then, most of the positive current will rapidly exceed the negative trigger voltage (-V t) through the conducting Shi Xi control rectifier. The above-mentioned lock effect occurs and is turned on, so the above-mentioned negative voltage will rise to the sustaining voltage (closed), and then most of the negative current will be quickly eliminated by the conducting silicon control, six Vh, and ESD current. According to the above, the two-way electrostatic discharge protection device according to the present invention can not only prevent the ESD impact of the positive polarity voltage from damaging tc ^, but also prevent the ESD of the negative polarity voltage from being formed. Impact. Effectively solve the problems encountered by traditional technology. Σ Criminal root = The disclosed trigger network can shorten the two-way static: the time required for the silicon control rectifier in the electrical protection device to turn on? Electrical Discharge The chance of a circuit being damaged by electrostatic stress. And $ s' significantly reduces the default. Although the present invention is disclosed in the preferred embodiment, the scope of the present invention, anyone familiar with this technology collection; welcome to use it within the spirit and scope of the team, when something can be done = this does not leave The protection scope of the present invention shall be subject to the attached application designation ^ Retouching 1 as defined in the present invention.

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The drawings are briefly explained in order to make the following aspects of the present invention special, and the special attacks and advantages can be more obvious and easy to understand. Below: 车 乂 佳 ^ example, and in conjunction with the accompanying drawings, make a detailed description as shown in the figure Explanation: The first diagram is shown in the value of iridium, and the second diagram is a cross-sectional view of the i-th semiconductor device. The equivalent circuit diagram of the cold body device of the first-your figure. Figure d shows the traditional silicon control. Figure 4 shows that the root is too private ^^ :: for 1 -V curve. Sectional view of protective device. Figures 5A to 5D of the two-way electrostatic discharge described in the χ μ% example are transmitted respectively, +, and α miscellaneous &, gate & ^ Goods 4 field report is triggered according to the original A ΑΙ & 丄Possible circuit structure of the network. Fig. 6 in the example described above is an equivalent circuit diagram showing a discharge protection device according to the present invention. The two-way static electricity not shown in Figure 4 Figure 7 shows the I-V curve of the protective device according to the present invention. … 丨 The description of the two-way electrostatic discharge symbols described above: 1 1, 4 0 ~ P-type substrate 12, 42A, 42B ~ N-type well regions 13, 15, 46A, 46B, 48 ~ P-type doped regions 14, 16, 44A , 44B ~ N-type doped region 1 8 ~ V ss potential 19, 47 ~ junction 塾 4 9 ~ trigger network A, B ~ node

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Claims (1)

1243467 6. Application for patent scope 1. A two-way electrostatic discharge protection device suitable for a bonding pad, comprising: a first type semiconductor substrate; a first and second type well area and a second and second type well area formed on The first type semiconductor substrate; a first first type doped region and a first second type doped region formed in the first and second type well regions and coupled to a reference level; a second A first type doped region and a second second type doped region are formed in the second and second type well regions and are coupled to the bonding pads; a third first type doped region is formed in the first and second type doped regions. A first-type semiconductor base φ bottom; and a trigger network coupled between the third first-type doped region and the reference level. 2. The two-way electrostatic discharge protection device according to item 1 of the scope of the patent application, wherein the first-type doped region, the first-type well region, the first-type semiconductor substrate, and the second-type well region Forms a first silicon-controlled rectifier. 3 · The two-way electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the second first type doped region, the second second type well region, the first type semiconductor substrate, and the first second type well region Forms a second silicon-controlled rectifier. 4. The two-way electrostatic discharge protection device according to item 3 of the scope of patent application, wherein the trigger network is used to shorten the time required for one of the first silicon-controlled rectifier and the second silicon-controlled rectifier to turn on. 0492-9306twf (nl); 91-055; robert.ptd Page 13 1243467 VI. Patent application scope 5. The two-way electrostatic discharge protection device described in item 1 of the patent application scope, wherein the above trigger network includes a serial connection Resistance and capacitance. 6. The two-way electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the trigger network is a capacitor. 7. The two-way electrostatic discharge protection device according to item 1 of the scope of the patent application, wherein the trigger network includes: a MOS transistor having a coupling to the third first type doped region and the reference level, respectively. A source drain and a gate; and a resistor coupled between the gate and the reference level. 8. The two-way electrostatic discharge protection device according to item 7 of the scope of the patent application, wherein the trigger network further includes a capacitor coupled between the gate and the third first type doped region. 9. The two-way electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the first type is a P type. I. The two-way electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the first type is an N type. II. A two-way electrostatic discharge protection device suitable for a bonding pad, comprising: a P-type semiconductor substrate; a first N-type well region and a second N-type well region formed on the aforementioned P-type semiconductor substrate; A P-type doped region and a first N-type doped region are formed in the first N-type well region and are coupled to a reference level; a second P-type doped region and a second N-type doped region Miscellaneous area formed in the above 0492-9306twf (nl); 91-055; robert.ptd Page 14 1243467 6. The scope of the patent application is the second N-type well area, which is coupled to the bonding pad; a third P-type doped area is formed in the above A P-type semiconductor substrate; and a trigger network coupled between the third P-type doped region and the reference level. 12. The two-way electrostatic discharge protection device according to item 11 of the scope of patent application, wherein the first P-type doped region, the first N-type well region, the P-type semiconductor substrate, and the second N-type well region constitute a First silicon controlled rectifier. 13. The two-way electrostatic discharge protection device according to item 11 of the scope of patent application, wherein the second P-type doped region, the second N-type well region, the P-type semiconductor substrate, and the first N-type well region constitute a Second silicon controlled rectifier. 14. The two-way electrostatic discharge protection device according to item 13 of the scope of patent application, wherein the trigger network is used to shorten the time required for one of the first silicon-controlled rectifier and the second silicon-controlled rectifier to be turned on. . 15. The two-way electrostatic discharge protection device according to item 11 of the scope of patent application, wherein the trigger network includes a resistor and a capacitor connected in series. 16. The two-way electrostatic discharge protection device according to item 11 of the scope of patent application, wherein the trigger network is a capacitor. 1 7. The two-way electrostatic discharge protection device according to item 11 of the scope of the patent application, wherein the trigger network includes: a MOS transistor having a third P-type doped region and a reference level, respectively A source electrode and a gate; and a resistor coupled between the gate and the reference level. 1 8. The two-way electrostatic discharge protection device according to item 17 of the scope of the patent application, wherein the trigger network further includes a capacitor coupled to the gate. 0492-9306twf (nl); 91-055; robert.ptd page 15 1243467 6. Scope of patent application and the third p-type doped region mentioned above. I 0492-9306twf (nl); 91-055; robert.ptd page 16