TWI242849B - Solder bump structure formed on integrated circuit package substrate and method for fabricating the same - Google Patents

Abstract

A solder bump structure formed on an integrated circuit package substrate and a method for fabricating the same are proposed. A first conductive film is formed on an insulating layer of the substrate, and a first resist layer is formed thereon with a plurality of openings to expose the first conductive film. A patterned circuit layer including a plurality of pads is formed within the openings by an electroplating method, and a second resist layer is formed thereon without covering the pads. After a first solder material and a metal protective layer are in turn formed on the pads by an electroplating method, the second resist layer, first resist layer and the first conductive film underneath the first resist layer are removed. An insulating protective layer is formed over the surface of the substrate with openings to expose the pads, and a second conductive film is formed thereon. A third resist layer is formed on the second conductive film with openings to expose the second conductive film on the pads, and a second solder material is formed within the openings of the third resist layer by an electroplating method. After the third resist layer and the second conductive film underneath the third resist layer are removed, a solder bump is formed on the pad by a reflow-soldering process.

Description

1242849 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a structure and a manufacturing method thereof, which refers to an integrated circuit packaging substrate = circuit board, and particularly to a structure and a manufacturing method of a pre-solder bump. The turtle connection pad uses electroplating method | [prior art], clothing method. Since IBM introduced package technology in 1960, compared to the introduction of flip-chip packaging (FliP chip I technology is characterized by semiconductor wafer (Wlre bond) technology, flip-chip tin bumps instead of ordinary gold wires The electrical connection between the two boards can increase the packaging density to reduce the sealing through welding. The advantage of the flip-chip technology is that it does not require the use of a long full length: the size of the chip. I is in the current flip chip technology; Mo: can improve the electrical performance of the South. Electrically configured on the electrical surface] ft conductive bulk circuit (ic) wafer white (| also formed on the organic circuit board Phase pads), and two touches between the body chip and the circuit board, so that the semiconductor I is placed on the circuit board, so that 2 is arranged with the electrical contact surface facing down, and the electrical properties between the circuit boards j into the block or to provide the chip with an adhesive material, please refer to the 16th figure, the connection is shown in the figure. The figure shows a number of metal bumps day after day components. As above I, and several made of solder Electrode pads on the chip 13 u Contact pads on the circuit board 16 5_ ^ .. 1 4 is formed under the recording temperature of organic I. With 2 = f, tin bumps 1 are pre-edited. 4 metal bumps u can be shaped: 2 :: ~ tin bumps "Back to Xue Zhi Corresponding to the ~ solder joint 17. The solder bump fresh solder joint

] 7357 全 想 .ptd Page 7 1242849 V. Description of the invention (2) '一 ^ ~~ ^-(Solder bump j〇int), you can enter-+ the gap between the boards is filled with primer material 18 , / Said the film to [the thermal expansion difference between the electrical circuit board i6 and reduce the solder connection. 13 and FIG. 2 show a conventional organic circuit board 2 which is in contact with ㈣21 on the surface, and is typically made of metal; ^ 24, Fragmentation: An organic insulating protective layer 24 is formed on the surface of the circuit board 2 such as the green lacquer temple, which is formed on the circuit layer and provides the edge characteristics. Among them, the insulating protective layer 24 is formed with: electricity; the openings are exposed Out the contact pads 2 丨 on the surface of the circuit board. Hard numbers ^ contact solder pads 21 are formed with pre-solder bumps 25 for subsequent formation of flip-chips ^ contact pads are used to deposit solder. The steel industry generally uses steel plates, which can be referred to as stencil printing. Today ’s communications, networking and computer growth can be reduced. Packages such as IC area array (BGA) and flip-chip ChiP size eh ipm0 (ju 1 e) and other packages often play a higher-speed computing pad size with microprocessors and chips. When the pads are currently used, the industry mainly uses templates. Printing technology) to form solder bumps on the material of the circuit board. Furthermore, it is the plate of the template, so the stencil printing technology. However, in actual operation, due to the large size and high density and multi-pin characteristics of various portable (P 0 rtab 1 e) products, Flip chip, chip size package (csp, package) and multi-chip modules (MCM, MuUi) have gradually become the mainstream in the packaging market, and they are matched with high-performance chips such as graphics chips to improve performance. However, these structures are bound to reduce the line width and

1242849 V. Description of the invention (3) When the P series is shrinking, the size of the contact pads of the shielded part is further reduced, and it is also caused by the sound of the insulation, which makes the stencil printing technology | Die is not easy | due to the technical bottleneck of the hole 1 process of the template. Moreover, the size of the template of huihui material | is correct. Because the number of solder materials | the more number'remains in the template | the front used in the next printing, therefore'usually the problem of cleaning and cleaning of the template is not always the same ^ 1. In addition, there may be electrical | pre-soldering, also due to the Made of solder, the reliability of the formed pre-solder | just tested. That is, in the opening of the protective layer, Jin Bu's, therefore, in the subsequent effective separation from the circuit board or the electrical connection is not generated, there is still tin material inside the wall of the sticky hole, otherwise the process Plating method material shape bonding force 'due to the complete bonding of the solder material during the drawing process

] 7357 全 恋 .ptd Page 9 The presence of the insulating protective layer on the circuit board will cover the area 'causing the exposed protective insulating layer to be soldered to form the space occupied by the protective layer of the solder bump. The size of the template openings in the height shadow will inevitably decrease accordingly, which will not cause the manufacturing cost of the template to increase, and it is more distant and difficult to pass the solder material, resulting in accuracy. In addition to the stencil printing technology, the number of stencil printing must be confirmed. And cleanliness (V is C 0 Sity), and when printing is followed by more solder material, the quantity and shape are inconsistent with the design specifications. After using a certain number of printing times, the shape and size of the solder material must be easily generated. Inconvenience and reduced reliability. The contact area on the pad is formed in the opening area of the insulating protection layer. The contact area on the pad has a limited strength. The solder material cannot be pre-soldered. The solder material is only formed when the contact between the insulating material and the pad is only the opening. The block will not be able to provide that wafer force and even cause problems between the wafer and the circuit board. || p_ 1242849 ---__ V. Description of the invention (4) '------ ^ Therefore' In view of the above problems, poor joints, strong sound, and ϋ can avoid the formation of solder slaves, etc., and effectively exist in the- Circuit ;;: The yield rate of the brush technology process is too low, and it has become the current desire to form a pre-solder on the ground. [Summary of the Invention] ^ Fruit 砀. In view of the shortcomings of the conventional technology described above, the main purpose of the invention of soldering of integrated circuit package substrates is to use electric money to seal the beautiful block structure in integrated circuits and its manufacturing method to form a pre-soldering material. 1 The electrical connection pad on the surface of the soil plate is another object of the present invention. # The tin bump structure and the manufacturing method thereof, a solder material is formed on the soldering surface of the two or two integrated circuit sealing substrates. The contact area of the surface material on the whole is beneficial to the bonding strength of the j 2 pad and the deposited solder material according to another object of the present invention. The structure of the tin bump and its manufacturing method are: # # The solder material is formed on the substrate of the compensation circuit package substrate. Otherwise, the entire upper surface layer of the electrical connection pad effectively clamps the solder material < Insulation protection on the substrate surface is another task of the present invention to increase the push-pull force of the solder kick material. Tin bump structure and its manufacturing method, 彳 Γ, 彳 ', the solder protection layer of the integrated circuit package substrate exists, which is exposed ^ to avoid the subsequent deposition of zinc due to the insulation on the surface of the electrical board: ;: The electrical connection of the edge protection layer is reduced in size. The purpose of the present invention is:-the problem of alignment. 〕 Provide an integrated solder bump structure and its manufacturing method, and increase the size and spacing of the solder pads on the ^ i package substrate, so as to avoid the electrical connection in the template printing technology. The opening must change accordingly

17357 Quan 懋 .ptd Page 10 1242849 V. Description of the invention (5) Small, which makes it difficult to open the mold and increase the manufacturing cost of the template, and it is difficult to let the solder material pass through because the template has a small hole spacing. , Resulting in bottlenecks in process technology. Another object of the present invention is to provide a solder bump structure of a integrated circuit package substrate and a method for manufacturing the same, avoiding the need to wipe and clean the stencil after using it for a period of time in the conventional stencil printing technology. The more solder material on the stencil hole wall, which affects the amount and size of solder material to be printed next time, causing inconvenience and reliability of the process. In order to achieve the above disclosure and other objectives, the present invention discloses a method for manufacturing a solder bump structure of an integrated circuit package substrate. The main steps include: providing an insulating layer, which can be a substrate with a single-layer or multi-layer circuit. A surface insulating layer, and a first conductive film is formed on the insulating layer; a patterned first resistance layer is formed on the first conductive film, so that the first conductive film is exposed outside the plurality of openings of the first resistance layer ; Performing a plating process to form a patterned circuit layer in the first resist layer Jingkou, the patterned circuit layer includes a plurality of electrical connection pads; forming a second on the remaining patterned circuit layers other than the electrical connection pad A resistance layer, so that the electrical connection pad is exposed to the second resistance layer; a plating process is performed to form a first solder layer on the electrical connection pad; the second resistance layer, the first resistance layer, and the cover are removed A first conductive film under the first resistive layer; an insulating protective layer is formed on the surface of the substrate, and the insulating protective layer has an electrical connection pad exposed outside the opening, and a second is formed on the insulating protective layer and its opening surface A conductive film; a third resist layer is formed on the second conductive film, and the third resist layer has a second conductive film exposed on the electrical connection pad outside the opening; a plating process is used to open the third resist layer The electrical connection

] 7357 全懋 .ptd Page 1] 1242849 V. Description of the invention (6) The second guide of the pad π L ... 丄, μ sound and the bearing of the bean 成 into the second solder layer; and remove the first P Xihan, the first Emperor He Er of the dead corpse and make the electrical connection pad: 2: 2 4: After that, a can be reflowed to block. The first brother of the first one and the second solder layer form a solder bump that is the first solder formed by the thinning power deposit. ^ Μ μ is contaminated during the process. The metal protective film is plated on the first solder layer with love = I, and a solder layer of f 2 ^ is completed.覆 The chip-on-chip of this electrical continuous pad has a tin package substrate, which can be applied to 1 t & Japanese-style + conductor chip bonding, and the ancient and eighth electrode electrode chip bonding, flip-chip soldering Board error: flip-chip semi-crystalline packaging components and other semiconductor device board-to-board soldering, as well as the overlay reference, the above-mentioned solder bumps on the substrate, the invention also revealed-a kind of integrated circuit seal Completely covered the product i ,: structure, mainly including: a first fresh material layer, ϊ insulation protection, system ::, 2 upper surface of the electrical connection pads of the package substrate; two have openings outside the package ^; package substrate Surface, and the insulation layer 1 aw leads to the thunderous layer 4 and the second solder layer 2-the first solder layer in the center portion of the pad; on the solder layer. Α 中 兮 # 系 is formed in the opening of the insulation protection layer This form a solder bump. The second solder layer can be re-soldered with the first solder layer. Compared with the conventional method, an insulating protection layer is formed to cover the surface of the circuit packaging substrate with a board printing technology to the insulation ^丨 After connecting around the pad, use the table again :: Guided by 0 tin material :::: The size and pitch of the electrical connection pads are reduced, and the opening is reduced by __ with 通 =

] 7357 全懋 .Pt (j 1242849 V. Description of the invention (?) Causes the template to open mold's deposition, the template is removed, the manufacturing cost is raised, the solder material is not easy to pass through, and the reliability is reduced; etc. The technical inconvenience and structure of the process are shown in Figure 2. In the present invention, it is used to make a patterned circuit junction image to cover :: a conductive film with a second resistance layer for the shadow structure. For areas other than the connection pads (if the patterned circuit is defined and the outer part is not covered with the second resistive layer), the electrical connection pads with pre-solder material are formed on the electrical connection! With the same surface +, the upper surface is electroplated to form an electrical connection pad when the electrical connection pad is formed ::::: bucket I 'to provide subsequent formation of a solder bump on top of the solder layer to provide greater contact. Then, the first material is destroyed in the first; the protective film is used to avoid contamination in the subsequent processes and to have insulation protection. The husband's editor, the circuit structure is shaped to protect the environment from pollution; the package substrate is free of The central area of the external connection pad;:; The protective layer has an electric dipper exposed outside the opening. The shape is formed on the electrical connection pad for depositing a second solder I in the opening of the insulating protection layer. V: 臈 The first solder layer and the second solder layer are re-soldered. Electrically connected to the upper hill: the body is formed with fresh tin bumps, and the bottom of this solder bump # /, Hyun-刖 at the first solder layer formed) has the same as the electrical connection pad Contact area, therefore, compared with the conventional structure, the solder bumps generated only on the insulating protective layer '/ part of the electrical connection pad area have a more: = nature, in addition, the middle portion of the solder bumps of the present invention is Controlled by the insulation J joint (that is, the surface layer layer portion previously formed in the opening of the insulation protection layer) '俾 When the solder bump is subsequently bonded to the electronic device ^ =

Page 13] 7357 全懋 .ptd 1242849 V. Description of the invention (8)

For a better push-pull force [Embodiment] and effective electrical connection to the electronic device ^ The following describes the embodiment of the present invention by specific specific examples. Other advantages and effects. The present invention can also be implemented or applied by other specific embodiments. The details in this specification can be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Ding Ge Please refer to FIGS. 3A to 3N for a detailed description of a preferred embodiment of the method for manufacturing the fresh tin bump structure of the integrated circuit mounting substrate of the present invention. Referring to FIG. 3A, first, a substrate having a single-layer or multi-layer circuit is provided and a first conductive film 31 is formed on a dielectric insulating layer 30 on the surface of the substrate; the insulating layer 30 may be, for example, epoxy resin ( Ep〇xy resin), polyethylene, Polyimide, Cyanate Ester, Glass fiber, Bismaleimide Triazine (μ, Bismaleimide Triazine) or mixed Made of materials such as epoxy resin and glass fiber (FR5), this first conductive film 31 is mainly used as the current conduction required for the later-described electroplated metal layer (including the patterned circuit structure and the solder layer on the electrical connection pad). path. The first conductive film 3 丨 may be formed of a metal, an alloy, or a stack of several metal layers, and may be formed of a metal selected from the group consisting of copper, tin, nickel, chromium, titanium, and a copper-chromium alloy. The conductive film 31 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless ore, or chemical deposition, such as g PU ^ ering, evaporation, arc vapor, and the like. Deposition

1242849 V. Description of the invention (9) Deposition), ion beam sputtering, laser ablation deposition, plasma-assisted chemical vapor deposition or electroless plating. However, according to practical experience, the conductive film 31 is preferably composed of electroless copper particles. Referring to FIG. 3B, the first conductive film 3 is covered with a first resist layer 32 by printing, spin coating, or lamination. The first resist layer 32 may be, for example, a dry film or a liquid photoresist. Photoresist, etc., and the second resist layer 32 can be formed with a plurality of openings 32 through patterning processes such as exposure and development, or by laser technology. The opening 3 2 0 is formed so as to expose a portion of the first conductive film 3 where a patterned circuit structure is to be formed. Referring to FIG. 3 C, a plating process is performed to form a pattern in the first resist opening 3 2 0. The patterned circuit layer 3 3 has a plurality of electrical connection pads 3 3 0. Of course, it is also possible to form only an electrical connection pad portion only on the insulating layer on the surface of the substrate, and no conductive line is formed. Please refer to FIG. 3D, and form a second layer on the electrical circuit layer 33. The material of the second resistive layer 34 is exposed outside the resistive layer, and the second resistive layer 32 is exposed. Of course, if there are electrical connection pads without conductive circuit layers. Figure 3 4 except for the electrical connection pad 3 3 0, so that the material of the electrical connection pad 3 3 0 resistance layer 3 4 can be equivalent to the formation of only components on the substrate surface insulation layer, and it is not necessary to cover it. For the second resistance, please refer to the process of electroplating (Eiectropiating) through the limbs of the first tomb ^ 1 and the electrical connection pad 3 3 0

Π357 Quan 懋 .ptd Page 15 1242849 V. Description of the Invention (1) The first solder layer 3 having the same area size as the electric connection pad 3 3 0 is directly formed on the electric connection pad 3 3 0. 5 1. The material of the first solder layer 3 51 may be one selected from the group consisting of tin, tin, silver, copper, silver, tin, zinc, tin, tin, magnesium, indium, tellurium, and gallium. Please refer to FIG. 3F. In addition, in order to protect the first solder layer 3 5 1 formed first from being contaminated or damaged in the subsequent process environment, another one can be continuously formed by electroplating on the first solder layer 3 5 1 The metal protective film 3 5 2 covers the first solder layer. The metal protective film 3 5 2 may be made of, for example, gold (Au). Please refer to FIG. 3G, and then remove the second resistive layer 3 4 and the first resistive layer 32 °. Please refer to FIG. 3, which can be removed by etching technology. Covered first conductive film 31. Please refer to FIG. 3I. Then, the surface of the package substrate is covered with an insulation protection layer 36. The insulation protection layer may be a solder resist layer, such as a green paint, to protect the package substrate from external environmental pollution. In addition, the insulation protection layer 3 6 can be formed with a plurality of openings 3 6 0 through processes such as exposure and development or directly using laser technology, so that the completed surface is plated with a first solder layer 3 5 1 The electrical connection pad 3 3 with the metal protective film 3 5 2 can be exposed in the opening 3 6 0 of the insulating protective layer. Please refer to Figure 3J. Then, it is formed by physical vapor deposition, chemical vapor deposition, electroless plating or chemical deposition, such as sputtering, vapor deposition, arc vapor deposition, ion beam sputtering, laser fusion deposition And plasma-assisted chemical vapor deposition or electroless plating on the insulating protective layer 36 and its opening

] 7357 全懋 .ptd Page 16 1242849 " ----___________ V. Description of the invention (11) = 6 0 The first conductive film 37 is formed on the surface, and the material of the second conductive film π can be the same as the first A conductive film. Please refer to FIG. 3K, and then the second conductive film 37 is covered with a third resist layer 38 by printing, spin coating or laminating, and patterned by exposure (ExpoSure) and development (Development). In the process, the third resist layer 38 is formed with a plurality of openings 3 8 0 so as to expose the second conductive film 37 having electrical conductivity g. Λ = Refer to FIG. 3L, and then use the electroplating process to pass the current conduction path of the second conductive film 3, and open the solder layer 3 5 3 in the third resist layer, and the material of the second solder layer is γ ^ ~ ^ „The tenth-increasing material can be equivalent to the first solder layer. Please refer to FIG. 3M, and repeat the R-R into Xi Di-Road f, layer 38, and a conductive film 37 which is covered by it. Please refer to FIG. 3N, and then form a solder bump on the 33 ° at the temperature of the first solder which is sufficient to make the electroplating in Qu Zhi's bath-protection%. The block Yl4 " tin material is re-soldered as shown in Figures 3M and 3N, that is, the solder bump structure of the display board, which is restored ;: The integrated circuit packaging base layer 351 of this matter is completely covered The semi-conducting ghost structure includes a first-recorded upper surface, and the first :: layer '= ... sexual connection 533 3 5 2; —insulating protection layer 3 6; The film insulation protection layer 36 has an opening exposed on the surface of the sealing substrate, and the second solder layer 353 is formed into an electrical connection. The center of 330 is formed in the opening of the insulating protection layer

ΙΙ111] 7357 懋 .ptd Page 17 pi

IL

Claims (1)

1242849 / ^ 7 / r __ Case No. 92132114 @ 年 〇 月 favorite_ 6. Application for Patent Scope 1. A method for manufacturing a solder bump structure of an integrated circuit package substrate, comprising: forming a first layer on a substrate surface insulation layer A conductive film; forming a first resistive layer on the first conductive film, and the first resistive layer having a plurality of openings to expose the first conductive film; performing a plating process to form a pattern in the first resistive layer opening A circuit layer, the patterned circuit layer including a plurality of electrical connection pads; forming a second resistance layer on the patterned circuit layer, and exposing the electrical connection pad to the second resistance layer; and performing a plating process to the Forming a first solder layer on the electrical connection pad; removing the second resistive layer, the first resistive layer, and a first conductive film covering the first resistive layer; forming an insulating protective layer on the surface of the substrate, and the insulating protective layer The layer has a central portion of the electrical connection pad exposed outside the opening, and a second conductive film is formed on the insulating protection layer and the opening surface thereof; a third resistance layer is formed on the second conductive film, and the third resistance layer has an opening It is exposed outside the electrical connection pad of the second conductive film; electroplating process to form a second layer of solder resist layer in the third opening; and removing the second conductive film and the third layer is covered by the barrier. 2. The method for manufacturing a solder bump structure of an integrated circuit package substrate according to item 1 of the scope of the patent application, wherein after forming a first solder layer on the electrical connection pad, a metal protective film can be formed on the first solder layer. ,to avoid ] 7357 (Revised version) .ptc Page 22 1242849 /? R _ case number 92132114 4 years,) month LS said amendment _ 6, scope of patent application In the subsequent process environment, the first solder layer is polluted and damaged by the outside world. 3. The method for manufacturing a solder bump structure of an integrated circuit package substrate according to item 1 or 2 of the scope of patent application, further comprising performing a reflow process to form a first solder layer and a second solder layer on the electrical connection pad to form a solder bump. Piece. 4. For example, the method for manufacturing a solder bump structure of an integrated circuit package substrate according to item 1 of the scope of patent application, wherein the conductive film is mainly used as a current conduction path required for the metal layer described later. 5. For the method for manufacturing a solder bump structure of an integrated circuit package substrate according to item 1 of the scope of patent application, the conductive film may be selected from the group consisting of copper, tin, nickel, chromium, titanium, and copper-chromium alloy. One. 6. For example, the method for manufacturing a solder bump structure of a integrated circuit package substrate according to item 1 of the patent scope, wherein the conductive film can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, and chemical One of the forms of deposition is formed. 7. For the manufacturing method of the solder bump structure of the integrated circuit package substrate according to item 1 of the patent application scope, wherein the resist layer is one of a dry film and a liquid photoresist. 8. For the manufacturing method of the solder bump structure of the integrated circuit package substrate according to item 1 of the patent application scope, wherein the insulation protection layer is a solder resist layer. 9. A method for manufacturing a solder bump structure of a package circuit package substrate, comprising: forming a first conductive film on an insulating layer on a substrate surface; forming a first resistance layer on the first conductive film, and the first resistance layer The first conductive film is exposed outside a plurality of openings; ] 7357 (Revised version). P * tc Page 23 1242849 ^ n ^ _Case No. 92132114 / month / month _ Amendment VI. Patent application for plating process to form multiple electrical connections in the first barrier layer opening Pad 5 and forming a first solder layer on the electrical connection pad to remove the first resistive layer and a first conductive film covering the first resistive layer to form an insulating protective layer on the surface of the substrate and the insulating protective layer has an opening The central portion 5 of the electrical connection pad is exposed outside and a second conductive film is formed on the insulating protection layer and the open V surface thereof. A second resistive layer is formed on the second conductive film, and the second resistive layer has an exposed outside. The second conductive film 9 on the electrical connection pad is subjected to an electroplating process to form a second solder layer 5 in the second resist layer opening and to remove the first resist layer and the second conductive film covered thereon 0 1 0 · If you ask for item 9 of the patent scope Manufacturing method of solder bump structure of integrated circuit package substrate 5 Wherein, after forming a first solder layer on the electrical connection pad, a metal protective film 9 can be formed on the first solder layer to avoid the first in the subsequent process environment. The solder layer is polluted and damaged by the outside world. 1 1 · As claimed in the patent / rhr, the method of solder bump structure of the integrated circuit package substrate of Zhangyewei item 9 or 10 includes a reflow process to make the first solder layer and the first solder layer on the electrical connection pad. Two solder layers form solder bumps. 0 2. The method of manufacturing solder bump structures for integrated circuit package substrates as described in item 9 of the patent application. 1 of which 5 This conductive film is mainly used as the current conduction required for the electric metal layer described later. path. 1 3.Please refer to the solder bump structure method of the integrated circuit package substrate of 々 / Γ around item 9 of which. 5 The conductive film can be made of white copper tin λ nickel, chromium, ] 7357 (revised version) .ptc page 24 1242849 case number 92132114 Amendment 6. Scope of patent application One of the groups consisting of titanium and copper-chromium alloys. 14. According to the method for manufacturing a solder bump structure of an integrated circuit package substrate according to item 9 of the scope of patent application, wherein the conductive film can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, and One of the methods of chemical deposition. 15. The method for manufacturing a solder bump structure of an integrated circuit package substrate according to item 9 of the scope of patent application, wherein the resist layer is one of a dry film and a liquid photoresist. 16. The manufacturing method of the solder bump structure of the integrated circuit package substrate according to item 9 of the scope of patent application, wherein the insulation protection layer is a solder resist layer. 1 7. —A solder bump structure of an integrated circuit package substrate includes: a first solder layer that completely covers the upper surface of the electrical connection pad of the integrated circuit package substrate; an insulating protective layer formed on A surface of the substrate, and the insulation protection layer has a first fresh material layer outside the center of the electrical connection pad outside the opening; and a second solder layer formed on the first solder layer and filled in the insulation protection layer In the opening. 18. According to the solder bump structure of the integrated circuit package substrate of item 17 in the scope of patent application, a metal protective film may be formed on the first solder layer to avoid the first solder layer in a subsequent process environment. Pollution and destruction by the outside world. 19. The solder bump structure of the integrated circuit package substrate according to item 17 or 18 of the scope of patent application, wherein a metal can be formed on the first solder layer. ] 7357 (Revised version) .ptc Page 25, 1242849 A h, (_ Case No. 92132114 J 丨 > Revision _ 6. Apply for a patent protection film to prevent the first solder layer from being affected by the outside world in the subsequent process environment Pollution and damage. 20. For example, the solder bump structure of the integrated circuit package substrate of item 17 in the scope of patent application, wherein the insulation protection layer is a solder resist layer. 2 1. The structure of the solder bump includes: a lower end portion of the solder bump, the area of which is the same as the size of the electrical connection pad on the surface of the substrate to which it is connected; a middle portion of the solder bump, which is opposite to the lower end portion of the solder bump; An indented structure is formed, which is covered by the insulating protective layer formed on the surface of the substrate to the lower end of the solder bump on the electrical connection pad, so that the middle portion of the solder bump is the insulating protective layer. Embedded; and the upper end of a solder bump, the insulation protection layer is exposed to the outside, which forms a convex structure with respect to the middle portion of the solder bump. 2 2. As the product of the 21st scope of the patent application Electric circuit The solder bump structure of the mounting substrate, wherein the lower end portion of the solder bump of the solder bump is composed of a first solder layer, and its area is the same as the size of the electrical connection pad on the surface of the substrate to which it is connected. By increasing the contact area between the electrical connection pad and the solder material, the strength of the solder bump bonding force is increased. 2 3. As in the solder bump structure of the integrated circuit package substrate of the patent application No. 21, wherein the solder bump The middle portion of the solder bump of the block is formed by a portion of a second solder layer formed in the opening of the insulating protection layer on the surface of the substrate. The solder bump is made by extending the insulating protection layer to cover the electrical connection pad of the portion. Formed in the middle of the solder bump ] 7357 (Revised version) .ptc Page 26 1242849 Case No. 92132114 Amended 6. The scope of the patent application is relatively concave, so that the middle part of the solder bump of the tin solder bump is embedded in the insulation protection layer to improve Push and pull force of solder bumps. 24. The solder bump structure of the integrated circuit package substrate according to item 21 of the patent application scope, wherein the upper end of the solder bump of the solder bump is formed by a second solder layer on the exposed exposed protective layer. It is partially formed and has a convex portion for the semiconductor package substrate to be connected and electrically connected to the electronic device. ] 7357 (revised version) .ptc page 27 1242849) 1351 6/6