TWI242681B - Pixel structure of a liquid crystal display - Google Patents
Pixel structure of a liquid crystal display Download PDFInfo
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12426811242681
五、發明說明(1) 發明所屬之技術領铋 本發明是有關於一種晝素結構(pixel structure), 且特別是關於一種液晶顯示裝置之'晝素結構及其修補方 法,其中具有儲存電容(storage capacitor)。 先前技術 P进者问科技之發展’視訊產品’特別是數位化之視气 或影像裝置已經成為在一般日常生活中所常見的產品。這 些數位化之視訊或影像裝置中,顯示器是一個重要元件, 以顯示相關資訊。使用者可由顯示器讀取資訊,或進而控 制裝置的運作。而且,為了配合現代生活模式,視訊或^ 像裝置之體積日漸趨於薄輕。傳統的陰極層射線管 (cathode ray tube,簡稱CRT)雖然仍有其優點,但是其 需佔用大體積且耗電。因此,配合光電技術與半導體製、生 技術’面板式的顯示器已被發展出成為目前常見之顯示$ 產品如液晶顯示器。 " 旦-由於液晶顯示器具有低電壓操作、無輻射線散射、重 篁輕以及體積小等傳統陰極射線管所製造之顯示器無法達 到的優點,因此成為近年來顯示器研究的主要課題,更被 =十一世紀顯示器的主流。目前液晶顯示器的發展, ^ 一矩陣式(active matrix)液晶顯示器最被看好成為 辦A _主,的產品,這是由於當掃描配線(scan line)數 又:了,若各個畫素皆需由外部來驅動時,每一個畫素所 ===的驅動時間(duty)將會很少,結果將使顯示器的顯 不特性變差。V. Description of the invention (1) The technical field to which the invention belongs is bismuth. The present invention relates to a pixel structure, and more particularly to a pixel structure of a liquid crystal display device and a method for repairing the pixel structure. storage capacitor). Prior technology P-entrants asked the development of technology 'video products', especially digital video or imaging devices have become common products in daily life. In these digital video or imaging devices, the display is an important component to display related information. The user can read the information from the display or control the operation of the device. Moreover, in order to cope with modern living modes, the size of video or video devices is becoming thinner and lighter. Although the traditional cathode ray tube (CRT) still has its advantages, it needs to occupy a large volume and consume power. Therefore, panel-type displays that are compatible with optoelectronic technology and semiconductor manufacturing and production technology have been developed into common display products such as liquid crystal displays. " Once-due to the low-voltage operation, non-radiation scattering, light weight, and small size of traditional cathode ray tubes can not achieve the advantages of traditional cathode-ray tube displays, it has become the main topic of display research in recent years, has been = The mainstream of eleventh century displays. At present, the development of liquid crystal displays, ^ a matrix (active matrix) liquid crystal display is most optimistic to become the product of A _ main, this is because when the number of scan lines (scan line) again: When driven externally, the driving time (= ty) of each pixel will be very small, and as a result, the display characteristics of the display will be deteriorated.
1242681 五、發明說明(2) --------- 主動矩陣式液晶顯示器直接在晝素電極(pi xel electrode)處形成電晶體(transist〇r)等主動元件 (acti ye element),來控制液晶顯示器的資料寫入。其中 又以薄膜電晶體液晶顯示器被視為現今液晶顯示器的主流 之一。當晝素電極處於選擇之狀態下(即打開” 〇N,,的狀態 下),吼號將寫入此晝素上;當畫素電極處於非選擇的狀 態下(即關閉"OFF”的狀態下),其中之儲存電容可維持 驅動液晶之電位。因此,液晶呈現了靜態(static)的特 性。而習知具有儲存電容之薄膜電晶體液晶顯示器的晝素 結構如第1圖所示。 第1圖係習知一種具有儲存電容之晝素結構的上視簡 圖。請參照第1圖,習知之晝素結構包括第一金屬層 (Metal 1)102、介電層 119、通道層(channel layer)104、第二金屬層(Metal 2)106、保護層(未繪示) 以及晝素電極(pixel electr〇de)110。第一金屬層102係 配置在一基板(未繪示)上,且第一金屬層102包括一掃描 配線(scan line)114、一閘極116以及一共用配線(common line )118。而介電層119覆蓋第一金屬層102,通道層104 則配置於閘極11 6上方之介電層11 9上。第二金屬層1 0 6則 配置在基板上,且第二金屬層106包括一源極120a、一没 極120b、一資料配線(data 1 ine)l 22以及一電容電極 124,其中源極120a與汲極120b配置於閘極116上方之通道 層104兩側,且電容電極124與第一金屬層102之共用配線 11 8互相疊置成一儲存電容,而閘極11 6、通道層1 0 4、源1242681 V. Description of the invention (2) --------- Active matrix liquid crystal display directly forms acti ye elements such as transistor (transistor) at the pi xel electrode, To control the writing of data on the LCD. Among them, the thin film transistor liquid crystal display is regarded as one of the mainstream of the current liquid crystal display. When the day electrode is in the selected state (that is, in the state of ON), the roar will be written on this day element; when the pixel electrode is in the non-selected state (that is, closed " OFF " State), where the storage capacitor can maintain the potential driving the liquid crystal. Therefore, the liquid crystal exhibits a static characteristic. The structure of a conventional thin-film transistor liquid crystal display with a storage capacitor is shown in Fig. 1. Fig. 1 is a schematic top view of a conventional daylight structure having a storage capacitor. Please refer to FIG. 1. The conventional daylight structure includes a first metal layer 102, a dielectric layer 119, a channel layer 104, a second metal layer 106, and a protective layer (not shown). (Shown) and a pixel electrode 110. The first metal layer 102 is disposed on a substrate (not shown), and the first metal layer 102 includes a scan line 114, a gate 116, and a common line 118. The dielectric layer 119 covers the first metal layer 102, and the channel layer 104 is disposed on the dielectric layer 119 above the gate electrode 116. The second metal layer 106 is disposed on the substrate, and the second metal layer 106 includes a source 120a, an electrode 120b, a data wiring 122, and a capacitor electrode 124, where the source electrode 120a is The drain electrode 120b is disposed on both sides of the channel layer 104 above the gate 116, and the capacitor electrode 124 and the common wiring 11 of the first metal layer 102 are stacked on each other to form a storage capacitor, and the gate electrode 116 and the channel layer 104 ,source
11949twf.ptd 第7頁 1242681 五、發明說明(3)""""' ' " "~ 極120a以及汲極1201)係組成一薄膜電晶體126。再者,保 遵層係配置於第一金屬層1〇2、介電層119以及第二金屬層 106上,其中保護層具有兩開口128與13〇,分別暴露出電 ,電極124和汲極120b。晝素電極1 1〇係位於保護層上,且 藉由開口 1 2 8與電容電極1 2 4電性連接以及開口 1 3 〇與汲極 I 2 0 b電性連接。 此外,在前述晝素結構上配置一彩色濾光片基板,並 在兩基板間置入液晶,則可完成一薄膜電晶體液晶顯示 器。 由於上述薄膜電晶體液晶顯示器中的晝素内的液晶之 穿透率(transmittance)需依賴前述之晝素電極11〇以及彩 色渡光基板上的透明電極間的夾差電壓所決定。因此,當 儲存電容處(即電容電極124與共用配線118之間)的介電層 II 9發生破裂140時,將造成薄膜電晶體將^⑽訊號傳至書 素電極11 0處(即發生短路),使得晝素電極丨丨〇以及彩色濾 光基板上的透明電極間的夾差電壓變成〇,因而導致在扭 轉向列型(twisted nematic,TN)結構的晝素成為恆定之 党點(normally white)、在多領域垂直對準型 (multi - domain vertically alignment,MVA)結構的書素 成為恒定之暗點(normally black)。前述現象隨著薄膜電 晶體液晶顯示器商品特性愈來愈在乎亮/暗點規袼的此 時’將造成固定的產量減少(yield loss)。 發明内容 因此,本發明之目的之一是提供一種液晶顯示裝置,11949twf.ptd Page 7 1242681 V. Description of the Invention (3) " " " " '' " ~ The electrode 120a and the drain electrode 1201) form a thin film transistor 126. Furthermore, the compliance layer is disposed on the first metal layer 102, the dielectric layer 119, and the second metal layer 106. The protective layer has two openings 128 and 130, which respectively expose electricity, the electrode 124 and the drain electrode. 120b. The day element electrode 1 10 is located on the protective layer and is electrically connected to the capacitor electrode 1 2 4 through the opening 1 2 8 and electrically connected to the drain electrode I 2 0 b through the opening 1 30. In addition, a color filter substrate is arranged on the aforementioned daylight structure, and a liquid crystal is placed between the two substrates to complete a thin film transistor liquid crystal display. The transmissivity of the liquid crystal in the daylight element in the above thin film transistor liquid crystal display depends on the above-mentioned daylight element electrode 11 and the voltage between the transparent electrodes on the color substrate. Therefore, when the dielectric layer II 9 at the storage capacitor (that is, between the capacitor electrode 124 and the common wiring 118) is cracked 140, it will cause the thin film transistor to transmit a signal to the book electrode 110 (ie, a short circuit occurs). ), So that the interstitial voltage between the day electrode and the transparent electrode on the color filter substrate becomes 0, thus causing the day element in the twisted nematic (TN) structure to become a constant party point (normally white, and the multi-domain vertically aligned (MVA) structure of the book element has become a constant dark spot (normally black). The foregoing phenomenon will cause a fixed yield loss as the commercial characteristics of the thin film liquid crystal display become more and more concerned with the light / dark spot specification. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device.
!242681 '發明說明(4) Μ改善液晶 產生的缺陷 本發明 電容處的介 本發明 可修補儲存 維持儲存電 本發明 電容位於共 致時所產生 本發明 電容位於另 的介電層發 本發明 電容位於掃 裂時所產生 本發明 平面切換模 晶顯示裝置 產生的缺陷 本發明 示裝置,以 缺陷。 顯示裝置之儲存 ,進而維持產量 之再一目的是提 電層發生破裂時 供一種晝素結構 所產生的缺陷。 之另一目的疋提供一種儲存電容 電容處的介電層發生破裂時所產 容的功效。242681 'Explanation of the invention (4) M improves the defects generated by the liquid crystal The capacitor of the present invention The invention can repair the storage and maintain the stored electricity The defect generated by the planar switching mode crystal display device of the present invention generated during the cracking is shown in the device of the present invention. The purpose of storage of the display device, and thus maintaining the yield, is to provide a defect caused by a daylight structure when the electric layer is broken. Another object of the present invention is to provide an effect of storage capacitance when a dielectric layer at a capacitor is broken.
電容處的介電層發生破裂時所 之又一目的是提供一種晝素結構 善儲存電容處的 用配線上,以改 的缺陷。 之又一目的是提 一晝素結構之掃 生破裂時所產生 之又一目的是提 描配線上,以改 的缺陷。 之又一目的是提 式(In-Plane Sw 中,以改善儲存 供一種畫素結構 描配線上,以改 的缺陷。 供一種畫素結構 善儲存電容處的 供一種畫素結構 itching Mode , 電容處的介電層 ,可改善儲存 之修補方法, 生的缺陷,以 ,具有一儲存 介電層發生破 ,具有一儲存 善儲存電容處 ’具有一儲存 介電層發生破 ’可應用於同 簡稱IPS)的液 發生破裂時所 之又一目的是提供一種同平面切換模式液晶顯 改善儲存電容處的介電層發生破裂時所產生的 根據上述與其它目的,本發明提出一種液晶顯示裝When the dielectric layer at the capacitor is broken, another purpose is to provide a day-to-day structure to store the capacitor on the wiring to correct the defects. Another purpose is to improve the defects caused by the scanning and rupture of the elemental structure. Another purpose is to improve the defects in In-Plane Sw (in-Plane Sw) to improve the storage for a pixel structure. For a pixel structure, a capacitor structure is provided for a pixel structure in itching mode. The dielectric layer can improve the repair method of storage. The defects are that a storage dielectric layer is broken, a storage capacitor with a good storage capacitor is used. Another purpose of the IPS) liquid is to provide a coplanar switching mode liquid crystal display to improve the dielectric layer at the storage capacitor. According to the above and other purposes, the present invention provides a liquid crystal display device.
1242681 ------ 五、發明説明(5) f,包括一弟一基板、一第二基板、一液曰 一 谷電極、一介電層、一第二電容 曰曰 第一電 電極、-主動元件以及一透明電極。第1素 第:基板上,”層則位於第一電容極係,於 極係位於^電層上,其中第二電容電極具有一凸I:谷電 ”,其中保護層具有—心,暴露出巧:以::容 邛。而畫素電極是位於保護層上, 凸 護層之開口與第-雷宠雷托少几山*旦素電極係猎由保 電極並未完全連接,其中晝素 ::件是位於第-基板上 兩=則位於弟―基板上’且與畫素電極分別位於液晶層之 本發明再提出一種晝素結構,至少包括一盘 ,容電極、一介電層、一保護層以及一晝 二雷- 第;!容電極上’第二電容電極則位於介電;上層 電容電極具有-凸出部’位於第一電容電極 口:ίΐ出Ϊ護蓋第二電容電極,其中具有-開 護芦” 之凸出部。而晝素電極則覆蓋保 極^奏 開口與第二電容電極電性連接,其中晝素電 極並未元全覆蓋於第二電容電極上方之保護層上 ϋ明又提出-種儲存電容之修補方法:適於修補 ^ i '、、,、。構之儲存電容,其特徵在於當儲存電容的第—與 H949twf.ptd 第10頁 1242681 五、發明說明(6) 第二電容電極 以使第一與第 將晝素電極作 依照本發 括在切斷第二 覆蓋之第二電 極0 本發明再 晝素結構包括 一金屬層、一 在一基板上, 及一閘極。而 發生短路時,切斷 二電容電極改變点二電容電極之凸出部, 為儲存電容之上^4為儲存電容之下電極,而 电極。 明的較佳實施例所 …、 電容電極之凸出部二,上述之修補方法更包 容電極上方焊接^谈,再經由未被晝素電極 弟一電容電極與第二電容電 種晝素社★塞 金屬:了構,具有一儲存電容,此種 以及 佥 介電層、一通道層、一第 +思二f素電極。第一金屬層係配置 覆包括掃描配線(scan line)以 m _ 一金屬層,通道層則配置於閘 ::金屬層則配置在基板上,且第二 Φ ^ _ 貝料配線(data line)以 邱奋Γ極與掃描配線係互相疊置,且 搞p ^於知描配線以外的區域上,而 、八® ^通道層兩側。再者,保護層 以】及第二金屬層上,其中保 第二 一開口 ,而第一開口暴露出 ώ證汗二則暴露出汲極。晝素電極係 田弟一開口盘雷办 一寬合電極之凸出部電性 & i I玉電性連接,其中畫素電極並 極上方之保護層。 種晝素結構’具有一儲存電容此種 提出一 一第一 保護層 且第一 介電層 極上方之介電層上。 金屬層包括一源極、 及一電容電極,其中 電容電極具有 源極與 >及極配 係配置於第一 護層具有一第 電容電極之凸 位於保護層上 連接以及藉由 未完全覆蓋於電容電 本發明又提出一 一凸出 置於閘 金屬層 一開口 出部、 ,且藉 第二開1242681 ------ V. Description of the invention (5) f, including a substrate, a second substrate, a liquid electrode, a valley electrode, a dielectric layer, a second capacitor, a first electrical electrode, -Active element and a transparent electrode. The first element: on the substrate, "the layer is located on the first capacitor electrode system, and the electrode system is on the electrical layer, where the second capacitor electrode has a convex I: valley electricity", where the protective layer has a heart, which is exposed Qiao: Take :: Rong Hong. The pixel electrode is located on the protective layer, and the opening of the convex protective layer is not completely connected to the first electrode of the thunder-ray petite retort. The element electrode is not completely connected. The upper two = are located on the "substrate" and are located on the liquid crystal layer separately from the pixel electrode. The present invention further proposes a daylight structure, which includes at least a disk, a capacitive electrode, a dielectric layer, a protective layer and a thunderbolt. -No ;! The second capacitor electrode on the capacitor electrode is located in the dielectric; the upper capacitor electrode has a “protrusion” on the first capacitor electrode port: the second capacitor electrode with a protective cover, which has a “open protective lug” protrusion The day element electrode covers the opening of the polar electrode and is electrically connected to the second capacitor electrode, wherein the day element electrode is not completely covered on the protective layer above the second capacitor electrode. Ming also proposed a repair of a storage capacitor. Method: It is suitable for repairing the storage capacitor constructed by ^ i ',,,, ..., which is characterized in that when the first and the H949twf.ptd of the storage capacitor are on page 10, 1242681 V. Description of the invention (6) The second capacitor electrode makes the first The second electrode is used in accordance with the present invention to cut off the second electrode of the second cover. The second electrode structure of the present invention includes a metal layer, a substrate, and a gate electrode. When a short circuit occurs, the electrode is cut. The breaking point of the second capacitor electrode is the protruding portion of the second capacitor electrode, which is the upper electrode of the storage capacitor, and the lower electrode of the storage capacitor, and the electrode. The repair method is more inclusive of electrodes Welding on the upper side, and then passing the capacitor electrode and the second capacitor of the day capacitor electrode to the second capacitor type. The plug structure: a structure with a storage capacitor, such as a dielectric layer, a channel layer, a The first + second element electrode. The first metal layer is configured to include a scan line with m _ a metal layer, the channel layer is disposed on the gate: the metal layer is disposed on the substrate, and the second Φ ^ _ The data line is stacked with Qiu Fen pole and scanning wiring system, and is located on the area outside the wiring, and on both sides of the channel layer. Furthermore, the protective layer is ] And the second metal layer, in which the second opening is maintained, and the first opening is exposed to the second electrode and the drain is exposed. The day element electrode is a protruding part of Tiandi, an opening plate, and a wide closing electrode. Electrical & i I jade electrical connection, in which the pixel electrode and the protective layer above the pole. This kind of day element structure 'has a storage capacitor. This puts forward a first protective layer and a dielectric layer above the first dielectric layer. On the electrical layer. The metal layer includes a source electrode and a capacitor electrode, It has a source electrode and a pair of electrodes arranged on the first protective layer, and a convex electrode with a first capacitor electrode is connected on the protective layer and is not completely covered by the capacitor. An opening, and a second opening
11949twf.ptd 第11頁 1242681 五、發明說明(7) 晝素結構包括一第一金屬層 二金屬層、一保護層以及一 在一基板上,且第一金屬層 (common 1 ine)以及一閘極 c 通道層則配置於閘極上方之 在基板上,且第二金屬層包 線以及一電容電極,其中電 置,且電容電極更具有一凸 上,而源極與汲極配置於閘 保護層係配置於第一金屬層 其中保護層具有一第一開口 暴露出電容電極之凸出部、 電極係位於保護層上,且藉 部電性連接以及藉由第二開 電極並未完全覆蓋於電容電 本發明另外提出一種晝 種晝素結構包括一第一金屬 第二金屬層、一保護層以及 配置在一基板上,第一金屬 配線。介電層則覆蓋第一金 上,而包括一源極、一汲極 極,其中電容電極與共用配 具有一凸出部,位於共用配 置於知描配線上方之介電層 、一介電層、一通道層、—第 晝素電極。第一金屬層係配置 包括一知描配線、一共用配線 而介電層覆蓋第一金屬層, 介電層上。第二金屬層則配置 括一源極、一没極、一資料配 容電極與共用配線係互相疊 出部位於共用配線以外的區域 極上方之通道層兩側。再者, 、介電層以及第二金屬層上, 以及一第二開口 ,而第一開口 第一開口則暴露出汲極。畫素 由第一開口與電容電極之凸出 口與汲極電性連接,其中晝素 極上方之保護層。 素結構’具有一儲存電容,此 層、一介電層、一通道層、一 一晝素電極。而第一金屬層係 層包括一掃描配線以及一共用 屬層。第一金屬層配置在基板 、一資料配線以及一電容電 線係互相疊置,且電容電極更 線以外的區域上。通道層則配 與源極及沒極之間。而保護層11949twf.ptd Page 11 1242681 V. Description of the invention (7) The day element structure includes a first metal layer, two metal layers, a protective layer, and a substrate, and the first metal layer (common 1 ine) and a gate The electrode c channel layer is arranged on the substrate above the gate electrode, and the second metal layer covered wire and a capacitor electrode are electrically disposed, and the capacitor electrode is further convex, and the source electrode and the drain electrode are disposed in the gate protection. The layer is arranged on the first metal layer, wherein the protective layer has a protruding portion with a first opening exposing the capacitor electrode, the electrode is located on the protective layer, and is electrically connected by the portion and is not completely covered by the second open electrode. Capacitive electricity The present invention further provides a daytime-daytime-daylight structure including a first metal, a second metal layer, a protective layer, and a first metal wiring disposed on a substrate. The dielectric layer covers the first gold, and includes a source electrode and a drain electrode, wherein the capacitor electrode and the common electrode have a protruding portion, and the common electrode layer, a dielectric layer, a dielectric layer, One channel layer, the first day element electrode. The first metal layer system configuration includes a trace wiring, a common wiring, and a dielectric layer covering the first metal layer, and the dielectric layer. The second metal layer includes a source electrode, a polar electrode, a data-capacitor electrode, and a common wiring system. The overlapping portions are located on both sides of the channel layer above the poles in areas other than the common wiring. Furthermore, the dielectric layer and the second metal layer are provided with a second opening, and the first opening and the first opening expose the drain electrode. The pixel is electrically connected to the drain electrode through the first opening and the protruding port of the capacitor electrode, wherein the protective layer is above the day pixel electrode. The element structure 'has a storage capacitor, a layer, a dielectric layer, a channel layer, and a day electrode. The first metal layer system layer includes a scan wiring and a common metal layer. The first metal layer is disposed on a region where the substrate, a data wiring, and a capacitor line are superimposed on each other, and the capacitor electrode is not lined. The channel layer is matched between the source and the end. Protective layer
11949twf.ptd 第12頁 1242681 五、發明說明(8) 則配置於第一金屬層、介電層以一 護層具有一第一開口 第一金屬層上,其中保 電容電極之ί出而第-開口暴露出 位於保護層上,且!^由m 、j暴路出汲極。畫素電極是 萨由m - ^ #措由第一開口與電容電極電性連接以及 ίίί:: 口與沒極電性連接1中晝素電極並未完全ί 盍於電谷電極上方之保護層上。 不凡王復 括平面切換模式液晶顯示裝置,包 極」晶層、電容電 梅 _ 曰 苐一電谷電極、一保護層、一查辛雷 對,而液晶層夾於第一基板鱼第二與苐一基板相 極則位於第—基板上。"層是二第-電容電 二電容電極則位於介電層上,”第 電極上。第 覆蓋第二電容電極,其中保護=士門;者2護層係 電容電極之凸出部。晝素電極則是位於::路出 接,其中畫素“並電=凸出部電性連 :蔓層上。而主動元件是位於第一基板上,且盘 性相連。共通電極則位於保護層_L,且鱼金::素電極電 性隔離。 且與畫素電極彼此電 本發明因為在電容電極的設計上 夕 位於其相對應金屬層以外的區域上,用來二里部〜’ 電容電極電性相連的部位。並且在書 ^旦素電極與 旦I電極中設計成未完 11949twf.ptd 第13頁 124268111949twf.ptd Page 12 1242681 V. Description of the invention (8) The first metal layer is disposed on the first metal layer, the dielectric layer has a first opening with a protective layer, and the capacitor electrode The opening is exposed on the protective layer, and! ^ Drain the drain from m and j. The pixel electrode is electrically connected to the capacitor electrode by the first opening and the 开口 :: the mouth is electrically connected to the electrode 1 The day element electrode is not completely placed on the protective layer above the valley electrode on. Unusual Wang Fu ’s flat switching mode liquid crystal display device, including polarized crystal layers, capacitors, plummets, electric valley electrodes, a protective layer, and a pair of chasing thunder, while the liquid crystal layer is sandwiched between the first substrate, the second substrate, and the first substrate. The substrate phase pole is located on the first substrate. "The layer is the second-capacitance capacitor. The second-capacitor electrode is located on the dielectric layer," on the second electrode. The second layer covers the second capacitor electrode, where protection = Shimen; the second layer is the protruding portion of the capacitor electrode. The pixel electrode is located on the :: out connection, where the pixel "and electricity = the protrusion is electrically connected to the: manifold. The active element is located on the first substrate and is discontinuously connected. The common electrode is located on the protective layer_L, and the fish gold :: element electrode is electrically isolated. The pixel electrode is electrically connected to the pixel electrode in the design of the capacitor electrode, and is located on a region other than the corresponding metal layer. And in the book ^ denier electrode and denier I electrode designed as unfinished 11949twf.ptd page 13 1242681
:!:=電?::;=層’所以當儲存電容部位的 與電容電極之連接,電極之凸出㉝,即晝素電極 區域(即烊點)上方捏ί込擇性地經由未被晝素電極覆蓋之 直ίϋ 疋儲存電容之上電極一部份的電容電極,使 用成為修補後之儲存電容的下電#,以保有儲存 顔旦ί讓本發明之上述和其他目#、特徵、和優點能更明 ς ’ ,下文特舉較佳實施例,並配合所附圖式,作詳細 說明如下: ' 實施方式 本發明之概念可應用於各種樣式的儲存電容(st〇rage capacitor)上,請參考下列之實施例與其附圖,但是這些 實施例只是用於舉例而不是作限定之用。 第一實施例 第2圖係依照本發明之一第一實施例之晝素結構 (pixel structure)的上視簡圖,其中具有一種稱為Cst on common的儲存電容。請參照第2圖,本實施例之晝素結 構包括一第一金屬層(Metal 1)102、一介電層119、一通 道層(channel layer)l〇4、一第二金屬層(Metal 2)106、 一保護層以及一晝素電極(pixel electrode)ll〇。第一金 屬層102係配置在一基板(未繪示)上,且第一金屬層1〇2包 括一掃描配線(s c a η 1 i n e) 11 4、一閘極11 6以及一共用配 線(common line )118。而介電層119覆蓋第一金屬層1〇2,:!: = Electricity? :: ; = layer 'So when the storage capacitor part is connected to the capacitor electrode, the electrode protrudes, that is, the pin above the day element area (ie, the point) is selectively passed through the line not covered by the day element electrode. ίϋ 疋 Capacitor electrodes that are part of the upper electrode of the storage capacitor, use the power-down # which becomes the repaired storage capacitor, to keep the storage Yan Dan, so that the above and other objectives, features, and advantages of the present invention can be made clearer. ', The following describes the preferred embodiment in detail, and in conjunction with the accompanying drawings, the detailed description is as follows:' Embodiments The concept of the present invention can be applied to various types of storage capacitors, please refer to the following implementation Examples and their drawings, but these examples are for illustration purposes only and are not intended to be limiting. First Embodiment FIG. 2 is a schematic top view of a pixel structure according to a first embodiment of the present invention, which has a storage capacitor called Cst on common. Please refer to FIG. 2. The diurnal structure of this embodiment includes a first metal layer (Metal 1) 102, a dielectric layer 119, a channel layer 104, and a second metal layer (Metal 2). 106), a protective layer and a pixel electrode 110. The first metal layer 102 is disposed on a substrate (not shown), and the first metal layer 102 includes a scan wiring (sca η 1 ine) 11 4, a gate electrode 116, and a common line. ) 118. The dielectric layer 119 covers the first metal layer 102.
11949twf.ptd 第14頁 1242681 五、發明說明(ίο) 通道層104則配置於閘極116上方之介電層上。第二金屬層 1 0 6則配置在基板上,且第二金屬層1 〇 6包括一源極1 2 〇 a、 一汲極120b、一資料配線(data line)122以及一電容電極 124,其中電容電極124與共用配線118係互相疊置,且電 容電極124在位於共用配線118以外的區域上更具有一凸出 部224,而源極120a與汲極120b則配置於閘極116上方之通 道層1 04兩側,而閘極1 1 6、通道層1 04、源極1 20a以及汲 極120b係組成一薄膜電晶體126。 再者’請繼續參照第2圖,保護層(未緣示)係配置於 第一金屬層102、介電層119以及第二金屬層106上,其中 保護層具有一第一開口 1 28以及一第二開口 1 30,而第一開 口 128暴露出電容電極124的凸出部224、第二開口 130則暴 露出薄膜電晶體126的汲極120b。晝素電極110係位於保^ 層上,且藉由第一開口 128與電容電極124的凸出部2 24電 性連接以及藉由第二開口 13〇與汲極12〇b電性連接,其中 晝素電極110並未完全覆蓋於電容電極丨24上方之保護層。 為更詳細說明本發明之結構,請見第3圖。 f 3圖所示係第2圖之I — !剖面示意圖。請參照第3 =’前述本發明之畫素結構中的儲存電容包括共用配線 、介電層119、電容電極124、保護層1〇8以及畫素電極 你认。而共用配線118是位於一基板300上,介電層丨19則是 仅2共用配/線118上。電容電極124則位於介電層11Θ上。 護二fn:08係覆Ϊ電容電極124。而晝素電極110則位於保 曰 上,且藉由保護層108之開口128與電容電極124的11949twf.ptd Page 14 1242681 V. Description of the Invention (ίο) The channel layer 104 is disposed on the dielectric layer above the gate electrode 116. The second metal layer 106 is disposed on the substrate, and the second metal layer 106 includes a source 120a, a drain 120b, a data line 122, and a capacitor electrode 124. The capacitor electrode 124 and the common wiring 118 are superposed on each other, and the capacitor electrode 124 has a protrusion 224 on an area outside the common wiring 118, and the source electrode 120a and the drain electrode 120b are arranged in a channel above the gate electrode 116. Both sides of the layer 104 are the gate electrode 116, the channel layer 104, the source electrode 120a, and the drain electrode 120b to form a thin film transistor 126. Furthermore, please continue to refer to FIG. 2. The protective layer (not shown) is disposed on the first metal layer 102, the dielectric layer 119, and the second metal layer 106. The protective layer has a first opening 128 and a The second opening 130 and the first opening 128 expose the protruding portion 224 of the capacitor electrode 124, and the second opening 130 exposes the drain electrode 120 b of the thin film transistor 126. The day electrode 110 is located on the protective layer, and is electrically connected to the protrusion 2 24 of the capacitor electrode 124 through the first opening 128, and is electrically connected to the drain electrode 120b through the second opening 13, where The day electrode 110 does not completely cover the protective layer above the capacitor electrode 24. To explain the structure of the present invention in more detail, please refer to FIG. 3. Figure 3 is a schematic diagram of the section I—! in Figure 2. Please refer to 3 = 'The storage capacitor in the pixel structure of the present invention includes a common wiring, a dielectric layer 119, a capacitor electrode 124, a protective layer 108, and a pixel electrode. The common wiring 118 is located on a substrate 300, and the dielectric layer 19 is only on the common wiring 118. The capacitor electrode 124 is located on the dielectric layer 11Θ. The protective second fn: 08 system covers the capacitor electrode 124. The day element electrode 110 is located on the circuit board, and through the opening 128 of the protective layer 108 and the capacitor electrode 124
1242681 五、發明說明(11) 凸出部224電性連接。再者,畫素電極丨1()暴露出部分電容 電極124上方的保護層1〇8。另外,有另一基板31〇與基板 3 0 0相對,且於兩基板3丨〇、3 〇 〇之間夾有一液晶層3 2 〇。此 外’在基板310上還有一透明電極312,且與晝素電極11() 刀別位於液晶層3 2 0之兩側。當儲存電容處(即電容電極 1 2 4與共用配線11 8之間)的介電層丨丨9發生破裂2 1 〇 (請見第 2圖)而造成短路時,需從切斷線2〇〇切斷電容電極124之凸 出部224,再選擇性地經由焊點3〇2焊接共用配線118與 容電極1 24。 立另=,晝素電極11〇並未完全覆蓋於電容電極124上方 豆::3 :以作很多變形,如第4圖所示。請參照第4圖, 圖7 2 =中S =之第一實施例之另一晝素結構的上視簡 電極124'上方、之圖的差異在於晝素電極110中暴露出電容 作區严Γ。除此之Λ陷部Λ400範圍更大,以增加焊接時的操 方的形狀還可以是一 中暴露出電容電極124上 行的修補方法如第5/所示 前述結構所進 電容之步第一實施例之畫素結構的儲存 有儲存電容之查::多照第5圖,於步驟5〇〇中’提供具 極(即第一 # 素、、構,其中儲存電容包括一第一電容電 電極"Ρ第中的共用配線)、-介電層、-第 電極,且第雷」列中的電容電極)、-保護層以及-書辛 —凸出部,而第_ 電今電極以外的區域上具有 電谷電極之凸出部與晝素電極電性相 11949twf.ptd 第16頁 1242681 五、發明說明(12) 然後,於步驟51〇中,儲存電容的第一與第二電容 =疋否發生短路?之後,如果儲存電容的第一與第二電 沒有發生短路,則不需要進行修補;如果儲存電容的 一與第二電容電極發生短路而有導通的情形時,則進 步,520 ’切斷第二電容電極之凸出部,以使短路的第一 與第二電容電極改變成為儲存電容之下電極,而將晝素電 極作為儲存電·容之上電極。此外,為進一步確保第一與第 二電容電極是互相導通的,可選擇性地於步驟5 2〇之後進 行步驟530,經由未被晝素電極覆蓋之第二電·容電極上方 焊接第一與第二電容電極。 再者’當儲存電容經過修補後,其儲存電容值因為在 修補前後的差異不大,故可維持正常運作。而以上論述係 根據公式C= e(A/d),其中C是指電容值、ε是上下電極之 間的夾層的常數、Α是上下電極之重合面積、d則是上下電 極之間的距離。由於修補前後之ε相差不大(介電層與保、 護層的ε相差不大),而修補後之Α值略小於修補前之a 值’不過因為修補後之cl值(保護層的厚度)也略小於修補 前之d值(介電層的厚度),所以整體儲存電容值變化不 大。甚至可改變保護層與介電層之厚度與材質以及改變各 金屬層與晝素電極的重合面積,以獲得最佳的結果。 第二實施例 第6圖係依照本發明之一第二實施例之晝素結構的± 視簡圖,其中具有一種稱為Cst on gate的儲存電容。請 參照第6圖,本實施例之晝素結構與第一實施例的書素$1242681 V. Description of the invention (11) The protruding portion 224 is electrically connected. In addition, the pixel electrode 1 () exposes a protective layer 108 over a portion of the capacitor electrode 124. In addition, there is another substrate 31o opposite to the substrate 300, and a liquid crystal layer 320 is sandwiched between the two substrates 3100 and 300. In addition, there is a transparent electrode 312 on the substrate 310, and it is located on both sides of the liquid crystal layer 3 2 0 with the day electrode 11 (). When the dielectric layer at the storage capacitor (that is, between the capacitor electrode 1 2 4 and the common wiring 11 8) ruptures 2 1 〇 (see Figure 2) and causes a short circuit, the cut-off line 2 〇 〇 Cut off the protruding portion 224 of the capacitor electrode 124, and then selectively weld the common wiring 118 and the capacitor electrode 124 through the solder joint 302. In other words, the day element electrode 110 does not completely cover the capacitor electrode 124. Bean :: 3: To make a lot of deformation, as shown in Figure 4. Please refer to FIG. 4. FIG. 7 2 is the top view of the top electrode 124 ′ of another daylight structure of the first embodiment of S = in the first embodiment. The difference is that the capacitance working area is exposed in the daylight electrode 110. . In addition, the range of Λ depression Λ400 is larger to increase the shape of the operator during welding. It can also be a repair method that exposes the capacitor electrode 124 upwards as shown in 5 / the first step of the capacitor structure. For example, the pixel structure is stored with a storage capacitor: according to FIG. 5, in step 500 ′, a polarizer (that is, the first element) is provided, and the storage capacitor includes a first capacitor electric electrode. " P common wiring), -dielectric layer, -electrode, and capacitor electrode in the thunder column), -protective layer and -Shusin -protrusions, and other than The electrical phase of the projection with the valley electrode on the area and the day electrode electrode 11949twf.ptd Page 16 1242681 V. Description of the invention (12) Then, in step 51, the first and second capacitances of the storage capacitor = 疋Does a short circuit occur? After that, if the first and second capacitors of the storage capacitor are not short-circuited, no repair is required; if one of the storage capacitors and the second capacitor electrode are short-circuited and turned on, the process progresses, and 520 'cuts off the second The protruding portion of the capacitor electrode changes the shorted first and second capacitor electrodes into the lower electrode of the storage capacitor, and the day element electrode is used as the upper electrode of the storage capacitor. In addition, to further ensure that the first and second capacitor electrodes are conductive with each other, step 530 may be optionally performed after step 5 20, and the first and second capacitor electrodes are welded over the second capacitor electrode that is not covered by the day electrode. Second capacitor electrode. Furthermore, when the storage capacitor is repaired, the storage capacitor value can maintain normal operation because there is not much difference between before and after repair. The above discussion is based on the formula C = e (A / d), where C is the capacitance value, ε is the constant of the interlayer between the upper and lower electrodes, A is the overlap area of the upper and lower electrodes, and d is the distance between the upper and lower electrodes. . Because the difference between ε before and after repair is not large (the difference between ε of the dielectric layer and the protective layer is not large), the A value after repair is slightly smaller than the a value before repair, but because the cl value after repair (the thickness of the protective layer) ) Is also slightly smaller than the d value (thickness of the dielectric layer) before repair, so the overall storage capacitor value does not change much. It is even possible to change the thickness and material of the protective layer and the dielectric layer, and to change the overlap area of each metal layer and day electrode to obtain the best results. Second Embodiment FIG. 6 is a schematic diagram of a daytime structure according to a second embodiment of the present invention, which has a storage capacitor called a Cst on gate. Please refer to FIG. 6, the structure of the day element of this embodiment and the book element of the first embodiment
II 11949twf.ptd 第17頁 1242681II 11949twf.ptd Page 17 1242681
構最大的不同在於其中的第一金屬層l〇2之共用配線 11 8 (請見第2圖)改成另一個掃描配線11 4。而其餘的構 件:介電層119、通道層104、第二金屬層106、保護層(未 缘示)、畫素電極1 1 0、第一金屬層1 〇 2之掃描配線1丨4、間 極1 1 6與第二金屬層1 〇 6之源極1 2 〇 a、汲極1 2 0 b、資料配線 1 2 2、電谷電極1 2 4都與苐一貫施例相同或類似。而且,各 個構件的配置也與第一實施例雷同。另外,其中晝素電極 110中暴露出電容電極124上方的形狀還可以是一開口或: 一缺角等。 疋 第三實施例 , 第7圖係依照本發明之一第三實施例之晝素結構的上 視簡圖,其可應用於同平面切換模式(ln — pianeThe biggest difference is that the common wiring 11 8 (see FIG. 2) of the first metal layer 102 is changed to another scanning wiring 11 4. And the remaining components: the dielectric layer 119, the channel layer 104, the second metal layer 106, the protective layer (not shown), the pixel electrode 1 10, the scanning wiring 1 of the first metal layer 1 02, and The electrode 1 16 and the source 12 2a of the second metal layer 1 06, the drain 1 2 0b, the data wiring 1 2 2 and the valley electrode 1 2 4 are the same as or similar to the conventional embodiment. Moreover, the arrangement of each member is similar to that of the first embodiment. In addition, the shape above the capacitive electrode 124 exposed in the day element electrode 110 may also be an opening or a notch.疋 The third embodiment, FIG. 7 is a schematic top view of a daylight structure according to a third embodiment of the present invention, which can be applied to the in-plane switching mode (ln — piane
Switching Mode,簡稱IPS)的液晶顯示裝置中。請參照第 7圖,本實施例之晝素結構包括一第一金屬層7〇2、—介電 層719、一通道層704、一第二金屬層706、一保護層(未繪 示畫素電極7 10a以及一共通電極71〇b。第一金屬層7〇92 係配置在一基板(未繪示)上,且第一金屬層7〇2包括—掃 描配線714以及一第一電容電極(或是共用配線)718。而1介 電層719覆蓋第一金屬層7〇2。第二金屬層7〇6則包括—源1 極72 0a、一汲極720b、一資料配線72 2以及一第二電容電 極7 2 4 ’其中第一電容電極7 2 4與共用配線71 8係互相叠_ 置,且第二電容電極724在位於第一電容電極71 8以外"的區 域上更具有一凸出部2 2 4,通道層7 0 4則配置於掃描配線品 714上方之介電層719與源極720a、沒極720b之間,品: 4 而部分Switching Mode (IPS for short) liquid crystal display device. Please refer to FIG. 7. The daytime pixel structure of this embodiment includes a first metal layer 702, a dielectric layer 719, a channel layer 704, a second metal layer 706, and a protective layer (pixels not shown). The electrode 7 10a and a common electrode 71b. The first metal layer 7092 is disposed on a substrate (not shown), and the first metal layer 702 includes a scan wiring 714 and a first capacitor electrode ( Or common wiring) 718. And a dielectric layer 719 covers the first metal layer 702. The second metal layer 706 includes a source 1 electrode 72 0a, a drain electrode 720b, a data wiring 72 2 and a The second capacitor electrode 7 2 4 'wherein the first capacitor electrode 7 2 4 and the common wiring 71 8 are overlapped with each other, and the second capacitor electrode 724 is further provided in a region outside the first capacitor electrode 71 8 " The protruding portion 2 2 4 and the channel layer 7 0 4 are arranged between the dielectric layer 719 and the source electrode 720a and the non-electrode 720b above the scan wiring product 714.
1242681 7、發明說明(14) ' 一 --- 掃描配線714、通道層7〇4、源極72 0a以及汲極72〇1}係組 一薄膜電晶體726。 々再者,請繼續參照第7圖,保護層(未繪示)係配置於 第一金屬層702、介電層719以及第二金屬層7〇6上,其中 保護層具有一第一開口 728以及一第二開口 73〇,而第一開 口 728暴露出第二電容電極724的凸出部224、第二開口 73〇 則暴露出薄膜電晶體726的汲極720b。畫素電極710a係位 於保護層上,且藉由第一開口 728與第二電容電極724的凸 出部224電性連接以及藉由第二開口73〇與汲極72〇1)電性連 接其中晝素電極710a並未完全覆蓋於第二電容電極724 上方之保護層另外,畫素電極71〇a中暴露出第二電容電極 724上方的形狀還可以是一開口或是一缺角等。共通電極 710b則同樣位於保護層上且與晝素電極71〇a電性隔離,其 中晝素電極710a例如是梳狀電極,因而共通電極71〇b也可 以是梳狀電極並與畫素電極7i〇a交錯配置。 當本實施例之儲存電容處(即第二電容電極了 24與第一 電谷電極71 8之間)的介電層71 9短路時,可從切斷線2〇〇切 斷第二電容電極724之凸出部224,以維持此一儲存電容的 運作。之後,也可選擇性地經由焊點3 〇 2焊接第一電容電 極718與第二電容電極724,以確保第一電容電極718與第 二電容電極724是導通的。 綜上所述,本發明之特點之一為在電容電極的設計上 特別多一個凸出部,位於其相對應金屬層以外的區域上, 用來作為晝素電極與電容電極電性相連的部位。並且在畫1242681 7. Description of the invention (14) '-Scanning wiring 714, channel layer 704, source 72 0a, and drain 72 0 1} are a thin film transistor 726. (Further, please continue to refer to FIG. 7. The protective layer (not shown) is disposed on the first metal layer 702, the dielectric layer 719, and the second metal layer 706. The protective layer has a first opening 728. And a second opening 730, and the first opening 728 exposes the protruding portion 224 of the second capacitor electrode 724, and the second opening 730 exposes the drain electrode 720b of the thin film transistor 726. The pixel electrode 710a is located on the protective layer, and is electrically connected to the protruding portion 224 of the second capacitor electrode 724 through the first opening 728 and electrically connected to the drain electrode 72〇1) through the second opening 73o. The day electrode 710a does not completely cover the protective layer above the second capacitor electrode 724. In addition, the pixel electrode 71a may expose the shape above the second capacitor electrode 724 as an opening or a notch. The common electrode 710b is also located on the protective layer and is electrically isolated from the day electrode 71oa. The day electrode 710a is, for example, a comb-shaped electrode. Therefore, the common electrode 710b can also be a comb-shaped electrode and is connected to the pixel electrode 7i. 〇a staggered configuration. When the dielectric layer 71 9 at the storage capacitor in this embodiment (that is, between the second capacitor electrode 24 and the first valley electrode 71 8) is short-circuited, the second capacitor electrode may be cut from the cutting line 200. The protruding portion 224 of 724 maintains the operation of this storage capacitor. After that, the first capacitor electrode 718 and the second capacitor electrode 724 can also be selectively welded through the solder joint 30 to ensure that the first capacitor electrode 718 and the second capacitor electrode 724 are conductive. To sum up, one of the features of the present invention is that the capacitor electrode has a particularly large protruding portion, which is located in a region other than the corresponding metal layer, and is used as a place where the day electrode and the capacitor electrode are electrically connected. . And drawing
11949twf.ptd 第19頁 1242681 五、發明說明(15) 素電極中没计成未完全覆 以當作為下電極的第一金屬層方之保護層,所 :金屬層發生短路時,例如儲存J容G電極-部份的第 之連接,使原本作為下電二出厶:畫=極與電容電極 部份的電容電極成為修補二=原本是上電極 ί儲存電容的功用,進而4=ji:,:電極,以保 量。 竹,寻膜電日日體液晶顯示器之產 雖然本發明已以較佳實施例 、 限疋本發明,任何熟習此技藝者 然其並非用以 2範圍内,當可作各種之更動盥;^不脫離本發明之精神 範園當視彳& & t 飾,因此本發明之保護 田視後附之申凊專利範圍所界定者為準。 ll949twf •Ptd 第20頁 1242681 圖式簡單說明 第1圖係習知一種具有儲存電容之薄膜電晶體液晶顯 示器的畫素結構的上視簡圖。 第2圖係依照本發明之第一實施例之薄膜電晶體液晶 顯示器的上視簡圖。 第3圖所示係第2圖之I - I剖面示意圖。 第4圖係依照本發明之第一實施例之另一畫素結構的 上視簡圖。 第5圖係修補本發明之第一實施例之晝素結構的儲存 電容之步驟流程圖。 第6圖係依照本發明之第二實施例之晝素結構的上視 簡圖。 第7圖係依照本發明之第三實施例之晝素結構的上視 簡圖。 【圖式標示說明】 102、106、702、706 :金屬層 104、704 :通道層 110、710a ·晝素電極 11 2 :無遮蔽部位 11 4、71 4 :掃描配線 I 1 6 :閘極 II 8 :共用配線 119、719 :介電層 1 2 0 a、7 2 0 a :源極 120b、720b ·>及極11949twf.ptd Page 19 1242681 V. Explanation of the invention (15) The element electrode is not counted as a protective layer that is not completely covered by the first metal layer as the lower electrode, so when the metal layer is short-circuited, for example, storage capacity The connection between the first part of the G electrode and the second part makes it originally used as the power-down second output: drawing = the capacitor electrode of the electrode part and the capacitor electrode becomes the repair two = originally the function of the storage capacitor of the upper electrode, and then 4 = ji :, : Electrode to ensure volume. Bamboo, the production of film-seeking electric day and day body liquid crystal display Although the present invention has been limited to the present invention with a preferred embodiment, anyone skilled in this art is not used in the 2 range, it can be used for various changes; ^ Without deviating from the spirit of the present invention, the & & t decoration should be considered, so the protection of the present invention as defined by the scope of the patent application attached shall prevail. ll949twf • Ptd Page 20 1242681 Brief Description of Drawings Figure 1 is a simplified top view of the pixel structure of a thin film transistor liquid crystal display with a storage capacitor. Fig. 2 is a schematic top view of a thin film transistor liquid crystal display according to a first embodiment of the present invention. Figure 3 is a schematic sectional view taken along the line I-I in Figure 2. Fig. 4 is a schematic top view of another pixel structure according to the first embodiment of the present invention. Fig. 5 is a flow chart of steps for repairing the storage capacitor of the daytime structure of the first embodiment of the present invention. Fig. 6 is a schematic top view of a daylight structure according to a second embodiment of the present invention. Fig. 7 is a schematic top view of a day element structure according to a third embodiment of the present invention. [Illustration of diagrammatic symbols] 102, 106, 702, 706: Metal layers 104, 704: Channel layers 110, 710a · Day electrode 11 2: Unshielded parts 11 4, 71 4: Scanning wiring I 1 6: Gate II 8: Common wiring 119, 719: Dielectric layers 1 2 0 a, 7 2 0 a: Source 120b, 720b
11949twf.ptd 第21頁 1242681 圖式簡單說明 1 2 2、7 2 2 :資料配線 124、718、724 :電容電極 126、72 6 :薄膜電晶體 128 、130 、728 、730 :開 〇 1 4 0、2 1 0 :破裂處 2 0 0 :切斷線 2 24 :凸出部 3 0 0、3 1 0 :基板 3 0 2 :焊點 3 1 2 :透明電極 3 2 0 :液晶層 4 0 0 :凹陷部位 500〜530 :步驟 7 1 0 b ·共通電極11949twf.ptd Page 21 1242681 Brief description of the drawings 1 2 2, 7 2 2: Data wiring 124, 718, 724: Capacitor electrodes 126, 72 6: Thin film transistors 128, 130, 728, 730: On 0 1 4 0 2 1 0: Rupture 2 0 0: Cutting line 2 24: Bump 3 0 0, 3 1 0: Substrate 3 0 2: Solder joint 3 1 2: Transparent electrode 3 2 0: Liquid crystal layer 4 0 0 : Recessed part 500 to 530: Step 7 1 0 bCommon electrode
11949twf.ptd 第22頁11949twf.ptd Page 22
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