1242326 九、發明說明： 【發明所屬之技術領域】 本發明係相關於-種時序回復電路（t i m i ng r⑽慨y circuit)，尤指一種以牛頓方法（Newt〇n，s脱让〇幻為基 礎而發展出來之時序回復電路。 【先前技術】 在無線通訊系統中，一接收器所接收到之無線電訊號必 ^經過適當的同步化程序後，方能為電 連接於5亥接收器後方之解調器（dem〇duiator)正確地解 调’而日守序回復電路（timing recovery circuit)便為執行 該同步化程序之一種電子電路。 請參閱第1圖，第1圖為習知一時序回復電路1〇之功 能方塊圖。時序回復電路1〇包含一取樣時脈產生器 (sampling clock generator)12、一取樣器（saropler)l4、 一内插器（interpolator)16、以及一資料濾波器（data filter)18 〇 取樣時脈產生器12產生一取樣時脈Ts，其周期為ts ; 1242326 取樣器14依據取樣時脈Ts取樣―盔 上/、 热線電訊號X(t)、並繼 而產生一取樣訊號x(mTs);内插ρ β -lb u 一内插間隔 (interp〇lai：i〇n 内插取樣訊號 x(mTs)、並繼 而產生γ_ 波器18濾除内插訊號 Y(kTi)内之雜訊（noise)、並繼而將_出 ^内插訊號YKkTQ輸出 至電連接於時序回復電路10後之解嘴β Α 夂<鮮凋态内，以備解調。 雨已言之，為了雜該解調H能正確地解調經資料遽波 器18之濾、波作用過後而產生之内插訊號Yf(kTi)，時序回 復電路10另包含一時序錯誤偵測器（timing打⑺r detectors、以及一電連接於時序錯誤制器2〇及内插 器16間之時序錯誤控制器（timing err〇r咖㈣Μ”。 時序錯誤偵測器20偵測潛藏於内插訊號Yf⑽）中之時 序錯誤（timing enw)、並繼而產生」時序錯誤訊號e ; ，序錯誤控制器22依據時序錯誤訊號e產生用以控制内插 益16之時序補償（timing—咐咐）訊號#，以儘可能地減 小潛藏於資，波器18接下來所輪出之_訊號Yf(㈤ 夺序’曰為相應地，該解調器便可更正確地解調内插 訊號 Yf(kTi)。 由於時序回復電路10所輸出至該解調器之内插訊號 Yf(kTl)中所潛藏的時序錯誤之大小，與該解調器能否正择 1242326 地解調内插訊號Yf(kT〇間之關係至為密切，具體言之，時 序回復電路10所輸出至該解調器之内插訊號Yf(kTi)中所 潛藏的時序錯誤越小，該解調器就越能正確地解調内插訊 號MkTi)，因此，習知時序回復電路10之設計人員無不 絞盡腦汁地以各種數學上或物理上之方法為基礎，嘗試著 發展出可精確地計算出時序補償訊號//、並進而使内插訊 號Yf(kTi)中所潛藏的時序錯誤減至最小之時序回復電路。 【發明内容】 因此本發明之主要目的在於提供一種以牛頓方法 (Newton’ s method)為基礎而發展出來之時序回復電路， 其可使潛藏於内插訊號Yf(kTi)中之時序錯誤減至最小。 根據本發明之申請專利範圍，本發明係揭露一種以牛頓 方法為基礎而發展出來之時序回復電路，其包含：一取樣 時脈產生器，用來產生—取樣時脈；—取樣器，用來依據 該取樣時脈取樣-輸人於該時序回復電路之無線電訊號、 並、、麈而產生一取樣訊號；_内插器，用來依據一當前時序 、偵汛號内插該取樣巩號、並繼而產生一内插訊號；一時 =錯誤偵測器，用㈣測該内插訊號中所潛藏之時序錯 並、、而產生一當前時序錯誤訊號，該當前時序錯誤訊 唬為該當前時序補償訊號之函數；一微分器，用來產生一 1242326 2時序錯誤訊號，該微分時相誤訊號係為該 補:員訊號之微分函數…第_除法器，用來將該 = 讯號除以該微分時序錯誤訊號；_第_減法哭τ〜疾 當前時序補^ "σ用來將該 除法器所輸出之該時序錯工 广除以該微分時序錯誤訊號、並繼而產生—接續曰番 遽’其輕接續於該當前時序補償訊號；—第―延二 :，用來於-個該取樣時脈之周期後將該第—減法 之接_序補償訊號回授至該第—減法m則 :器，用來於一個該取樣時脈之周期後將該第—延遲二 哭月,入至該第—減法器之接續時序補償訊號輸人至該微二 在本發明之較佳實施例中，該微分器包含：―第 =來於一個該取樣時脈之周期後將該時序錯誤帅 斤輪出之前行時序錯誤訊號輪入至誃 ，」 時序錯誤訊麟、緊接續科 、ia。 莰只於〇亥刖仃時序錯誤訊號；一第二、请 去态，用來將該時序錯誤偵 4 號诘土兮哲 °»所輸出之當則日寸序錯誤郭 2去該弟三延遲器所輸出之前行時序錯誤訊號； 減去 遲°。所輸出之當前時序補償訊號 成去该第二延遲器所輸出… 、、扣EO + 仃日才序補償訊號，一第二除 去态，用來將該第二減法哭 ^ 灸的所輪出之當前時序補償訊號減 皮 这弟二減法器所輸出之當前時 序補^訊號減去該前行時戽誌 丁了序補償訊號；一第一比較器，用 1242326 來將該弟二減法n所輸出之料時序補償錢減去該前行 時序補償訊號與-預定值相比…第四延遲器，用來於— 個該取樣時脈之周期後輪出該微分時序錯誤訊號；以及— 多工器i絲依據該第—比較器_該當前時序補償訊號 減去該别㈣序補償訊號與該預定值間之相比結果、 ㈣將該第二除法器所輸出之（當前時序補償訊號減去該 可打時序補償職）除以⑽當㈣相償訊號減去該 時序補償訊號）或該第四該第—除法器所輸出之微分時序 錯誤訊號輸出至該第一除法器。 根據本發明之中請專利範圍，本發明另揭露—種亦係以 牛頓方法為基礎而發展出來之時序回復電路，其包含：一 取樣時脈產生器，用來產生—取樣時脈；—取樣器，用來 依據該取樣時脈取樣_輸人於該時序回復電路之無線電訊 ，、並繼而產生-取樣訊號；―内插器，用來依據一當前 時^補償訊號内插該取樣訊號、並繼而產生一内插訊二； 一，錯誤㈣II，絲_該_訊號巾所潛藏之時序 錯决、、並繼而產生一當前時序錯誤訊號，該當前時序錯誤 汛唬為該當前時序補償訊號之函數；一第三延遲器，用來 於、，個該取樣時脈之周期後輸出該時序錯誤偵測器所輪出 仃吩序錯誤訊號，該當前時序錯誤訊號係緊接續於該 月日守序錯誤訊號；一第二減法器，用來將該時序錯誤偵 則所輪出之當前時序錯誤訊號減去該第三延遲器所輪出 1242326 之前行時序錯誤訊號；—向右 號將該第二減法器所產 用來依據-增/減訊 前時序錯誤訊號減去該第^=錯誤_器所輪出之當 訊號向右移位、並繼而^ 所輸出之前行時序錯誤 多工二 微出當前時序錯誤訊號，·- 夕工时，该向右移位器所輪 於入5 #夕 w 械刀田別4序錯誤訊號係 輸入至该多工器之第-輪入端；一向左移位器 多工器所輸出之微分當前時序錯誤訊號向左移位； 延遲盗，用來於一個該取樣時脈之周期後將該多工器所輸 ^之微^前時序錯誤减賴至該多巧之第二輸入 :二：第二比較器’用來比較該時序錯誤摘測器所輸出之 田月纟日才序錯疾訊號與該向左移位器所輸出之向左移位後之 微分當前時序錯誤訊號、並繼而產生該增/減訊號；一增減 器，用來依據該增/減訊號增減該當前時序補償訊號、並繼 而產生接續時序補償訊號，其係緊接續於該當前時序補 偵汛號，一第_延遲器，用來於一個該取樣時脈之周期後 將該增減器所輸出之接續時序補償訊號回授至該增減器； 以及第一比較器，用來比較該第二比較器所輸出之增/ 減訊號與一預定訊號、並繼而控制該多工器擇一地將該第 四延遲器所輸出之微分當前時序錯誤訊號或該向右移位器 所輸出之微分當前時序錯誤訊號輸入至該向左移位器。 在本發明之第二實施例中，該向左移位器可將該多工器 所輸出之微分當前時序錯誤訊號向左移位一個及二個位 11 1242326 元 ^應地，該向右移位器可將該第二減法器所輸出之兮 遲器所輪出之前行時序錯誤訊號向右移位—個及二=延 7Γ 。 儿 本發明之優點係在於，隨著該一哭 產生之時序補償訊號的數謂器所 < 9加，鑲恰序回设電路可蔣 ;曰藏於該㈣祕號巾之日铸料侷限在對胁 之 解調能力之預定時序錯誤範圍内， ^周為之 接於該時序回復電路之後，如此—來，該==電連 地解調該時序回復電路中之内插輯產生之内確 此外，該第二實施财所揭露之時序回復電 =面積遠比該較佳實施例中所揭露之時序回復電路戶;需 狀面積，所以，減地’科二實關帽揭露之斤= =電路之製造成本錢低_錄實關 序回復電路之製造成本 0路之時 【實施方式】 本發明之時序回復電路係以牛頓方法（_細，s method)為基礎而發展出來的。在經過有限次數之重 過後，該時序回復電路可依據—解之賴能力:強^ 12 1242326 將潛藏於内插訊號Yf(kTi)中之時序錯誤侷限在一預定時 序錯誤範圍内，其中該預定時序錯誤係對應於該解調器之 解調能力。 一般而言，牛頓方法係用以求解一多項式/00之近似根 (approximate root)。牛頓方法求解多項式/(x)之近似根之 過程略述如后：/(X)在x = 之泰勒級數（Tayl〇r，SseriM) 為/(xQ +心/(Xq) + /’⑷(式一），假設4艮小，那 麼（式一）可簡寫為/(XQ4^)%/(^) +八式二）；令 你。+七0、及，（式二）可改寫為(式三） /0。） ^ Ύ ε 稱為多項式f(x)的根位置(r00t，s p〇siti〇n)之 償係數（first-order offset);接著，令，以計^ 出緊接續於禮之a ’也就是，£1=_錯；如此繼續下去y 可計算出多項式/W的根位置之第（η+ι)級補償係數 是、=_懲(式四）。由於W…所以，（式四)可改; 為式五)。透過適當地選取〜，牛頓方▲ “ 重覆運算錄⑷之増加、轉_ ^ root)x㈣之/(X)之近似根 、 …、根（rea: 誤議限於，之範圍内近似根與真實极、間之 -預定範圍。 、)與編間之差異係小於 13 1242326 請參閱第2圖，第2圖為本發明之較佳實施_例中—以上 述之牛頓方法而發展出來的時序回復電路5〇 圖。除了包含取檬时脈產生器12、取樣器14、内插哭Η、 以及資料濾波器18外，時序回復電路5〇另包含連接 於資料濾波器18之時序錯誤偵測器52、一電連接^時序 錯誤偵測器52之微分器（differentiator)54、—電連日^於 時序錯誤偵測器52及微分器54之第一除法器如屯—電= 接於第一除法器56及内插器16之第一減法器卯、—電連 接於第一減法器58及内插器16之第一 D型正反器⑶私 nip-fl〇p)60、以及一電連接於第一 D型正反器6〇、第一 減法态58.、及微分器54之第二D型正反器62。本質上 第一 D型正反器60、及第二D型正反器62皆為一^延遲 器（delayer)。 為了方便說明起見’（式五改寫如后： 一默式六) 時序錯誤偵測為52依據一當前（current)時序補償來號 从產生一當前時序錯誤訊號，具體言之，時序錯誤偵測 器52依據當前時序補償訊號凡於執行完畢諸如 '1242326 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a kind of timing recovery circuit (timi ng r⑽y circuit), especially a method based on Newton's method The developed timing recovery circuit. [Prior Art] In a wireless communication system, the radio signal received by a receiver must be properly synchronized before it can be connected to the rear of the receiver. The demodulator is correctly demodulated, and the timing recovery circuit is an electronic circuit that executes the synchronization process. Please refer to Fig. 1. Fig. 1 is a conventional timing recovery. Functional block diagram of circuit 10. The timing recovery circuit 10 includes a sampling clock generator 12, a saropler 14, an interpolator 16, and a data filter ( data filter) 18 〇 The sampling clock generator 12 generates a sampling clock Ts with a period of ts; 1242326 The sampler 14 samples according to the sampling clock Ts-on the helmet / hotline signal X (t), and continues Generate a sampling signal x (mTs); interpolate ρ β -lb u an interpolation interval (interp〇lai: i〇n interpolate the sampling signal x (mTs), and then generate γ_wave filter 18 to filter out the interpolation signal Noise in Y (kTi), and then output the _out ^ interpolation signal YKkTQ to a solution β Α 夂 < fresh state after being electrically connected to the timing recovery circuit 10 for demodulation. Rain has said that in order to mix the demodulation H to correctly demodulate the interpolated signal Yf (kTi) generated by the filtering and wave action of the data waver 18, the timing recovery circuit 10 further includes a timing error detector. (Timing detectorr detectors, and a timing error controller (timing err0r cafe) which is electrically connected between the timing error controller 20 and the interpolator 16. The timing error detector 20 detects the signal hidden in the interpolation Yf⑽) timing error (timing enw), and then generates a "timing error signal e;", the sequence error controller 22 generates a timing compensation (timing-command) signal for controlling the interpolation benefit 16 according to the timing error signal e # In order to reduce the hidden potential as much as possible, the next wave_18 Yf (讯Accordingly, the demodulator can more accurately demodulate the interpolation signal Yf (kTi). Because the timing hidden in the interpolation signal Yf (kTl) output from the timing recovery circuit 10 to the demodulator The magnitude of the error is closely related to whether the demodulator can correctly demodulate the interpolation signal Yf (kT0), specifically, the interpolation signal output from the timing recovery circuit 10 to the demodulator. The smaller the timing error hidden in Yf (kTi), the better the demodulator can correctly demodulate the interpolation signal (MkTi). Therefore, the designers of the known timing recovery circuit 10 have racked their brains with various mathematics Based on the above or physical methods, try to develop a timing recovery circuit that can accurately calculate the timing compensation signal //, and then minimize the timing error hidden in the interpolation signal Yf (kTi). [Summary of the Invention] Therefore, the main object of the present invention is to provide a timing recovery circuit based on the Newton's method, which can reduce the timing error hidden in the interpolation signal Yf (kTi) to The smallest. According to the scope of patent application of the present invention, the present invention discloses a timing recovery circuit developed based on the Newton method, which includes: a sampling clock generator for generating-sampling clock;-a sampler for Sampling according to the sampling clock-inputting the radio signal, and, 麈 in the timing recovery circuit to generate a sampling signal; _ interpolator, which is used to interpolate the sampling signal, An interpolation signal is then generated; one time = an error detector, which detects the timing errors hidden in the interpolation signal and generates a current timing error signal, which is compensated for the current timing error A function of the signal; a differentiator used to generate a 1242326 2 timing error signal, the differential time-phase error signal is the complement: the differential function of the staff signal ... The _ divider is used to divide the = signal by the Differential timing error signal; _th_subtraction cry τ ~ current current timing compensation ^ " σ is used to divide the timing error output of the divider by the differential timing error signal, and then generate-then "Panyu 'is lightly connected to the current timing compensation signal;-the second extension: used to return the first-subtraction connection sequence compensation signal to the first-after-a cycle of the sampling clock- Subtraction m rule: a device used to delay the second crying month after a period of the sampling clock, and input the sequential timing compensation signal of the first subtraction device to the microsecond in the present invention. In the embodiment, the differentiator includes: ―the first time from the cycle of the sampling clock, the timing error signal is turned to the previous timing error signal, and the timing error signal is turned to 誃, ia.莰 Only the signal of timing error at 〇 HAI; a second, please go to state, used to detect the timing error of No. 4 诘 土 西哲 ° »The current day order error output by Guo 2 is delayed by the brother The previous timing error signal output by the controller; minus °. The output of the current timing compensation signal is output from the second delayer, ..., EO + the next day's sequence compensation signal, a second removed state, used to turn the second subtraction cry. The current timing compensation signal is subtracted. The current timing compensation signal output by the second subtractor is subtracted from the previous line. Zhi Zhiding reduced the sequence compensation signal. A first comparator uses 1242326 to output the second subtraction n. The timing compensation amount minus the previous timing compensation signal is compared with the -predetermined value ... the fourth delayer is used to rotate the differential timing error signal after a period of the sampling clock; and-the multiplexer According to the comparison result between the first comparator and the current timing compensation signal minus the other sequence compensation signal and the predetermined value, the current output of the second divider (the current timing compensation signal minus the The timing compensation can be performed) divided by the current phase compensation signal minus the timing compensation signal) or the differential timing error signal output by the fourth and the first divider is output to the first divider. According to the patent scope of the present invention, the present invention further discloses a timing recovery circuit also developed based on the Newton method, which includes: a sampling clock generator for generating-sampling clock;-sampling Device for sampling and inputting the radio signal of the timing recovery circuit according to the sampling clock, and then generating a -sampling signal; an interpolator for interpolating the sampling signal according to a current time compensation signal, Then, an interpolation signal II is generated; one, error II, the timing of the hidden signal signal is wrong, and then a current timing error signal is generated, and the current timing error is flooded into the current timing compensation signal. Function; a third delayer is used to output the sequence error signal rotated by the timing error detector after the period of the sampling clock, and the current timing error signal is immediately followed by the day and month. Sequence error signal; a second subtractor, used to subtract the current sequence error signal rotated out by the third delayer 1242326 from the current sequence error rotation signal;-to The right number is used to subtract the ^ = error_rounder when the signal produced by the second subtractor is used to correct the timing error signal before the signal is shifted to the right, and then ^ output the previous line timing The error multiplexer 2 is slightly out of the current timing error signal. ·-When working on the evening, the right shifter turns into the 5th round. # 夕 w 刀 刀 田 别 4 sequence error signal is input to the first round of the multiplexer. End; the differential current timing error signal output by the left-shifter multiplexer is shifted to the left; delay stealing is used to output the ^ micro-previous timing of the multiplexer after a period of the sampling clock The error is reduced to the second input of the multiplicity: two: the second comparator 'is used to compare the sequence error signal of Tianyue the next day output by the timing error picker and the output of the left shifter. After shifting to the left, the differential current timing error signal is generated, and then the increase / decrease signal is generated; an increase / decrement device is used to increase or decrease the current timing compensation signal according to the increase / decrease signal, and then generate a continuous timing compensation signal It is a successor to the current timing compensation detection flood number, a first delayer, used to After the period of the sampling clock, the continuous timing compensation signal output from the increase / decrement device is fed back to the increase / decrement device; and a first comparator is used to compare the increase / decrease signal output from the second comparator with a Predetermining a signal and then controlling the multiplexer to selectively input the differential current timing error signal output from the fourth delayer or the differential current timing error signal output from the right shifter to the left shifter . In the second embodiment of the present invention, the left shifter may shift the differential current timing error signal output by the multiplexer to the left by one and two bits. 11 1242326 Yuan correspondingly, the right shift The bit device can shift the timing error signal of the previous line output by the second subtracter to the right by one and two = 7Γ. The advantage of the present invention is that, with the timing compensation signal generated by the cry, the digital predicator < 9 plus, the set-back sequence circuit can be set; the day casting material is hidden in the secret towel. Within a predetermined timing error range of the threat demodulation capability, ^ week is connected to the timing recovery circuit, so-here, the == is electrically demodulated by the interpolation in the timing recovery circuit. Indeed, the timing recovery electricity disclosed by the second implementation financial institution = the area is much larger than the timing recovery circuit households disclosed in the preferred embodiment; the need-shaped area is reduced by the amount of ground exposed by the second section of the key = = The manufacturing cost of the circuit is low. _ When the manufacturing cost of the record-sequence recovery circuit is 0. [Embodiment] The timing recovery circuit of the present invention is developed based on the Newton method (s method). After a limited number of repetitions, the timing recovery circuit can be based on the ability to solve the problem: strong ^ 12 1242326 Limits the timing errors hidden in the interpolation signal Yf (kTi) to a predetermined timing error range, where the predetermined The timing error corresponds to the demodulation capability of the demodulator. In general, Newton's method is used to solve the approximate root of a polynomial / 00. The Newton method to solve the approximate root of the polynomial / (x) is briefly described as follows: / (X) Taylor series (Taylor, SseriM) at x = is / (xQ + heart / (Xq) + / '⑷ (Formula 1), assuming that 4gen is small, then (Formula 1) can be abbreviated as / (XQ4 ^)% / (^) + Eight Form 2); let you. +70, and (Formula 2) can be rewritten as (Formula 3) / 0. ) ^ Ύ ε is called the first-order offset of the root position (r00t, sp0siti〇n) of the polynomial f (x); then, let ^ be a ^ followed by ritual a ', that is, £ 1 = _wrong; in this way, y can calculate the (η + ι) th level compensation coefficient of the root position of the polynomial / W, = _ punishment (formula 4). Since W ..., (Formula 4) can be modified; it is Formula 5). By appropriately selecting ~, Newton's square ▲ "Addition of repeated operations, ⑷ ^ root) x ㈣ of / (X) approximate root, ..., root (rea: misunderstanding is limited to the range of approximate root and real The difference between the poles and between the predetermined ranges is less than 13 1242326 Please refer to Figure 2, which is a preferred embodiment of the present invention. _ In the example-the timing response developed by the Newton method described above. The circuit 50. In addition to the clock generator 12, the sampler 14, the interpolator, and the data filter 18, the timing recovery circuit 50 also includes a timing error detector connected to the data filter 18. 52. An electrical connection ^ differentiator 54 of the timing error detector 52,-electrical continuous ^ the first divider of the timing error detector 52 and the differentiator 54 such as Tun-electricity = connected to the first division The first subtractor 卯 of the divider 56 and the interpolator 16, the first D-type flip-flop 60 (electrically connected to the first subtractor 58 and the interpolator 16), and an electrical connection At the first D-type flip-flop 60, the first subtraction state 58., and the second D-type flip-flop 62 of the differentiator 54. Essentially The first D-type flip-flop 60 and the second D-type flip-flop 62 are both a delayer. For convenience of description, '(Formula 5 is rewritten as follows: a silent style 6) Timing error detection For 52, a current timing error signal is generated according to a current timing compensation signal. Specifically, the timing error detector 52 is based on the current timing compensation signal.
Early-Late、Zero-Crossing、及Μ紐等演算法後，產生舍 前時序錯誤訊號ΦΟ ;微分器54微分時序錯誤備測哭52 14 1242326 所產生之當前時序錯誤訊號纷並繼而產生—微分當 序錯誤訊號如；第-除法器56將當前時序錯誤訊號細除 以微分當前時序錯誤訊號心、並將一相除結果勃專送至 第一減法器58 ;第-減法器卯從第- D型正反器)60所輪 出之當前時序補償訊號凡中減去相除結果器、並繼而產 生=續（SUCCeeding)時序補償訊號凡+^係 一減法器58所產生之後續時序補償訊號从+1回授 至弟一減法器58’反面言之’在第一減法器別從當前時 序補償訊U減去相除結果怒、並繼而產生後續時序 補償訊號凡+1之前，第一 D刑 訊Μ送至第—ip 58 τ η已將當前時序補償 减法58 了；弟二d型正反器62於— 個取樣時脈T S過播膝笛_ rv ? 〇ty 序補償笊笋^僂、、，、一聖正反态60所產生之後續時 仏況U运至微分器54，同樣地，反面言之，在 —D型正^6G將當前時序補償訊^傳送至第一減法器 之同時，第二D型正反哭 ° 序補償值、、， to62娜料（P⑽dlng)時 接綠 $至微分11 54，#前時序補償訊號Μ系緊 接、'灵於前行時序補償訊號〜。 /、 ^本發明之較佳實施例中，微分器Μ包含一電連接於 守序錯誤躺器52及第一除法器56之第三d型正反器、 15 1242326 64、一電連接於第三D型正反器64之第二減法器66、一 電連接於第二減法器66之第二除法器68、一電連接於第 一及第二D型正反器60及62之第三減法器76、一電連接 於第三減法器76之第一比較器72、一電連接於第一除法 器56之第四D型正反器70、以及一電連接於第二除法器 68、第一比較器72、及第四D型正反器70之多工器74。 本質上，第三D型正反器64、及第四D型正反器70亦皆 為一種延遲器。 第三及第四D型正反器64及70、第二及第三減法器66 及76、以及第二除法器68之運作過程係分別相同於第一 及第二D型正反器60及62、第一減法器58、以及第一除 法器56之運作過程，於茲不贅，其中，第二除法器68所 產生之^等效上係等於微分當前時序錯誤訊號Early-Late, Zero-Crossing, and New Zealand algorithms generate timing error signals before rounding; Φ0; differentiator 54 differential timing errors are ready to test; 52 14 1242326 The current timing error signals are generated one after another—differential when The sequence-error signal is as follows; the first-divider 56 divides the current timing-error signal by a derivative of the current-time-error error signal, and sends the divided result to the first subtractor 58; the first-subtractor, from the first-D Type flip-flop) The current timing compensation signal rotated by 60 is subtracted from the divider and then generated = SUCCeeding timing compensation signal + + is a subsequent timing compensation signal generated by a subtractor 58 from +1 feedback to Brother One Subtractor 58 'On the other hand' Before the first subtractor subtracts the division result from the current timing compensation signal U, and then generates a subsequent timing compensation signal where +1, the first D torture Μ is sent to —ip 58 τ η has subtracted 58 from the current timing compensation; the second d-type flip-flop 62 has over-sampled the clock flute _ rv? 〇ty sequence compensation 笊 笊 ,, ,, the follow-up situation of a holy positive and negative state 60 is transported to The differentiator 54, similarly, on the other hand, while -D type positive 6G transmits the current timing compensation signal ^ to the first subtractor, the second D type positive and negative cryo order compensation values, ,,, and 62 (P⑽dlng) Connect green $ to differential 11 54, # before timing compensation signal M is immediately followed by 'Lingyu ahead of time timing compensation signal ~. /, ^ In a preferred embodiment of the present invention, the differentiator M includes a third d-type flip-flop, which is electrically connected to the sequence error rectifier 52 and the first divider 56, 15 1242326 64, and an electrical connection to the third A second subtractor 66 of the three D-type flip-flop 64, a second divider 68 electrically connected to the second subtractor 66, a third of the first and second D-type flip-flops 60 and 62 A subtractor 76, a first comparator 72 electrically connected to the third subtractor 76, a fourth D-type flip-flop 70 electrically connected to the first divider 56, and a second divider 68 electrically connected, The first comparator 72 and the multiplexer 74 of the fourth D-type flip-flop 70. In essence, the third D-type flip-flop 64 and the fourth D-type flip-flop 70 are also a type of retarder. The operations of the third and fourth D-type flip-flops 64 and 70, the second and third subtractors 66 and 76, and the second divider 68 are the same as those of the first and second D-type flip-flops 60 and 60, respectively. 62. The operation processes of the first subtractor 58 and the first divider 56 are not repeated here. Among them, the ^ generated by the second divider 68 is equivalent to the differential current timing error signal.
Hi 心/Ο;第一比較器72比較當前時序補償訊號凡是否相同於 前行時序補償訊號，也就是比較當前時序補償訊號//„與 前行時序補償訊號/^間之差是否等於” 〇” ；多工器74依 據第一比較器72比較當前時序補償訊號％與前行時序補償 訊號〜間之差是否等於” 0”之比較結果選擇性地將第二 除法器68所產生之微分當前時序錯誤訊號A/Ο或第四D型 正反器70所輸出之微分前行時序錯誤訊號A/vJ傳送至第 一除法器56，其中，微分當前時序錯誤訊號4凡)係緊接續 16 I242326 於链分前行時序錯誤訊號e(/Vi)。舉例來說， 7 D 米一比較哭 2比較出當前時序補償訊號凡係相同於前行時序補俨』^ 义〜！，多工器74將微分前行時序錯誤訊號e(u傳送至#唬 除法器56 ;反之，若第-比較器72比較出當前時序】 汛號八係不相同於前行時序補償訊號凡^，多工器M 當前時序錯誤訊號e("j傳送至第一除法器5β。 '刀 剷已言之，隨著η之增加，牛頓方法可求解出八）之近 似根χ„+1、而/D與/(U間之差異係小於該預定 ι闺，相應 地，在經過有限次數之運算過後，以牛頓方法而發展出來 之時序回復電路50可將潛藏於内插訊號Yf(kTi)中之時序 錯誤偶限在對應於該解調器之解調能力之預定時序辞，範 圍内，如此一來，該解調器便可正確地解調時序回復電路 50中之内插器16所產生之内插訊號Yf(kTi) 了。 在時序回復電路50中，第一除法器56係用來將當前時 序錯誤訊號e(凡)除以微分當前時序錯誤訊號(或微分前 行時序錯誤訊號A/v!)，視第一比較器72比較當前時序補 償訊號从與前行時序補償訊號/^間之差是否等於，，〇”之 比較結果而定）、並將一相除結果(或)傳详5楚 一減法器58，另外，第二除法器68係用來將第二減法器 66所產生之（ΦΟ-Φ^))除以第三減法器76所產生之 17 1242326 (凡、並繼而產生另一相除結果^，也就是微 分當前時序錯誤訊號4凡）。然而’在數位數字運算之過程 中，一第一數位數字（例如微分當前時序錯誤訊號A/Ο)乘 以2n等效上係等於該第一數位數字向左平移n個位元，另 一方面，一第二數位數字除以f等效上係等於該第二數位 數字向右平移η個位元，因此，時序回復電路50可依據此 數位數字所具有之特殊性質而進一步地被簡化。 請參閱第3圖，第3圖為本發明之第二實施例中一時序 回復電路100之功能方塊圖。除了包含取樣時脈產生器 工2、取樣器14、内插器16、資料濾波器18、時序錯誤偵 測器52、第一 D型正反器60、第三D型正反器64、第二 減法器66、第四D型正反器70、第一比較器72、及多工 器74外，時序回復電路1〇〇另包含一電連接於多工器74 之向左移位器102、一電連接於向左移位器1〇2及時序錯 誤偵測器52之第二比較器104、一電連接於第一 D型正反 器60、第二比較器104、及内插器16之增減器 (increment/decrement)106、以及一電連接於第二減法器 66及多工器74間之向右移位器1〇8。 向左移位器102將微分當前時序錯誤訊號心从)向左平移 一位兀及二位元、並繼而產生一二倍微分當前時序錯誤訊 18 1242326 及一四倍微分當前時序錯誤訊號上，其中，二倍 ^刀畜則時序錯誤訊號心2係二倍於微分當前時序錯誤 ίίΐίΤ而四倍微分當前時序錯誤訊號如“係四倍於微 1Ϊ:時序錯誤訊號6(/〇，此外，向左移位器1〇2另將微 刀田則日守序錯誤訊號如、二倍微分當前時序錯誤訊號 :(二〆及四倍微分當前時序錯誤訊號4),4分別乘以（—υ、 產生—負微分當前時序錯誤訊號〜山、—負二倍微 :口田刖日守序錯誤訊號‘丄2、及一負四倍微分當前時序錯誤 汛唬</〇〜，第二比較器1〇4比較向左移位器1〇2所產生之 各個時序錯誤訊號（如二倍微分#前時序錯誤訊號心2及 四倍微分當前時序錯誤訊號心*等）與當前時序錯誤訊號 ΦΟ間之大小、並繼而產生一增/減訊號+/—;增減器1〇6 依據第二比較器丨04所產生之增/減訊號+/—增減當前時序 補償訊號凡、並繼而產生後續時序補償訊號& ;第一比較 為72比較增/減訊號+/—是否為一不變訊號” 〇” ，增減器 106於接收到不變訊號” 時，不會對當前時序補償訊號 凡增減任何數值，換言之，增減器1〇6於接收到不變訊 號0時所產生之後續時序補償訊號凡+1係等於當前時序 補儐甙號凡，向右移位益108依據增/減訊號+/—將第二減 法器66所產生之（φο-φ^))向右平移〇位元、一位元、或 二位元、並繼而產生微分當前時序錯誤訊號以从）；多工器 74依據第一比較器72比較增/減訊號+/—是否為不變訊 號0之比較結果選擇性地將向右移位器1〇8所產生之 19 1242326 知支刀田月ίι時序錯誤訊號e(A)或第四1)型正反器所輸出之 微料行日铸錯誤訊號〜傳送至向左移位器⑽。舉例 來广，右第一比較器72比較出增/減訊號+/-為不變訊 唬0 ，多工器74將微分前行時序錯誤訊號e(//ni)傳送至 向左移位器102 ;反之’若第一比較器72比較出增/減訊 就+/-並非不變訊號” Q” ’多工器74將微分當前時序錯誤 訊號4/0傳送至向左移位器1〇2。 扦序回復電路1〇〇之運作過程說明如后： 田比較出g如日$序錯誤訊號“凡)係仍大於四倍微分當 w時序錯誤訊號時，第二比較器1〇4產生一四倍 增加訊號” +4” ，增減器106於接收到四倍增加訊 就+4後’將當前時序補償訊號仏減少四個切片時 間Tchip、並繼而產生等於（當前時序補償訊號凡—四個切 片時間Tchip)之後續時序補償訊號‘，而向右移位器 108於接收到四倍增加訊號，，+4,，後，將第二減法器 66所接下來產生之（,(从+1)—向右平移二位元、並繼 而產生一微分接續時序錯誤訊號4八+1)，其中接續時序 錯誤訊號φ/„+1)係時序錯誤偵測器52依據後續時序補 仏訊號乂+1所產生之接續時序錯誤訊號e(^^)，而微分接 績時序錯誤訊號e (凡+1)係緊接續於微分當前時序錯誤訊 號4/0。此外，由於第一比較器72比較出增/減訊號 +/〜（等於四倍增加訊號” +4”）並非不變訊號，，〇” ， 20 1242326 因此，多工态74將向右移位器ι〇8所產生之微分接續 時序錯誤訊號4八+1)傳送至向左移位器1〇2 ; (2) 當比較出當前時序錯誤訊號</〇係介於四倍微分當前 時序錯誤訊號^仏‘與二倍微分當前時序錯誤訊號 A/O,2之間時，第二比較器104產生一二倍增加訊 號’’ +2” ，增減器1〇6於接收到二倍增加訊號，，+2” 後，將當前時序補償訊號a減少二個切片時間Tchip、並 繼而產生等於（當前時序補償訊號凡—二個切片時間Hi heart / 〇; The first comparator 72 compares whether the current timing compensation signal is the same as the previous timing compensation signal, that is, compares whether the current timing compensation signal // „and the previous timing compensation signal / ^ are equal to” 〇 The multiplexer 74 compares the difference between the current timing compensation signal% and the previous timing compensation signal ~ according to the first comparator 72 to determine whether the difference between the timing compensation signal and the previous timing compensation signal is equal to "0". The timing error signal A / 0 or the differential forward timing error signal A / vJ output from the fourth D-type flip-flop 70 is transmitted to the first divider 56. Among them, the differential current timing error signal 4 where) is followed by 16 I242326. The timing error signal e (/ Vi) is forwarded on the chain. For example, 7 D meters compares to cry 2 and compares the current timing compensation signal. It is the same as the previous timing compensation signal. "^ ~~, multiplexer 74 The differential forward timing error signal e (u is transmitted to the #blatter divider 56; otherwise, if the current timing is compared by the -comparator 72] The eighth line of the flood number is not the same as the forward timing compensation signal where ^, multiplexer M Current timing error signal e (" j sent to A divider 5β. 'The shovel has said that with the increase of η, Newton's method can solve the approximate root of χ) χ „+1, and the difference between / D and / (U is smaller than the predetermined one, Correspondingly, after a limited number of operations, the timing recovery circuit 50 developed by the Newton method can even limit the timing error hidden in the interpolation signal Yf (kTi) to the demodulation capability corresponding to the demodulator. Within the predetermined timing range, the demodulator can correctly demodulate the interpolation signal Yf (kTi) generated by the interpolator 16 in the timing recovery circuit 50. In the timing recovery circuit 50, The first divider 56 is used to divide the current timing error signal e (when) by the differential current timing error signal (or the differential previous line timing error signal A / v!), And compare the current timing compensation signal with the first comparator 72 From the difference between the timing compensation signal and the previous line, the difference is equal to ， 0 ″), and the result of the division (or) is passed to the 5th divider 58, and the second divider 68 Is used to divide (ΦΟ-Φ ^)) produced by the second subtractor 66 by the third subtractor 76 The generated 17 1242326 (where, and then produces another division result ^, which is the differential current timing error signal 4 Fan). However, in the process of digital calculation, a first digital number (such as differential current timing error signal A / Ο) multiplied by 2n is equivalent to the first digit shifted n bits to the left, on the other hand, a second digit divided by f is equivalent to the second digit shifted to the right η bits, therefore, the timing recovery circuit 50 can be further simplified according to the special properties of the digital figure. Please refer to FIG. 3, which is a timing recovery circuit 100 in the second embodiment of the present invention. Function block diagram. In addition to the sampling clock generator 2, the sampler 14, the interpolator 16, the data filter 18, the timing error detector 52, the first D-type flip-flop 60, the third D-type flip-flop 64, the first In addition to the two subtractors 66, the fourth D-type flip-flop 70, the first comparator 72, and the multiplexer 74, the timing recovery circuit 100 further includes a left shifter 102 electrically connected to the multiplexer 74. A second comparator 104 electrically connected to the left shifter 102 and the timing error detector 52, a second comparator 104 electrically connected to the first D-type flip-flop 60, the second comparator 104, and an interpolator An increment / decrement 106 of 16 and a right shifter 108 which is electrically connected between the second subtractor 66 and the multiplexer 74. The left shifter 102 shifts the differential current timing error signal to the left by one bit and two bits, and then generates one or two times the differential current timing error signal 18 1242326 and one or four times the differential current timing error signal. Among them, two times the timing error signal heart 2 is twice as different as the current timing error, and four times the current timing error signal as differential is "four times as long as the time difference 1": timing error signal 6 (/ 〇, in addition, to The left shifter 102 also multiplies the micro-flight field and the sequence-following error signal such as, twice the differential current timing error signal: (two and four times the differential current timing error signal 4), and 4 is multiplied by (—υ, Generated-negative differential current timing error signal ~ mountain,-negative double differential: Koda Koriichi day-order error signal '丄 2, and a negative quadruple differential current timing error flood blunt / / ~ ~, the second comparator 1 〇4 Compare each timing error signal generated by the left shifter 102 (such as 2 times differential # before timing error signal heart 2 and 4 times differential current timing error signal heart *) with the current timing error signal ΦΟ. Up / down No. +/-; increase / decrement device 106 According to the increase / decrease signal generated by the second comparator 丨 04 +/- increase or decrease the current timing compensation signal, and then generate a subsequent timing compensation signal &; the first comparison is 72 compares the increase / decrease signal +/— whether it is a constant signal “〇”. When the increase / decrement device 106 receives the constant signal ”, it will not increase or decrease any value for the current timing compensation signal. In other words, the increase / decrement device 1 06 The subsequent timing compensation signal +1 generated when the constant signal 0 is received is equal to the current timing compensation signal, which shifts to the right. 108 According to the increase / decrease signal +/— the second subtractor (Φο-φ ^) generated by 66 is shifted to the right by 0 bits, one bit, or two bits, and then a differential current timing error signal is generated to follow); the multiplexer 74 compares according to the first comparator 72 Increase / decrease signal +/— Whether the comparison result is a constant signal 0 Selectively shifts the right shifter 1 0 to 19 1242326 to know the timing error signal e (A) or the fourth 1 The micro-material cast error signal output by the) type flip-flop is transmitted to the left shifter ⑽. For example, the right first comparator 72 compares the increase / decrease signal +/- 0 to the constant signal, and the multiplexer 74 transmits the differential forward timing error signal e (// ni) to the left shifter. 102; Conversely, if the first comparator 72 compares the increase / decrease signal, +/- is not a constant signal. "Q" 'The multiplexer 74 transmits the differential current timing error signal 4/0 to the left shifter 1. 2. The operation process of the sequence recovery circuit 100 is explained as follows: Tian compares g as the daily order error signal "everything" is still greater than four times the differential. When w timing error signal, the second comparator 104 generates a four. Multiplying the signal “+4”, the increaser 106 reduces the current timing compensation signal 仏 by four slice times Tchip after receiving a four-fold increasing signal +4, and then generates an equal to (the current timing compensation signal where—four The subsequent timing compensation signal of the slice time Tchip), and the right shifter 108 receives a four-fold increase signal, +4 ,, and then generates the next (, (from +1 ) —Panning two bits to the right, and then generating a differential connection timing error signal 4-8 + 1), where the connection timing error signal φ / „+ 1) is the timing error detector 52 according to the subsequent timing compensation signal 乂 + The sequential timing error signal e (^^) generated by 1, and the differential timing timing error signal e (where +1) is immediately following the differential current timing error signal 4/0. In addition, since the first comparator 72 compares the increase / decrease signal + / ~ (equal to a four-fold increase signal "+4") is not a constant signal, 0 ", 20 1242326. Therefore, the multiplexing mode 74 will shift to the right The differential connection timing error signal generated by the device ι〇8 is sent to the left shifter 102; (2) When the current timing error signal is compared < / 〇 is between four times the differential current timing When the error signal ^ 仏 'and the double differential current timing error signal A / O, 2, the second comparator 104 generates a doubled signal "+2", and the doubler 106 receives twice. Increase the signal. After +2 ”, reduce the current timing compensation signal a by two chip times Tchip, and then generate equal to (the current timing compensation signal where—two chip times
Tchip)之後續日寸序補償訊號凡+1，而向右移位器於接φ 收到二倍增加訊號” +2”後，將第二減法器66所產生 之（ )向右平移一位元、並繼而產生微分接續 時序錯誤訊號4八+1)。此外，由於第一比較器72比較出 增/減訊號+/-(等於二倍增加訊號” +2”）並非不變訊 唬0 ，因此，多工器74將向右移位器1〇8所產生 之微分接續時序錯誤訊號e，(〜1：)傳送至向左移位器 102 ； ^ (3) 當比較出當前時序錯誤訊號</〇係介於二倍微分當前 時序錯誤訊號e⑺丄與微分當前時序錯誤訊號之間 時，第二比較器1〇4產生--倍增加訊號，，+1，，，增 減裔106於接收到一倍增加訊號” +1”後，將當前時 序補償訊號A減少一個切片時間Tehip、並繼而產生 (當前時序補償訊號凡-一個切片時間TcMp)之後續時序 補償訊號/^+1，而向右移位器1〇8於接收到—倍增加訊 21 1242326 號’’ +Γ後，將第二減法器66所產生之（^^)1(^) 向右平移◦位元（也就是不作任何的位元移位運算）、 並繼而產生微分接續時序錯誤訊號。此外，由於 第一比較器72比較出增/減訊號+/_(等於一倍增加訊 號” +Γ )並非不變訊號，，0” ，因此，多工器74將向 右移位器108所產生之微分接續時序錯誤訊號傳 送至向左移位器1 〇 2 ; (4)當比較出當前時序錯誤訊號係介於微分當前時序錯 誤訊號與負微分當前時序錯誤訊號心义)_1時，第二 比較器104產生不變訊號，，〇，，，增減器1〇6於接收到 不變訊號” 0” 不對當前時序補償訊號八增減任何 數值、並繼而產生等於當前時序補償訊號凡之後續時 序補償訊號凡+1，而向右移位器1〇8於接收到不變訊 號” 〇，，後，對第二減法器66所產生之（也不 作任何的位兀移位運算（因為向右移位器1〇8於接收到 不變訊號，，0，，後，其所產生之微分接續時序錯誤訊號 e(〜0根本不會被多工器74傳送至向左移位器1〇2，所 以，向右移位器108也就不必在（⑽一⑽）之位元移 位運异上浪費任何心力了）、並繼而產生微分接續時序 錯誤訊號4凡+1)。此外，由於第一比較器72比較出增/ 減訊號+/-(等於不變訊號，，『）為不變訊號”『，因 =，多工器74將第四_正反器、7〇戶斤產生之微分當 剞日寸序錯決δίΐ號e ("J傳送至向左移位器1 〇 2 ; 22 1242326 ⑸當比較出當前時序錯誤訊號侧系介於負微分當前時 序錯誤訊號·與負二倍微分當前時序錯誤訊號 之間日寸’第二比較器1〇4產生_一倍減少訊 號’’ -Γ :增減器106於接收到一倍減少訊號，，” 後，將當前時序補償訊U加-個切㈣間W並 繼而產生料（當前時序補償訊號从+-個切片時間 ―)之後、序補償訊號〜，而向右移位g⑽於接 收到一倍減少訊號，，-1，，後，將第二減法器66所產生 之（札、):)）向^平移〇位元（也就是不作任何的位 疋移位運π)、並繼而產生微分接續時序錯誤訊號 此外，由於第一比較器72比較出增/減訊號 * (等於倍減少訊號，，]，，）並非不變訊號，，〇，，， S此，多工器74將向右移位器1〇8所產生之微分接續 =序錯誤訊號<)傳送至向左移位器102 ; a車乂出田如日才序錯誤訊號e〇„)係介於負二倍微分當 二時序錯㉔訊號e (仏與貞四倍微分當前時序錯誤訊 =(/〇:之間時’第二比較器1〇4產生一二倍減少訊 少 2 ，增減器106於接收到二倍減少訊號”一2” 將當前時序補償訊號从增加二個切片時間Tchip、並 繼而產生等於（當前時序補償訊號二個切片時間 hlP)之後績時序補償訊號凡+1，而向右移位器108於接 收到二倍減少訊號，，-2”後，將第二減法器66所產生 向右平移一位元、並繼而產生微分接續 23 1242326 時序錯誤訊號此外，由於第一比較器72比較出 增/減訊號(等於二倍減少訊號，，—2”）並非不變訊 说° ’因此，多工器74將向右移位器1〇8所產生 之微分接續時序錯誤訊號，坎+1)傳送至向左移位器 102 ;以及 (7)當比較出當前時序錯誤訊號ΦΟ係小於負四倍微分當 刖日才序錯誤訊號^時，第二比較器1〇4產生一四倍 減少訊號’’〜4” ，增減器1〇6於接收到四倍減少訊 號-4”後，將當前時序補償訊號凡增加四個切片時 間Tchip、並繼而產生等於（當前時序補償訊號凡+四個切 片時間Tchip)之後續時序補償訊號凡+1，而向右移位器 108於接收到四倍減少訊號，，-4”後，將第二減法器 66所產生之（e(X+1)-♦))向右平移二位元、並繼而產生 微刀接、’日T序錯误訊號e (凡+1)。此外，由於第一比較器 72比較出增/減訊號+/—(等於四倍減少訊號，，—4”）並 非不變訊號” 〇” ，因此，多工器74將向右移位器1〇8 所產生之微分接續時序錯誤訊號^αΛ+1)傳送至向左移位 器 102 〇 由於向左移位器1〇2及向右移位器1〇8可藉由將輸入其 内之訊號（例如微分當前時序錯誤訊號心及（也Η⑹） 等）連接至複數個受控於增/減訊號+/_之多工器之方式加 以貝施’所以，除了取樣時脈產生器U、取樣器14、内插 24 1242326 器16、以及資料濾波器18外，時序回復電路100所包含 者大多為占據較小面積之多工器及比較器。反觀，除了取 樣時脈產生器12、取樣器14、内插器16、以及資料濾波 器18外，時序回復電路50所包含者卻為需占據相當大面 積之除法器（例如第一及第二除法器56及68)。請參閱第1 表及第2表，第1表列出一除法器於包含不同位元數時所 需占據之面積（gate count)，第2表列出一比較器於包含 不同位元數時所需占據之面積。由第1表及第2表中可明 顯地看出，當包含相同之位元數時（例如該除法器係將一 16位元之數字除以一 8位元之數字，而該比較器比較二16 位元之數字），該除法器所需占據之面積（1866. 7)竟是該比 較器所需占據之面積（121)的15倍之多，換言之，其内包 含移位器及比較器之時序回復電路100所需占據之面積係 遠小於其内包含除法器之時序回復電路50所需占據之面 積。 在本發明之第二實施例中，向左移位器102係將微分當 前時序錯誤訊號向左平移一位元及二位元、並繼而產 生相關之時序錯誤訊號。當然，本發明之時序回復電路中 之向左移位器也可將微分當前時序錯誤訊號4/0向左平移 任意個位元、並繼而產生相關之時序錯誤訊號，惟需注意 的是，該時序回復電路中之向右移位器之位元移位動作則 必需對應於該向左移位器之位元移位動作。 25 1242326 此外，由於時序回復電路50中之第二除法器68係將第 二減法器66所輸出之（妙至多除以二或四，視第三 減法為76所輸出之（八―〜）而定，相應地，第二除法器68 僅需占據很小的面積即可，因此，時序回復電路⑽中之 向右移位③1G8可以第二除法器68所取代，時序回復電路 100中之第二除法器68可將第二減法器66所輸出之 (♦”)-<〜)）除以第二比較器104所輸出之增/減訊號。 相較於習知技術，本發明之時序回復電路係以牛頓方法 而發展出來的’應科頓方法之可準確地求解—多項式之 2性’辦序回復電路亦可將其所產生之内插訊號笊㈤ 中所，藏之時序錯誤侷限在—預定時序錯誤範_，其中 =貝疋錯1^係對應於連接於該時序回復電路後之解調 調能力’如此一來，該解調器便可正確地解調内插 ^〇HTl)。在本發明之較佳實施例中，時序回復電路 Hrf鼓面積之除法器。“，在本發明之第 回復電路100係包含僅需占據較小面積 序口; ，因此’其内包含移位肢比較器之時 之時相復其心含除法器 路100之制m 據積，相應地，時序回復電 本。心成本也會遠小於時序回復電路5〇之製造成 26 1242326 【圖式簡單說明】 第1圖為習知一時序回復電路之功能方塊圖。 第2圖為本發明之較佳實施例中一時序回復電路之功能方 塊圖。 第3圖為本發明之第二實施例中一時序回復電路之功能方 塊圖。 第1表列出一除法器於包含不同位元數時所需占據之面 積。 第2表列出一比較器於包含不同位元數時所需占據之面 積。 【主要元件符號說明】 10 、 50 、 時序回復電路 12 取樣時脈產生器 100 14 取樣器 16 内插器 18 資料濾波器 20、52 時序錯誤偵測器 22 時序錯誤控制 54 微分器 器 56 第一除法器 58 第一^咸法器 27 1242326 60 第一 D型正反 62 第二D型正反器 器 64 第三D型正反 66 第二減法器 器 68 第二除法器 70 第四D型正反器 72 第一比較器 74 多工器 76 第三減法器 102 向左移位器 104 第二比較器 106 增減器 108 向右移位器 28Tchip) 's subsequent day-sequence compensation signal is +1, and the right shifter shifts the () generated by the second subtractor 66 to the right by one after receiving the doubled signal “+2” from φ Yuan, and then generates a differential connection timing error signal (48 + 1). In addition, since the first comparator 72 compares the increase / decrease signal +/- (equal to double the increase signal "+2") is not a constant signal bluff 0, therefore, the multiplexer 74 will shift to the right by 108. The generated differential connection timing error signal e, (~ 1 :) is transmitted to the left shifter 102; ^ (3) When comparing the current timing error signal < / 〇 is between twice the differential current timing error signal e⑺ Between 丄 and the differential current timing error signal, the second comparator 104 generates a doubling signal, +1, +1, and increases or decreases 106. After receiving the doubling signal "+1", it will The timing compensation signal A is reduced by one slice time Tehip, and a subsequent timing compensation signal (the current timing compensation signal where-one slice time TcMp) is subsequently generated / ^ + 1, and the right shifter 108 receives a fold increase. After the signal No. 21 1242326 + Γ, the (^^) 1 (^) produced by the second subtractor 66 is shifted to the right by ◦ bits (that is, no bit shift operation is performed), and then differential is generated. Connect to timing error signal. In addition, since the first comparator 72 compares the increase / decrease signal + / _ (equal to double the increase signal "+ Γ") is not a constant signal, 0 ", the multiplexer 74 will shift the signal to the right by 108. The generated differential connection timing error signal is transmitted to the left shifter 1 〇 2; (4) When it is compared that the current timing error signal is between the differential current timing error signal and the negative differential current timing error signal)) _ 1, The two comparators 104 generate a constant signal, 0 ,, and the incrementer 10 receives a constant signal "0". It does not add or subtract any value to the current timing compensation signal, and then generates a signal equal to the current timing compensation signal. The subsequent timing compensation signal is +1, and the right shifter 108 receives the constant signal "0", and then generates the second subtracter 66 (and does not perform any bit shift operation (because After receiving the constant signal, 0, 0, the right shifter 108 generates a differential connection timing error signal e (~ 0 will not be transmitted to the left shifter 1 by the multiplexer 74 at all). 〇2, so the right shifter 108 does not have to be The element shifts waste any effort), and then generates a differential connection timing error signal (4 where +1). In addition, because the first comparator 72 compares the increase / decrease signal +/- (equal to the constant signal ,, ") Is a constant signal" ", because =, the multiplexer 74 sends the differential of the fourth _ flip-flop and the 70-kilogram to the next day. The sequence number e (" J is shifted to the left) Bit 1 〇 2; 22 1242326 ⑸ When comparing the current timing error signal side is between the negative differential current timing error signal and the negative double differential current timing error signal. The second comparator 1104 generates _ Double-decreasing signal "-Γ: After receiving double-decreasing signal," incrementer 106 "adds the current timing compensation signal U to a time interval W and then generates the material (the current timing compensation signal changes from +- After slicing time ―), the sequence compensation signal ~ is shifted to the right to reduce the received signal by doubling the signal, -1, and after that, the (Za,) :)) generated by the second subtractor 66 is shifted toward ^ Shift 0 bits (that is, do not shift any bits), and then generate a differential connection timing error In addition, since the first comparator 72 compares the increase / decrease signal * (equal to the multiply decrease signal ,,] ,,) is not a constant signal ,,,,,,, and S, the multiplexer 74 will shift to the right. Differential continuity generated by 108 = sequence error signal <) is transmitted to the left shifter 102; a car sequence out of the field as the day sequence error signal e0) is between a negative double differential and a second sequence error ㉔Signal e (4 times differential between 贞 and 贞, current timing error signal = (//: between 'the second comparator 104 generates a double reduction signal less 2 and the increase / decrement device 106 receives a double reduction signal when received “One 2” adds the current timing compensation signal from two chip times Tchip, and then generates equal to (the current timing compensation signal two chip times hlP) after the timing compensation signal is +1, and the right shifter 108 receives After doubling the signal, -2 ", the second subtracter 66 is shifted to the right by one bit, and then a differential connection is generated. 23 1242326 Timing error signal In addition, the first comparator 72 compares the increase / decrease The signal (equivalent to doubling the signal, -2 ") is not a constant signal. 'Therefore, The worker 74 transmits the differential connection timing error signal generated by the right shifter 108 to the left shifter 102; and (7) when the current timing error signal is compared, it is less than minus four. When the differential signal is not sequenced the next day, the second comparator 104 generates a four-fold reduction signal `` ~ 4 ''. After receiving the four-fold reduction signal -10, the multiplier 10 The current timing compensation signal is increased by four chip times Tchip, and a subsequent timing compensation signal equal to (the current timing compensation signal is + four chip times Tchip) is then +1, and the right shifter 108 receives four times After reducing the signal, -4 ", (e (X + 1)-♦)) generated by the second subtractor 66 is shifted to the right by two bits, and then a micro-blade connection and a 'day T sequence error signal are generated. e (where +1). In addition, since the first comparator 72 compares the increase / decrease signal +/— (equal to a four-fold decrease signal, —4 ”) is not a constant signal“ 0 ”, the multiplexer 74 will shift the shifter 1 to the right. 〇8 Differential connection timing error signal generated ^ αΛ + 1) is transmitted to the left shifter 102 〇 As the left shifter 102 and the right shifter 108 can be inputted to Signals (such as differentiating the current timing error signal heart and (also), etc.) are connected to multiple multiplexers controlled by the increase / decrease signal + / _. Except for the sampler 14, the interpolation 24 1242326 16 and the data filter 18, most of the timing recovery circuit 100 includes multiplexers and comparators occupying a relatively small area. In contrast, in addition to the sampling clock generator 12, the sampling In addition to the divider 14, the interpolator 16, and the data filter 18, the ones included in the timing recovery circuit 50 are dividers (for example, the first and second dividers 56 and 68) that need to occupy a considerable area. See section 1. Table 2 and Table 1. Table 1 lists the amount of time a divider needs to occupy when it contains different numbers of bits. Gate count, Table 2 lists the area that a comparator needs to occupy when it contains different numbers of bits. It can be clearly seen from Tables 1 and 2 that when the same number of bits is included (For example, the divider divides a 16-bit number by an 8-bit number, and the comparator compares two 16-bit numbers), the area occupied by the divider (1866. 7) actually 15 times the area occupied by the comparator (121), in other words, the area occupied by the timing recovery circuit 100 including the shifter and the comparator is much smaller than the timing recovery including the divider Area required by the circuit 50. In the second embodiment of the present invention, the left shifter 102 shifts the differential current timing error signal to the left by one bit and two bits, and then generates a related timing error signal. Of course, the left shifter in the timing recovery circuit of the present invention can also shift the differential current timing error signal 4/0 to the left by any number of bits, and then generate related timing error signals, but it should be noted that Right shift in the timing recovery circuit The bit shifting action of the device must correspond to the bit shifting action of the left shifter. 25 1242326 In addition, since the second divider 68 in the timing recovery circuit 50 outputs the output of the second subtractor 66 (The division is at most divided by two or four, depending on the third subtraction output (eight-~) of 76. Accordingly, the second divider 68 only needs to occupy a small area. Therefore, the timing recovery circuit ⑽ The right shift of the middle ③ 1G8 can be replaced by the second divider 68, and the second divider 68 in the timing recovery circuit 100 can divide (♦ ")-< ~) output by the second subtractor 66 by the first Increase / decrease signal output by the two comparators 104. Compared with the conventional technology, the timing recovery circuit of the present invention is developed based on Newton's method, which can accurately solve the "cocott method"-polynomial's duality. The sequence recovery circuit can also interpolate the generated The hidden timing error in the signal is limited to the predetermined timing error range_, where = 贝 疋 ERROR1 ^ corresponds to the demodulation and modulation capability after being connected to the timing recovery circuit. In this way, the demodulator will The interpolation can be correctly demodulated (^ HT1). In a preferred embodiment of the present invention, the divider of the timing recovery circuit Hrf drum area. "In the first recovery circuit 100 of the present invention, the sequence port only needs to occupy a small area; therefore, 'there is a time when the shift limb comparator is included therein, and the heart is divided by the system with the divider circuit 100. Correspondingly, the timing recovery electronic book. The cost of the heart will also be much less than the manufacturing of the timing recovery circuit 50. 26 1242326 [Schematic description] Figure 1 is a functional block diagram of a conventional timing recovery circuit. A functional block diagram of a timing recovery circuit in a preferred embodiment of the present invention. FIG. 3 is a functional block diagram of a timing recovery circuit in a second embodiment of the present invention. The first table lists a divider including different bits. The area required for the number of digits. Table 2 lists the area required for a comparator when it contains different numbers of bits. [Description of the main component symbols] 10, 50, Timing recovery circuit 12 Sampling clock generator 100 14 Sampler 16 Interpolator 18 Data filter 20, 52 Timing error detector 22 Timing error control 54 Differentiator 56 First divider 58 First ^ method 27 1242326 60 First D-type forward and reverse 62 No. Two D type Flip-flop 64 Third D-flip 66 Second subtractor 68 Second divider 70 Fourth D-flip 72 72 First comparator 74 Multiplexer 76 Third subtractor 102 Left shifter 104 Second comparator 106 Increase / decrement 108 Right shifter 28