1241779 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於數位影像廣播系統之符號解交錯 器，詳言之，係關於一種利用單埠記憶體之符號解交錯器。 【先前技術】 符號解交錯器為數位影像廣播系統（digital vide〇 br〇adcast， DVB)之接收器中通道解碼的一個主要部分，負責將傳送端 所打散的資料順序還原。符號解交錯器是採用區塊解交錯 的方法’一個符號資料長度（Ιχ)在2k mode包含1512筆資 料或在8k mode包含6048筆資料。進入解交錯符號的資料按 輸入順序可以定義為一序列Yin = (yinQ，yi^， ymNmax-i)，解交錯後的資料之輸出順序序列可以表示為向 量 Y〇Ut = (y〇Ut〇, 丫_1，y〇Ut2,...... y — Nmax·!)，符號内之資料交錯 前後之排列順序方式按照先前技術文獻1(，，Digital Vide〇 Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television，’’ ETSI EN 300 744 Vl.4.1，Jan· 2001·)之定義 如下： y0Utq=yinH⑷當正交分頻多工（ofdm)的符號是偶數。 y°utH⑷=yinq當正交分頻多工（ofdm)的符號是奇數。 在先前技術文獻1中定義H(q)為一排列函數。依據以上的 定義，在電路的運作上，可以針對偶數符號按輸入資料順 序寫入記憶體位置0、1、2―1，從記憶體讀出時則 按位置H(0)、H(l)、H(2)…、汛〜匪―1)的順序取出資料以達 到解交錯的目的；奇數符號的解交錯順序剛好相反，是以 97877.doc 1241779 H(q)順序寫入，以循序方式讀出。由於奇偶的解交錯順序 不同，因此在先前技術文獻 2(L_ Horvath，I. Dhaou，H. Tenhunen and J. Isoaho， "A novel， high-speed reconfigurable demapper symbol deinterleaver architecture for DVB-T，’’ in Proc. IEEE International Symposium on Circuits and Systems^ vol. 4, Orlando, FL USA, June 1999, pp. 382-385.)的符號解交錯器的荦構乃使用兩個記憶體，每個記 憶體大小可以容納整個符號大小，一個負責儲存偶數符號 資料，另一個儲存奇數符號資料，各由一個H(q)產生器來 控制。然而，由於奇偶符號乃是交替輸入，處理偶數符號 的輸入可與處理先前奇數符號的輸出同時一併考量，此時 都是採用循序的位置；同樣的在處理奇數符號的輸入與偶 數符號的輸出都按H(q)的順序讀寫。既然讀寫位置一樣， 就可以利用同樣的記憶體來處理奇偶符號，而不須要使用 到兩塊不同記憶體。 由以上的說明可知解交錯須要H(q)產生器電路計算位 址。若以查表方式儲存H(q)的方式設計電路，須要一個至 少〃max大小的記憶體。若按先前技術文獻1提供的方塊圖設 計，只須很少的電路，但其缺點在於不一定每個週期都能 產生H(q)值，如果當週期有資料輸入，得將資料先儲存在 緩衝暫存器，此一緩衝暫存器的數目會隨著H(q)無法產生 的週期數增加。 因此，有必要提供一種創新且具進步性的之符號解交錯 器，以解決上述問題。 【發明内容】 97877.doc 1241779 本發明之目的在於提供-種用於數位影像廣播系統之符 號解交錯器，該符號解交錯器用以將一輸入符號中之一符 號資料序列解交，為-輸出資料序列，該輸入符號具有— 符號大小，該符號資料序列具有複數個符號資料，該等符 號資料之數目為-符號資料長度。該符號解交錯器包括： -第-讀出位址產生器、—第二讀出位址產生器、一第一 寫位址產生器、一第二寫入位址產生器及一單谭記憶 "Λ第靖出位址產生器用以於該符號資料屬於偶數符 號時，產生-讀出位址。該第二讀出位址產生器用以於該 符號資料屬於奇數符號時，產生一讀出位址。該第一寫入 位址產生器用以於該符號資料屬於偶數符號時，產生二寫 入位址。s亥第一寫入位址產生器用以於該符號資料屬於奇 數符號時，產生二寫入位址。該單蟑記憶體用以於解交錯 時儲存該等符號資料，該料記憶體具有四個料記憶體 區塊，其中，依據寫入位址或讀出位址，一第一單埠記憶 體區塊用以存取該寫人位址或讀出位址小於符號大小之一 半且為偶數之符號資料，—第二單埠記憶體區塊用以存取 該寫入位址或讀出位址小於符號大小之—半且為奇數之符 號資料，-第三單埠記憶體區塊用以存取該寫入位址或讀 出位址大於等於符號大小之—半且為偶數之符號資料，一 第四單璋記憶體區塊用以存取該寫入位址或讀出位址大於 等於符號大小之一半且為奇數之符號資料。 本發明之符號交錯器適當地將單埠記憶體分割成四個獨 立的區塊，分別針對奇偶及高低編號之資料負責存取，不 97877.doc 1241779 僅可以使用比先前技術文獻2小—半的記憶體，同時讓資料 的讀寫在同一週期發生且在同一區塊之單埠記憶體區塊的 ，率降到非常低’因此本發明可以使用單埠記憶體來實現 符號解交錯器’且由於本發明之該第二寫入位址產生器於 一週期可產生二個寫人位址，故只須額外少許約Q 5%總記 憶體大小的緩衝暫存器，可大幅減少符號解交錯器所須記 憶體之電路面積大小，並有效降低數位影像廣播系統之晶 片成本。 【實施方式】 參考圖卜其係本發明之㈣衫錯_之架構示意圖。 本發明之符號解交錯器1()係用於數位影像廣播系統，該符 號解交錯HU)用以將-輸人符號中之—符號資料序列解交 錯為-輸出資料序列，該輸人符號具有—符號大小⑻，該 符號資料序列具有複數個符號資料，該等符號資料之數目 為-符號資料長度…)。本發明之符號解交錯器1〇主要包 括：-第-讀出位址產生器"、一第二讀出位址產生器… -第-寫入位址產生器13、一第二寫入位址產生㈣及一 單埠記憶體1 8。 該第-讀出位址產生tin用以於該符號資料屬於偶數符 號時，產生-1#出位址。依據先前技術文獻4之定義，唁 第-讀出位址產生⑽可為-Q函數產生器。該第二讀出^ 址產生益12用以於該符號資料屬於奇數符號時，產生一讀 出位址。依據先前技術文獻^之定義，該第二讀出位址產貝 生器12可為一 H(Q)函數產生器。 97877.doc 1241779 該第一寫入位址產生器1 3用以於該符號資料屬於偶數符 號時’產生至少一寫入位址。依據先前技術文獻1中之定 義，該第一寫入位址產生器13可為一 Q函數產生器。該第二 寫入位址產生器14用以於該符號資料屬於奇數符號時，產 生至少一寫入位址。依據先前技術文獻丨中之定義，該第二 寫入位址產生器14可為一 H(Q)函數產生器。 該單埠記憶體18用以於解交錯時儲存該等符號資料，該 單埠記憶體18具有四個單埠記憶體區塊18ι、182、183、 1 84。其中，依據寫入位址或讀出位址，一第一單埠記憶體 區塊181用以存取該寫入位址或讀出位址小於符號大小之 一半且為偶數之符號資料；一第二單埠記憶體區塊182用以 存取該寫入位址或讀出位址小於符號大小之一半且為奇數 之符號資料；一第三單埠記憶體區塊183用以存取該寫入位 址或讀出位址大於等於符號大小之—半且為偶數之符號資 料，第四單埠δ己憶體區塊184用以存取該寫入位址或讀出 位址大於等於符號大小之—半且為奇數之符號資料。 本發明之符號解交錯㈣之該單埠記憶體_分割成四 個區塊來錯開讀寫衝突。以該符號大小（L)為觀(8k)為例 說明’該第-單埠記憶體區塊181與該第二單埠記憶體區塊 182之記憶體大小為綱xW位元，該第三單埠記憶體區塊 1 83與該第四單埠記憶體區塊184之記憶體大小為·xW 位元’其中W代表符號内每筆資料的位元寬度。 本^月之單埠記憶體18區分為四塊單痒記憶體區塊可 、襄:貝料的σ貝寫發生在同一區塊的機率降到非常低。每次 97877.doc 1241779 ;符號解交錯器10接受-筆新的符號資料，同時也產生一 輸出：科’因此每一週期資料須讀寫—次。以偶數符號 2例，其解交錯方式是以循序讀寫，由於連續兩個數一定 =個钱、-個偶數的特性，本發明之四塊料記憶體 :塊之可偶的分類，可以讓其中之—單蟑記憶體區塊負責 頃取時，另-單埠記憶體區塊就負責寫人，不會導致衝突。 右。以先料術文獻！中定義^⑷函數讀寫時，其係以奇 文相解交錯’由於連續兩個H⑷位址，在大部分的情況， :仙⑷位址會小於符號大小㈦之-半，下-個Η⑷位址 a大於符號大小（L)之一半，在此情況下，本發明之單淳圮 __讀寫不會㈣突。此外’若有時連續兩個Η⑷位 址都小於符號大小（L)之一半時，且此兩個Η⑷位址剛好為 -個為奇數，下一個為偶數時，則在該單埠記憶體_寫 也Γ會有衝突。但若不是’若有時連續兩個1^⑷位址都小 於符號大小（L)之-半時’且若此兩個Η⑷位址剛好均為奇 數時，則可能會有讀寫同一區塊的問題發生。此時，二 的符號資料必須先儲存於一緩衝暫存_中，以待稍後寫 入。 ”、、 本發明之符號解交錯器丨〇在每一週期的運作可以歸納 以下步驟： 、’、馬 1·先設定讀寫資料之指標心=〇，.= -i，type=〇; 2·判斷目前處理的符號資料屬於偶數或奇數符號，來決 定此週期讀出與寫入位址的產生方式： U)當符號資料屬於偶數符號（type===0)時： 97877.doc -10- 1241779 i. 讀出位址RA=〜，該讀出位址係由該第一讀出位址 產生器11所產生。 ii. 由該第一寫入位址產生器13產生一第一寫入位址 WA1 =〜及一第二寫入位址WA2=〜+1。 (2)當符號資料屬於奇數符號： i·讀出位址，該讀出位址係由該第二讀出位 址產生器12所產生。 ii.由該第二寫入位址產生器14產生一第一寫入位址 …八卜研〜）及一第二寫入位址〜人2=叫九+1)。 3·判斷每一個位址（RA，WA1，WA2)所對應的單埠記憶 體區塊： 本發明之該符號解交錯器1〇之實施例係每次讀出一 筆資料，寫入位址至多兩個，將這些讀出位址或寫入 位址由下列的演算法判斷每一個位址所對應處理的 單埠記憶體區塊。 (1) 若該寫入位址或讀出位址小於符號大小之一半且 為偶數’屬於該第一單埠記憶體區塊1 8 1 ; (2) 該寫入位址或讀出位址小於符號大小之一半且為 奇數，屬於該第二單埠記憶體區塊182 ; (3) 若該寫入位址或讀出位址大於等於符號大小之一 半且為偶數，屬於第三單埠記憶體區塊丨83 ; (4) 若該寫入位址或讀出位址大於等於符號大小之一 半且為奇數’屬於第四單埠記憶體區塊丨84。 判斷有無發生記憶體讀寫衝突，來決定此週期實際執1241779 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a symbol deinterleaver for a digital video broadcasting system. In particular, it relates to a symbol deinterleaver using a port memory. [Prior art] The symbol deinterleaver is a major part of channel decoding in the receiver of a digital video broadcasting system (DVB), which is responsible for sequentially restoring the data scattered by the transmitting end. The symbol deinterleaver is a block deinterlacing method. A symbol data length (Iχ) contains 1512 pieces of data in 2k mode or 6048 pieces of data in 8k mode. The data entering the deinterleaved symbol can be defined as a sequence Yin = (yinQ, yi ^, ymNmax-i) according to the input order, and the output sequence sequence of the deinterleaved data can be expressed as a vector Y〇Ut = (y〇Ut〇, Ya_1, y〇Ut2, ... y — Nmax ·!), The arrangement of the data in the symbol before and after the interleaving is in accordance with the prior art document 1 (,, Digital Vide〇Broadcasting (DVB); Framing structure, The definition of channel coding and modulation for digital terrestrial television, ETSI EN 300 744 Vl.4.1, Jan 2001 ·) is as follows: y0Utq = yinH. When the sign of orthogonal frequency division multiplexing (ofdm) is even. y ° utH⑷ = yinq when the orthogonal frequency division multiplexing (ofdm) sign is odd. H (q) is defined as a permutation function in the prior art document 1. According to the above definition, in the operation of the circuit, the memory can be written to the memory positions 0, 1, 2 and 1 according to the input data order according to the even number symbols. When read from the memory, the positions are H (0) and H (l). , H (2) ..., Xun ~ Bian ~ 1) in order to de-interleave; the de-interlacing order of odd symbols is just the opposite, written in 97877.doc 1241779 H (q) order, in a sequential manner read out. Due to the different de-interlacing order of parity, in the previous technical literature 2 (L_ Horvath, I. Dhaou, H. Tenhunen and J. Isoaho, " A novel, high-speed reconfigurable demapper symbol deinterleaver architecture for DVB-T, '' The symbol deinterleaver in Proc. IEEE International Symposium on Circuits and Systems ^ vol. 4, Orlando, FL USA, June 1999, pp. 382-385.) uses two memories, each of which is the size of It can accommodate the entire symbol size, one is responsible for storing even symbol data, and the other is storing odd symbol data, each of which is controlled by an H (q) generator. However, since the even and odd symbols are alternately input, the processing of the input of the even symbol can be considered together with the output of the previous odd symbol, and the sequential position is used at this time; the input of the odd symbol and the output of the even symbol are also processed at the same time. Both read and write in the order of H (q). Since the read and write positions are the same, the same memory can be used to process the parity symbols without using two different memories. From the above description, we know that deinterleaving requires the H (q) generator circuit to calculate the address. If the circuit is designed by storing H (q) in a look-up table, a memory with a size of at least 大小 max is required. If it is designed according to the block diagram provided in the previous technical literature 1, only a few circuits are required, but its disadvantage is that it may not generate H (q) value every cycle. If data is input during the cycle, the data must be stored in Buffer registers. The number of buffer registers will increase with the number of cycles that H (q) cannot generate. Therefore, it is necessary to provide an innovative and progressive symbol deinterleaver to solve the above problems. [Summary of the Invention] 97877.doc 1241779 The purpose of the present invention is to provide a symbol deinterleaver for a digital video broadcasting system. The symbol deinterleaver is used to deinterleave a symbol data sequence in an input symbol as an output. Data sequence, the input symbol has-symbol size, the symbol data sequence has a plurality of symbol data, and the number of these symbol data is-symbol data length. The symbol deinterleaver includes:-a first read address generator,-a second read address generator, a first write address generator, a second write address generator, and a single memory " Λ first out address generator is used to generate-read out the address when the symbol data belongs to even symbols. The second read address generator is used for generating a read address when the symbol data belongs to odd symbols. The first write address generator is used for generating two write addresses when the symbol data belongs to an even symbol. The first write address generator is used to generate two write addresses when the symbol data belongs to odd symbols. The single cockroach memory is used to store the symbol data during de-interleaving. The material memory has four material memory blocks, of which a first port memory is based on a write address or a read address. The block is used to access the writer address or read address symbol data that is less than half of the symbol size and is an even number, the second port memory block is used to access the write address or read bit The address data is smaller than the symbol size—half and odd symbol data, and the third port memory block is used to access the write address or read address greater than or equal to the symbol size—half and even symbol data A fourth single memory block is used to access symbol data whose write address or read address is greater than or equal to one-half of the symbol size and is an odd number. The symbol interleaver of the present invention appropriately divides the port memory into four independent blocks, which are responsible for accessing the parity and high-low numbered data, not 97877.doc 1241779, which can only be used smaller than half of the previous technical document 2- Memory, while allowing data to be read and written in the same cycle and in the same block of the RAM memory block, the rate is reduced to very low 'so the invention can use RAM memory to implement the symbol deinterleaver' And because the second write address generator of the present invention can generate two writer addresses in one cycle, only a small additional buffer register of about Q 5% of the total memory size is required, which can greatly reduce symbol solutions. The circuit area of the memory required by the interleaver effectively reduces the chip cost of the digital video broadcasting system. [Embodiment] Reference is made to the schematic diagram of the present invention. The symbol deinterleaver 1 () of the present invention is used in a digital video broadcasting system, and the symbol deinterlacer HU) is used to deinterleave a symbol data sequence in an input symbol into an output data sequence. The input symbol has —Symbol size⑻, the symbol data sequence has a plurality of symbol data, and the number of such symbol data is-symbol data length ...). The symbol deinterleaver 10 of the present invention mainly includes:-the first-read address generator ", a second read address generator ...-the-write address generator 13, a second write Address generation and a port memory 18. The -read address generation tin is used to generate a -1 # out address when the symbol data belongs to an even symbol. According to the definition in the prior art document 4, 唁 -read address generation ⑽ can be a -Q function generator. The second read address generation benefit 12 is used to generate a read address when the symbol data belongs to odd symbols. According to the definition in the prior art document, the second read address generator 12 can be an H (Q) function generator. 97877.doc 1241779 The first write address generator 13 is used to generate at least one write address when the symbol data belongs to an even symbol. According to the definition in the prior art document 1, the first write address generator 13 may be a Q-function generator. The second write address generator 14 is used to generate at least one write address when the symbol data belongs to odd symbols. According to the definition in the prior art document, the second write address generator 14 may be an H (Q) function generator. The port memory 18 is used to store the symbol data when de-interlaced. The port memory 18 has four port memory blocks 18m, 182, 183, and 184. Among them, according to the write address or read address, a first port memory block 181 is used to access the symbol data whose write address or read address is less than half of the symbol size and is an even number; The second port memory block 182 is used to access the write address or the read address is less than one and a half of the symbol size and the symbol data is odd; a third port memory block 183 is used to access the The write address or read address is greater than or equal to one-half of the symbol size and the symbol data is even. The fourth port δ memory block 184 is used to access the write address or read address. Symbol size—half and odd symbol data. The memory of the symbol de-interlacing of the present invention is divided into four blocks to stagger read and write conflicts. Taking the symbol size (L) as the view (8k) as an example, the memory sizes of the first-port memory block 181 and the second-port memory block 182 are outline xW bits, and the third The memory sizes of the Anbu memory block 1 83 and the fourth Anbu memory block 184 are · xW bits', where W represents the bit width of each piece of data in the symbol. This month's Lubu memory 18 is divided into four single-itch memory blocks. The probability that σ shell writes to the same block in the same block is reduced to a very low level. Each time 97877.doc 1241779; the symbol deinterleaver 10 accepts-new symbol data, and also produces an output: Section 'so each period of data must be read and written-once. Take 2 cases with even symbols, the de-interlacing method is sequential reading and writing. Due to the characteristics of two consecutive numbers must be = money and-even numbers, the four-block memory of the present invention: the even classification of blocks, can When one of them-the single cockroach memory block is responsible for taking, the other-the port memory block is responsible for the writer, which will not cause conflicts. right. Based on the prior art literature! In the definition of the ^ 交错 function, it is de-interlaced with odd texts. Because of two consecutive H⑷ addresses, in most cases, the ⑷⑷ address will be smaller than the symbol size ㈦-half, next-Η⑷ The address a is larger than one and a half of the symbol size (L). In this case, the single read and write of the present invention does not cause a burst. In addition, 'If sometimes two consecutive addresses are less than one and a half of the symbol size (L), and the two addresses are exactly-one is an odd number, and the next is an even number, then in the port memory _ Writing also conflicts. But if it is not 'if sometimes two consecutive 1 ^ ⑷ addresses are less than-half-time of the symbol size (L)', and if these two Η⑷ addresses are exactly odd numbers, there may be read and write of the same block The problem occurred. At this time, the symbol data of two must be stored in a buffer temporary storage_ for later writing. "、 The operation of the symbol deinterleaver of the present invention in each cycle can be summarized in the following steps: ', Ma 1. First set the index for reading and writing data = 0,. = -I, type = 0; 2 · Determine whether the symbol data currently processed belongs to even or odd symbols, to determine the generation method of read and write addresses in this cycle: U) When the symbol data belongs to even symbols (type === 0): 97877.doc -10 -1241779 i. Read address RA = ~, the read address is generated by the first read address generator 11. ii. A first write is generated by the first write address generator 13. The input address WA1 = ~ and a second write address WA2 = ~ + 1. (2) When the symbol data belongs to odd symbols: i. Read address, the read address is the second read bit Generated by the address generator 12. ii. The second write address generator 14 generates a first write address ... eight buyan ~) and a second write address ~ person 2 = called nine + 1 ). 3. Determine the port memory block corresponding to each address (RA, WA1, WA2): The embodiment of the symbol deinterleaver 10 of the present invention reads one piece of data at a time and writes There are at most two addresses, and these read addresses or write addresses are judged by the following algorithm for the corresponding port memory block of each address: (1) If the write address or read bit The address is less than one-half and half of the symbol size and belongs to the first memory block 1 8 1; (2) The write address or read address is less than one-half and half of the symbol size and is odd, belonging to the second Anbu memory block 182; (3) If the write address or read address is greater than or equal to one-half of the symbol size and is an even number, it belongs to the third memo block 丨 83; (4) If the write The input address or read address is greater than or equal to one-half of the symbol size and is an odd number, which belongs to the fourth memory block. 84. Determine whether a memory read or write conflict occurs to determine the actual execution of this cycle.
97877.dOC -11 - 1241779 々亍的a己憶體t買寫動作。 (1) 依據讀出位址RA，由四個單埠記憶體區塊其中之 早蜂a己憶體區塊言買取資料，％ = % +1 ; (2) 付说資料先儲存於該緩衝暫存器15 ; (3) 右碩出位址RA與該第一寫入位址WA1不屬於同一 塊單埠記憶體區塊，從緩衝暫存器15取出符號資料 依寫入位址WA1寫入所屬之單埠記憶體區塊， 〜=+1 · (4) 若讀出位址RA與該第一寫入位址WA1及該第二寫 入位址WA2皆屬於不同區塊之單埠記憶體區塊，且 該緩衝暫存器15中還有未寫入的符號資料，則從緩 衝暫存器15取出符號資料依據該第二寫入位址 WA2寫入所屬之單埠記憶體區塊，〜=〜+1; 5·判別目前該符號資料序列之符號資料是否處理完 畢’以決定是否更換奇偶符號設定。 (1) 若％ ==#隨，即讀取完畢，則％=0且typeM-type ; 其中，符號資料長度（#max)在2k模式下為1512，在 8k模式下為6048。 (2) 若如==Armax，即寫入完畢，則如=〇 (3) 若讀取及寫入均未處理完畢，則重複上述步驟2。 茲以符旎大小為2k模式為例詳細說明本發明之符號解交 錯器1〇之操作，假設從符號資料屬於偶數符號開始： 週期1 · 心〇 ’讀出第一單埠記憶體區塊1 8 1中的奇數 符號中第0筆符號資料。 97877.doc 12 1241779 週期2 :似=心=1，讀出第二單埠記憶體區塊182中的奇數 符號中第1筆資料。 〜一 〇，寫入第一單埠記憶體區塊1 8 1中的偶 數符號中第0筆資料 週期3 :肋=%=2，讀出第一單埠記憶體區塊181中的奇數 符號中第2筆資料。 =〜二1，寫入第二單埠記憶體區塊182中的偶數 符號中第1筆資料。 循序時’言買寫皆可交錯於不同區塊記憶體。 假設整個符號之1512筆資料處理完，則換成以H(q)函數 的順序讀取記憶體中15 12筆偶數符號和寫入1512筆奇數符 號。 週期1 週期2 週期3 似=丹(《/? = 〇) = 〇，靖屮筮 错抱 口貝出第一早埠記憶體區塊1 81中 的偶數符號中第〇筆資料。 兄4 = //(% =1) = 1024，靖屮筮一留 σ貝出第二早埠記憶體區塊183 中的偶數符號中第1024筆資料。 _ =好(〜=0) = 0，宜筮 馬入第一早埠記憶體區塊1 8 1中 的奇數符號中第〇筆資料。 似=2) = 16，靖屮筮留 σ貝出第一早埠記憶體區塊181中 的偶數符號中第16筆資料。 寫入第三單埠記憶體區塊1 83 ^41 = //(^=1) = 1024 , 中的奇數符號中第1 〇24筆資料。 以上3個週期’讀取與寫入記憶體都可交錯，假如到了第 八筆資料： 97877.doc -13- 1241779 週期 18 :似=^(%=17) = 140， σ 出弟一早埠記憶體區塊1 8 1 中的偶數符號中第140筆資料。 _ =叫〜=16) = 66，屬 一 〇〇 屬於弟一早埠記憶體區塊 m’與讀出位址屬於同-塊記憶體，寫入暫 停’不執行寫入。 週期19 似=//(%=18) = 1136， 出弟二早埠記憶體區塊183 中的偶數符號中第113 6筆資料。 阶 1 = //(〜=16) = 66， 弟早埠記憶體區塊18 1 中的奇數符號中第66筆資料。 週期20 似=扒％ =19) = 514，讀屮 出第一早埠記憶體區塊1 8 1 中的偶數符號中第5 14筆資料。 ㈣= i/(L140 ，屬於第一單埠記憶體區塊 181，與讀出位址屬於同持 葡％ |J塊圮憶體，寫入暫 停，不執行寫入。 假如到了第二十三筆資料。 週期23 :似=扒％=22)=刚9，讀出黛 貝出第四早埠記憶體區塊184 中的偶數符號中第1089筆資料。 ⑽ 1 = //(〜=19) = 514,宜 口 罵第一早埠記憶體區塊181 中的奇數符號中第5 14筆資料。 隱=//(‘=2〇) = 1288，寫时 馬入第二夺埠記憶體區塊 183中的奇數符號中第1288筆資料。 在週期23時，可同時寫入兩筆資料，該 平μ τ卞成％衝暫存器1 5儲 存著寫入位址為Η(21)和Η(22)的資料。由於本發明之該第 二寫入位址產生器14於一週期可產生二個寫入位址，因 14 97877.doc 1241779 此，在影像廣播接受器的應用下，本發明符號解交錯器i 〇 所須的緩衝暫存器1 5至多只須3 1筆。 本發明之符號交錯器1〇，適當地將單埠記憶體18分割成 四個獨立的區塊，分別針對奇偶及高低編號之資料負責存 取，不僅可以使用比先前技術文獻2小一半的記憶體，同時 讓資料的讀寫在同一週期發生且在同一區塊之單埠記憶體 區塊的機率降到非常低，因此本發明使用單埠記憶體18來 實現符號解交錯器10，且由於本發明之該第二寫入位址產 生器14於一週期可產生二個寫入位址，故只須額外少許約 〇·5%總記憶體大小的緩衝暫存器15，可大幅減少符號解交 錯器所須記憶體之電路面積大小。 本發明之符號解交錯器10另包括二多工器16、17及一控 制器19其中，一第一多工器16係連接至該第一讀出位址 產生器11及該第二讀出位址產生器丨2 ; 一第二多工器丨？係 連接至該第一寫入位址產生器13及該第二寫入位址產生器 14。5亥控制器19用以控制該符號解交錯器1 〇内各元件之動 作。 參考圖2 ’其顯示本發明之讀出位址產生器2〇之架構示意 圖。本發明之讀出位址產生器20可應用於符號解交錯器 1〇 ’作為該符號解交錯器1〇之該第二讀出位址產生器12。 本發明之該讀出位址產生器2〇包括：一讀出移位暫存器 21、一讀出邏輯運算器22、一讀出函數計算器23及一讀出 位址檢查器24。 該讀出位址產生器20於每週期產生―個坷…函數值以提 97877.doc -15- 1241779 供一讀出位址。H(q)函數值依據先前技術文獻丨可由下列的 演算法產生： q = 0; for (ζ· = 0;ζ· < = z. +1) { if (/ == 〇 〇r i ~ 1) R] = 0; if (/ = 2) i?; =1; elsei?；=5F(i?M) if (_;) < u {H(q) = Pr(R；);q = q + l;} 期都能產生-筆Η⑷位址，因此本發明之該讀出位址產生 器20將在同一週期同時產生及;+1& (2值，其產生的方法乃是 藉由函數的遞迴運算產生 '气·,，4(欠在以模式為十 個位元的數值，在8k模式為十二個位元的數值）。針對H(q) 函數值的計算，本發明以2k模式為例說明，該讀出移位暫 存器21所存的值假設為-第_讀出數值（、，為確保每一週 基於以下5尸函數的定義，在2k模式為：97877.dOC -11-1241779 买 's a memory body t buy and write action. (1) According to the readout address RA, the early bee a memory module of the four Anbu memory blocks buys the data,% =% +1; (2) The data is stored in the buffer first Register 15; (3) The right out address RA and the first write address WA1 do not belong to the same memory block. The symbol data is taken from the buffer register 15 and written according to the write address WA1. Into the own memory port of the port, ~ = + 1 · (4) If the read address RA, the first write address WA1 and the second write address WA2 belong to different ports of the different port Memory block, and there is unwritten symbol data in the buffer register 15, then the symbol data is taken from the buffer register 15 and written to the corresponding port memory area according to the second write address WA2 Block, ~ = ~ + 1; 5. Determine whether the symbol data of the current symbol data sequence has been processed 'to determine whether to change the parity symbol setting. (1) If% == # follows, that is, after reading,% = 0 and typeM-type; Among them, the symbol data length (#max) is 1512 in 2k mode and 6048 in 8k mode. (2) If == Armax, the writing is completed, then == 0 (3) If both reading and writing are not processed, repeat step 2 above. The operation of the symbol deinterleaver 10 of the present invention is described in detail by using a 2k mode of symbol size as an example. It is assumed that the symbol data starts from an even number of symbols: Cycle 1 · Heart 0 'reads out the first memory block 1 8 The 0th symbol data of odd symbols in 1. 97877.doc 12 1241779 Cycle 2: Like = Heart = 1, read the first data in the odd symbol in the second memory block 182. ~ 10, write the 0th data period in the even symbol in the first bank memory block 1 8 1 3: rib =% = 2, read the odd symbol in the first bank memory block 181 The second data. = ~ Two 1, write the first data in the even symbol in the second memory block 182. In sequential order, words can be written in different blocks of memory. Assuming that the 1512 records of the entire symbol have been processed, they are read in the order of H (q) function in the memory of 15 12 even symbols and 1512 odd symbols are written. Cycle 1 Cycle 2 Cycle 3 Like = Dan ("/? = 〇) = 〇, Jing Yi wrongly held out the 0th data in the even symbol in the first early memory block 1 81. Brother 4 = // (% = 1) = 1024, Jing Yiyi reserves sigma out of the 1024th data in the even symbol in the second early port memory block 183. _ = OK (~ = 0) = 0, it is better to enter the 0th data in the odd symbol in the first early memory block 1 8 1. (= 2) = 16, Jing 屮 筮 贝 出 to produce the 16th data in the even symbol in the first early port memory block 181. Write the 3rd serial port memory block 1 83 ^ 41 = // (^ = 1) = 1024, the 1st 024th data in the odd symbol. The above 3 cycles' read and write memory can be interleaved. If the eighth data is reached: 97877.doc -13- 1241779 Cycle 18: it seems that = ^ (% = 17) = 140, σ is the first memory of the younger brother. The 140th record in the even symbol in block 1 8 1. _ = Called ~ = 16) = 66, belonging to 〇〇 memory block m ′ and the read address belong to the same-block memory, write pause ′ does not perform writing. Period 19 looks like = // (% = 18) = 1136, the 113th record of the even number in the memory block 183 of the second brother ’s early port. Level 1 = // (~ = 16) = 66, the 66th data in the odd symbol in the memory block 18 1 of the younger brother. Cycle 20 (=% = 19) = 514, read out the 5th and 14th data in the even symbol in the first early memory block 1 8 1. ㈣ = i / (L140, belongs to the first port memory block 181, and the read address belongs to the same %% of the J block memory, the writing is suspended, and writing is not performed. If it reaches the twenty-third Cycle data 23: Like == %% = 22) = Just 9, read out the 1089th data in the even symbol in the fourth morning port memory block 184 from Dai Bei. ⑽ 1 = // (~ = 19) = 514, it is better to scold the 5th and 14th data in the odd symbols in the first early port memory block 181. Hidden = // (‘= 2〇) = 1288, at the time of writing, he entered the 1288th data in the odd symbol in the second seizure memory block 183. At cycle 23, two pieces of data can be written at the same time, and the flat μ τ 卞 %% of the register 15 stores the data written to the addresses Η (21) and Η (22). Because the second write address generator 14 of the present invention can generate two write addresses in one cycle, 14 97877.doc 1241779 Therefore, in the application of the video broadcast receiver, the symbol deinterleaver i of the present invention i 〇 The required buffer register 15 is only 31 at most. The symbol interleaver 10 of the present invention appropriately divides the port memory 18 into four independent blocks, and is responsible for accessing the parity and high-low numbered data, and not only can use half of the memory than the previous technical document 2 At the same time, the read and write of data occurs at the same cycle and the probability of the memory block in the same block is reduced to very low. Therefore, the present invention uses the memory 18 to implement the symbol deinterleaver 10, and because The second write address generator 14 of the present invention can generate two write addresses in one cycle, so only an additional buffer register 15 with a total memory size of about 0.5% can be used, which can greatly reduce symbols. The circuit area of the memory required by the deinterleaver. The symbol deinterleaver 10 of the present invention further includes two multiplexers 16, 17 and a controller 19. Among them, a first multiplexer 16 is connected to the first read address generator 11 and the second read. Address generator 丨 2; A second multiplexer 丨? It is connected to the first write address generator 13 and the second write address generator 14. The controller 19 is used to control the operations of the elements in the symbol deinterleaver 10. Referring to FIG. 2 ', a schematic diagram of the architecture of the read address generator 20 of the present invention is shown. The read address generator 20 of the present invention can be applied to a symbol deinterleaver 10 'as the second read address generator 12 of the symbol deinterleaver 10. The read address generator 20 of the present invention includes a read shift register 21, a read logic operator 22, a read function calculator 23, and a read address checker 24. The read address generator 20 generates a 坷 ... function value every cycle to provide 97877.doc -15-1241779 for a read address. The H (q) function value can be generated by the following algorithms according to the prior technical literature: q = 0; for (ζ · = 0; ζ · < = z. +1) {if (/ == 〇〇ri ~ 1 ) R] = 0; if (/ = 2) i ?; = 1; elsei ?; = 5F (i? M) if (_;) < u {H (q) = Pr (R;); q = q + l;} period can generate-pen address, so the read address generator 20 of the present invention will simultaneously generate and +1 & (2 value, the method of generating it is by The recursive operation of the function produces 'Q · ,, 4' (a value of ten bits in the mode of under, and a value of twelve bits in the mode of 8k). For the calculation of the value of the H (q) function, the present invention Taking the 2k mode as an example, the value stored in the read shift register 21 is assumed to be the _th read value (, to ensure that each week is based on the following definition of the corpse function, in the 2k mode:
Ri =Κ^8ν..,α1?α0]Ri = Κ ^ 8ν .., α1? Α0]
Ri+l = SF(R.) = [a〇 ®Ri + l = SF (R.) = [A〇 ®
Ri+2 =SF(SF(R：)) = [ai ®a49a0®a3,a9,as^.9a2] 因此，該讀出邏輯運算器22用以與該讀出移位暫存器21 依據該第一讀出數值產生一第二讀出數值（I)及一第三讀 出數值（^)。該讀出邏輯運算器22具有二互斥或邏輯閘與 "亥靖出移位暫存器21配合以產生該第二讀出數值（及,:+|)及第 三讀出數值（A—2)。 該讀出函數計算器23用以將該第一讀出數值及該第 二讀出數值（（,）以—PT函數分別計算得—第—讀出位址值 97877.doc -16- 1241779 (’）及一弟一 a買出位址值打(及/+1)。該讀出函數計算琴2 3包 括一弟一讀出函數計算器2 3 1及一第二讀出函數計算器 232。該第一讀出函數計算器231用以將該第一讀出數值（巧 以一 PT函數計算得該第一讀出位址值朽Ά.)。該第二讀出函 數汁异器232用以將該第二讀出數值（'.+1)以一 pT函數計算 得該第二讀出位址值抑(式+1)。 該讀出位址檢查器24用以檢查該第一讀出位址值ΡΓ(/?;) 及該第二讀出位址值W(i?/+1)是否小於該符號資料序列之該 符號資料長度（#_)。該讀出位址檢查器24用以於該第一讀 出位址值小於該符號資料長度時（Ρ7ΧΛ;)<Λ^χ)，輸出該第一 碩出位址值ΡΓ('·)，且下一週期之該讀出移位暫存器2丨之值 為该第二讀出數值及m。若該第一讀出位址值大於該ζ符號 資料長度時，輸出該第二讀出位址值P7Xi?;+i)，且 下一週期之該讀出移位暫存器之值為該第三讀出數值 心2。因此，本發明之該讀出位址產生器2〇可以確保於每週 期產生一個H(q)函數值以提供一讀出位址。本發明之該第 二讀出位址產生器20另包括二多工器25、26及一讀出控制 單元27。 參考圖3，其顯示本發明之寫入位址產生器3〇之架構示意 圖本發明之寫入位址產生器3 0可應用於符號解交錯器 1 〇，作為該符號解交錯器1 〇之該第二寫入位址產生器丨4。 本發明之該寫入位址產生器3〇包括：一寫入移位暫存器 31、一寫入邏輯運算器32、一寫入函數計算器33及一寫入 位址檢查器34。 97877.doc -17 - 1241779 /寫入位址產生器30於每週期產生連續二個H(q)、H(q+1) 函數值以提供兩個寫入位址。如上述該讀出位址產生器20 之^异法，該寫人移位暫存器31用以儲存_第—寫入數值 只寫入讀運异裔32用以與該寫入移位暫存器3 1依據 只弟寫入數值（及，)產生一第二寫入數值（4)、一第三入 數值卜）、一第四寫入數值（（)及-第五寫入數值（（4)。 乂寫入远輯運算器32具有四互斥或邏輯閘。 該寫入函數計算器33用以將該第一寫入數值（尤）、該第一 *數值（）、5亥第二寫入數值（心2)及該第四寫入數值 以一 Ρ Τ函數分別計算得一第一寫入位址值冰）、一第二寫 入位^㈣）、一第三寫入位址值叫+2)及一第四寫入位 ^值㈩)。該寫入函數計算器3 3包括-第-寫入函數計算 ^331、—第二寫入函數計算器332、-第三寫入函數計算 器333及-第四寫入函數計算器334。 ^寫』入位址檢查器Μ用以檢查該第一寫入位址值 ,、該第二寫入位址值ΡΓ(心!）、該第三寫入位址值pr«2) 及孩第四寫入位址值是否小於該符號資料序列之該 符唬貝料長度(Λ^χ)，並輸出二寫入位址。另外，該寫入位 址檢查器34用以決定下-週期之寫人移位暫存器31之值係 為該第三寫入數值（4〇、該第四寫入數值（仏）或該第五寫 入數值（心4)。因此，本發明之該寫入位址產生器3〇可以確 保於母週期產生一寫入位址。本發明之該寫入位址產生器 3〇另包括二多工器35、36、37及一寫入控制單元％。 惟上述實施例僅為說明本發明之原理及其功效，而非用 97877.doc -18- 1241779 以限制本發明。因此，習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1為本發明之符號解交錯器之方塊示意圖； 圖2為本發明之讀出位址產生器之方塊示意圖；及 圖3為本發明之寫入位址產生器之方塊示意圖。 【主要元件符號說明】 10 本發明之符號解交錯器 11 第一讀出位址產生器 12 第二讀出位址產生器 13 第一寫入位址產生器 14 第一寫入位址產生器 15 緩衝暫存器 16 第一多工器 17 第一多工器 18 單埠記憶體 19 控制器 20 本發明之讀出位址產生 21 讀出移位暫存器 22 讀出邏輯運算器 23 項出函數計算器 24 頃出位址檢查器 25、26 多工器Ri + 2 = SF (SF (R :)) = [ai ®a49a0®a3, a9, as ^ .9a2] Therefore, the read logic operator 22 is used to connect with the read shift register 21 according to the The first read value generates a second read value (I) and a third read value (^). The readout logic operation unit 22 has two mutually exclusive OR logic gates and the " Haijing out shift register 21 to generate the second readout value (and, ++) and the third readout value (A -2). The read-out function calculator 23 is used to calculate the first read-out value and the second read-out value ((,) by —PT function, respectively — — the first read-out address value 97877.doc -16-1241779 ( ') And a brother and a buy address values (and / + 1). The readout function calculator 2 3 includes a brother and a readout function calculator 2 3 1 and a second readout function calculator 232 The first readout function calculator 231 is used for the first readout value (the first readout address value is calculated by using a PT function.). The second readout function juicer 232 The second read value ('. + 1) is calculated by a pT function to obtain the second read address value (formula +1). The read address checker 24 is used to check the first read address value. Whether the read address value PΓ (/ ?;) and the second read address value W (i? / + 1) are smaller than the symbol data length (#_) of the symbol data sequence. The read address check The device 24 is configured to output the first master address value PΓ ('·) when the first read address value is smaller than the symbol data length (P7 × Λ;) < ^^ χ), and the next cycle The value of the read shift register 2 丨 is the second read value m. If the first read address value is greater than the length of the z-symbol data, the second read address value P7Xi?; + I) is output, and the value of the read shift register in the next cycle is The third reads the numerical center 2. Therefore, the read address generator 20 of the present invention can ensure that an H (q) function value is generated every week to provide a read address. The second read address generator 20 of the present invention further includes two multiplexers 25, 26 and a read control unit 27. Referring to FIG. 3, there is shown a schematic diagram of the architecture of the write address generator 30 of the present invention. The write address generator 30 of the present invention can be applied to the symbol deinterleaver 1 0, as the symbol deinterleaver 1 0. The second write address generator 4. The write address generator 30 of the present invention includes a write shift register 31, a write logic operator 32, a write function calculator 33, and a write address checker 34. 97877.doc -17-1241779 / Write address generator 30 generates two consecutive H (q), H (q + 1) function values every cycle to provide two write addresses. As described above, the read address generator 20 is different, the writer shift register 31 is used to store the _th—the write value is only written to the read transport alien 32 and used to temporarily shift the write shift. Register 3 1 generates a second written value (4), a third input value (bu), a fourth written value ((), and a fifth written value ( (4). The write remote calculator 32 has four mutually exclusive OR logic gates. The write function calculator 33 is used to write the first written value (especially), the first * value (), 5 The second write value (heart 2) and the fourth write value are respectively calculated by a PT function (a first write address value ice), a second write bit (^ ㈣), a third write The address value is called +2) and a fourth write bit ^ value ㈩). The writing function calculator 33 includes a first writing function calculator 331, a second writing function calculator 332, a third writing function calculator 333, and a fourth writing function calculator 334. ^ Write ”into the address checker M is used to check the first write address value, the second write address value PΓ (heart!), The third write address value pr« 2), and the child Whether the fourth write address value is less than the symbol data length (Λ ^ χ) of the symbol data sequence, and output the second write address. In addition, the write address checker 34 is used to determine whether the value of the writer shift register 31 in the next-cycle is the third write value (40, the fourth write value (仏), or the third write value). The fifth write value (heart 4). Therefore, the write address generator 30 of the present invention can ensure that a write address is generated in the mother cycle. The write address generator 30 of the present invention further includes Two multiplexers 35, 36, 37 and one write control unit%. However, the above embodiment is only for explaining the principle and effect of the present invention, and is not intended to limit the present invention to 97877.doc -18-1241779. Therefore, Xi Those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of the rights of the present invention should be as listed in the scope of patent applications described below. [Simplified description of the drawings] Figure 1 is the symbol of the invention Block diagram of the deinterleaver; Figure 2 is a block diagram of the read address generator of the present invention; and Figure 3 is a block diagram of the write address generator of the present invention. [Description of the main component symbols] 10 of the present invention Symbol deinterleaver 11 first read address generator 12 Second read address generator 13 First write address generator 14 First write address generator 15 Buffer register 16 First multiplexer 17 First multiplexer 18 Port memory 19 Controller 20 Read address generation 21 Read shift register 22 Read logic operator 23 Item function calculator 24 All address checker 25, 26 Multiplexer
97877.doc -19- 1241779 27 讀出控制單元 30 本發明之寫入位址產生器 31 寫入移位暫存器 32 寫入邏輯運算器 33 寫入函數計算器 34 寫入位址檢查器 35 > 36 、 37 多工器 38 寫入控制單元 181 第一單埠記憶體區塊 182 第二單埠記憶體區塊 183 第三單埠記憶體區塊 184 第四單埠記憶體區塊 231 第一讀出函數計算器 232 第二讀出函數計算器 331 第一寫入函數計算器 332 第二寫入函數計算器 333 第三寫入函數計算器 334 第四寫入函數計算器 97877.doc -20-97877.doc -19- 1241779 27 Read control unit 30 Write address generator 31 Write shift register 32 Write logic operator 33 Write function calculator 34 Write address checker 35 > 36, 37 multiplexer 38 write control unit 181 first port memory block 182 second port memory block 183 third port memory block 184 fourth port memory block 231 First reading function calculator 232 Second reading function calculator 331 First writing function calculator 332 Second writing function calculator 333 Third writing function calculator 334 Fourth writing function calculator 97877.doc -20-