TWI241768B - Slew rate controlled output circuit - Google Patents

Abstract

An output circuit comprises an input node, an output node, a first output transistor, a second output transistor, a first slew rate control circuit, and a second slew rate control circuit. The first output transistor and the second output transistor are coupled in series. The first slew rate control circuit is coupled between the first output transistor and a first power supply terminal. The second slew rate control circuit is coupled between the second output transistor and a second power supply terminal. The input node is coupled to gates of the first output transistor and the second output transistor. The output node is coupled to a common node of the first output transistor and the second output transistor.

Description

1241768 15338twf.doc / 006 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to an output circuit for slew mte control. There is a kind of [prior art] electronic device such as a personal computer (busy) or semi-reliable, IC, IC and integrated circuit communicate with each other. Each IC example uses a common bus, use, news two: = (== from 1C chip directly to one or more other Ic crystals · Tiger exchange-a letter f # u (for example, low-voltage series =: Road Cut the output circuit (thin coffee), the speed is called the road speed phase: use 3 turn rate. If the output circuit is not: combined, it may also affect: _b .; For the output driver, the rise and fall slew rate of the special driver is important. The slew rate of the output circuit will vary with the manufacturing process, the working ink, and the work. The external load capacitance of the output terminal changes (variati. ns) And with the electricity υϊ1 (1 chip becomes smaller in physical size, it becomes more difficult to control the operating characteristics such as the wafer-turn rate in the wafer. In the semiconductor wafer 1241768 15338twf.doc / 006 wafer manufacturing process Variations may cause transistors with the same design to have different characteristics. For example, the amount of current provided by the transistor will affect its slew rate, and this amount of current is related to many factors, including transistor size, gate-source voltage And parameters related to manufacturing. Crystal size and gate-source voltage can be controlled well, but because of existing doping techniques

Imperfections in technology and other manufacturing techniques, the characteristics of the manufacturing process generally still change between transistors. Therefore, output circuits with the same design and the same specific operating characteristics may not operate at different speeds as expected, and may have slew rates that do not meet specifications. In addition, the operating characteristics of the 'transistor' will change as the temperature changes. When the 1C wafer becomes hot, the transistor operates more slowly. Conversely, when the 1C wafer becomes cold, the transistor 1 operates more quickly. Therefore, the ordinary loss is 3 Greek: the slew rate changes with temperature. The operating temperature of the output driver can be transferred. The slew rate deviation of some wheel-out drives 11 was originally specified.

Temperature (abbreviated as PVT) :: 2: Input: Circuit ’Regardless of the process 1 pressure and the slew rate. The text is still kept specific and comparative. [Summary of the invention] The purpose of the present invention is to provide a slew rate of how voltage and temperature change. 'The temple specifically called an output circuit, regardless of the process, fixed and symmetrical slew rate nodes. An output thunder failed. The second-round output transistor II includes an input node, an output diode, an output transistor, and a first circuit. 6 1241768 15338twf.doc / 〇〇6 said ij: slew rate control circuit. The first output transistor and the second output transistor are coupled in series to the first output transistor and the second output rate control circuit is connected to the second output transistor. Between the power terminals. The input node _ is connected to the first; the common node of the body and the first: the output transistor. For the above and other purposes of the present invention, the preferred embodiments of the present invention are described below, and cooperate with them; [Embodiment] FIG. U shows a preferred embodiment of the fortune-making circuit—a preferred embodiment ^ ^ 110 110 ^ an output transistor 130, a second output transistor 140, a rate control circuit 15G, and a second slew rate control circuit 160. The output transistor 130 and the second output transistor 14 are switched in series. 2: The speed control circuit 150 is coupled between the first-power terminal 170 and the second-input crystal m. f Two slew rate control circuits 丨 _ are connected to the-= output, crystal 14. And between the second power supply terminal. The gate between input node ιι〇1 to the first output transistor 13〇 and the second output transistor # 一. The output node 12o is coupled to a common node (cmmnonnode) of the first output transistor 13o and the first output transistor 140. When the turn-out voltage is switched from high level to low level or from low level to 1241768 15338twf.doc / 006

^ Standard: the first output transistor 130 and the second output transistor 140 are "white conductive" and I operate in the saturation region. The resistance of the first-output transistor 130 and the second-output transistor 14G will affect the rising slew rate and the falling slew rate. For process, power supply voltage, and temperature fluctuations, electrical characteristics (such as the resistance of the first power transmission crystal 130 and the second power output crystal 140) will also change as the output voltage rises from the output node 120. In order to reduce the range that the slew rate may not meet the requirements and may not be symmetrical, the first and second slew rate control circuits can provide a variable resistance value to compensate for the first output transistor 130 and the first Any difference in resistance between the two output transistors 14o. By adjusting this variable resistance value, the first return =; ί: the equivalent resistance value of two and the first output transistor 130 (the input shown in Figure 1 = the upper + part of the private circuit), and the second = ⑼㈣Second output transistor⑽ (the output circuit shown in Figure i; =, the resistance value, the two are substantially the same. For example, such as: 丄 The output transistor 130 has a resistance value that is greater than that of the second output transistor 14? If the resistance value is 1 ', then the variable of the second-response circuit will be lighter than the variable resistance of the third-rate control circuit to compensate for the resistance between the first-output transistor and the second-output transistor 14o. The upper half and lower half of the value difference circuit have substantially the same output, so the rising slew rate is substantially the same as the falling slew rate. Therefore, the output of the body is lighter from the high level of the dragon level and from Low level to high level; symmetrical. Because the first and second slew rate control circuit 150 and the second slew rate control circuit 8 1241768 15338twf.d0c / Q () 5 the variable resistance of the second is to respond to changes in power supply voltage and temperature And dynamically ^ so the resistance value of the upper half of the output circuit 实质上 is still substantially the same as that of the lower two: the resistance value of the half Same. Therefore, the rising slew rate and the slew rate are still symmetrical during these changes. In the example, 'the first output transistor 130 is a PMOS transistor-and the second output transistor is a 14 transistor N] y [〇s transistor terminal provides a positive voltage VDD to the output terminal 1ΩΠ _, and the source ground voltage to the output circuit 100. The two terminals provide the drain of the transistor m and the source of the transistor 140 to the first circuit 100. For the input η, the hand-made circuit 160. The output. The input is "," the 110 is coupled to the gate of the PMOS transistor 130 and the gate of the _s transistor 140. In the ::: [-Output transistor 130 and the second round of transistor;: similar transistor. The second power supply terminal 180 can provide a lower positive voltage than the first: 疋 other kinds of positive voltage, or can be provided by the source terminal Figure 2 shows the circuit and circuit diagram of the present invention. Compared with the figure "shown: a preferred embodiment of the output circuit 200 includes a $: 100, the second slew rate control shown in Figure 2 wins. Circuit 16n—the variable resistor. The first variable resistor 240 is based on the newer brother—it can be adjusted by the resistance number 2 50. The first Variable power: = The first bias signal of the second bias signal is adjusted: the output of the second bias circuit of the self-diode 210 _ between the wheel point m 9 1241768 15338twf.doc / 006 points. Output resistance 210 can reduce the in-use: the signal reflection caused by any impedance mismatch between the load circuits. In the circuit of Figure 2, the first capacitor 220 is connected to the "-". The ugliness of the crystal 140 and the second variable resistor 25 ° and ―the first output power and the second capacitor 23G can be changed ―capacitance 220, but it will also slow down the symmetry of the rise and fall of the circuit in one embodiment. In the first round, the body is "屮" and the second output transistor 14 is used. The terminal 170 provides a positive voltage VDD, which is a power source for the Yamachi * Electricity Day, and provides a ground voltage to the output; the road wheel is coupled to the output node 120. ^ ^ The terminal of the transistor 130 and one terminal of the 'sm capacitor to _8 capacitor 220 are lightly connected to the ground voltage. "The first one is coupled to the other end of the first variable lightning resistance Tungu 220 *-^ 30; !: ^ ™ One end is lightly connected to the second variable voltage. The second source is the other source of the capacitor 23 °. ^ Jin Xie and Xie still the transistor resistor [draw: circuit diagram of the output circuit shown in Figure 2, where The variable power source includes a resistor and a /, Y, and the first variable resistance is 24 μC, which is a light-weight connection. As shown in Figure 3, 310 and the first-Ma Chunjia real surface contains the first- Resistor " ri-ri_ 320 is coupled in parallel. The first control transistor

A lower resistance than the second output transistor 14 can be used for operation. The voltage of the first bias voltage signal is increased as much as possible to increase the resistance of the first variable resistor 24. The voltage of the second bias signal is increased as much as possible to reduce the resistance value of the second resistor 250. Therefore, the equivalent resistance value of the first output transistor and the first variable resistor 24G, and the equivalent resistance value of the second output transistor 14 () and the second variable resistor 250 will be substantially the same. When the operating temperature rises, the resistance of the first output transistor 130 rises: in response to the temperature change, the first bias circuit reduces the voltage of the first bias signal as much as possible to make the first variable resistor 240 The resistance value is reduced. Similarly, 'because the operating temperature rises, the resistance value of the second output transistor 上升 also rises;? In response to the temperature change, the second bias circuit increases the voltage of the first bias alum as much as possible. To reduce the resistance of the second variable resistor 25 to 1241768 15338twf.doc / 〇〇6 320 the gate is coupled to the first bias circuit node of the first bias circuit-the second variable resistor The first preferred embodiment of 25 ° includes a second + resistor 330 and a second control transistor 34 ° connected in parallel. The second control: the gate of the body 340 is reduced to the second bias signal section of the second bias circuit. The first: the resistor 310 and the first control transistor 32 are connected in parallel to realize the variable resistor 240. Features. The larger the resistance of the first resistor 31 is, the larger the adjustable resistance range of the variable resistor is. The gate of the first control transistor 32o is connected to the first-bias signal from the first-bias circuit to control the amount of current flowing through the first control transistor 32o and the first resistor 31o, respectively, so as to provide Required equivalent resistance. The same operating principle applies to the second resistor 330 and the second control transistor 340. Due to changes in the semiconductor manufacturing process, the first output transistor 13〇11 1241768 15338twf.doc / 006 "the equivalent resistance of Leyi W transistor 130 and the first variable resistor 24G, and the second round of power The equivalent resistance of the crystal 14 and the second resistable 25G is substantially the same. When the power supply of the power supply terminal rises, the resistance value of the first output transistor ^ will generally decrease * due to the increase in operating speed. In response to the change of ^, the first-bias circuit increases the first-bias signal as much as possible, so that the resistance of the first variable resistor 24G is increased. Similarly, the resistance of the second input I, electricity: day, 140 will generally decrease i = in response to the increase of the power supply voltage, and the change of the return voltage 'the second bias circuit reduces the first-bias as much as possible [_ Voltage to increase the resistance of the second variable resistor ㈣. I During the fluctuation of the power supply voltage, 'equivalent resistance value of the first round transistor ⑽ and the first -1 · ^ = 240' and the equivalent resistance value of the second output transistor 第一 the first available ^ _25G, the essence of the two The same crystal 32 ^ = 1 ^ the third transistor m and the first control flute ... / transistor. Both the second output transistor 14 and the brother-tech transistor 340 are NMOS transistors. Two S3: VDD 'and the second power terminal 180 provides a ground voltage. PM〇s〇 PM: electricity: the first end of the first resistor 310 and _. PMMOS: 13〇 Π to the other end of the first resistor 310, transistor 34. The source is lightly connected: the end: NM〇S NM0S is connected to 34 °, connected to one end of the f-three private resistance 330 and grounded. NM0S: the body is coupled to the other end of the second resistor 330, the source of the Xingtun crystal 140, and one end of the second capacitor 23o. The _ partial dust signal 12 124 $ ^ 78 ^ 80 received by the MOS transistor 320. When the voltage of the mine is lower, the PMOS transistor 320 is more conductive. More current flows through the PMOS transistor 320. The resistance of the first variable resistor 240 is reduced. When the voltage of the first bias voltage received by the gate of the PMOS transistor 320 is higher, the conduction degree of the PMOS transistor 320 is lower. Even more; the current flows through the PMOS transistor 320. The resistance of the first variable resistor 240 will increase. When the voltage of the second bias signal received by the gate of the NMOS transistor 340 is lower, the NMOS transistor 340 is less conductive ^

Less current flows through the NMOS transistor 340. The resistance of the second variable resistor 25 will increase. When the voltage of the second bias signal received by the gate of the NMOS transistor 34o is higher, the NMOS transistor 34o has a higher conduction sound. More current flows through the NMOS transistor 34. Secondly, the resistance of resistance 250 will decrease. Figure 4 also shows the circuit diagram of the output circuit shown in Figure 2, which includes a transistor connected in parallel. As shown in Figure 4

And a second embodiment of the second variable resistor ⑽. In this = ’variable resistor contains the first-control transistor

; :: ^ = 对 _ 接 ’and the second variable resistor 250 includes the first and fourth control transistors 440 coupled in parallel. Fan Ye used "other methods to realize the first variable resistor _ Jiudi a variable resistor 250. Then, the first: ^ empty ^ electric = body 410 and a second control transistor sample in parallel to make a '^ ^ Function of resistor 240. The second control transistor Liubei flows through the 2nd connection of the first-Lai signal to control the electricity of the division S crystal 410 and the second control transistor 42. 13 1241768 15338twf.doc / 006 ^ In order to provide the required equivalent resistance value, the related operating principles are applicable to the second control transistor 430 and the fourth control transistor 44. In one embodiment, the first control transistor 41 and the second control transistor 420 are both It is a PMOS transistor. The third control transistor '"and the fourth control transistor 440 are all NMOS transistors. The first power supply provides positive ink VDD 'and the second power supply terminal 180 provides a ground voltage. The sources of the transistors 410 and 420 are all connected to VDD. The drain electrodes of pM0s W0 and 420 and the free poles of PM0s transistor 40 are all to the -th output transistor 13G < 3PM 0s transistor side gate = the first-furnace signal node of the flat dust circuit . Similarly, for the second transistor, the drains of the NMOS transistors 430 and 44 are transferred to the first-output transistor 140. The gates of the source transistors of the NMOS transistors 43 and 44 are coupled to the second output transistor 140. Voltage signal | = body_ 之 门 _ The second biased first PMOS transistor 410 connected to the second bias circuit is at Vds resistance-like, and does not conduct the drain and source of the crystal at vDS < Vpth Voltage difference, V series p 'DS electricity "from ^ ^ to Vpt ^ pM0s transistor critical 1h = ld v = age). The second PM0S transistor 420 is the same as in :: value :: t, while in,> The V-time has a very electric body 420, a PMMOS transistor 410, and a second electric body 420 connected in parallel. The function is like the resistance of a variable resistor and the entire first bias signal. The principle applies. It is related to the __Sf_43QfT area. The same state and the second NMOS transistor 14 1241768 15338twf.d〇c / 〇〇6 440 〇 Leyi biased the wrong way and the measured potential range, the two terms are respectful with one-volume Same function—sensor, sense… original package [and, temperature change (referred to as ρντ change). For the response m: dynamic 3 change = an output resistance 13 〇 and the second round output resistance '-bias Μ The circuit adjusts the first-bias signal to control the first-240, and the second bias circuit makes the cross-current lightning resistance 25 " ... The first is to control the second variable voltage 50. At this point, the brother a variable resistor 24〇With The equivalent resistance value of a round of transistor ⑽, and the second variable resistor 2 筮-J meaning package resistance 250 and the special resistance value of the first round of transistor 140, the two will still be substantially the same. Figure 5! The first preferred embodiment of the bias circuit in the present invention will be shown in FIG. 5. The bias circuit 500 provides the same bias signal as & system-variable resistor and the second The variable resistance is 25g. Therefore, the common display signal node can be applied to the first signal node and the second bias signal node. The bias circuit includes the first bias transistor 510 and the second bias transistor 520 in series and connected across Between the first power supply terminal 17 and the second power supply terminal 18G. The first-bias signal node and the second bias signal node are lightly connected to the gate of the first bias transistor 510 and the second bias transistor 520 The closed-pole and first bias transistor 51 and the second bias transistor: total: node. In addition, the electrical characteristics of the first bias transistor 510 are substantially the same as the electrical characteristics of the first-output transistor 13G. The electrical characteristics of the second bias transistor 520 are substantially the same as those of the second round transistor 140. The gas characteristics are the same. In an implementation method of the first preferred embodiment, the first bias transistor 510 is a PMOS transistor and the second bias transistor 52 is a NM MOS 15 1241768 15338twf.doc / 006 愐 i / u eight π power supply VU13, and the second terminal provides ground power. PM0S transistor 51 2 source VDD. NM0S transistor 52 0 source ground. M 0 ^ = 510 and The gate and sink of the NMOS transistor 52G share a bias signal node. Due to the similar characteristics of the daggers, if the PMQS transistor 13O IsTMOS transistor 140 has a low resistance, the pM0s transistor will also work with a lower resistance than the NMOS transistor 52. The voltage of the bias signal from the bias circuit 500 will be higher than VDD / 2. The higher voltage bias signal reduces the resistance of the first variable resistor 240 (including the PMOS transistor 1 ^) and increases the resistance of the second variable resistor 250 (including the NMOS transistor). Therefore, during the process variation, the equivalent resistance of the PM0S transistor 130 and the first variable resistor 24o, and the equivalent resistance of the NMOS transistor 140 and the second variable resistor 25o, both It will be substantially the same. When the temperature or power supply voltage rises, the resistance of the first output transistor 13 and the second output transistor 140 will change differently. The adjusted fortress 5a will change the first variable resistor 240 and The second variable resistor 250 compensates for the difference in resistance between the first output transistor 30 and the second output transistor 140. A second embodiment of the first bias circuit and the second bias circuit are shown in FIGS. 6A and 6B, which provide a first bias signal and a second bias signal, respectively. These two independent bias signals can be more accurately controlled through the negative feedback work of an operational amplifier during process, power supply voltage and temperature fluctuations! 241768 15338twf.doc / 006 maintains the first and second revolutions rate,. 6A and 6B are circuit diagrams showing a second preferred embodiment of the bias circuit in the present invention. As shown in FIGS. 6A and 6B, they are a second embodiment of the first bias circuit: and the second bias circuit 65. The first bias circuit _ includes a first bias variable resistor 610, a first bias transistor 62, a bias operational amplifier 63G, and a rising slew rate control resistor_. The second terminal of the bias variable resistor 61G from Wei to the first power terminal m ϊη㈣10 is coupled to the tube of the first bias transistor 620 and the second terminal of the bias transistor 620 is coupled to the- The bias operation is the positive input terminal and the rising slew rate control resistor 640 =. The other end of the rising slew rate control resistor 640 is rigid. The first bias transistor is closed: =, the first bias operational amplifier 63. The negative input terminal 鳊, and the voltage of the power terminal-the average voltage of the power terminal =. The first bias op amp 62 = the first bias voltage can be used to make a light contact. In addition, the electrical characteristics of the% I terminal and the first-bias signal section-slew rate ^ resistance ㈣ are substantially the same as those of the first variable resistor 240 of the first circuit, and the electrical characteristics of the transistor 620 are substantially the same as The first-output power: The electrical characteristics of the body 13 are the same. In the same way, the second bias circuit 65 ° ™ ^ aa0 " 670 ^ -end: the falling slew rate control resistor 69. The main power source 钿 170. Falling slew rate control resistor 690 17 1241768 15338twf.doc / 006 The positive input terminal of the two-biased butterfly amplifier 680 and the first input #, edit. The second bias voltage op amp 080 has a different power supply terminal, and the voltage of this power supply terminal is the average power of the first power trace terminal m and the second power supply terminal. ; = Second :, 67, her second biased variable resistor _ The second biased transistor 070 gate button 蛀 $ 常 ^ Brother editor The voltage-variable resistor 660 Xi M lightly connected to the Pa source terminal 170. The first terminal of the second bias d Tiexi R is coupled to the second power terminal 180. The second bias i 11 and the adjustment terminal of 060 are coupled to the second output terminal and the second ㈣w ~ 状 连 # is enlarged to 680 and the electrical characteristics of the resistance 660 ~, occupy. In addition, the second bias variable variable resistor 250 ^ has the same electrical characteristics as that of the second circuit of the loopback circuit, the rising, port / metastatic transistor 140. The resistance of the rising slew rate control resistor _ control resistor 690 is the same. The value of μ 贝, lower ~ slew rate is determined by the sum of the electrical circuit rise ^ slew ± rate control resistance 640 and _ resistance (CL).彳, 'Rise' the capacitance of the load carrier circuit For a first-order system, R ~ t / q. The capacitance is PS and the load transfer rate is two or two = and the resistance is 2 ° ohms). When the rise-back requirement rises, the difference between the electric ink difference at the logic high level is divided by the negative feedback function of the piezo amplifier 630. The equivalent resistance of the -bias 610 and the first bias transistor 620 is substantially 18 1241768. 15338tvvf.doc / 006-('The resistance value of Riding Anri Sun Body 620 is changed, the first bias value will be adjusted in 5 weeks' to ensure that the first biased variable resistor 610 plate and the first biased transistor 620 The equivalent resistance value will still be the same. In addition, the variable resistor 610 simulates the first variable resistor 240 of the-slew rate control circuit. The-biased crystal ㈣ simulation-the output transistor The -_ signal of the biased operational amplifier 630, the equivalent resistance of the first variable resistor 24G and the -first output transistor 13G is -biased, and the variable resistor 61G is equivalent to the -biased crystal 62. The resistance values will be essentially the same. Therefore, during the period of ρντ, the upper rate is qualitatively constant, but it is constant. The same principle applies to the second bias circuit. By setting the rising slew rate ㈣ resistance _Essentially the same as the resistance value of the falling slew rate control resistor 690, the rising and falling slew of the output voltage They should be the same and symmetrical to each other. For the second embodiment of the first bias circuit 600 and the first bias circuit 650 shown in FIGS. 6A and 6B, those skilled in the art should be able to: The first bias variable resistor 610 and the second bias variable resistor ^; ^ are implemented using many different methods, as long as they respectively simulate the first variable resistor 240 and the second slew rate control of the first turning ^ control circuit + The second variable resistor 250 is sufficient. A Figure 7A shows the circuit diagram of the bias circuit shown in Figure 6A, where the variable resistor includes a resistor and a transistor coupled in parallel as shown in Figure 7A The first bias variable resistor 610 may include a first bias voltage ^ 19 1241768 15338twf.doc / 〇〇6 L: and a first adjustment transistor 715 'This first-bias variable resistor acts like the first rotation The first rate control circuit :: = r:; r works

A private resistor 310 and a first control transistor 320 are prepared. FIG. 7B is a circuit diagram of the bias circuit shown in FIG. 6B, in which a variable resistor and a transistor are lightly connected in parallel. As shown in FIG. 7B, the resistor _ may include a second bias transistor and a transistor 765 'this second bias variable resistor_ serves as the first of the second variable resistor 25 of the second slew rate control circuit. A better one works as an example. In this embodiment, the second variable resistor includes a second resistor 330 and a second control transistor 34. In one embodiment, the first adjustment transistor 715 and the -preferred transistor ^ are preferably PMOS transistors. The second adjustment transistor and the first bias transistor 77 ° are preferably NMOS transistors. The first power terminal 170 provides a positive voltage VDD, and the second power terminal 180 provides a ground. The first bias resistor 71 °, the pM0s transistor 72 °, and the rising slew rate ㈣ resistor 740 are connected across the ((ν〇Ι)) and ground: the gate of the PM0S transistor 720 is grounded. The pM0s transistor 715 and the first bias resistor 71o are connected lightly in parallel. The positive input terminal of the first waste-amplified operational amplifier state 730 is coupled to a common node of the pMOS transistor 72 and the rising slew rate control resistor 740. A negative input terminal of the first bias operational amplifier 73 is coupled to a power source having a reference voltage VDD / 2. An output terminal of the first bias operational amplifier 730 is coupled to a gate of the PMOS transistor 715 and a first bias signal node. 20 1241768 15338twf.doc / 006 A slew rate control resistor 79 °, NMOS transistor 77 °, and -1st left resistance 76G are connected in series and connected across the power supply (vdd) and ground =. NMOS transistors are very lightly connected. Radisson transistor = 65 and the second bias resistor is connected in parallel. The second bias calculation puts the positive wheel input of σσ to the common node of the falling slew rate control resistor 790 and the electric carcass 770. The second biased operational amplifier 780 is connected to a power source with a reference voltage / 2. An output terminal of the second bias amplifier 780 is coupled to the nm pole and a second bias signal node. Figure 8 of W 765 is a circuit diagram of a preferred embodiment of an output circuit with different input and output signals in the present invention. As shown in Figure 8, an output circuit with different input and output signals can reduce the ground bounce effect caused by signal switching. The output circuit 输 includes an input point 810, an input complementary node 815, an output node 82, an output complementary node 825, a first output transistor 83 and a second output transistor_series minus, a third output transistor 835, and a fourth The output transistor is coupled in series, the first slew rate control circuit 85 and the second slew rate control circuit 860. The first slew rate control circuit 85 is coupled between the first power supply terminal and a common node of the first output transistor 830 and the third output transistor 835. The second slew rate control circuit 860 is coupled between the second power terminal 88Po and a common node of the second output transistor 840 and the fourth output transistor 845. The input node 810 is coupled to the gate of the first output transistor 83 and the gate of the first output transistor 840. The input complementary node 815 is lightly connected to the gate of the second output transistor 835 and the gate of the fourth output transistor 21 1241768 15338twf.doc / 〇〇6. The output node 820 is coupled to a common node of the first output transistor 830 and the second output transistor 840. The output complementary node 825 is coupled to a common node of the first output transistor 835 and the fourth output transistor 845. — In one embodiment, the first output transistor 830 and the third output transistor 835 are both PMOS transistors, and the second output transistor 84o = and the fourth output transistor 845 are NMOS transistors. The input node_ is coupled to the gate of the PMOS transistor 830 and the gate of the NMOS transistor 84o. The input complementary node 815 is coupled to the gate of the PMOS transistor 835 and the gate of the NMOS transistor 845. The output node 820 is connected to the drain of the PMOS transistor 830 and the drain of the NMOS transistor 84. The output complementary node 825 is lightly connected to the drain of the pMOS transistor 835 and the drain of the NMOS transistor 845. The first slew rate control circuit 85 is lightly connected to the sources of the PMOS transistors 830 and 835. The second slew rate suppression circuit 860 is coupled to the source of the NMOS transistors 84 and 8. FIG. 9 shows a circuit diagram of another preferred embodiment of an output circuit with different input and output signals in the present invention. As shown in FIG. 9, the output circuit 900 further includes a first resistor 910, a second resistor 92, a first capacitor ㈣, and a second capacitor 940. The first slew rate control circuit 850 includes a first variable resistor 950 'and the second slew rate control circuit 85 includes a second variable resistor 960. The first output resistor 910 is lightly connected between the output node 820 and the common node of the first, output transistor 83G and the second output transistor. The first output resistor 920 is connected between the wheel-out complementary node 825 and the common node of the third output transistor 835 and the fourth output transistor 845. The first output resistance 9H) and the second output resistance 92 ° can alleviate the distortion of the reflection signal caused by the impedance matching of the circuit and the circuit of 22 1241768 I5338twf.doc./〇〇6. A capacitor 930 connected to the second power terminal 880 is coupled to the body capacitor, the third output transistor 835, and the first capacitor and the second capacitor altogether: Lang point. The second capacitor 940 is coupled to a second node of the second power supply terminal, the first output transistor _, the fourth output transistor 845, and the first output capacitor 960. The first capacitor 930 and the second output capacitor 94G can Improve the symmetry of the rising and falling slew rate of the output, but ^ may also slow down the circuit operation speed. The first output transistor tt and the third output transistor

If two MOSFET transistors, the second output transistor and the fourth output transistor 845 are both nm = VDD, and one terminal of the second power supply terminal 88 ’resistor 910 is lightly connected to the output node 820. The first output two s-terminals are connected to the poles of the PMMOS transistor 830 and to the drain of the two-pole " ". The-terminal of the second output resistor 920 is lightly connected to the output complementary point 825. The other end of the second output resistor 92 is connected to the drain of the PMOS transistor 835, and the terminals of the resistor 950, _S transistor 830 are connected to the source of the ㈣ + / crystal 835. One of the second capacitors 940 is coupled to the ground electrode M. The 3__ variable resistor 960 of the second capacitor 940 and the NMOS transistor 84 are the source of the body 845. "The source of the version _ and the first and second preferred embodiments of the first variable resistor of the NMOS transistor can both be used. 23 1241768 15338twf.doc / 006 The technique X is now a variable resistor 950, dual listening This and the second preferred embodiment can be used to implement the second to the second, the second to the second-the same, the first bias circuit 500 and 600, ~ ~ = = 960. Examples are The first and first resistors 950, which can be used to generate a first bias signal to the second and second, and the second bias circuits 500 and 650, can both be used to generate a second bias signal to Although the present invention has been disclosed in the preferred embodiment as above, the present invention is well-defined, and anyone skilled in this art can make some modifications and retouching within the scope of money = not for use. Therefore, the scope of the spirit should be regarded as a poster. Please define it _ Ming Bao's gift [simple description] '' '' pole ° road map '' ㈣ her towel __ electrical circuit of her best embodiment = material is The circuit diagram of the resistor of the preferred embodiment of material 1 in this wealth, where the variable resistor includes a resistor and a transistor and FIG. 4 shows the composition of the output circuit shown in FIG. 2The resistor consists of two transistors connected in parallel. Talk about the diagram 'where the variable circuit = the embodiment of the first preferred embodiment of the bias circuit in the present invention is shown. The two preferred embodiments are shown in Figures 7A and 7B! 6A. The circuit of the bias circuit shown in FIG. 24 1241768 15338twf.doc / 006, in which the variable resistor includes a resistor and a transistor coupled in parallel. FIG. 8 is a circuit diagram of a preferred embodiment of an output circuit with different input and output signals according to the present invention. FIG. 9 is a circuit diagram of another preferred embodiment of an output circuit with different input and output signals in the present invention. [Description of Symbols of Main Components] • 100, 200, 800, 900: turn-out circuit 11 〇 · input node 120: output node 130: first output transistor-140 · • second output transistor 15, 85: first slew rate control circuit 160, 860: second slew rate control circuit 170, 870: first power supply terminal 180, 880: second power supply terminal 210, 910, 920: output resistance 220, 930: first Capacitors 230, 940: Second capacitors 240, 950: First variable resistor 250, 960: Second variable resistor 310, first resistor 320, first control transistor 330, second resistor 25 1241768 15338twf.doc / 006 340: first Two control transistors 410. First control transistor 420: Second control transistor 430: Third control transistor 440: Fourth control transistor 500, 600, 650: Bias circuits 510, 520: Bias voltage Crystal 610: First biased variable resistor 620, 720. ·-Biased transistor 630, 730: First biased operational amplifier 640, 740: Rising slew rate control resistor 660: Second biased variable resistor '670, 770: second bias transistor * 680, 780: second bias op amp 690, 790 : Falling slew rate control resistor 710: first bias resistor 715: first bias transistor 760: second bias resistor 765: second trim transistor 810: input node 815: input complementary node 820: output node 825: Output complementary node 830: first output transistor 26 1241768 15338twf.doc / 006 835: third output transistor 840: second output transistor 845: fourth output transistor

27

Claims (1)

1241768 15338twf.doc / 006 10. Scope of patent application: 1. An output circuit, including: an input node; an output node; a first output transistor and a second round output band, a first slew rate The control circuit is coupled in series with the body, between the transistor and a first power terminal, which is connected to the first output And providing a variable resistance-second slew rate control circuit coupled between the and-the second power supply terminal, configured to provide a transistor to which the input node is coupled to the first-and- The output pole of the second output transistor, the output === the output transistor and the second output transistor = :: = node) ° 2 · The output circuit as described in item 4 of Wei 4 of Shen Zhuan, The slew rate of the input voltage at the output node does not change significantly with process, voltage, and temperature variations. 3. The output circuit as described in item 1 of the scope of patent application, further comprising: an output resistor coupled to the output node and a node of the first output body and the second output transistor. The output circuit as described in item 1 of Shenyan's patent scope further includes: a first capacitor, which is coupled to the second power terminal and the first round power-emitting crystal and the first slew rate control A common node of the circuit; and a second capacitor coupled to the second power terminal and the second round of power 28 1241768 15338twf.doc / 006 the common node of the crystal and the second slew rate control circuit. 5. The output circuit according to item 1 of the scope of patent application, wherein the first slew rate control circuit includes a first variable voltage, wherein the resistance value of the -variable resistor should be derived from the -first bias. A first-bias signal of the voltage circuit; and the second slew rate control circuit includes a second variable resistor, wherein the resistance value of the second variable resistor is in response to one from a second bias circuit The second bias signal. 6. The output circuit as described in item 5 of Shenjing's patent scope, wherein the first variable resistor includes a first resistor and a first control transistor coupled in parallel, wherein the gate coupling of the first control transistor Connected to a first bias signal node of the first bias circuit; and the second variable resistor includes a second resistor and a second control transistor coupled in parallel, wherein the second control transistor The gate is coupled to a second bias signal node of the second bias circuit. 7. The output circuit as described in item 6 of the patent claim, wherein the first output transistor and the first control transistor are both PMMOS transistors, and the second output transistor and the second control transistor The transistors are all NMOS transistors. 8. The output circuit according to item 6 of the scope of patent application, wherein the first bias circuit includes a first bias transistor and a second bias transistor coupled in series and connected across the first power source. Between the terminal and the second power terminal, the first bias signal node is connected to the gate of the first bias transistor, the gate of the second bias transistor, and the first bias transistor and 29 1241768 15338twf.doc / 006 The common node of the second piezoelectric crystal; r dry Γ bias circuit includes ~ the third bias transistor and-the fourth bias transistor are connected in series to You La Si and Si Bi Bi terminal Gate, # 衣, 5 is connected to the first power terminal and the second power gate: the first: the signal node is coupled to the gate of the second bias transistor 222r, the four piezoelectric crystal And the common node of the third bias transistor and the "fourth bias transistor; and" the electrical characteristics of the first bias transistor and the electrical characteristics of the third bias transistor are substantially the same as the first bias transistor The electrical characteristics of an output transistor are the same, and the electrical characteristics of the first bias transistor and the body The electrical characteristics are substantially the same as those of the second output transistor. ^ The output circuit according to item 8 in the scope of the patent application, wherein the first-output transistor, the first control transistor, the first bias transistor, and the third bias day-day body are all PMQS devices. Crystal, and the first: tritium transistor, the second control transistor, the second bias transistor and the fourth bias transistor are all NMOS transistors. The output circuit as described in item 5 of the scope of the patent application, wherein the first bias circuit of 5xuan includes a -th bias-variable resistor, a first bias transistor, a -th bias operational amplifier, and- Rising resistance;… the first: the first-wheel of the bias variable resistor is connected to the first-power terminal, the second terminal of the «Heidi left-side Dingshi resistor is coupled to the f terminal of the first bias transistor, . The second end of the first bias transistor is coupled to the positive end of the first bias operational amplifier and the first 30 1241768 15338twf.doc / 006 end of the rising slew rate control resistor. The second terminal of the resistor __ the second terminal, the-bias transistor is very lightly connected to the second: the negative wheel of the bias op amp's negative end is lightly connected to a thunder ' A power supply terminal and the output terminal of the second two-biased waste transporter to the 鄕 -bias resistance adjustment terminal and the first bias signal node; Wendian I (the second bias calendar circuit includes a second biasing transformer Resistance, piezoelectric crystal, a second bias operation to amplify the resistance; and ^ amplification "and a falling slew rate control of the falling slew rate control resistor-connected to the first power supply: put control The second terminal of the resistor is the second bias terminal = the positive input terminal of the amplifier and the negative input terminal of the second bias op amp of the second bias transistor is reduced to the -power terminal and the voltage of the power source t is The second power supply terminal and the second power supply terminal = electricity; the second end of the bias transistor is light. To the first: terminal of the second bias variable resistor ^ the open terminal of the second bias transistor is lightly connected to the first-power terminal, the 4: the second terminal of the cross-connectable resistor is coupled to the second power Terminal, the adjustment terminal of the second 3-k resistor can be connected to the output terminal 2 of the second bias operational amplifier and the first and bias signal nodes; wherein the first bias variable resistor and the first bias The voltage and the first variable resistor of the first slew rate control circuit and the first transistor have substantially the same electrical characteristics. The second bias variable encapsulation! And the second bias The piezoelectric crystal has substantially the same electrical characteristics as the second variable resistor and the second output transistor of the second slew rate control circuit 31 1241768 15338twf.doc / 006. Substantially _ impedance. K to sheep dagger system 11. The output circuit described in item 6 of the scope of patent application, the-bias circuit includes-a first bias resistor, a second crystal,-the-bias Piezoelectric crystal,-the first-bias operation to amplify the rising slew rate control resistance, where the- The piezo and the transistor are connected in parallel to form the first bias-variable resistor; X °° the first bias resistor, the first bias transistor, and the rising return rate control circuit are connected and reduced across — Between the source and the source terminal 'the positive input terminal of the-bias operational amplifier _ =-the common node of the bias transistor and the rising slew rate control resistor, = the negative of a bias operational amplifier The input terminals are connected;; = 1 £ is the output of the voltage-biased operational amplifier of the power supply terminal and the second power supply terminal connected to the first-transistor transistor and the first bias signal node; A The second bias circuit includes a second bias resistor, a second tuned crystal, a second bias transistor, and a second bias ^ 1 operational amplifier: a falling slew rate control resistor, of which The bias resistor and; the ^ th rectifier transistor are coupled in parallel to form a second bias variable resistor; and the falling slew rate control resistor, the second bias transistor and two bias resistors are serially reduced and connected across Between the _th power source terminal and the driving source terminal, the positive input shaft of the second bias operation amplifier A || The common node of the rate control resistor and the second bias transistor, = the second bias operation amplifies the IIL terminal to the power terminal and the voltage of the power terminal 32 1241768 15338twf.doc / 006 is the first power terminal and the first -The first pole and the second bias signal node of the wheel of the two-bias operational amplifier; the gate of the withering private crystal, wherein the first bias variable resistor and the first slew rate control circuit 3 The bias transistor split-output transistor has substantially the same electrical and the first resistance and the second bias transistor and the second bias transistor The second variable resistor and the second output circuit of the Leiweng Ke, · ^ μer, 4th solar body ', have the same electrical hole characteristics & Hongsheng slew rate control electrical resistance has Substantially _'s impedance. Decrease_rate control 12. The output circuit as described in item 5 of the scope of patent application, the -variable resistor includes-the first control transistor and two = transistor in parallel coupling, the -th control transistor- Terminal = the first terminal of the transistor and the first power terminal. The second terminal of the first transistor is reduced to the gate of the second control transistor. The gate of the transistor and the first output transistor. , Control = = = to the first voltage-check signal ^ the second variable resistor includes a third control transistor and a fourth control transistor in parallel minus the third control transistor The first terminal is connected to the first terminal of the control transistor, the gate of the third control transistor, and the first output transistor. The second position of the third control transistor is connected to the emperor crystal. The second terminal and the second power terminal, the closed pole of the fourth control pen crystal _ to the second bias circuit-the second bias signal section 33 1241768 15338twf.doc / 006 Ο 13. · A kind of output circuit, including: an input terminal and an input complementary node · an output node and an output complementary node · a first output transistor and a second Sheshan third output transistor and a first crystal Serial coupling;-the first slew rate control (slew coffee) = electric f-body connected in series to the two source terminals and the first output transistor and the third important; ^ point (c__Gde) is configured to improve = Two slew rate control circuits, connected between a second power supply terminal and the first output transistor and the fourth output transistor, are configured to provide variable resistance; "▲ ^, read human gp The point is reduced to the question of the first-round transistor and the gate of the second output transistor. The output node is secreted to the common node of the first output transistor and the second output transistor, and the input complementary node. Lightly connected to the gate of the third output transistor and the gate of the twenty-four output transistor, the output complementary section is connected to the common node of the third output transistor and the fourth output transistor. 14 · If stated Output circuit described in patent scope item 13 In which, the output voltage at the output point and the output voltage on the complementary node do not have a slew rate ^ Ik 'Private writing pressure and temperature variations (variations) and there is a significant change.' 15 · As in the 13th patent application scope The output circuit described above also includes 34 1241768 15338twf.doc / 006 & a query for the common point of the transistor; and the output power is' coupled to the output complementary node and the third output is also "the brother four rounds out Common node of transistor. — Including 16. The wheel-out circuit as described in item 13 of the scope of the patent application, more specifically, a ‘first capacitor, coupled to the second power supply terminal and the 忒 The second output transistor and the first rotation ^: node; and a common capacitor of the dry circuit to remove a second capacitor, and lightly connect to the second power terminal and the second output transistor and the phase output transistor. The total with the second slew rate control circuit = I ?. The output circuit as described in item 13 of the scope of patent application, wherein the first slew rate control circuit includes a first variable resistor / where the first variable The resistance value of the resistor responds to a bias signal from a first bias circuit; and the second slew rate control circuit includes a second variable resistor, where the resistance value of the second variable resistor is a response Two or two bias signals from a second bias circuit. $ 一 18. The output circuit according to item 17 of the scope of patent application, wherein the first variable resistor includes a first resistor and a first control circuit connected in parallel and lightly connected, wherein the first control circuit The gate of the crystal is lightly connected to a first bias signal node of the bias circuit; and the second variable resistor includes a second resistor and a second control transistor 35 1241768 15338twf.doc / 006 3, kiss A second bias signal node of a bias circuit of ij is found in ij. = ^^ Special fiber circuit of the wheel-out circuit described in item 18, wherein the transistor ^ outputs the transistor and the first control transistor tb # /, _body, and the second output transistor and the first ::: = MoS NMQS transistor. The industrial package and the Japanese body are all specialized, and the 8 described output roads are connected in series and connected across the first electrical second offset = the first partial waste signal node _ source the second partial electrical The common node of the crystal; "The second bias circuit of the electric body and the mouth is composed of one or two bands. The electric characteristics of the second bias transistor and the body of the fourth bias transistor are substantially different. The disc and the four biased transistors are the same. 彳 "The electrical characteristics of Beishangbai and the second output transistor are applied to the output circuit described in Item 20 of the If mountain patent scope, in which the-output transistor, the-control Transistor, the first: bias ink 36 1241768 15338twf.doc / 006 transistor and the third bias transistor are the second output transistor, the second control transistor, the first: body Hai and the fourth The bias transistors are NMO S transistors. The output circuit described in item 17 of the scope of patent application, the first bias circuit includes a first biased variable resistor, a first crystal, a first voltage operational amplifier, and- Ascent rate The first terminal of the first bias variable resistor is lightly connected to the first power terminal, and the second terminal of the variable bias resistor is connected to the second terminal of the first biased crystal. Lightly connected to the positive input terminal of the first bias operation amplifier and the first terminal of the rising slew rate control resistor, the second terminal of the rising slew rate control resistor _ to the second power terminal 'the second bias voltage The gate surface of the transistor is connected to the second power terminal, the negative input terminal of the first and a biased operational amplifier is coupled to a power terminal, and the voltage of the primary terminal of the transistor is the first power terminal and the second The voltage at the power supply terminal is averaged, and the output terminal of the first bias operational amplifier is coupled to the adjustment terminal of the first bias variable resistor and the first bias signal node; the first bias circuit includes a first Two bias variable resistors, a second bias transistor, a second bias op amp, and a falling slew rate control resistor; and a first terminal of the falling slew rate control resistor is coupled to the first power terminal , The second terminal of the falling slew rate control resistor is coupled to the second bias operation The positive input terminal of the amplifier and the first terminal of the second biased transistor. The negative input terminal of the second biased operational amplifier is coupled to a power terminal and the power terminal 37 j241768 l5338iwf.d〇c / 〇〇6 The voltage is the average value of the electric dust on the second end of the second biased crystal of the first power source, the second biased variable resistor of the second biased crystal with the second biased variable resistor The second 11th horse is connected to the first power supply terminal, and the bias variable resistance is adjusted. The second power supply terminal, the second output terminal, and the second preferred signal node are the inputs of the biased op amp. Wherein, the first bias voltage can be changed with the first slew rate control circuit and the first bias transistor output wheel transistor has substantially the same phase as the first variable resistance and the first resistance and the The second preferred transistor = characteristics, the second bias voltage is variable, the second variable resistor has a second slew rate control circuit, and the electrical characteristics of the upper and lower Ditzon 4-wheel-out pen crystals are substantially the same Resistance has essentially the same resistance = control resistance and this falling slew rate control Body, - a first partial iv = partial core;? Resistance, a first adjusting electric rise rate control resistor, ... calculate the amplifier and -then rectify the μ ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, and the resistance of the first steel and the first steel: said, the sub-coupling forms a first Bias variable resistor;. 4 The first bias resistor, the first emperor, the resistor is connected in series and connected across the first ===== turn two = 1 The positive input of the biased operational amplifier is connected to i; 1 And the hill point of the rising slew rate control resistor—calculate; the negative input terminal of the device is connected to the -power terminal and the electricity :: Μ 糸 The voltage between the first -power terminal and the second power terminal is averaged, the first 38 1241768 15338twf.doc / 006-the output of the biased operational amplifier is reduced to the third pole and the first biased signal node; Xun Wang-Zhi-Zhi Crystal, Xuan Di: The bias circuit includes a second bias resistor, a drop-down two-transistor, a second bias op amp, and a control resistor below the second bias resistor. Electricity's rectifier transistor is connected in parallel with the Kuma connection to form a second bias variable electrical follower, and χ, the falling slew rate control resistor, the i-th! Piezo-resistor is connected in series to the first-power-second; In between, the positive input terminal of the second bias operational amplifier is coupled to; the common node of the second second crystal is-voltage system; when the negative wheel input terminal is coupled to a power terminal and the power terminal The voltage between the source terminal and the second power terminal is averaged, and the output terminal of the Ϊ i π amplification is coupled to the second adjusting transistor and the second bias signal node; -The bias variable resistor and the first bias transistor, the first variable resistor and the first variable resistor and the second variable resistor have the same electrical characteristics, the second bias can be And the second polarized ink crystal and the second slew rate control circuit are respectively a resistor and the The two output transistors have substantially the same resistance, and the rising slew rate control resistance and the falling back resistance have substantially the same impedance. As claimed, the output circuit described in item 17 of the monthly patent scope, where The resistor includes a first control transistor and a second control transistor. The first end of the first control transistor is connected to the 39 1241768 15338twf.doc / 006 Terminal and the first power terminal, the second terminal of the first control transistor is coupled to the second terminal of the second control transistor, the gate of the first control transistor, and the first output transistor, the The gate of the second control transistor is coupled to a first bias signal node of the first bias circuit; and the second variable resistor includes a third control transistor and a fourth control transistor in parallel. Connected to the first end of the second control transistor to the first end of the fourth control transistor, the gate of the third control transistor, and the second output transistor. The second terminal is coupled to the fourth control The second terminal of the transistor and the second power terminal, the gate of the fourth control transistor is coupled to a second bias signal section of one of the second bias circuits