1241662 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種金屬氧化半導體裝置及其製作方法， 詳言之，係關於一種具有内部阻絕層之金屬氧化半導 置及其製作方法。 、 【先前技術】 集合美國、歐洲、台灣、日本和韓國之半導體技術協會 (SIA)之專家所共同制訂之國際半導體技術藍圖，訂出未來 製作奈米金氧化半導體元件技術之方向，也提出了一些 瓶，：對於傳統CM0S製程來講，最嚴重的問題（issues); 能是漏電流問題，太多的寄生PN接面電容與嚴重的超短通 道效應。參考圖1所示，習知之金屬氧化半導體裝置⑺包 括：一基板11、一本體12、一源極13、一汲極14、一閘極 氧化層15及一閘極16。該本體12形成於該基板丨丨上。該源 極13及該汲極14形成於該基板丨丨上且設置於該本體12之側 邊。若該基板11與該本體12為！>型，該源極13及該汲極14 為N型，故pn接面之區域過大，而造成漏電流之問題與太 多的寄生PN接面電容。另外，在該習知金屬氧化半導體裝 置1〇之該源極13及該汲極14間之通道17具有嚴重的超短通 道效應。 參考圖2所示，其顯示習知具有矽覆絕緣S0I基板之金屬 氧化半導體裝置20。該習知之金屬氧化半導體裝置2〇包 括：一基板21、一本體22、一源極23、一汲極24、一閘極 氧化層25及一閘極26。該基板21具有一基底211及一埋入氧 97878.doc 1241662 統之性能也因此大幅降低。同時也產生了金屬氧化半導體 裝置的門檻啟動電壓(Thresh〇ld v〇ltage)對超薄厚度不均 勻性之嚴重敏感問題。 化層2】2。利用埋入氧化層212減少pN接面，以減少漏電流 和寄生PN接面電容。習知金屬氧化半導體裝置_可舒緩 超短通道效應，但為了進—步解決漏電流、寄生電容與超 短通道問《，卻完全仰賴超薄厚度时薄層。然因為咖 具有-完全隔離梦薄層之埋氧化層（Buried〇xide)，散熱不 易而造成通道層之帶電載子嚴重地被自我加熱，元件和'系 同樣的，在液晶薄膜顯示器應用之薄膜電晶體（金屬氧化 半導體裝置)也會遭遇嚴重之漏電流、自我加熱效應和均句 超薄厚度需求等問體。 目前解決上述問題的方法並不多見，而同時能夠解決漏 電流、寄生電容與超短通道效應、自我加熱效應、浮體 (Floating Body Effect)與屈膝效應（Kink Effect)及單拴走火 效應（Smgle Latch Up)四大問題之方法亦屬稀有。如前所 述，為了解決嚴重之漏電流問題、寄生電容和超短通道效 應問題’ 一些製作厚度均勻性好的超薄矽薄膜之專利被提 出’也有利用比較好之旁側絕緣材質來減低隔離島之漏電 流（如美國專利第5,034,789號及第5,053,353號）。解決自我 加熱效應問題之專利，幾乎沒有。解決浮體與屈膝效應問 題之專利（如美國專利第6,746,937號，第6,794,716號），大 都是利用具有浪費面積的本體缚點端（B〇dy tie)的元件架 構。另外’美國專利號第6,218,249號及第5,43〇,315號揭示 97878.doc 1241662 雖然能製得出性能較佳太 之不米兀件，然而因為都是利用傳 、至乳化半導體架構和傳統之SOI架構配合超淺接面 深度，但都未能同時減輕或解決上述提出的問題。 【發明内容】 部。该閘極氧化層形成於該半導體層上 該閘極氧化層上。 ”本么明之目的在於提供一種具有内部阻絕層之金屬氧化 半導體#置，包括：_基板、_本體、—内部阻絕層、一 二‘電之半導體層、一閘極氧化層及一閘極層。該本體形 成於違基板上。該内部阻絕層形成於該基板上且設置於該 本體之側邊。忒具導電之半導體層形成於該本體及該内部 阻絕層上，該半導體層具有-中央部、-源極部及一沒極 遠閘極層形成於 本卷明之另一目的在於提供一種具有内部阻絕層之金屬 氧化半導體裝置之製作方法，包括以下步驟：⑷提供一基 板；（b)形成一本體於該基板上；（c)形成一内部阻絕層於該 基板上且於該本體之側邊；（d)形成一具導電之半導體層於 該本體及該内部阻絕層上；（e)形成一閘極氧化層於該半導 體層上；（f)形成一閘極層於該閘極氧化層上，係相對於該 本體位置之該閘極氧化層上；及（g)於該半導體層形成一源 極部及一汲極部。 本發明之金屬氧化半導體裝置利用該内部阻絕層介入該 本體與该源極部及该沒極部之間’以取代原來之PN接面， 可降低金屬氧化半導體裝置中PN接面的面積而大幅降低漏 電流與PN接面電容。且經由適當選擇材質，也同時能夠解 97878.doc 1241662 決或終止原來金屬氧化半導體裝置之PN接面之電場及壓制 其造成之元件空乏區向本體延展，進而可以同時壓制超短 通道效應，且沒有浮體效應及自我加熱效應。 【實施方式】 請參閱圖3，其顯示本發明金屬氧化半導體裝置之示意 圖。本發明之具有内部阻絕層之金屬氧化半導體裝置3〇主 要包括··一基板3 1、一本體32、一内部阻絕層33、一具導 電之半導體層34、一閘極氧化層39及一閘極層35。 該基板可為矽覆絕緣（SOI)基板（如SIMOX，BESOI，或 SmartCut等SOI基板）、鍺覆絕緣（G0I)基板、晶圓基板、玻 璃基板、塑膠基板、藍寶石（Sapphire)基板、鑽石基板或ΙΠ 一 V族基板等等。 參考圖4Α所示，其顯示具有埋入氧化層之基板。該基板 41具有一基底411及一埋入氧化層（Buried 〇xide)412。該埋 入氧化層412係形成於該基底411之上。參考圖4B所示，其 顯示具有埋入氧化層之基板，該埋入氧化層具有一通道。 該基板42具有一基底421及一埋入氧化層422。該埋入氧化 層422係形成於該基底421之上，且該埋入氧化層422中具有 一通道423 ’該通道係相對於該本體之下，以連接該基底 與該本體。 另外，有些基板（例如SOI基板）其最下面為一基底層，中 間為絕緣埋層，其上面具有可導電之半導體層。再者，有 些基板（如玻璃基板）具有一絕緣基底，其上具有或可成長一 層導電之半導體薄層。而傳統普通晶圓基板，其基板即為 97878.doc 1241662 基底可^電之半導體層就直接應用基底之接近表面層。 再參考圖3，該本體32形成於該基板31上。該内部阻絕層 33形成於β亥基板3 !上且設置於該本體”之側邊。該内部阻 絕層33之材質係選自由二氧切、氮㈣、氧氮氧_〇)、 工氣I (Air Gap)、具有不同摻雜雜質濃度之金屬矽化物、 或金屬所組成之群。 该具導電之半導體層34形成於該本體32、該内部阻絕層 33上。該半導體層34具有一中央部341、一源極部342及一 汲極部343。該中央部341可與該本體32視為一體。該金屬 氧化半導體裝置30之該源極可包括該源極部342及一第一 半導體區塊347 ;該汲極可包括汲極部343及一第二半導體 品鬼348局邛成長的该半導體層34，是以本體32及該第一 半導體區塊347與第二半導體區塊348當晶種（Seed)。 忒半導體層34之中央部341係於該本體32上，或該本體32 及部分内部阻絕層33上，該源極部342及該汲極部343係分 別於该中央部341之側邊，且於部分阻絕層33上。該半導體 曰34之；度可為〇·5 nm至1 〇 ηη]^ 〇·5 nm以上。該半導體層 Μ係選自由第四族或m_v族材料所組成之群，如以，g。 SiC、SiGe、...GaAs等以增加金屬氧化半導體裝置之移動 率亦可开》成雙或多層來形成制張力（Tensile Strain)或壓縮 力（Compressive Strain)來加強金屬氧化半導體裝置通道層 之載子移動率。 因此，本發明之金屬氧化半導體裝置3〇的pN接面為内部 阻、、、邑層3 3所取代，僅存的pn接面在該局部成長的半導體層 97878.doc 1241662 34中，亦即，該中央部341與該源極部342之接面344，及該 中央邛341與该源極部343之接面345。該接面344及345係容 午金屬氧化半導體裝置之通道載子（Channel Carrier)能進 出之適§進出口。該適當出口大小由局部成長之半導體層 34所決定。換句話說，本發明之該金屬氧化半導體裝置之 側面（SideWall)都為淺溝隔離（STI)之絕緣氧化層和内部阻 、、邑層環繞，僅剩下該局部成長之半導體層34之該出口大小 的PN接面344與345。 廣義言之，習知隔離之氧化層和氧化埋層也是阻絕1>?^接 面，可用相同或不同之絕緣材質。本發明之内部阻絕層係 為全面性之阻絕PN接面，包含阻絕本發明之該源極與^本 體，和該汲極與該本體間2PN接面。如此可進一步消除更 多的PN接面面積與寄生的接面電容，且可鬆弛高性能金屬 氧化半導體裝置與電路系統對元件極薄本體厚度之需求。 該閘極層35形成於該閘極氧化層39上。該閘極層35具有 :金屬矽化物層352及一多晶矽層351，該金屬矽化物層 係於該多晶矽層351上，該閘極層35係形成相對於該本體Μ 位置之該半導體層34上。該閘極層35與該半導體層Μ 可先成長約0.5至2奈米之閘極二氧化矽層39或其他等效厚 度約相同之高κ值介電材料。該多晶矽層351及該金屬矽化 物層352具有適當高摻雜濃度以使門檻電壓（Thresh^d Voltage)最佳化。 本發明之金屬氧化半導體裝置30另包括一第—保護層 353，該第一保護層353為氮化矽層，該氮化矽層具有一頂 97878.doc •10- 1241662 部及一側部，該頂部用以覆蓋該金屬矽化物層352，該側部 用以覆蓋金屬矽化物層352及該多晶矽層351之側邊，該頂 部之厚度為10 nm至20 nm，該側部之厚度為5 nm至1〇 nm。 值得注意的是該頂部和該側也可選用適當之不同低K值材 質取代，且厚度可依元件需求尺寸做適當改變。 本發明之金屬氧化半導體裝置30另包括一第二保護層 36,該第二保護層36可為二氧化矽層或適當之低K值材質， 口亥弟一保羞層形成於该第一保護層3 W之側邊。本發明之金 屬氧化半導體裝置30另包括一源極接觸層37及一汲極接觸 層38，分別於該源極部342及該汲極部343上。 參考圖5A至圖5D，其顯示本發明具有内部阻絕層之金屬 氧化半導體裝置5G之第—實施例製作方法示意圖。參考圖 5A，首先提供一基板51。該基板“具有一基底5ΐι及一埋入 乳化層512。然後形成一本體52於該基板51上。可利用活性 蝕刻（RIE)技術定義出金屬氧化半導體裝置％之該本體 52。邊本體52除了當成長半導體層54之晶種外，有助於碰 撞游離之電洞與熱能之排除，值得注意的是，其該本體^ 之鬲度可變化，且本體52之長與寬亦皆可以變化，以得到 較佳且易於控制的元件之本體效應（B〇dy ㈣。隨後形成 内部阻絕層53於該基板51上且於該本體52之側邊。該内 邛阻絕層53係以邊襯製程形成於該本體52之側邊。 再形成一具導電之半導體層54於該本體52及該内部阻絕 層53上。該半導體層54可利用如低溫低壓之化學氣相沉積 (CVD)、濺鍍或電漿加強化學氣相沈積方法形成於該本體w 97878.doc 1241662 上。接著，在該半導體層54上可成長約〇 5至2奈米之閉極 二氧化㈣55或其他等效厚度約相同之高κ值介電材料。 』再形成-閘極層56於該閘極二氧化矽層”上，係相對於 -亥本體52位置之上。該閘極層56包括一金屬矽化物層⑹ 及-多晶矽層561。因此依序形成該多晶矽層561及該金屬 矽化物層562。該金屬矽化物層562係形成於該多晶矽層561 上。之後再形成一保護用之氮化矽層563,該氮化矽層係於 該金屬石夕化物層562之上。之後為了製作更小的奈米級元 件可再進行電子束直寫製程，或進行以石夕化錯當辅助形 成一氧化矽之硬光罩製程，用於形成該閘極層％。值得注 意的是，該金屬⑦化物層562可於閘極定義後再形成。該間 2層56不限於必須為上述之二層結構，該閘極層兄可為適 當功函數（Work Function)之單層或多層之不同金屬，以使 門檻電壓最佳化。 參考圖5B ’再進行邊襯製程，於閘極層兄兩側形成氮化 矽邊襯564和565。該保護用之氮化矽層563及該氮化矽邊襯 564和565可視為一第一保護層，覆蓋該閘極層。之後為進 行源極與汲極之離子佈植，首先地毯式蒸鍍一層離子佈植 散射用之二氧化矽（或其它他低K值材質）層57,該二氧化矽 層57可為一第二保護層，用以覆蓋該第一保護層及該半導 體層54。 ^後於该半導體層54形成一源極部542及一汲極部543。 可利用離子佈植方法，以該閘極層56當遮罩，於該半導體 層54中自行對準形成該源極部542及該汲極部543。該源極 97878.doc 12 1241662 部542及該汲極部543之間為一中央部54卜為了有效降低源 /汲極之串接電阻，離子佈植方法的能量和劑量需要作適當 的調整’以便在緊接著之後的適當高溫下進行熱修護 (Thermal Annealing)製程以形成最適當的源極部542與該中 央部541之接面，及該汲極部543與該中央部541之接面。值 得注意的是，該半導體層54在形成該金屬氧化半導體之通 道之A中央邛541 ’因為有該本體52當晶種，經過此熱修護 動作，該半導體層54的品質無庸置疑。 參考圖5C，利用敍刻將該散射用二氧化石夕層仰成於該 第-保護層周邊之第二保護層邊襯571和572。參考圖5〇， 然後利用閘極層56及其第一保護層及第二保護層邊襯571 和572 ’於暴露之源/汲極作自我對準之升起式源/汲極製 程’當然可配合習知之金屬矽化物製程，也可直接以習知 之。金以自我對齊及邊襯製程形成源極接觸層如與沒極 ㈣層582 °最後可再以自我對準形式餘刻暴露出之導電石夕 薄層，之後地毯式填入適當保護絕緣材質(如丽：1241662 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a metal oxide semiconductor device and a manufacturing method thereof. In particular, it relates to a metal oxide semiconductor device having an internal barrier layer and a manufacturing method thereof. [Previous technology] The international semiconductor technology blueprints developed by experts from the Semiconductor Technology Association (SIA) in the United States, Europe, Taiwan, Japan, and South Korea are gathered to set the direction for the future production of nano-gold oxide semiconductor devices. Some bottles: For the traditional CMOS process, the most serious issues (leakage current), too much parasitic PN junction capacitance and severe ultra-short channel effects. Referring to FIG. 1, a conventional metal oxide semiconductor device ⑺ includes: a substrate 11, a body 12, a source 13, a drain 14, a gate oxide layer 15 and a gate 16. The body 12 is formed on the substrate 丨 丨. The source electrode 13 and the drain electrode 14 are formed on the substrate 丨 丨 and are disposed on the sides of the body 12. If the substrate 11 and the body 12 are! > The source 13 and the drain 14 are N-type, so the area of the pn junction is too large, causing a problem of leakage current and too much parasitic PN junction capacitance. In addition, the channel 17 between the source electrode 13 and the drain electrode 14 of the conventional metal oxide semiconductor device 10 has a serious ultra-short channel effect. Referring to Fig. 2, there is shown a conventional metal oxide semiconductor device 20 having a silicon-coated insulating SOI substrate. The conventional metal oxide semiconductor device 20 includes a substrate 21, a body 22, a source electrode 23, a drain electrode 24, a gate oxide layer 25 and a gate electrode 26. The performance of the substrate 21 having a substrate 211 and an embedded oxygen 97878.doc 1241662 system is also greatly reduced. At the same time, the threshold sensitivity of the metal oxide semiconductor device (Threshold Voltage) is seriously sensitive to the unevenness of the ultrathin thickness.化 化 2】 2. The buried oxide layer 212 is used to reduce the pN junction to reduce leakage current and parasitic PN junction capacitance. The conventional metal oxide semiconductor device can alleviate the ultra-short channel effect, but in order to further solve the leakage current, parasitic capacitance and ultra-short channel problems, it depends entirely on the thin layer at ultra-thin thickness. However, because the coffee has a buried oxide layer (Buried Oxide) that completely isolates the dream thin layer, the heat carrier is not heated easily, and the charged carriers in the channel layer are seriously heated by themselves. The components are the same as those used in liquid crystal thin film displays. Transistors (metal oxide semiconductor devices) also suffer from severe leakage currents, self-heating effects, and ultra-thin thickness requirements. At present, there are not many methods to solve the above problems, and at the same time, it can solve the leakage current, parasitic capacitance and ultra-short channel effect, self-heating effect, floating body effect and knee flexion effect, and single bolt fire effect ( Smgle Latch Up) The four major approaches are also rare. As mentioned before, in order to solve the problems of serious leakage current, parasitic capacitance and ultra-short channel effect, some patents for making ultra-thin silicon films with good thickness uniformity have been proposed. There are also better side insulation materials to reduce isolation Island leakage current (such as U.S. Patent Nos. 5,034,789 and 5,053,353). There are few patents to solve the problem of self heating effect. Most of the patents (such as US Pat. Nos. 6,746,937 and 6,794,716) that solve the problem of floating body and knee flexion effect use component structures with body tie points with wasted areas. In addition, U.S. Patent Nos. 6,218,249 and 5,43〇, 315 disclose 97878.doc 1241662. Although it can produce non-trivial parts with better performance, it is because of the use of transmission and emulsification semiconductor architecture and tradition. The SOI architecture matches the super shallow junction depth, but it fails to alleviate or solve the problems mentioned above at the same time. SUMMARY OF THE INVENTION Ministry. The gate oxide layer is formed on the semiconductor layer and on the gate oxide layer. The purpose of this Meming is to provide a metal oxide semiconductor device with an internal barrier layer, including: _ substrate, _ body,-internal barrier layer, a semiconductor layer of one or two electricity, a gate oxide layer and a gate layer. The body is formed on the substrate. The internal barrier layer is formed on the substrate and disposed on the side of the body. A conductive semiconductor layer is formed on the body and the internal barrier layer. The semiconductor layer has a center. The source, the source, and the far gate layer are formed in the present document. Another purpose is to provide a method for manufacturing a metal oxide semiconductor device with an internal barrier layer, including the following steps: (1) providing a substrate; (b) Forming a body on the substrate; (c) forming an internal barrier layer on the substrate and on the side of the body; (d) forming a conductive semiconductor layer on the body and the internal barrier layer; (e) ) Forming a gate oxide layer on the semiconductor layer; (f) forming a gate layer on the gate oxide layer, relative to the gate oxide layer on the body position; and (g) on the semiconductor Layer A source portion and a drain portion. The metal oxide semiconductor device of the present invention uses the internal barrier layer to intervene between the body and the source portion and the non-polar portion to replace the original PN interface, which can reduce metal oxidation. The area of the PN junction in a semiconductor device greatly reduces the leakage current and the capacitance of the PN junction. And through proper selection of materials, it can also solve or terminate the electric field of the PN junction of the original metal oxide semiconductor device and suppress it. The resulting empty area of the component extends to the body, which can simultaneously suppress the ultra-short channel effect without floating body effect and self-heating effect. [Embodiment] Please refer to FIG. 3, which shows a schematic diagram of a metal oxide semiconductor device according to the present invention. The present invention The metal oxide semiconductor device 30 having an internal barrier layer mainly includes a substrate 31, a body 32, an internal barrier layer 33, a conductive semiconductor layer 34, a gate oxide layer 39, and a gate layer. 35. The substrate can be a silicon-on-insulator (SOI) substrate (such as a SIMOX, BESOI, or SmartCut SOI substrate), a germanium-on-insulator (G0I) substrate, or a wafer substrate. , Glass substrate, plastic substrate, sapphire substrate, diamond substrate or III-V substrate, etc. Referring to FIG. 4A, it shows a substrate with an embedded oxide layer. The substrate 41 has a substrate 411 and a substrate A buried oxide layer (Buried Oxide) 412. The buried oxide layer 412 is formed on the substrate 411. Referring to FIG. 4B, it shows a substrate having a buried oxide layer, the buried oxide layer having a channel. The substrate 42 has a substrate 421 and a buried oxide layer 422. The buried oxide layer 422 is formed on the substrate 421, and the buried oxide layer 422 has a channel 423 'which is opposite to the body Underneath, to connect the base and the body. In addition, some substrates (such as SOI substrates) have a base layer at the bottom, a buried insulating layer in the middle, and a conductive semiconductor layer on top. In addition, some substrates (such as glass substrates) have an insulating substrate on which a thin conductive semiconductor layer can be grown. For the conventional ordinary wafer substrate, the substrate is 97878.doc 1241662. The semiconductor layer on the substrate can be directly applied to the surface layer of the substrate. Referring again to FIG. 3, the body 32 is formed on the substrate 31. The internal barrier layer 33 is formed on the β-Hier substrate 3 and is disposed on the side of the body. The material of the internal barrier layer 33 is selected from the group consisting of dioxane, nitrogen, oxygen, nitrogen, oxygen, oxygen, and oxygen. (Air Gap), metal silicides with different doping impurity concentrations, or groups of metals. The conductive semiconductor layer 34 is formed on the body 32 and the internal barrier layer 33. The semiconductor layer 34 has a center A portion 341, a source portion 342, and a drain portion 343. The central portion 341 can be considered as one body with the body 32. The source of the metal oxide semiconductor device 30 can include the source portion 342 and a first semiconductor Block 347; the drain electrode may include a drain portion 343 and a second semiconductor layer 34 grown by the second semiconductor product 348, and the body 32 and the first semiconductor block 347 and the second semiconductor block 348 are used as Seed. (1) The central portion 341 of the semiconductor layer 34 is attached to the body 32, or the body 32 and a portion of the internal barrier layer 33, and the source portion 342 and the drain portion 343 are located at the central portion, respectively. The side of 341 is on the partial barrier layer 33. The semiconductor is called 34; the degree may be 0. 5 nm to 1 〇ηη] ^ 0.5 nm or more. The semiconductor layer M is selected from the group consisting of Group IV or m_v materials, such as, g. SiC, SiGe, ... GaAs, etc. to increase the metal The mobility of an oxidized semiconductor device can also be opened in two or more layers to form a tensile strain or a compression force to enhance the carrier mobility of the channel layer of a metal oxide semiconductor device. Therefore, the metal oxidation of the present invention The pN junction of the semiconductor device 30 is replaced by the internal resistance, junction, and junction layers 33. The only remaining pn junction is in the locally grown semiconductor layer 97878.doc 1241662 34, that is, the central portion 341 and the The connection surface 344 of the source portion 342 and the connection surface 345 of the central 邛 341 and the source portion 343. The connection surfaces 344 and 345 are suitable for the channel carriers of the Rongwu metal oxide semiconductor device. §Import and export. The proper exit size is determined by the locally grown semiconductor layer 34. In other words, the side wall of the metal oxide semiconductor device of the present invention is an insulating oxide layer and internal resistance of shallow trench isolation (STI). Surrounded by The exit-sized PN junctions 344 and 345 under the locally grown semiconductor layer 34. Broadly speaking, the conventionally isolated oxide layer and buried oxide layer are also barriers 1 >? ^ Junction, the same or different insulating materials can be used The internal barrier layer of the present invention is a comprehensive barrier PN interface, including the source and the body of the invention, and the 2PN interface between the drain and the body. This can further eliminate more PN interfaces. The surface area and the parasitic connection capacitance can relax the requirements of the extremely thin body thickness of the high-performance metal oxide semiconductor device and circuit system. The gate layer 35 is formed on the gate oxide layer 39. The gate layer 35 includes a metal silicide layer 352 and a polycrystalline silicon layer 351. The metal silicide layer is formed on the polycrystalline silicon layer 351. The gate layer 35 is formed on the semiconductor layer 34 at a position M relative to the body. . The gate layer 35 and the semiconductor layer M may first grow a gate silicon dioxide layer 39 of about 0.5 to 2 nanometers or other high kappa dielectric materials having the same equivalent thickness. The polycrystalline silicon layer 351 and the metal silicide layer 352 have a suitably high doping concentration to optimize the threshold voltage. The metal oxide semiconductor device 30 of the present invention further includes a first-protection layer 353. The first protection layer 353 is a silicon nitride layer. The silicon nitride layer has a top portion of 78878.doc • 10-1241662 and a side portion. The top is used to cover the metal silicide layer 352, the side is used to cover the sides of the metal silicide layer 352 and the polycrystalline silicon layer 351, the thickness of the top is 10 nm to 20 nm, and the thickness of the side is 5 nm to 10 nm. It is worth noting that the top and the side can also be replaced with appropriate materials with different low-K values, and the thickness can be appropriately changed according to the required size of the component. The metal-oxide semiconductor device 30 of the present invention further includes a second protective layer 36, which may be a silicon dioxide layer or a suitable low-K material, and a mouthguard layer is formed on the first protection layer. Side of layer 3 W. The metal oxide semiconductor device 30 of the present invention further includes a source contact layer 37 and a drain contact layer 38 on the source portion 342 and the drain portion 343, respectively. Referring to FIG. 5A to FIG. 5D, there is shown a schematic diagram of a method for manufacturing a first embodiment of a metal oxide semiconductor device 5G having an internal barrier layer according to the present invention. Referring to FIG. 5A, a substrate 51 is first provided. The substrate "has a base 5 mm and an embedded emulsified layer 512. A body 52 is then formed on the substrate 51. The active body (RIE) technology can be used to define the body 52 of the metal oxide semiconductor device. The side body 52 is in addition to When the seed crystal of the semiconductor layer 54 is grown, it helps to eliminate the holes and thermal energy that are free from collisions. It is worth noting that the degree of the body ^ can be changed, and the length and width of the body 52 can also be changed. In order to obtain a better and easier-to-control body effect (Body dy), an internal barrier layer 53 is then formed on the substrate 51 and on the side of the body 52. The internal barrier layer 53 is formed by an edge lining process. On the side of the body 52. A conductive semiconductor layer 54 is formed on the body 52 and the internal barrier layer 53. The semiconductor layer 54 can be formed by chemical vapor deposition (CVD), sputtering or A plasma-enhanced chemical vapor deposition method is formed on the body w 97878.doc 1241662. Then, on the semiconductor layer 54, a closed-electron hafnium dioxide 55 or other equivalent thickness of about 0.05 to 2 nanometers can be grown. High kappa dielectric materials "Re-formed-the gate layer 56 on the gate silicon dioxide layer" is located above the -Hai body 52. The gate layer 56 includes a metal silicide layer ⑹ and-a polycrystalline silicon layer 561. Therefore, according to The polycrystalline silicon layer 561 and the metal silicide layer 562 are sequentially formed. The metal silicide layer 562 is formed on the polycrystalline silicon layer 561. Then, a silicon nitride layer 563 for protection is formed, and the silicon nitride layer is formed on the polysilicon layer. The metal oxide layer is on top of 562. In order to make smaller nano-level components, an electron beam direct writing process may be performed, or a hard mask process using silicon oxide to assist in the formation of silicon oxide is used to form The gate layer%. It is worth noting that the metal halide layer 562 can be formed after the gate is defined. The intermediate layer 56 is not limited to the two-layer structure described above, and the gate layer layer can be a suitable function. Function (Work Function) of single or multiple layers of different metals to optimize the threshold voltage. Referring to FIG. 5B ', a side lining process is performed to form silicon nitride side linings 564 and 565 on both sides of the gate layer. The silicon nitride layer 563 for protection and the silicon nitride side liners 564 and 565 may It is a first protective layer covering the gate layer. After that, in order to perform ion implantation of the source and the drain, firstly, a layer of silicon dioxide (or other low-K material) for ion implantation is carpet-evaporated. Layer 57, the silicon dioxide layer 57 may be a second protective layer for covering the first protective layer and the semiconductor layer 54. A source portion 542 and a drain portion 543 are then formed on the semiconductor layer 54 The source electrode portion 542 and the drain electrode portion 543 can be formed by self-alignment in the semiconductor layer 54 with the gate layer 56 as a mask using an ion implantation method. The source electrode 9878.doc 12 1241662 portion 542 And the drain portion 543 is a central portion 54. In order to effectively reduce the source / drain series resistance, the energy and dose of the ion implantation method need to be appropriately adjusted so as to be performed at an appropriate high temperature immediately after. The thermal Annealing process is used to form the most appropriate interface between the source portion 542 and the central portion 541, and the interface between the drain portion 543 and the central portion 541. It is important to note that the quality of the semiconductor layer 54 is unquestionable because the semiconductor layer 54 is located at the center A of the metal oxide semiconductor channel 541 'because the body 52 is used as a seed crystal and undergoes this thermal repair operation. Referring to Fig. 5C, second scatter layer 571 and 572 of the scattering stone dioxide layer are formed on the periphery of the first-protection layer by using engraving. Referring to FIG. 50, and then using the gate layer 56 and its first and second protective layers 571 and 572 'self-aligned lifting source / drain process on the exposed source / drain' of course It can cooperate with the conventional metal silicide process, or it can be directly used. Gold forms a source contact layer by self-aligning and edge lining processes, such as 582 ° and non-polar layer. Finally, a thin layer of conductive stone can be exposed in a self-aligning manner at a later time. Afterwards, a suitable protective insulation material is carpet-filled Ru Li:
Tetraethyl〇nh〇SlH㈣。另外值得注意上述最後製程 後’痛就如同自動隔離，無須所謂的淺溝隔離或其他 隔離技術’且可以最少的光罩，製得更小的奈米元件斑系 統。其次，最後的接觸窗和金屬連線的製程都為習知之現 有技術，不再贅述。 因此，利用本發明第一實 半導體裝置50具有低漏電流 短通道效應。 施例製作方法製作之金屬氧化 低寄生接面電容和能壓制超 97878.doc 13 1241662 ，考圖6,其顯示利用本發明第二實施例製作方法製作之 具有㈣阻絕層之金屬氧化半導體裝置60之示意圖。該第 -““列製作方法與第一實施例之製作方法大致相同，其 不同之處在於絲板61沒有如石夕覆絕緣（則）基板之埋入 氧化層。因A，該本體52與基板61同體，故不會有自我加 熱效應、浮體效應，和屈膝效應。並且，當金屬氧化半導 體裝置60之升起源極接觸層581與汲極接觸層如被形成 後，必須使用活性離子蝕刻技術進行淺溝隔離製程，之後 再利用習知的接觸窗和金屬連線的製程技術來完成製作。 參考圖7 ’其顯示利用本發明第三實施例製作方法製作之 具有内部阻絕層之金屬氧化半導體裝置70之示意圖。該第 一實施例裝作方法與第一實施例之製作方法大致相同，不 同之處在於該基板71具有一基底711及一埋入氧化層川， 且該埋入氧化層712具有—通道713。首先提供一秒晶圓基 板，接著在該基板上形成一絕緣埋氧化層712，然後以一通 I長度采以通道寬度（Lw)大小或適當且較小之鏤空光罩配 合正光阻劑於該絕緣埋氧化層蝕刻出該鏤空大小之空洞， 之後在不移除上項蝕刻之光阻層下進行清洗，隨後直接在 該空洞上直接成長適當厚度之單晶或多晶之該本體52。之 後，所有的製程步驟與第一實施例之製作方法完全相同， 故不予贅述。 因此’利用本發明第三實施例製作方法製作之金屬氧化 半導體裝置70具有低漏電流、低寄生接面電容和能壓制超 短通道效應、且無浮體與屈膝效應及無自我加熱效應。因 97878.doc -14- 1241662 此本發明之金屬氧化半導體裝置70可應用於低成本之傳統 矽晶圓基板上，以大幅降低製作高性能電路與單晶片系統 之成本。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1為習知金屬氧化半導體裝置之示意圖； 圖2為習知具有埋入氧化層之金屬氧化半導體裝置之示 意圖； 圖3為本發明具有内部阻絕層之金屬氧化半導體裝置之 示意圖； ~ 圖4A為具有埋入氧化層之基底之示意圖； 圖4B為具有通道之埋入氧化層之基底之示意圖； 圖5A至圖513為本發明具有内部阻絕層之金屬氧化半導 體裝置之第一實施例製作方法示意圖； =為利用本發明第二實施例製作方法製作之金屬氧化 牛導體裝置之示意圖；及 圖7為利用本發明第三實施例製作 丰導鲈# $ 衣邗方法製作之金屬氧化 千導體裝置之示意圖。 【主要元件符號說明】 10 習知之金屬氧化半導體裝置 基板 97878.doc 11 1241662 12 本體 13 源極 14 >及極 15 閘極氧化層 16 閘極 17 通道 20 習知之金屬氧化半導體裝置 21 基板 22 本體 23 源極 24 汲極 25 閘極氧化層 26 閘極 30 本發明之金屬氧化半導體裝置 31 基板 32 本體 33 内部阻絕層 34 具導電之半導體層 35 閘極層 36 第二保護層 37 源極接觸層 38 汲極接觸層 39 閘極氧化層 41 基板 97878.doc -16- 基板 本發明之金屬氧化半導體裝置 基板 本體 内部阻絕層 具導電之半導體層 閘極氧化層 閘極層 第二保護層 本發明之金屬氧化半導體裝置 基板 本發明之金屬氧化半導體裝置 基板 基底 埋入氧化層 中央部 源極部 汲極部 源極部與中央部間之接面 汲極部與中央部間之接面 第一半導體區塊 第二半導體區塊 多晶矽層 金屬石夕化物層 -17- 1241662 353 第一保護層 411 基底 412 埋入氧化層 421 基底 422 埋入氧化層 423 通道 511 基底 512 埋入氧化層 541 中央部 542 源極部 543 汲極部 561 多晶矽層 562 金屬矽化物層 563 氮化矽層 564 、 565 氮化矽邊襯 571 > 572 第二保護層邊襯 581 源極接觸層 582 汲極接觸層 711 基底 712 埋入氧化層 713 通道 97878.doc -18-TetraethylOnnOSlH㈣. It is also worth noting that after the above-mentioned final process, the pain is like automatic isolation, so-called shallow trench isolation or other isolation technologies are not needed, and a smaller nano-element spot system can be made with a minimum of masks. Secondly, the process of making the final contact window and metal wiring is a known existing technology and will not be described again. Therefore, the semiconductor device 50 using the first embodiment of the present invention has a low leakage current and short channel effect. The metal oxide low parasitic junction capacitor manufactured by the manufacturing method of the embodiment and can suppress the super-97878.doc 13 1241662, as shown in FIG. 6, which shows a metal oxide semiconductor device 60 having a rubidium barrier layer manufactured by the manufacturing method of the second embodiment of the present invention. The schematic. The manufacturing method of the "-" "column is substantially the same as the manufacturing method of the first embodiment, except that the wire plate 61 is not covered with a buried oxide layer such as an insulating substrate. Because A, the body 52 is the same body as the substrate 61, so there is no self-heating effect, floating body effect, or knee flexion effect. In addition, after the metal oxide semiconductor device 60 rises the source contact layer 581 and the drain contact layer, if formed, a shallow trench isolation process must be performed using an active ion etching technique, and then a conventional contact window and a metal connection Process technology to complete the production. Referring to FIG. 7 ', a schematic diagram of a metal oxide semiconductor device 70 with an internal barrier layer manufactured by a manufacturing method according to a third embodiment of the present invention is shown. The fabrication method of the first embodiment is substantially the same as the fabrication method of the first embodiment, except that the substrate 71 has a base 711 and a buried oxide layer, and the buried oxide layer 712 has a channel 713. First, a one-second wafer substrate is provided, and then an insulating buried oxide layer 712 is formed on the substrate. Then, a through I length is adopted with a channel width (Lw) size or a suitable and small hollow mask with a positive photoresist on the insulation. The buried oxide layer etches the hollow-sized cavity, and then cleans it without removing the photoresist layer etched above, and then directly grows the single-crystal or poly-crystalline body 52 of appropriate thickness directly on the cavity. After that, all the process steps are exactly the same as those of the first embodiment, so they will not be described in detail. Therefore, the metal oxide semiconductor device 70 manufactured by the manufacturing method of the third embodiment of the present invention has a low leakage current, a low parasitic junction capacitance, and can suppress an ultra-short channel effect, and has no floating body, knee flexion effect, and no self-heating effect. Because 97878.doc -14-1241662, the metal-oxide semiconductor device 70 of the present invention can be applied to a low-cost traditional silicon wafer substrate to greatly reduce the cost of manufacturing high-performance circuits and single-chip systems. However, the above embodiments are only for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of rights of the present invention should be listed in the scope of patent application mentioned later. [Brief description of the drawings] FIG. 1 is a schematic diagram of a conventional metal oxide semiconductor device; FIG. 2 is a schematic diagram of a conventional metal oxide semiconductor device having a buried oxide layer; and FIG. 3 is a metal oxide semiconductor device having an internal barrier layer according to the present invention 4A is a schematic view of a substrate with a buried oxide layer; FIG. 4B is a schematic view of a substrate with a buried oxide layer; FIG. 5A to FIG. 513 are metal oxide semiconductor devices having an internal barrier layer according to the present invention; Schematic diagram of the manufacturing method of the first embodiment; = is a schematic diagram of the metal oxide cattle conductor device manufactured by the manufacturing method of the second embodiment of the present invention; and FIG. 7 is a method of manufacturing the fengdao perch using the third embodiment of the present invention. Schematic diagram of the metal oxide thousand conductor device. [Description of main component symbols] 10 Conventional metal oxide semiconductor device substrate 97878.doc 11 1241662 12 Body 13 Source 14 > and 15 Gate oxide layer 16 Gate 17 Channel 20 Conventional metal oxide semiconductor device 21 Substrate 22 Body 23 source 24 drain 25 gate oxide layer 26 gate 30 metal oxide semiconductor device of the present invention 31 substrate 32 body 33 internal barrier layer 34 conductive semiconductor layer 35 gate layer 36 second protective layer 37 source contact layer 38 Drain contact layer 39 Gate oxide layer 41 Substrate 97878.doc -16- Substrate The metal oxide semiconductor device substrate of the present invention has an internal barrier layer having a conductive semiconductor layer, a gate oxide layer, a gate layer, and a second protective layer of the present invention. Metal oxide semiconductor device substrate The metal oxide semiconductor device substrate base of the present invention is embedded in the oxide layer in the central portion of the source portion and the drain portion. The interface between the drain portion and the center portion. The first semiconductor region Second semiconductor block Polycrystalline silicon layer Metal oxide layer-17- 1241662 353 First protective layer 411 substrate 412 buried oxide layer 421 substrate 422 buried oxide layer 423 channel 511 substrate 512 buried oxide layer 541 central portion 542 source portion 543 drain portion 561 polycrystalline silicon layer 562 metal silicide layer 563 silicon nitride layer 564, 565 Silicon nitride edge liner 571 > 572 second protective layer edge liner 581 source contact layer 582 drain contact layer 711 substrate 712 buried oxide layer 713 channel 97878.doc -18-