1241629 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種接合晶圓及其製法，尤指一種可形 成完整邊緣之高強度接合晶圓的方法。 【先前技術】 由於不同工業的需要，發展出了藉由晶圓接合（wafer b ο n d i n g)的方式將不同材料或相同材料接合在一起的技 術’因此產生了許多新產品。例如使用於省電元件和微機 電工業的絕緣層上覆石夕晶圓（silicon on insulator, SOI晶 圓）、可取代厚磊晶產品的矽_矽接合晶圓（siHc〇fVS⑴c〇n bonding wafer)、以及 S〇G(silic〇n 〇n g|ass)晶圓、 S〇S(silicon on sapphire)晶圓等等。 以S〇丨晶圓的常見製造方法為例，第一種方法是先在 一片石夕晶圓上長出一層二氧化矽（Si〇2)，將此晶圓與其他 曰曰圓接合’並且退火以增加接合強度，然後對接合後的晶 圓其中一片進行薄化處理（Thinning)以達到所需要的元件 層厚度。薄化處理的方法主要有輪磨（Grinding)及蝕刻（Etch back)兩種，採用蝕刻方式的又稱作bes〇I製程。如何做 到快速蝕刻，並且於蝕刻後能達到理想的厚度都是一項挑 戰。1241629 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a bonding wafer and a manufacturing method thereof, and particularly to a high-strength bonding wafer method capable of forming a complete edge. [Previous technology] Due to the needs of different industries, the technology of joining different materials or the same materials together by wafer bonding (wafer b ο n d i n g) has been developed ', thus generating many new products. For example, silicon-on-insulator wafers (SOI wafers) used in power-saving components and the micro-electromechanical industry, and silicon-silicon bonding wafers (siHc〇fVS⑴c〇n bonding wafers) that can replace thick epitaxial products ), And SOG (silicon ON ng | ass) wafers, SOS (silicon on sapphire) wafers, and the like. Taking the common manufacturing method of S〇 丨 wafers as an example, the first method is to first grow a layer of silicon dioxide (Si〇2) on a piece of Shi Xi wafer, and then join this wafer with other wafers. Annealing to increase the bonding strength, and then thinning one of the bonded wafers to achieve the required device layer thickness. There are two methods of thinning treatment: grinding and etching (Etch back). The etching method is also known as the besOI process. How to achieve rapid etching and achieve the desired thickness after etching is a challenge.
Canon公司則發展出ELTRAN (epitaxia丨丨ayer transfer)製程。在這個製程中，首先在一矽晶圓上形成多 孔矽層（porous |ayer)。然後在這個多孔矽層上生長磊晶 矽’並且在磊晶矽上生長一層二氧化矽（Si〇2)。該二氧化 1241629 矽層加熱黏合到另一矽晶H，復利用水刀自多 開，再用電浆移走剩下的多孔石夕晶層，最 ^ 理’或抛光使表面平坦。 用^退火處 第二種稱為SmartCut製程，是由s〇丨·tec公司所研發’ :理是在晶圓上植入-氫離子層’再和另-片晶圓連在 -起。經過高溫熱處理’使晶圓能夠從植入層分離，而得 :所需厚度的石夕薄層。但是’由於植入離子層會造成晶圓 又面缺陷增加，必須使用拋光技術使晶圓表面光滑。 人請參考第—圖所示，前述兩種方法都需要使用晶圓接 合技術，但是一般抛光後的晶圓（5 0 )，因為晶圓邊緣 的厚度移除速率不同，該拋光面的邊緣會有如圖中所示的 不平坦現象。 π乡罘一 A、二Β圖所示，兩晶圓之拋光面相對接 合後，7L件層晶圓（device wafer) ( 5丄）與承載層晶圓 (ndle wafer) ( 5 2 )兩者在邊緣的地方便無法完全密 口。凊筝閱第三A、三β圖所示，所以在元件層晶圓（5 1 )薄化的過程中，產生如圖所示元件層晶圓（5 1 )上 幅長Α1之長度大於下幅長Α2的情形，元件層晶圓（5工） 的邊緣會因為沒有承載層晶圓（5 2 )的支撐而產生碎裂。 若使用SmartCut方法，則因為邊緣傾斜的緣故，作 出來的SOI晶圓其元件層晶圖（5 1 )直徑會小於承載層 晶圓（5 2 )直徑，接合晶圓的整體外觀上會產生彷彿邊 緣缺損的樣子’其外觀類似第三A、三b圖所示。所以凡 疋使用直接晶圓接合（direct wafer bonding)技術，現行的 !241629 各種方法都會在接合晶圓的邊緣產生缺損區域。 德國Max Planck Institute則使用了直徑較大的曰片， 接合後再倒角（edge profiling)兩次以去除邊緣缺損區域。 這個方法在製作時，需要較大的載具，如晶圓匣 (cassette)、研磨載具（|apping carrjer)等等，因此需要修 改相關的配套措施。 【發明内容】 ,本發明之目的係提供一種具完整邊緣之接合晶圓及其 製法，其中構成該接合晶圓之元件層晶圓，其邊緣係無缺 損問題產生。 為達成前述目的，該接合晶圓之製法係包含： 結合一具有較短幅長之元件層晶圓於一般承載層晶圓 上以構成接合晶圓，纟中該凡件I晶圓之幅長 丨ength)短於該承載層晶圓之幅長； 後，修整晶圓之邊緣，並且薄化該元件層 晶圓形成底部較寬而頂部較窄之金字塔形 為增強接合面之接合強度 1 1 0 0 C的南溫爐中退火約1 具有完整邊緣之接合晶圓。 ’將接合晶圓置入950。〇至 至2小時。經過高溫熱處理 晶圓，使元件層 ’拋光後形成一 以刖述方式構成之接合晶圓，其外觀與一般晶圓或磊 晶晶圓完全相@ ’而且因為元件層的邊緣完整，所以增加 了該元件層晶圓的機械強度’提高了接合晶圓在元件製程 中的耐溫與耐壓能力，也同時增加了接合晶圓的可用面 1241629 【貫施方式】 人本毛明係使用一幅長較短的元件層晶圓並選擇性地配 "邊、、彖修整方法，經過熱處理、邊緣修整、薄化及拋光 處理’來獲得一具有完整邊緣的接合晶圓。該元件層晶圓 車乂佳巾田長可以是5〇μηι到獅㈣，惟並不偏限於此範圍内。 紐巾田長曰曰圓的製作方式，可以使用較薄的晶圓，或適當的 邊緣修整方式來獲得，惟並不偈限於此兩種方式。 以使用薄晶圓為例。請參閱第四圖所示，於一承載層 曰曰圓（1 1 )上係接合有一厚度較薄的元件層晶圓（1 2 )， 該車乂薄的兀件層晶圓（丄2 )較佳厚度可以是到 500μίη的厚度，惟並不侷限於此範圍内，必須強調的一點 疋邊兀件層晶圓（1 2 )和承載層晶圓（1丄）本身可以 是單層或多層結構，單層結構如矽或其它半導體材料，多 層結構可以包括磊晶層、氧化層、金屬層或是由任何材料 組成。 雖然該薄元件層晶圓（丄2 )同樣有邊緣傾斜的可能， 如圖上π區域所標示，但是因為該薄元件層晶圓（丄2) 的幅長較短，所以拋光後產生的t1傾斜區域非常靠近晶圓 外緣，而一般厚度的晶片的t2區域則離晶圓外緣較 該薄元件層晶圓（1 2 )拋光面的平坦面積比一般厚户的 元件層晶圓大，因此兩晶圓相對接合後，在邊緣修整並且 讓直徑縮小的過程中，可以較容易去除元件層晶圓（丄2 ) 邊緣的傾斜區域，同時讓元件層晶圓（丄2 )形成底部寬、 1241629 頂部窄的金字塔型’也就是如第五圖所示，經過邊緣修整 後，A4長度大於A3的情形，使得晶圓能夠承受薄化時候 的研磨或拋光麼力。 前述邊緣修整的過程中’目的係將接合晶圓（i 3 ) 的邊緣修成上幅長A5 (upper bevel |ength)較長、下幅長 A6(l〇wer bevel length)較短的邊緣外型（edge pr〇fi|e)，如 第五圖所示A5長度大於A6。經過適當的外型修整控制， 可以讓薄化後的上幅長仍然和下幅長長度相當，因而得到 外型和一般矽晶片完全相同的接合晶圓（1 3 )，在不考 慮邊緣内1mm的範圍内’此接合晶圓（1 3 )的元件層 晶圓（1 2)和承載層晶圓（1丄）的直徑差異小 邊緣Ο 1的方式可以疋機械方式：如倒角或搭配化學姓刻 方式或邊緣抛光（edge p。丨ishing)，但並不受限於這三種方 式0 如第六圖所示，為本發明接合晶圓（1 3 )之俯視平 面圖，藉由上述方式提高了晶圓的機械強纟，並可獲得- 邊緣完整的接合晶圓f 1 q、 0 日日回（1 3)。再者，藉由使用薄的元件 層曰曰圓（1 2 )’因為待移除的厚度較少，所以可以減少 薄化過程中產生的應力’因而降低接 曲度（warpage)。 " ::閱第七圖所示，為利用本發明之接合方式與習用 卜… 意圖。圖·t Α是習用方式，採 取般尽度與幅長之晶圓作兔；此麻日 .,.a ^ ^作為兀件層晶圓，故於薄化後該 兀件層日日圓的邊緣非呈平 十丨員狀怨，反之，利用圖七β的本 1241629 發明手段’該薄元件層晶圓（i 2) μ過薄化、邊緣修整 處理後可完全貼合於承載層晶圓（丄丄）表面上，構成一 完整邊緣的接合晶圓（1 3 )。 請參考第八圖所示，基於前述概念，亦可在接合兩片 承載層晶® ( 1 i )及元件層晶圓（丄2 )前，經過適當 的邊緣修整方式’讓兩晶圓（丄丄）（丄2)的幅長均變 得較圓、較短’令拋光傾斜區域非常靠近晶片邊緣，因此 在接合與退火後，㈣邊緣修整，可以較容易去除晶圓邊 、‘彖的未接合區域，若是採用此法，則該元件層晶圓（1 2 ) 之厚度較不受限制。 本發明之晶圓接合方式，可廣泛應用於s〇|(sj|jc〇n训 insulator)晶圓、矽-矽接合晶圓（s丨·丨丨·c〇n_sMjc〇n wafer)、以及 s〇G(smcon on glass)、s〇S(silicon on sapphire)或其他利用晶片接合方式做成的接合晶圓；該接 合晶圓可避免元件層邊緣產生缺損，如此一來則外觀與一 般晶圓或磊晶晶圓完全相同，而且因為元件層的邊緣完 t，所以增加了元件層的機械強度，也同時提高了晶圓可 用面積，相較於習知晶圓接合技術，本發明所達成之效果 確實具有顯著進步，於符合發明專利要件前提之下，爰依 法具文提出申請。 【圖式簡單說明】 第一圖··係一習用晶圓經拋光處理後其邊緣傾斜示意 圖。 第二A、二B圖：係習用晶圓經接合處理後之示意圖。 1241629 第三A、三B圖：係第二圖習用接合晶圓經薄化處理 後之不意圖。 弟四圖·為本創作兩晶圓接合尚未進行涛化處理之不 意圖。 第五圖：為本創作兩晶圓接合已進行薄化處理之示意 圖。 弟六圖·弟五圖接合晶圓之外觀不意圖。 第七A、七B圖：為本創作之接合方式與習用晶圓接 合方式兩者之對比示意圖。 第八圖：為本創作另一晶圓接合方式之示意圖。 【主要元件符號說明】 (1 1 )承載層晶圓 （1 2 )元件層晶圓 (1 3 )接合晶圓 （5 0 )晶圓 (5 1 )元件層晶圓 （5 2 )承載層晶圓Canon has developed the ELTRAN (epitaxia 丨 ayer transfer) process. In this process, a porous silicon layer is first formed on a silicon wafer. Then epitaxial silicon 'is grown on this porous silicon layer and a layer of silicon dioxide (SiO2) is grown on the epitaxial silicon. The 1241629 silicon dioxide layer is heated and bonded to another silicon crystal H, and then reused with a water jet to remove the remaining porous stone crystal layer with a plasma. The surface is flattened or polished. Using ^ Annealing Place The second type is called SmartCut process, which was developed by Sotec Corporation. The principle is to implant a hydrogen ion layer on the wafer and connect it to another wafer. After the high temperature heat treatment ', the wafer can be separated from the implanted layer to obtain a thin layer of Shi Xi with a desired thickness. However, as the implantation of the ion layer causes the wafer to increase surface defects, polishing technology must be used to smooth the surface of the wafer. Please refer to the figure. The two methods mentioned above need to use wafer bonding technology, but generally the polished wafer (50), because the thickness removal rate of the wafer edge is different, the edge of the polished surface will There are unevenness as shown in the figure. As shown in Figures A and B, when the polished surfaces of the two wafers are relatively bonded, both the 7L device wafer (5 丄) and the ndle wafer (5 2) Convenience on the edge cannot be completely tight. The kite reads the third A and three β diagrams, so during the thinning of the element layer wafer (5 1), the length of the upper layer A1 of the element layer wafer (5 1) is greater than the length of the lower layer. In the case of the length A2, the edge of the element layer wafer (5 workers) is chipped because it is not supported by the carrier layer wafer (5 2). If the SmartCut method is used, the diameter of the element layer crystal pattern (5 1) of the SOI wafer will be smaller than the diameter of the carrier layer wafer (5 2) because of the inclined edge, and the overall appearance of the bonded wafer will appear as if The appearance of the edge defect 'is similar to that shown in Figures A and B. Therefore, where direct wafer bonding technology is used, various methods of the current! 241629 will produce defect areas at the edges of the bonded wafer. The Max Planck Institute in Germany uses a larger diameter patch, and then edge profiling twice after the joint to remove the edge defect area. This method requires larger carriers such as cassettes, grinding carriers (applying carrjer), etc. during the production, so related supporting measures need to be modified. [Summary of the Invention] The object of the present invention is to provide a bonded wafer with a complete edge and a manufacturing method thereof, in which an edge of a component layer wafer constituting the bonded wafer is free from defects. In order to achieve the foregoing object, the manufacturing method of the bonded wafer includes: combining a component layer wafer with a shorter length on a general carrier layer wafer to form a bonded wafer, wherein the width of the I wafer丨 ength) is shorter than the length of the carrier layer wafer; after that, trim the edge of the wafer and thin the element layer wafer to form a pyramid with a wider bottom and a narrower top to increase the bonding strength of the bonding surface 1 1 Annealing about 1 bond wafer with complete edges in a 0 ° C South temperature furnace. ’Place the bonded wafer into 950. 0 to 2 hours. After high-temperature heat treatment of the wafer, the element layer is' polished 'to form a bonded wafer composed in the manner described, and its appearance is completely similar to that of ordinary wafers or epitaxial wafers.' Because the edge of the element layer is complete, it is increased. The mechanical strength of the element layer wafer 'improves the temperature and pressure resistance of the bonding wafer in the component manufacturing process, and also increases the usable surface of the bonding wafer 1241629 Longer and shorter component layer wafers are optionally configured with "edge, edge, and trimming methods. After heat treatment, edge trimming, thinning, and polishing processes," a bonded wafer with complete edges is obtained. The element layer wafer can be from 50 μm to lion, but it is not limited to this range. The manufacturing method of the round towel circle can be obtained by using a thin wafer or a proper edge trimming method, but it is not limited to these two methods. Take the use of thin wafers as an example. Referring to the fourth figure, a thin component layer wafer (1 2) is bonded to a carrier layer (1 1), and the thin component layer wafer (2) The preferred thickness can be up to 500μίη, but it is not limited to this range. It must be emphasized that the edge piece wafer (1 2) and the carrier layer wafer (1 丄) can be single or multiple layers. Structure, single-layer structure such as silicon or other semiconductor materials, multi-layer structure can include epitaxial layer, oxide layer, metal layer or consist of any material. Although the thin element layer wafer (丄 2) may also have an inclined edge, as indicated by the π area on the figure, because the thin element layer wafer (丄 2) has a shorter width, the t1 produced after polishing is The inclined area is very close to the outer edge of the wafer, and the flat area of the t2 area of the wafer of general thickness from the outer edge of the wafer is larger than the flat area of the polished surface of the thin element layer wafer (1 2) than the thicker element layer wafer. Therefore, after the two wafers are relatively bonded, in the process of trimming the edges and reducing the diameter, it is easier to remove the sloped area of the edge of the element layer wafer (丄 2), and at the same time, make the element layer wafer (丄 2) form a wide bottom, 1241629 The pyramid type with a narrow top is shown in the fifth figure. After edge trimming, the length of A4 is longer than A3, so that the wafer can withstand the grinding or polishing forces during thinning. In the aforementioned edge trimming process, the purpose is to trim the edge of the bonding wafer (i 3) into a shorter edge shape with a longer upper bevel (ength) and a shorter lower bezel A6 (l0wer bevel length). (Edge pr0fi | e), as shown in the fifth figure, A5 is longer than A6. After proper shape trimming control, the thinned upper length can still be equal to the lower length, so a bonded wafer (1 3) with exactly the same shape as a general silicon wafer can be obtained, without considering the edge 1mm Within the scope of 'the bonding wafer (1 3), the component layer wafer (12) and the carrier layer wafer (1 丄) have a small difference in diameter. The method of 1 can be mechanical: such as chamfering or matching chemistry The method of engraving or edge polishing (edge p. Ishing) is not limited to these three methods. As shown in the sixth figure, it is a top plan view of the bonded wafer (1 3) of the present invention. The mechanical strength of the wafer is obtained, and a bonded wafer f 1 q with a complete edge is obtained, and the day 0 is returned (1 3). Furthermore, by using a thin element layer, said circle (1 2) ', because the thickness to be removed is less, the stress generated during the thinning process can be reduced' and thus the warpage is reduced. " :: See figure 7 for the use of the joining method and customary use of the present invention ... Intention. Figure · t Α is a customary method, adopting the exhaustion and length of the wafer as a rabbit; this hemp day, .. a ^ ^ is used as a component layer wafer, so after thinning, the edge of the component layer and the Japanese yen Non-flattened grievances, on the contrary, using the invention method of 1241629 shown in Figure 7 β, the thin element layer wafer (i 2) μ can be completely bonded to the carrier layer wafer after being thinned and trimmed. Ii) On the surface, a full-edge bonded wafer (1 3) is formed. Please refer to the eighth figure. Based on the above concept, you can also use the appropriate edge trimming method to allow the two wafers (丄) to be bonded before bonding the two carrier layer wafers (1 i) and the component layer wafer (丄 2).丄) (丄 2) 's length becomes rounder and shorter.' The polished inclined area is very close to the wafer edge. Therefore, after bonding and annealing, the ㈣ edge trimming can easily remove the wafer edge, 彖 ' The bonding area, if this method is adopted, the thickness of the element layer wafer (1 2) is relatively unlimited. The wafer bonding method of the present invention can be widely applied to s〇 | (sj | jc〇n training Insulator) wafer, silicon-silicon bonded wafer (s 丨 · 丨 丨 · c〇n_sMjc〇n wafer), and s 〇G (smcon on glass), SOC (silicon on sapphire), or other bonded wafers made by wafer bonding; the bonded wafer can avoid defects at the edge of the component layer, so the appearance is the same as ordinary wafers. Or the epitaxial wafer is exactly the same, and because the edge of the element layer is t, the mechanical strength of the element layer is increased, and the available area of the wafer is also increased. Compared with the conventional wafer bonding technology, the effect achieved by the present invention is indeed It has made significant progress. On the premise that it meets the requirements for invention patents, it has filed an application in accordance with the law. [Brief description of the drawing] The first picture is a schematic diagram of the inclined edge of a conventional wafer after being polished. Figures A and B: diagrams of conventional wafers after bonding. 1241629 The third picture A and the third picture B are the intentions of the second picture after the conventional bonding wafer is thinned. Brother Four Figures · This is the intention of the two wafer bonding process that has not yet undergone Taoization. Fifth image: The schematic diagram of the thinning process of the two wafers for the creation. The appearance of younger brothers and younger brothers is not intended. Figures 7A and 7B: Comparison diagrams of the bonding method and the conventional wafer bonding method for this creation. Figure 8: Schematic diagram of another wafer bonding method. [Description of main component symbols] (1 1) Carrier layer wafer (1 2) Element layer wafer (1 3) Bonding wafer (50) Wafer (5 1) Element layer wafer (5 2) Carrier layer crystal circle
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