TWI241009B - Method for forming conductive bump and device having such made conductive bump - Google Patents

Method for forming conductive bump and device having such made conductive bump Download PDF

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Publication number
TWI241009B
TWI241009B TW92112165A TW92112165A TWI241009B TW I241009 B TWI241009 B TW I241009B TW 92112165 A TW92112165 A TW 92112165A TW 92112165 A TW92112165 A TW 92112165A TW I241009 B TWI241009 B TW I241009B
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Taiwan
Prior art keywords
bump
pad
layer
conductive
bumps
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TW92112165A
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Chinese (zh)
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TW200409327A (en
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Yu-Nung Shen
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Yu-Nung Shen
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Priority to TW92112165A priority Critical patent/TWI241009B/en
Priority to US10/833,150 priority patent/US20040219774A1/en
Publication of TW200409327A publication Critical patent/TW200409327A/en
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Publication of TWI241009B publication Critical patent/TWI241009B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]

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  • Wire Bonding (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

A device having conductive bumps comprises a semiconductor chip that has a pad installation surface and plural pads on the said surface, plural conductive bumps that are formed on the center of corresponded pads. Each conductive bump consists of a protruding point formed on the corresponded pad and a metal layer that is formed on the corresponded protruding point and extended to the corresponding pad surface.

Description

1241009 五、發明說明α) 【發明所屬之技術領域】 本發明係有關於一種形成導電凸塊的方法,更特別地 ’係有關於一種形成導電凸塊的方法及具有如此形成之導 電凸塊的裝置。 【先前技術】 基於環保的理由,在半導體製程中,含鉛的導電材料 或含錯量極低的導電材料已逐漸普遍地被使用代替含鉛量 極南的導電材料。 針對此一課題,本案申 部智慧財產局提出名稱為,, 凸塊的方法及具有如此形成 置”之第9 1 1 3 4 0 5 5號發明專 露與上述專利申請案所揭露 段。 ° 請人於2002年11月22日向經濟 一種於半導體晶元上形成導電 之導電凸塊的半導體晶片裝 利申請案。現在,本申諳宏姐 之手段不同之其他可行的j ι 此外,本案發明人亦發現,在BGA封裝產品 裝f體之與载有晶元之表面相對的表面上係童,封 :㈣式ί列的錫球。如上所述,含船量高的ί: “固以 合環保要求。 % %係不符 【發明内容】 之多年經 $有本發明 導電凸塊的 驗, 『_ 裝置 有鑑於此,本案發明人遂以其從事該行業 並本著精益求精之精神,積極研究改良, 種形成導電凸塊的方法及具有如此形成之 』產生。 本發明之目的是為提供一種形成導電凸塊的方法及具1241009 V. Description of the invention α) [Technical field to which the invention belongs] The present invention relates to a method for forming a conductive bump, and more particularly, to a method for forming a conductive bump and a method having the conductive bump thus formed. Device. [Previous Technology] For environmental reasons, in semiconductor manufacturing processes, conductive materials containing lead or conductive materials with extremely low levels of error have gradually been used instead of conductive materials with extremely low lead content. In response to this problem, the Intellectual Property Bureau of the application department of this case proposed the method of the bump and the method of forming it as described above, No. 9 1 1 3 4 0 5 5 and the above patent application. An application was filed on November 22, 2002 to the economics of a semiconductor wafer for forming conductive bumps on semiconductor wafers. Now, this application has other feasible methods that are different from those of Hongjie. In addition, the present invention It has also been found that on the surface of the body of the BGA package product opposite the surface on which the wafers are loaded, a child is sealed: a solder ball of the ί-type column. As described above, a high-volume ship: Meet environmental requirements. %% Is not in accordance with the [invention content] has been tested by the conductive bumps of the present invention for many years. "_ In view of this, the inventor of this case has been engaged in the industry and in the spirit of excellence, actively research and improve, The method of conducting bumps and having them so formed. The purpose of the present invention is to provide a method and a device for forming a conductive bump.

第4頁 1241009 五、發明說明(2) 有々此形成之導電凸塊的裝置。 根據本發明之— 含如下之步驟· 成導電凸塊的方法,包 烊墊安麥it ί 導體晶元,該半導體晶元具有- 光阻材料2數個安裝於該谭塾安褒表面上的焊墊;以 面上,該絕缘厚從- 丰體日日兀的整個焊墊安裝表 土形成有數個曝露該晶元之對應之谭墊之:二理 札,以并阳分划TTV 、、 亦 丁王心r天邛伤的穿 層的穿孔係祜:J成一覆蓋層於該絕緣層上以致於該絕緣 學沖洗等卢理:盖,該覆蓋層係藉著使用光罩的曝光和化 比:穿孔:Γ曝露孔所曝露之焊墊之中央部份的心 *露孔的形成之後,於該覆蓋層的每一個4 4设盍層之 』幵’成材料以致於每一個曝露孔内的凸點::内填 >主凸 ^處理後作為_個形成於—對應 (料在適當 覆蓋層移去且在形成於每一焊墊上的及把該 形成一金屬層以致於導電凸塊係被形々,、Μ電鍍方式 ~對應的凸點延伸到對應之焊墊的表面上母金屬層係從 根據本發明之另一特徵,一種形 ::如下之步W ··提供一半導體晶元,該^塊的方法, 、烊墊女裝表面及數個安裝於該焊墊壯I V體日日元具有 以光阻材料形成一絕緣層於該半導體曰衣表面上的焊墊; 表面上,該絕緣層係藉著使用光罩的曝2 Τ迠個焊墊安裝 理來形成有數個曝露該晶元之對應:σ化學沖洗等處 之坏墊之中央部份的穿Page 4 1241009 V. Description of the invention (2) Device having conductive bumps formed in this way. According to the present invention, the method includes the following steps: A method for forming a conductive bump, including a pad Anmai it ί conductor wafer, the semiconductor wafer has a photoresist material 2 mounted on the surface Welding pads: On the surface, the entire thickness of the insulation pads installed on the top pad of Fengti Riwu is formed with several corresponding Tan pads that expose the wafer: Erlizha, and TTV is divided into two parts. Ding Wangxin: The perforation system of the perforated layer of the wounded layer: J forms a covering layer on the insulating layer so that the insulation is washed. The cover is the exposure and conversion ratio of the covering layer by using a photomask. : Perforation: Γ After the formation of the exposed hole in the central part of the pad exposed by the exposure hole, a material is formed on each of the covering layers so that the inside of each exposed hole Bumps :: Filler> The main bumps are formed as _ corresponding after processing (the material is removed in an appropriate cover layer and formed on each pad and formed into a metal layer so that the conductive bump system Shaped, M plating method ~ Corresponding bumps extend to the surface of the corresponding pad The layer system according to another feature of the present invention, a form: the following steps W. provide a semiconductor wafer, the method of the block, the pad surface of the women's clothing and a number of IV body mounted on the pad The Japanese yen and the Japanese yen have pads formed on the surface of the semiconductor garment with an insulating layer made of a photoresist material. On the surface, the insulating layer is formed by using a photomask to expose a 2T pad mounting mechanism to form several exposures. Correspondence of this wafer: σ chemical washing, etc.

第5頁 五、發明說明(3) 孔’·於該絕緣層的每一穿孔内 面齊平之表面的光阻材料層,‘光「:有與該絕緣層之表 罩的曝光和化學沖先阻材料層係藉著使用光 之中央部份的曝露孔、:^成有數個曝露對應之焊墊 部份的面積係比4孔; 小,在光阻材料層之暖噯^ 、〒墊之中央部份的面積 的每一個曝露孔内係=^ Λ >成之後,於該光阻材料層 露孔内的凸,點形才、ϋ=點形成材料以致於每一個曝 對應之太旱墊上# n科在適以處理後作為-個形成於一 每一焊墊上的凸點技及把该光阻材料層移去且在形成於 電凸塊係被形成,今”、電錢方式开》成一金屬層以致於導 應之焊墊的表面上母—金屬層係從一對應的凸點延伸到對 根據本發明之 法,包含如下之I蛛另一特徵,一種形成導電凸塊的方 具有一焊墊安裝# ·提供一半導體晶元,該半導體晶元 墊;以光阻材^幵^及數個安裝於該焊塾安裝表面上的焊 安裝表面,該絕緣絕緣層於該半導體晶元的整個焊墊 處理來形成有數個1:稭著使用光罩的曝光和化學沖洗等 穿孔;於該絕緣岸二,°亥晶兀之對應之焊墊之中央部份的 以致於每_個、^ 母—個穿孔内係填注有凸點形成材料 一個形成於一對庳的凸點形成材料在適當的處理後作為 該絕緣層被移去:=烊墊上的凸點;把該絕緣層移去;在 以光阻材料形成一 f」於該晶元的整個焊墊安裝表面上係 使用光罩的曝光和2層以致於該寻凸點係被覆蓋,藉著 、 化學沖洗等處理,該保護層係形成有數Page 5 V. Description of the invention (3) Holes' · Photoresist material layer on the surface flush with the inner surface of each perforation of the insulating layer, 'light': there is exposure and chemical impact with the cover of the insulating layer The resist material layer is formed by using the exposure holes in the central portion of the light, and the area of the exposed pad portions is smaller than 4 holes. The smaller, the warmer layer of the photoresist material layer is. The central part of the area of each exposure hole = ^ Λ > After completion, the convexity in the exposed hole of the photoresist material layer, the point shape, ϋ = point forming material, so that each exposure corresponds to too dry The pad on the pad is treated as a bump formed on each pad and the photoresist material layer is removed and formed in the formation of the electric bump system. 》 Make a metal layer so that the mother-metal layer on the surface of the conductive pad extends from a corresponding bump to the method according to the present invention, which includes another feature of the following spider, a method for forming conductive bumps Have a solder pad installation # · Provide a semiconductor wafer, the semiconductor wafer pad; a photoresist material ^ 幵 ^ and number The solder mounting surface is mounted on the solder mounting surface, and the insulating layer is processed on the entire pad of the semiconductor wafer to form a plurality of perforations such as exposure using a photomask and chemical washing; on the insulating shore Second, the corresponding part of the central part of the soldering pad of the helium crystal is such that every _, ^ female-a perforation is filled with a bump forming material, and a bump forming material formed on a pair of After the treatment, the insulation layer is removed: = bumps on the pad; the insulation layer is removed; a photoresist is used to form a f "on the entire pad mounting surface of the wafer using a photomask exposure And 2 layers so that the bump-seeking system is covered, and the protective layer system is formed by processing such as chemical washing

第6頁 1241009 五、發明說明(4) 個用於曝露該等凸點的開孔;及在形成於每一焊墊上的凸 點上係以電鍍方式形成一金屬層以致於導電凸塊係被形 成,每一金屬層係從一對應的凸點延伸到對應之焊墊的表 面上。Page 6 1241009 V. Description of the invention (4) openings for exposing the bumps; and a metal layer is formed on the bumps formed on each pad by electroplating so that the conductive bumps are covered Formed, each metal layer extends from a corresponding bump to the surface of the corresponding pad.

根據本發明之又再一特徵’一種形成導電凸塊的方 法,.包含如下之步驟··提供一半導體晶元,該半導體晶元 具有一焊墊安裝表面及數個安裝於該焊墊安裝表面上的焊 墊;以光阻材料形成一絕緣層於該半導體晶元的整個焊墊 安裝表面,該絕緣層係藉著使用光罩的曝光和化學沖洗等 處理來形成有數個曝露該晶元之對應之焊墊之中央部份的 穿孔;於該絕緣層的每一個穿孔内係填注有凸點形成材料 以致於每一個穿孔内的凸點形成材料在適當的處理後作為 一個形成於一對應之焊墊上的凸點;把該絕緣層移去;及 在形成於每一焊墊上的凸點上係以電鍍方式形成一金屬層 以致於導電凸塊係被形成,每一金屬層係從一對應的凸點 延伸到對應之焊墊的表面上。According to still another feature of the present invention, a method for forming a conductive bump, comprising the steps of: providing a semiconductor wafer having a pad mounting surface and a plurality of mounting surfaces mounted on the pad; A photoresist material is used to form an insulating layer on the entire pad mounting surface of the semiconductor wafer. The insulation layer is formed by using a photomask to expose and chemically process the exposed wafer. Corresponding perforations in the central portion of the solder pad; each of the perforations of the insulating layer is filled with a bump-forming material so that the bump-forming material in each perforation is formed as a Bumps on the pads; remove the insulating layer; and a metal layer is formed on the bumps formed on each pad by electroplating so that conductive bumps are formed, and each metal layer is formed from a The corresponding bumps extend onto the surface of the corresponding pad.

根據本發明之又再一特徵,一種形成導電凸塊的方 法,包含如下之步驟:提供一半導體晶元,該半導體晶元 具有一焊墊安裝表面及數個安裝於該焊墊安裝表面上的焊 墊;以光阻材料形成一凸點形成層於該半導體晶元的整個 焊墊安裝表面,該凸點形成層係藉著使用光罩的曝光和化 學沖洗等處理來使得僅該凸點形成層之對應於該等焊墊之 中央部份的部份被留下作為凸點;及在形成於每一焊墊上 的凸點上係以電鍍方式形成一金屬層以致於導電凸塊係被According to still another feature of the present invention, a method for forming a conductive bump includes the steps of: providing a semiconductor wafer having a pad mounting surface and a plurality of pads mounted on the pad mounting surface. A solder pad; a bump forming layer is formed on the entire pad mounting surface of the semiconductor wafer by using a photoresist material, and the bump forming layer is formed by using a photomask to expose and chemically process the only bump A portion of the layer corresponding to the central portion of the pads is left as a bump; and a metal layer is formed on the bumps formed on each pad by electroplating so that the conductive bumps are

第7頁 1241009 五、發明說明(5) 形成,每一金屬層係從一對應的凸點延伸到對應之焊墊的 表面上。 根 法,包 具有一 墊;以 焊墊安 理,僅 被留下 元的整 罩的曝 對應之 金屬層 的凸點 根 法,包 一用於 有數個 料形成 層係藉 曝露該 個穿孔 點形成 去且在 據本發明 含如下之 焊墊安裝 光阻材料 裝表面上 該凸點形 作為凸點 個焊墊安 光和化學 凸點的穿 以致於導 延伸到對 據本發明 含如下之 安裝晶元 以矩陣形 一絕緣層 之再另 步驟: 表面及 形成一 ,藉著 成層之 :以光 裝表面 沖洗等 孔;及 電凸塊 應之焊 之又再 步驟: 的安裝 式排列 於該封 罩的曝 應之導 有凸點 一特徵, 提供一半 數個安裝 凸點形成 使用光罩 對應於該 阻材料形 上俾可覆 處理,該 ^種形 導體晶 於該焊 層於該 的曝光 等焊墊 成一絕 蓋該等 絕緣層 在每一凸點上係 成導電凸 元,該半 塾安裝表 半導體晶 和化學沖 之中央部 緣層於該 凸點,藉 係形成有 以電鍍方 塊的方 導體晶元 面上的焊 元的整個 洗等處 份的部份 半導體晶 著使用光 數個曝露 式形成一 係被形成,每一金屬層係從一對應 塾的表面上。 另一特徵 提供一封 表面及一 著使用光 基體之對 内係填注 材料在適當的處 形成於每一導電 裝基體 與該安 點的佈 整個佈 沖洗等 穿孔; 種形成導電 ,該封裝 裝表面相 設表面。 設表面上 處理來形 之導電接 裝基體的 光和化學 電接點的 形成材料以致於每一個穿 理後作為一凸點;及把該 接點上的凸點上係以電鍍 凸塊的方 基體具有 對且佈設 以光阻材 ,該絕緣 成有數個 於該絕緣層的每一 子L内的凸 絕緣層移 方式形成Page 7 1241009 V. Description of the invention (5) Formation, each metal layer extends from a corresponding bump to the surface of the corresponding pad. In the root method, the package has a pad; the solder root method is used, and the bump root method of the metal layer corresponding to the entire exposure of the element is left. The package method is used to form a plurality of layers by exposing the perforation point. On the surface of the photoresist material mounting surface containing the following pads according to the present invention, the bump shape is used as a bump for the pads and the chemical bumps so that the lead extends to the mounting crystals containing the following according to the present invention. Another step is to form an insulating layer in the form of a matrix: surface and form one, by layering: flush the holes with a light-loaded surface; and another step of welding the electrical bumps: the installation type is arranged in the enclosure The exposure guide has a feature of bumps, which provides half of a number of mounting bumps. A photomask is provided to correspond to the shape of the resistive material. The conductive conductor crystals are formed on the solder layer during the exposure and other welding processes. The insulation layer is formed as a conductive cover on each of the bumps. The semi-conducting central edge layer of the semiconductor crystal and the chemical punch is mounted on the bump, and a square conductor with a plated square is formed by this. The entire portion of the solder element on the wafer surface was washed in equal parts. The semiconductor crystal was formed using light and several exposure patterns were formed. Each metal layer was formed on a surface corresponding to 塾. Another feature is to provide a surface and a pair of interstitial filling materials using a light substrate, forming perforations at the appropriate place on each conductive package substrate and the cloth of the safety point, such as washing the entire cloth; Surface phase surface. Suppose that the light and chemical electrical contact forming material of the conductive mounting substrate is processed on the surface so that each of them is treated as a bump; and the bump on the contact is plated with a plated bump. The base body is provided with a photoresist material, and the insulation is formed by a plurality of convex insulation layers in each sub-L of the insulation layer.

第8頁 1241009 --—--- 五、發明說明(6) 一金屬層以致 應的凸點延伸 根據本替 含如下之步鄉 女裝晶元的安 以矩陣形式挪 一凸點形成層 光罩的曝光和 該等導電接點 點的形成之後 以致於導電凸 延伸到對應之 根據本發 包含如下之步 於安裝晶元的 個以矩陣形式 赴,藉由使用 點上係形成有 亡係以電鍍方 每一金屬層係 面上。 於導電凸塊係被形 到對應之導電接點 明之一嚇徵,一種 :提供 裝表面 列之導 於該封 化學 '沖 之中央 ’在每 塊係被 導電接 明之另 驟:提 安裝表 一封裝 及一 電接點 裝基體 洗等處 部份的 基體 該安 的佈 的整 理, 部份 一凸點上係 形成, 點的表 一特徵 供一封 面及一 排列之導電接 的印刷 一鋼板 一凸點 及在 式形成一金屬 從一對應的凸 母— 面上 5 _ 裝基 與該 點的 方法 形成 層以 點延 成, 的表 形成 ,該 裝表 設表 個佈 僅該 被留 以電 金屬 母一 面上 導電 封裝 面相 面; 叹表 凸點 下作 鑛方 層係 金屬層係從一對 凸塊的 基體具 對且佈 以光阻 面上, 形成層 為凸點 方法,包 有一用於 設有數個 材料形成 藉著使用 之對應於 ;及在凸 式形成一金屬層 從一對應的凸點 種形成金屬凸點的方法, 體,該封裝基體具有一用 安裝表面相對且佈設有數 佈設表面;以導電膠為材 ’於々基體之每_導會接 於每:導電接點上的凸點 致於導電凸塊係被形成, 伸到對應之導電接點的表 很據本發明之一衍徵,一 含:~半導體晶元,該半導/ί具有:電=的裝置, 數個安裝於該焊墊安裝表面7具有:二墊安裝表面 上的焊墊;及數個各形成於Page 81241009 ------ 5. Description of the invention (6) A metal layer extends the corresponding bumps. According to this step, a bump is formed in the form of a matrix to remove the bumps to form a layer of light. After the exposure of the cover and the formation of these conductive contacts, the conductive bumps extend to the corresponding ones. According to the present invention, the following steps are included in the installation of the wafer in a matrix form. Each metal layer on the plating side is on the surface. The conductive bumps are shaped to correspond to one of the conductive contact points. One is to provide the mounting surface guide at the center of the sealing chemistry. The other step is to conduct the conductive blocks. Another step is: Encapsulation and washing of an electrical contact with the substrate and other parts of the substrate should be finished with cloth. Part of a bump is formed on the surface. The table's characteristics are for one surface and an array of printed conductive plates. The bumps and the formation of a metal from a corresponding convex mother — 5 _ on the surface and the method of forming the base to form a layer with a dot extension, the table is formed, and the table cloth should only be left for electricity. On one side of the metal mother, the conductive packaging surfaces are opposite to each other. The metal layer is formed from a pair of bumps on the substrate and arranged on the photoresist surface under the bumps of the meter. The layer is a bump method. A plurality of materials are provided to correspond to each other by using; and a method for forming a metal bump from a corresponding bump in a convex type forming a metal layer, the package base has a mounting surface opposite to and arranged Laying the surface; using conductive glue as the material, each guide on the base is connected to each: the bumps on the conductive contacts cause the conductive bumps to be formed, and the table extending to the corresponding conductive contacts is according to the present invention. One of them includes: a semiconductor wafer, the semiconductor device has: an electric device, a plurality of pads mounted on the pad mounting surface 7 has: two pads on the pad mounting surface; and several Formed in

1241009 五、發明說明(7) 對應之焊墊 一形成於一 上且從該對 〇 之中央部份上的導電凸塊,每一導電凸塊包括 對應之焊墊上的凸點及一形成於該對應之凸點 應之凸點延伸到對應之焊墊之表面上的金屬 根據本發明之另 包含:一半導體晶元 於該焊墊 及數個安裝 對應之焊墊 屬層係形成 之中央部 於一對應 對應之焊墊的表面上 一導電凸塊。 根據本發明 置,包含:一封 的安裝表面及一 式排列之導 一對應之導 成於一對應 上且從該對 屬層。 【實施方式 在本發 是,在整個 號標示。此 件並非按實 電接 電接 之導 應之 之又 裝基 與該 點的 點上 電接 凸點 一特徵,一種具有導電凸塊的裝置, ,該半導體晶元具有一焊墊安裝表面 安裝表面上的焊墊;數個各形成於一 份上的凸點;及數個金屬層,每一金 之凸點上且係從.該對應之凸點延伸到 ,每一金屬層與對應的凸點共同形成 另一特徵,一種具有導電凸塊的裝 體,該封裝基體具有一用於安裝晶元 安裝表面相對且佈設有數個以矩陣形 佈設表面;及數個各形成於該基體之 的導電凸塊,每一導電凸塊包括一形 點上的凸點及一形成於該對應之凸點 延伸到對應之導電接點之表面上的金 明之較佳實施例被詳細描述之前,應要注意的 說明當中,相同的元件係從頭到尾由相同的標 外,為了清楚揭示本發明的特徵,圖式中的元 際比例描繪。1241009 V. Description of the invention (7) The corresponding solder pads are formed on one and the conductive bumps on the central part of the pair 0, each conductive bump includes a bump on the corresponding solder pad and one formed on the Corresponding bumps. The metal extending from the corresponding bumps to the surfaces of the corresponding pads. According to the present invention, a semiconductor wafer is formed on the pads and a plurality of central portions formed by the corresponding pads are mounted on the pads. A conductive bump is formed on a surface of a corresponding corresponding pad. The device according to the present invention includes: a mounting surface and an array of guides, a corresponding guide is formed on a corresponding and from the pair of layers. [Embodiment] In this issue, it is indicated on the entire number. This piece is not according to the characteristics of the actual electrical connection, and the mounting base and the point on the point are electrically connected to a bump. A device with conductive bumps. The semiconductor wafer has a pad mounting surface. Pads on the surface; a plurality of bumps each formed on a portion; and a plurality of metal layers, each of the gold bumps and extending from the corresponding bump to each metal layer and the corresponding The bumps collectively form another feature, a package body with conductive bumps, the package base body having a mounting surface for mounting wafers opposite to each other and a plurality of surfaces arranged in a matrix form; and a plurality of Conductive bumps. Each conductive bump includes a bump on a shape point and a preferred embodiment of Jin Ming formed on the surface of the corresponding bump extending to the corresponding conductive contact. Note that in the description, the same elements are marked by the same standard from beginning to end. In order to clearly reveal the features of the present invention, the inter-elemental proportions in the drawings are depicted.

第10頁 1241009 五、發明說明(8) 第一至八圖是為示意地描繪本發明之第一 ΐ形ΐί電凸塊之方法之流程的剖視圖。在本施例 ,導電凸塊係形成於一半導體晶元上。 土只施例 首先,請參閱第一圖所示,_丰宴卿曰 該半導體晶元!…焊墊安裝;:二及:首先被 =亥焊墊安裝表面η上的焊墊u (在圖式中僅^,安裝 丄:應要注意的是’該晶u τ以是為 :曰、圓個痒 =切割出來的單-晶元或者可以是為未從(圖 口出來的晶元。於該晶元!白勺每—個焊墊 片晶圓 層1 2係以電鍍方式形成。 上,一電鍍 接著,一絕緣層2係形成於該半導體曰 〆 墊安裝表面1 〇上,如在第二圖中所示。Ba 的整個焊 在本實施例中,該絕緣層2係由像感 n )、聚醯亞胺(polyimide)等等 # & : i w(Ph〇to 隨後,藉著使用光罩(圖2般的^阻材料形成。 =’該絕緣層2係形成有數個:和化學沖洗 ^ 1上之電鑛層12之Μ部份的在 以致於ί絕:層〜絕孔二:,材料^ 。错著使用光罩(圖中 1 = ’如在第四圖中所示 该覆蓋層3係形成 /、)的曝光和化學沖洗等處理, J電鍍層12之中央4 元1 ;對應之焊墊U上 應要注意的是, 的曝路孔30,如在第五圖中所示。 田母—曝露孔30所曝露之電鍍層丨2之中央 1241009 五、發明說明(9) 部=面積係'比由穿孔2〇所曝露 鍛層Μ之 面積小。 〜蓋層3之曝露孔3〇的形成之後,於該 孔30内填注凸點形成特料"致於 二=:::成材料4在適當的處理後作為 :亥凸點形成材料4可以是為導電膠、錫膏 笔材枓或者可以是為塑膠等等般的非導電材料 例中,該凸點形成材料4 I為穆雜有金、銀、 電金屬粉末中之任何一種或多種金屬粉末的導 然後,請參閱第七和八圖所示,該覆蓋層 且在开y成於每一電鍍層1 2上的凸點4上係以電 一金屬層5以致於導電凸塊係被形成。每一金 一對,的凸點4延伸到對應之電鍍層丨2的表面 第九至十六圖是為是為示意地描繪本發明 實施例之形成導電凸塊之方法之流程的剖視圖 實施例中,導電凸塊係形成於一半導體晶元上 請參閱第九圖所示,與第一較佳實施例相 體晶元1係首先被提供。該半導體晶元1具有 表面10及數個安裝於該焊墊安裝表面丨0上的焊 式中僅顯示一個焊墊)。於該晶元1的每一個 一電錄層1 2係以電鍍方式形成。 接著,一絕緣層2係以與第一較佳實施例 和材料形成於該半導體晶元1的整個焊墊安裝 中央部份的 覆蓋層3的 每一個曝露 一凸點,如 等等般的導 。在本實施 銅、I呂等導 電膠。 3 係被移去 鍍方式形成 屬層5係從 上。 之第二較佳 。在本較佳 〇 同,一半導 一焊墊安裝 墊1 1 (在圖 焊墊1 1上, 相同的形式Page 10 1241009 V. Description of the invention (8) The first to eighth figures are cross-sectional views for schematically depicting the flow of the first method of the present invention. In this embodiment, a conductive bump is formed on a semiconductor wafer. Example of soil only First, please refer to the first picture, _ Feng Yanqing said the semiconductor wafer! … Pad mounting ;: two and: firstly = pad u on the pad mounting surface η (only ^ in the drawing, mounting 丄): It should be noted that 'the crystal u τ is: A round itch = a single-crystal wafer that is cut out or a wafer that has not been removed from the drawing. In this wafer! Each of the solder pad wafer layers 12 is formed by electroplating. An electroplating is followed by an insulating layer 2 formed on the semiconductor pad mounting surface 10, as shown in the second figure. The entire soldering of Ba in this embodiment, the insulating layer 2 is formed by an image. n), polyimide, etc. # &: iw (Ph〇to Subsequently, by using a photoresist (Figure 2 as a ^ resist material). = 'The insulating layer 2 is formed of several: and Chemical washing ^ 1 of the M part of the electric ore layer 12 is so that 绝: layer ~ pore # 2 :, material ^. Use a photomask by mistake (1 = 'as shown in the fourth picture The cover layer 3 is formed by exposure, chemical cleaning, and other treatments. The center of the plating layer 12 is 4 yuan 1; the corresponding pad U should be noted that the exposure hole 30 of Shown in the picture: Tianmu-the plating layer exposed by the exposure hole 30 丨 2 center 1241009 V. Description of the invention (9) Part = area system 'is smaller than the area of the forged layer M exposed by the perforation 20. ~ Cover layer After the formation of the exposed hole 3 in 3, the bump 30 is filled with a special material for forming the hole 30, so that the two = ::: forming material 4 is treated as the following: The bump forming material 4 can be In the case of conductive adhesive, solder paste, or non-conductive materials such as plastic, the bump forming material 4 I is made of any one or more of metal powders including gold, silver, and electric metal powder. Then, referring to the seventh and eighth figures, the cover layer is electrically connected to a metal layer 5 on the bumps 4 formed on each of the plating layers 12 so that conductive bumps are formed. Each pair of gold bumps 4 extends to the surface of the corresponding plating layer 丨 2. The ninth to sixteenth diagrams are sectional views for schematically describing the flow of the method for forming a conductive bump according to the embodiment of the present invention. The conductive bump is formed on a semiconductor wafer. Please refer to FIG. An example phase body wafer 1 is provided first. The semiconductor wafer 1 has a surface 10 and several welding patterns mounted on the pad mounting surface (0 only one pad is shown). In each of the wafer 1 An electric recording layer 12 is formed by electroplating. Next, an insulating layer 2 is formed by using the first preferred embodiment and the material formed on the entire pad of the semiconductor wafer 1 at the center of the cover layer 3. Each one exposes a bump, such as a guide. In this implementation, conductive adhesives such as copper and I Lu are used. 3 systems are removed from the plating method to form a metal layer. 5 systems are above. The second is better. This is better. 〇Same, one half of the pad mounting pad 1 1 (the same form on the pad 11 in the figure)

第12頁 1241009 〜----- 五、發明說明(1〇) 如在第十圖中所示 的曝光:化=;!:]:同^:二光罩(圖中未示) 對應之電鍍層12之中央部份的穿巴孔2曰〇 ’ ::㉒:數個曝露 不。 你弟十一圖中所 隨後,於該絕緣層2的每一穿;^ 9n向沒^ 該絕緣層2之表面齊平表 糸形成一具有與 二圖中所示。 …表面的光阻材料層6,如在第十 ^使用光罩(圖中未示)進行曝光和 里,4光阻材料層β係形成 予冲冼#處 焊墊11之電鑛層12之中二 露該晶元1之對應之 中所示。 ”央^的曝露孔60,如在第十三圖 應要注意的是,由每一暖㊉^丨β Λ 中央部份的面積係比由穿孔2 鍍層12之 份的面積小。 坏* L之电鍍層1 2之中央部 在光阻材料層6之曝露孔6 〇的开彡士々& 佳實施例中所說明妒,於$ 、^成後,如在第一較 fin w / * 般 亥光阻材料層6的每一個氓丨 60内係填注有凸點形成材料4 〕母個曝路孔 材科4在適當的處理後作為-凸點,如在第十四 然後’請參閱第十五和+丄 一 係被移去且在形成於每一電二:不,該光阻材料層6 方式形成-金屬:5 :致的凸點4、…電鍛 係攸-對應的凸點4延伸到對應之電鑛層㈣表面上 1241009 五、發明說明(11) 。最後,該絕緣層2 係被移去。 第十七至二十三圖是為是為示意地描繪本發 較佳實施例之形成導電凸塊之方法之流程的剖 :二 較佳實施例中,導電凸塊係形成於一半導體晶—Θ 本 、請參閱第十七圖所示,與第„較佳實施例 導體晶元1係首先被提供。該半導體晶元〗具二:一半 裝表面1 0及數個安裝於該焊墊安裝表面】〇上^:=墊安 圖式中僅顯示一個焊墊)。於該半導體晶元2 (在 墊11上,一電鍍層12係以電鍍方式形成。 、母一個焊 接著,-絕緣層2係以與該第一較佳實施 式和材料來形成於該半導體晶元丨的整個焊墊=同的形 上,如在第十八圖中所示。 衣表面1 〇 與第一較佳貫施例相同,藉著使用光罩(圖 一 的曝光和化學沖洗等處理,該絕緣層2係形:未不) 對應之電鍍層1 2之中央部份的穿孔20,如在第之個曝露 示。 牡弟十九圖中所 隨後,如在第一較佳實施例中所說明般,於 π 2的每一個穿孔2〇内係填注有凸點形成材料4以層 個牙孔2 0内的凸點形成材料4在適當的處理後;母 ,如在第二十圖中所示。 …、一凸點 然後,該絕緣層2係被移去,如在第二十_圖中戶 不。在該絕緣層2被移去之後,請參閱第二十二^所= 於該晶元1的整個焊墊安裝表面1 0上係以光阻材^ 不’ 保護層7以致於該等凸點4係被覆蓋。 科形成一 1241009 五、發明說明(12) 接著,藉 等處理,該保 開孔7 0,如在 的形成之後, 鍍方式 屬層5 上。 第 佳實施 佳實施 本 流程係 處理流 與 緣層2 係以電 每一金 的表面 第 實施例 實施例 首 被提供 裝於該 形成一 係從一 二十四 例之形 例中, 較佳實 與第三 程相同 第三較 被移去 鍍方式 屬層5 上。 三十至 之形成 中,導 先,請 。該半 焊墊安 著使用光罩(圖中未示)的曝光和化學沖洗 護層7 係形成有數個用於曝露該等凸點4 的 第二十三圖中所示。在該保護層7 之開孔7 0 在形成於每一電鍍層1 2上的凸點4 上係以電 金屬層5以致於導電凸塊係被形成。每一金 對應的凸點4 延伸到對應之電鍍層1 2的表面 至二十 成導電 導電凸 施例之 較佳實 ,因此 佳實施 之後, 形成一 係從一 九圖是為 凸塊之方 塊係形成 在第二十 施例之在 ,其之詳 合|J不同, 在形成於 金屬層5 對應的凸 示意地描繪本發明之第四較 法之流程的剖視圖。在本較 於一半導體晶元上。 八圖中所示的處理 四至二十 第十七至 細說明於 在本較佳 十一圖中所示的 此係被省略。 實施例中,於該絕 每一電鍍層1 2上的凸點4 上 以致於導電凸塊係被形成。 點4 延伸到對應之電鍍層1 2 三十三圖是為示意地描繪本發明之第五較佳 導電凸塊之方法之流程的剖視圖。在本較佳 電凸塊係形成於一半導體晶元上。 參閱第三十圖所示,一半導體晶元1 係首先 導體晶元1具有一焊墊安裝表面1 0及數個安 裝表面1 0上的焊墊1 1 (在圖式中僅顯示一個 ❿Page 121241009 ~ ----- V. Description of the invention (10) Exposure as shown in the tenth picture: Hua =;!:]: Same as ^: two photomasks (not shown in the figure) corresponding The through hole 2 in the central portion of the plating layer 12 is 0 ′ :: ㉒: Several are not exposed. In the eleventh figure of your brother, at each pass of the insulating layer 2; ^ 9n to ^ the surface of the insulating layer 2 is flush with the surface of the insulating layer 2 as shown in FIG. … The photoresist material layer 6 on the surface, such as the tenth photomask (not shown in the figure) for exposure and exposure, 4 photoresist material layer β is formed in the electric ore layer 12 of the pad 11 at the pre-chong ## Zhong Erlu is shown in the corresponding one of the wafer. The central exposure hole 60, as shown in the thirteenth figure, should be noted that the area of the central part of each heating element ^ 丨 β Λ is smaller than the area of the plating layer 12 by the perforation 2. Bad * L The central portion of the electroplated layer 12 in the exposed hole 6 of the photoresist material layer 6 is described in the preferred embodiment. After $, ^ is completed, as in the first comparison fin w / * Each of the photoresist material layers 6 of the general photoresist material layer 60 is filled with a bump forming material 4] The female exposed hole material section 4 is treated as a -bump after appropriate processing, as in the fourteenth and then 'Please Refer to the fifteenth and + 丄 series are removed and are formed in each electric two: No, the photoresist material layer is formed in 6 ways-metal: 5: the bumps 4, ... electroforming system-corresponding The bump 4 extends to the surface of the corresponding electric ore layer 1001241009 V. Description of the invention (11). Finally, the insulating layer 2 is removed. The seventeenth to twenty-third drawings are for schematically depicting the present invention. Sectional flow of the method of forming a conductive bump in the preferred embodiment: In the second preferred embodiment, the conductive bump is formed on a semiconductor crystal—Θ this, please refer to Figure 17 , The first "conductor wafer in Example 1 was first provided by the preferred system embodiment. The semiconductor wafer has two: one half of the mounting surface 10 and several mounting surfaces on the pad mounting surface] 〇: ^: = pad mounting Only one pad is shown in the figure). On the semiconductor wafer 2 (on the pad 11, a plating layer 12 is formed by electroplating. A mother is welded, and an insulating layer 2 is formed on the semiconductor wafer with the first preferred embodiment and material. The entire pad of the element 丨 is the same shape, as shown in the eighteenth figure. The clothing surface 10 is the same as the first preferred embodiment. By using a photomask (exposure and chemical processing in FIG. 1 etc.) Treatment, the insulating layer 2 is shaped: not not) The perforation 20 in the central portion of the corresponding plating layer 12 is shown in the first exposure. The following is shown in the nineteenth figure, as in the first preferred implementation As illustrated in the example, the bump forming material 4 is filled in each of the perforations 20 of π 2 to form the bump forming material 4 in each of the perforations 20 after proper processing; the mother, as in the first It is shown in the figure.. ......., a bump. Then, the insulating layer 2 is removed, as in the twentieth_ figure. After the insulating layer 2 is removed, please refer to the twenty-second ^ So = a photoresist is placed on the entire pad mounting surface 10 of the wafer 1 ^ No 'the protective layer 7 so that the bumps 4 are covered. Section 1 1241009 V. Description of the invention (12) Next, by waiting for the treatment, the retaining opening 70 is formed on the layer 5 after the formation. The best implementation is the process flow and the edge layer 2 The first embodiment of the surface of each gold is provided in the first embodiment. The first layer is provided in a series from the twenty-four cases. It is preferably the same as the third pass. The third layer is removed. The plating method belongs to the layer 5. In the formation of 30 to 30 years, please, please. The semi-solder pad is equipped with a photomask (not shown) for exposure and chemical cleaning. The protective layer 7 is formed with several layers for exposing the bumps 4 As shown in the twenty-third figure, the opening 7 0 of the protective layer 7 is provided with an electric metal layer 5 on the bumps 4 formed on each of the plating layers 12 so that conductive bumps are formed. Each A gold corresponding bump 4 extends to the surface of the corresponding electroplated layer 12 to 20% of the conductive and conductive bumps. Therefore, after the implementation, a series of blocks from the nineteenth figure are bumps. Formed in the twentieth embodiment, the details of which | J are different, formed in The corresponding projection of the metal layer 5 schematically depicts a cross-sectional view of the fourth comparison method of the present invention. This comparison is compared with a semiconductor wafer. This system shown in the eleventh preferred figure is omitted. In the embodiment, the conductive bumps are formed on the bumps 4 on each of the plating layers 12. The dots 4 extend to the corresponding plating layers. 1 2 33 is a cross-sectional view schematically depicting the flow of the method of the fifth preferred conductive bump of the present invention. The preferred electrical bump is formed on a semiconductor wafer. See FIG. 30 It is shown that a semiconductor wafer 1 is firstly a conductor wafer 1 having a pad mounting surface 10 and pads 1 1 on a plurality of mounting surfaces 10 (only one is shown in the figure)

第15頁 1241009 五、發明說明(13) 焊墊)。於該晶元1 的每一個焊墊1 1上 電鍍方式形成。 電鍍層1 2係以 個焊墊 成層8 等等之 墨等等 缺 〇、、 等處理 層12之 圖中所 隨 方式形 層5 係 上。 應 能夠以 電鍍方 第 佳實施 佳實施 首 先被提 安裝於 接著,一凸點形成層8 安裝表面10上,如在 係可以由光阻材料或 低價金屬粉末中之任 的光阻材料形成。 後,藉著使用光罩( ,僅該凸點形成層8 中央部份的部份被留 示0 係形成於該半導體晶元1的整 第三十一圖中所示。該凸點形 摻雜有如金、銀、銅、鐵、銘 何一種或多種粉末或塑膠、石 圖中未示)的曝光和化學沖洗 之對應於該等焊墊1 1上之電鍍 下作為凸點8 0,如在第三十二 後,在形成於每一電鍍層1 2上的凸點8 0上係以電鍍 導電凸塊係被形成。每一金屬 伸到對應之電鍍層1 2的表面 成 從 金 對 屬層5以致於 應的凸點8 0延 要注意 如塑膠 式形成 三十四 例之形 例中, 先’請 供。該 該焊墊 的是,端視凸 電鍍、無化學 0 至三十八圖是 成導電凸塊之 導電凸塊係形 參閱第三十四 半導體晶元1 安裝表面1 0上 點8 0的材料而定,金屬層5 係 電解電鍍等等般之任何適當的 為示意地描繪本發明之第六較 方法之流程的剖視圖。在本較 成於一半導體晶元上。 圖所示,一半導體晶元1 係首 具有一焊墊安裝表面1 0及數個 的焊墊11 (在圖式中僅顯示一 111Page 15 1241009 V. Description of the Invention (13) Pad). It is formed on each pad 11 of the wafer 1 by electroplating. The plating layer 12 is a layer 8 of ink, etc., which is formed by a pad, etc. The layer 5 is formed on the layer 12 in the manner shown in the figure. It should be able to be the best implementation in the electroplating method. The first implementation is first mounted on the next, and a bump forming layer 8 is mounted on the mounting surface 10, for example, it can be formed of a photoresist material or a low-cost metal powder. Then, by using a photomask (, only the central portion of the bump forming layer 8 is left as 0. The system is formed as shown in the entire thirty-first figure of the semiconductor wafer 1. The bump shape is doped Exposure and chemical cleaning mixed with one or more powders such as gold, silver, copper, iron, or inscriptions (not shown in the stone drawings) and chemical cleaning correspond to the pads 8 as bumps 80 under the plating on these pads 1, such as After the thirty-second, the bumps 80 formed on each of the plating layers 12 are formed in a plating conductive bump system. Each metal extends to the surface of the corresponding electroplated layer 12 to form a metal bump 5 to the corresponding bump 80. It should be noted that in the case of thirty-four cases formed by plastic, first, please provide. The pads are end-view convex electroplated, non-chemical 0 to 38. The figure is a conductive bump system that is a conductive bump. See the material of the 34th semiconductor wafer 1 mounting surface 1 0 on point 8 0 In addition, the metal layer 5 is any appropriate cross-sectional view such as electrolytic plating or the like, which schematically depicts the flow of the sixth comparison method of the present invention. This is compared to a semiconductor wafer. As shown in the figure, a semiconductor wafer 1 series has a pad mounting surface 10 and several pads 11 (only one 111 is shown in the figure).

第16頁 1241009 五、發明說明(14) 個焊墊)。於 以電鍍方式形 接著,一 個焊墊 成層8 等等之 墨等等 缺 等處理 鍍層1 2 圖中所 隨 墊安裝 所示。 接 等處理 孔2 0, 夕k 式形成 5 係從 第 佳實施 佳實施 首 安裝表 係可以 低價金 的光阻 後,藉 ,,僅 之中央 示。 後,一 該晶元1 成。 凸點形成 面1 0上, 由光阻材 屬粉末中 材料形成 著使用光 該凸點形 部份的部 的每一個焊墊1 1上 電鍍層1 2係 一絕緣層2 表面1 0上俾可覆 著,藉 ,該絕 如在第 後,在 一金屬 一對應 三十九 例之形 例中, 先’如 著使用光 緣層2 係 三十八圖 形成於每 層5 以致 的凸點8 0 至四十二 成導電凸 導電凸塊 在第三十 層8 係形成於該半導體晶元1的整 如在第三十五圖中所示。該凸點形 料或推雜有如金、銀、銅、鐵、I呂 之任何一種或多種粉末或塑膠、石 〇 罩(圖中未示)的曝光和化學沖洗 成層8 之對應於該等焊墊1 1上之電 份被留下作為凸點8 0如在第三十六 係形成於該半導體晶元1的整個焊 蓋該等凸點8 0,如在第三十七圖中 罩(圖中未示)的曝光和化學沖洗 形成有數個曝露對應之凸點8 0的穿 中所示。 一焊墊1 1上的凸點8 0上係以電鍍方 於導電凸塊係被形成。每一金屬層 延伸到對應之電鍍層1 2的表面上。 圖是為示意地描繪本發明之第七較 塊之方法之流程的剖視圖。在本幸父 係形成於一半導體晶元上。 九圖中所示,一半導體晶元1係首Page 16 1241009 V. Description of the invention (14) pads). In the form of electroplating, a pad is formed of layer 8 and so on. Ink treatment etc. Plating layer 1 2 The installation of the pad is shown in the figure. After processing the hole 20, the k-type 5 is formed from the best implementation. The first installation table is a low-cost gold photoresist, and it is only shown in the center. After that, the wafer is 10%. On the bump forming surface 10, each pad 11 formed on the bump-forming portion using a material in the powder of the photoresist material is formed on the surface of the bump-shaped portion. 1 is an insulating layer 2 on the surface 10 It can be covered. By the way, in the last example, a metal one corresponds to the 39 cases. First, as in the book, the light edge layer 2 is used to form the 38 figures. 80 to 42% of the conductive bumps are formed on the semiconductor wafer 1 in the 30th layer of the 8 series as shown in the thirty-fifth figure. The bump material may be mixed with any one or more powders or plastics such as gold, silver, copper, iron, and aluminum, and exposed to a chemical mask (not shown in the figure) and chemically processed into layers. 8 The electrical components on the pad 11 are left as bumps 80, as in the thirty-sixth series, the entire solder cap formed on the semiconductor wafer 1, such bumps 80, as shown in the thirty-seventh figure ( Exposure and chemical processing (not shown in the figure) are formed in the exposure through a number of exposures corresponding to the bumps 80. The bumps 80 on a pad 11 are formed on the conductive bumps by electroplating. Each metal layer extends onto the surface of the corresponding plating layer 12. The figure is a sectional view schematically depicting the flow of the method of the seventh block of the present invention. The Yukio parent is formed on a semiconductor wafer. As shown in the nine figures, a semiconductor wafer 1 series head

第17頁 五、發明說明(〗5) 先被提供。該半導體晶元1具有〜 安裝於該焊墊安裝表面1 〇上的谭藝^墊 個焊墊)。 王u ( 個烊Π裝係、形成於該. 或养ΪΠ 該凸點形成層8 , 7梦嘁有如金、銀、銅、鐵、鋁等‘ 壬何-種或多種粉末或塑膠等^ 寻處理,僅言亥凸點形成層δ 2) ^ 份的:::皮作為凸關如在ί:;: 凸點δ〇四周的*面上係 之 隨後,—絕緣屑 J形成一 塾安裳表面10上俾;;,於該半導體 所示。 j设里该寺凸點8 0,如 等處理,該中未示)的 孔2 0,如在第 你t成有數個曝露對 然後,在:^圖中所示。 以致於導電凸塊係被二80”、以電鍍方式 點8 0延伸到對應帝乂成 母一金屬層5 —應要注意的是屯鍍層12的表面上。 每一焊墊上係形 雖然在以上所述的較 在於每一焊墊上/ 電鍍層,然而,相 形成有一電鍍層之下達 ! 安裝表面1 0及數個 在圖式t僅顯示— ^ 體晶元1白勺整 产、可以由光阻材料 <價金屬粉末中之 光阻材料形成。 曝光和化學沖洗 焊墊1 1之中央部 中所示。 每一焊墊1 1之在 電鍍層1 2。 日日元1 的整個焊 在第四十一圖中 曝光和化學沖洗 應之凸點8 0的穿 形成一金屬層5 係從一對應的凸 佳實施例中,於 同的效果係可以 成。Page 17 V. Description of Invention (〖5) is provided first. The semiconductor wafer 1 has a series of pads (Tan Yi ^ pads mounted on the pad mounting surface 10). Wang u (individual 烊 Π system, formed in this. Or Yang ΪΠ the bump formation layer 8, 7 nightmare is like gold, silver, copper, iron, aluminum, etc. 'Renhe-a variety of powder or plastic, etc. ^ Processing, only the bump formation layer δ 2) ^ parts of ::: skin as a protrusion is attached on the * surface around ί:;: bump δ〇 followed by,-the insulation chip J forms a safe The skirt 10 is embossed; as shown in the semiconductor. j set the temple bumps 8 0, such as processing, not shown in the above) hole 2 0, as in the t t there are several exposure pairs, and then, as shown in the figure. So that the conductive bumps are two 80 ", and the point 8 0 is electroplated to extend to the corresponding metal layer 5 of the Emperor's mother-it should be noted that the surface of the plating layer 12. Although the shape of each pad is above The comparison is on each pad / plating layer, however, the phase is formed under a plating layer! The mounting surface 10 and several are only shown in the diagram t — ^ Volume crystal element 1 can be produced entirely by light Resist material < Photoresist material in valence metal powder is formed. Exposure and chemical processing of pads 1 1 are shown in the central part. Each pad 11 is on the plating layer 12 2. The whole of the yen 1 is soldered on In the forty-first figure, a metal layer 5 is formed through the bumps 80 of the exposure and chemical processing. From a corresponding convex embodiment, the same effect can be achieved.

1241009 五、發明說明(16) 第四十二至四十八圖是為示意地描繪本發明之第八 佳實施例之形成導電凸塊之方法之流程的剖視圖。在心 佳實施例中,導電凸塊係形成於一BGA封裝基體上。 首先,請參閱第四十三和四十四圖所示,一BGA封 基體9係首先被提供。該BGA封裝基體9具有一適於安裝 晶元^目中未示)的安裝表面9〇及-與該安裝表面90相對 且佈a又有數個以矩陣形式排列之導電接點9 2的佈設表面 91 0 . 接著,一絕緣層2係形成於該封裝基體9的整個佈設 表面91上,如在第四十五圖中所示。 σ1241009 V. Description of the invention (16) The forty-second to forty-eight diagrams are cross-sectional views schematically depicting the flow of the method for forming a conductive bump according to the eighth preferred embodiment of the present invention. In a preferred embodiment, the conductive bumps are formed on a BGA package substrate. First, please refer to the forty-third and forty-four figures, a BGA package 9 is provided first. The BGA package base 9 has a mounting surface 90 suitable for mounting wafers (not shown in the head) and a mounting surface opposite to the mounting surface 90 and having a plurality of conductive contacts 92 arranged in a matrix. 91 0. Next, an insulating layer 2 is formed on the entire layout surface 91 of the package base 9, as shown in the forty-fifth figure. σ

Ik後,藉著使用光罩(圖中未示)的曝光和化學沖 等處理,該絕緣層2係形成有數個曝露該基體9之對應 導電接點9 2的穿孔2 0,如在第四十六圖中所示。 然後,於戎絕緣層2的每一個穿孔2 〇内係填注有 :成材料4以致於每一個穿孔2。内的凸點形成材料4在^ §的處理後作為一凸點,如在第四十七圖中所示。 應要注意的是,該凸點形成材料是為摻雜有金、 ,、鋁等導電金屬粉末中之任何一種或多種粉末的導電 膠’或者可以是為無鉛錫膏,或者可以是為塑膠材料。 然後,請參閱第四十八圖所示,該絕緣層2係被 且在形成於母-導電接點92上的凸點4上係以電鍍方 成一金屬層5以致於導電凸塊係被形成。每一金屬層5 ^ 從-制的凸點4 &伸到對應之導電接點92的表面上。係 第四十九至五十一圖疋為示意地描繪本發明《第九較 1241009 五、發明說明(17) 佳實施例之形成導電凸塊之方法之流程的剖 隹實施例中’導電凸塊係形成於〜BgA 壯 圖。在本較 首先,請參閱第四十九圖所示,與j ,體上。 ^BGA封裝基體9係首先被提供。弟八貫施例相同, 一用於安裝晶“圖中未示)的安;表面體9具有 表面9 0相對且伟設有數個以矩陣形式排 4 一與該安裝 佈設表面91。 J歹1之導電接點92的 接著,一凸點形成層8係形成於該封壯 饰設表面9 1上。該凸點形成層8係可以1 ^基體9的整個 種或 等處理 份 在 有如金、[銅、鐵、謂之低價金屬由且=或換雜 多種粉末或塑膠、石,墨##^阻材料开^之任何一 隨後,藉著使用光罩(圖中未示) ,僅該凸點形成層8之對應於 化學沖洗 、八成寺導電接點q ? 由 央部份的部份被留下作為凸點80 ’如在第五十圖中所示。 如 在凸點80的形成之後’在每—凸點8〇上係以電鍍方式 形成〆金屬層5以致於導電凸塊係被形成。每一金屬層5 係從一對應的凸點80延伸到對應之導電接點92的表面上, 在第五十一圖中所示。 第五十二至五十四圖是為示意地描纟會本發明之第十較 佳實施例之形成導電凸塊之方法之流程的剖視圖。在本較 佳實施例丁 叮 ☆一 …"八刊衣签II上0 贫先,請參閱第五十二圖所示,與第八實施例相同 .B G A封裝基體9係首先被提供。該B G A封裝基體9具 •用於安裝晶元(圖中未示)的安裝表面90及一與該安 佳實施例中,導電凸塊係形成於一 BGA封裝基體上 ' ,譜答間弟五十二圖所六,盘笛Λ杳:Λ:.ϊAfter Ik, through the use of a photomask (not shown), exposure and chemical processing, the insulating layer 2 is formed with a number of perforations 20 that expose the corresponding conductive contacts 92 of the substrate 9 as in the fourth Shown in the sixteenth figure. Then, each of the perforations 20 of the Yu Rong insulation layer 2 is filled with: a forming material 4 so that each of the perforations 2. The inner bump forming material 4 is treated as a bump after the treatment of ^ §, as shown in the forty-seventh figure. It should be noted that the bump-forming material is a conductive adhesive doped with any one or more powders of conductive metal powders such as gold, aluminum, and aluminum, or may be a lead-free solder paste, or may be a plastic material. . Then, referring to the forty-eighth figure, the insulating layer 2 is formed on the bump 4 formed on the mother-conductive contact 92 by electroplating to form a metal layer 5 so that the conductive bump is formed. . Each metal layer 5 ^ extends from the bump 4 made from-to the surface of the corresponding conductive contact 92. Figures 49 to 51 are diagrams schematically illustrating the flow of the method of forming a conductive bump according to the ninth aspect of the present invention. Block system is formed in ~ BgA magnificent picture. In the first part of this book, please refer to the figure 49, with j, on the body. ^ BGA package base 9 series is provided first. The eighth brother has the same example, one for mounting crystals (not shown in the figure); the surface body 9 has a surface 90, which is opposite to the surface, and is provided with a plurality of rows 4 in a matrix, one with the installation layout surface 91. J 歹 1 Next to the conductive contact 92, a bump-forming layer 8 is formed on the sealing surface 91. The bump-forming layer 8 can be the entire type of the substrate 9 or an equal treatment portion such as gold, [Copper, iron, so-called low-priced metal is made of == or mixed with a variety of powders or plastics, stone, ink ## ^ 阻 材料 开 ^ Any of the following, by using a photomask (not shown in the figure), only the The portion of the bump forming layer 8 corresponding to the chemical flushing, Bacheng Temple conductive contact q? The central portion is left as a bump 80 'as shown in the fifty figure. As shown in the formation of the bump 80 After that, the 〆metal layer 5 is formed by electroplating on each of the bumps 80 so that conductive bumps are formed. Each metal layer 5 extends from a corresponding bump 80 to a corresponding conductive contact 92 On the surface, it is shown in the fifty-first figure. The fifty-second to fifty-four figures are for schematically depicting the tenth best of the present invention. A cross-sectional view of the flow of the method for forming a conductive bump in this embodiment. In the preferred embodiment, Ding Ding ☆ one ... " Eight Magazines II, 0, please refer to Figure 52, and the eighth The embodiments are the same. The BGA package base 9 is provided first. The BGA package base 9 is provided with a mounting surface 90 for mounting a wafer (not shown) and a conductive bump formed in the same embodiment On a BGA package substrate, 'Sixty-two Figures, Sixth, Pandi Λ 杳: Λ: .ϊ

1241009_ 五、發明說明(18) 表面9 0相對且佈設有數個以矩陣形式排列之導電接點9 2的 佈設表面9 1。 接著,以導電膠為材料,藉由使用一鋼板9 3的印刷方 法,於該基體9 之每一導電接點9 2上係形成有一凸點4 。 如在第五十三圖中所示。 隨後,在形成於每一導電接點9 2上的凸點4 上係以電 鍍方式形成一金屬層5以致於導電凸塊係被形成。每一金 屬層5 係從一對應的凸點4 延伸到對應之導電接點9 2的表 、 面上,如在第五十四圖中所示。 綜上所述,本發明之『一種形成導電凸塊的方法及具 | 有如此形成之導電凸塊的裝置』,確能藉上述所揭露之構 造、裝置,達到預期之目的與功效,且申請前未見於刊物 亦未公開使用,符合發明專利之新穎、進步等要件。 _ 惟,上述所揭之圖式及說明,僅為本發明之實施例而 已,非為限定本發明之實施例;大凡熟悉該項技藝之人 仕,其所佞本發明之特徵範疇,所作之其他等效變化或修 飾,皆應涵蓋在以下本案之申請專利範圍内。1241009_ V. Description of the invention (18) The surface 90 is opposite and there are several conductive contacts 92 arranged in a matrix form. The surface 91 is arranged. Next, a bump 4 is formed on each of the conductive contacts 92 of the base body 9 by using a conductive adhesive as a material and a printing method using a steel plate 9 3. As shown in the fifty-third figure. Subsequently, a metal layer 5 is formed on the bumps 4 formed on each of the conductive contacts 92 by electroplating so that a conductive bump system is formed. Each metal layer 5 extends from a corresponding bump 4 to the surface and surface of the corresponding conductive contact 92, as shown in the fifty-fourth figure. In summary, the "a method for forming a conductive bump and a device with the conductive bump thus formed" of the present invention can indeed achieve the intended purpose and effect by the disclosed structures and devices, and apply It has not been seen in publications or used in public before, which meets the requirements of novelty and progress of invention patents. _ However, the drawings and descriptions disclosed above are only examples of the present invention, and are not intended to limit the embodiments of the present invention. Anyone who is familiar with the technology, does what is characteristic of the invention, Other equivalent changes or modifications should be covered by the scope of patent application in the following case.

第21頁 1241009_ 圖式簡單說明 第一至八圖是為示意地顯示本發明之第一較佳實施例 之形成導電凸塊之方法之流程的剖視圖, 弟九至十六圖是為不意地%員不本發明之弟二較佳貫施 例之形成導電凸塊之方法之流程的剖視圖; 第十七至二十三圖是為示意地顯示本發明之第三較佳 貫施例之形成導電凸塊之方法之流程的剖視圖; 第二十四至二十九圖是為示意地顯示本發明之第四較 佳實施例之形成導電凸塊之方法之流程的剖視圖; 第三十至三十三圖是為示意地顯示本發明之第五較佳 實施例之形成導電凸塊之方法之流程的剖視圖; 第三十四至三十八圖是為示意地顯示本發明之第六較 佳實施例之形成導電凸塊之方法之流程的剖視圖; 第三十九至四十二圖是為示意地顯示本發明之第七較 佳實施例之形成導電凸塊之方法之流程的剖視圖; 第四十三至四十八圖是為示意地顯示本發明之第八較 佳實施例之形成導電凸塊之方法之流程的剖視圖; 第四十九至五十一圖是為示意地顯示本發明之第九較 佳實施例之形成導電凸塊之方法之流程的剖視圖;及 第五十二至五十四圖是為示意地顯示本發明之第十較 佳實施例之形成導電凸塊之方法之流程的剖視圖。 【圖式之主要元件代表符號表】 半導體晶元 10 焊墊安裝表面 焊墊 12 電鍍層 絕緣層 20 穿孔Page 211241009_ Brief description of the drawings The first to eighth diagrams are cross-sectional views schematically showing the flow of the method for forming a conductive bump according to the first preferred embodiment of the present invention. The nineteenth to sixteenth diagrams are unintentional. A cross-sectional view of the flow of a method for forming a conductive bump in the second preferred embodiment of the present invention; Figures 17 to 23 are diagrams for schematically showing the formation of the conductive conductivity in the third preferred embodiment of the present invention. Sectional views of the flow of the bump method; Figures 24 to 29 are cross-sectional views schematically showing the flow of the method of forming a conductive bump according to the fourth preferred embodiment of the present invention; Thirty to thirty The third figure is a sectional view schematically showing the flow of the method for forming a conductive bump according to the fifth preferred embodiment of the present invention; the thirty-fourth to thirty-eighth figures are schematically showing the sixth preferred embodiment of the present invention A cross-sectional view of the flow of a method of forming a conductive bump according to an example; Figures 39 to 42 are cross-sectional views schematically showing the flow of a method of forming a conductive bump according to a seventh preferred embodiment of the present invention; Thirteen to forty-eight figures Sectional views for schematically showing the flow of the method for forming a conductive bump in the eighth preferred embodiment of the present invention; Figures 49 to 51 are for schematically showing the formation of the ninth preferred embodiment of the present invention A cross-sectional view of a flow of a method of a conductive bump; and FIGS. 52 to 54 are cross-sectional views schematically showing a flow of a method of forming a conductive bump according to a tenth preferred embodiment of the present invention. [Representative symbols for main components of the figure] Semiconductor wafer 10 Solder pad mounting surface Solder pad 12 Plating layer Insulation layer 20 Perforation

第22頁 1241009Page 22 1241009

圖式簡單說明 3 覆蓋層 30 曝露孑L 4 凸點形成材料 5 金屬層 6 光阻材料層 60 曝露孑L 7 保護層 70 開孔 8 凸點形成層 80 凸點 9 封裝基體 90 安裝表面 91 佈設表面 92 導電接點 93 鋼板Brief description of the drawing 3 Cover layer 30 Exposed 孑 L 4 Bump forming material 5 Metal layer 6 Photoresist material layer 60 Exposed 孑 L 7 Protective layer 70 Opening hole 8 Bump forming layer 80 Bump 9 Package base 90 Mounting surface 91 Installation 91 Surface 92 conductive contact 93 steel plate

Claims (1)

1241009_ 六、申請專利範圍 1. 一種形成導電凸塊的方法,包含如下之步驟: 提供一半導體晶元,該半導體晶元具有一焊墊安裝 表面及數個安裝於該焊墊安裝表面上的焊墊; 以光阻材料形成一絕緣層於該半導體晶元的整個焊 墊安裝表面上,該絕緣層係藉著使用光罩的曝光和化學 沖洗等處理來形成有數個曝露該晶元之對應之焊墊之中 央部份的穿孔; 以光阻材料形成一覆蓋層於該絕緣層上以致於該絕 緣層的穿孔係被覆蓋,該覆蓋層係藉著使用光罩的曝光 和化學沖洗等處理來形成有數個曝露對應之焊墊之中央 部份的曝露孔,由每一曝露孔所曝露之焊塾之中央部份 的面積係比由穿孔所曝露之焊墊之中央部份的面積小; 在覆蓋層之曝露孔的形成之後,於該覆蓋層的每一 個曝露孔内填注凸點形成材料以致於每一個曝露孔内的 凸點形成材料在適當的處理後作為一個形成於一對應之 焊墊上的凸點;及 把該覆蓋層移去且在形成於每一焊墊上的凸點上 係以電鍍方式形成一金屬層以致於導電凸塊係被形成, 每一金屬層係從一對應的凸點延伸到對應之焊墊的表面 上。 2. 如申請專利範圍第1項所述之方法,其中,在提供半導 體晶元的步驟中,於該晶元的每一個焊墊上係形成有一 電鍍層。 3. 如申請專利範圍第1項所述之方法,其中,在填注凸點1241009_ VI. Application for Patent Scope 1. A method for forming conductive bumps, including the following steps: Provide a semiconductor wafer having a pad mounting surface and a plurality of solders mounted on the pad mounting surface. A photoresist material is used to form an insulating layer on the entire pad mounting surface of the semiconductor wafer, and the insulation layer is formed by using a photomask to expose and chemically rinse to form a plurality of corresponding layers that expose the wafer Perforation in the central part of the pad; forming a covering layer on the insulating layer with a photoresist material so that the perforating system of the insulating layer is covered, and the covering layer is processed by exposure using a photomask and chemical processing A plurality of exposed holes are formed in the central portion of the corresponding pads. The area of the central portion of the pad exposed by each exposed hole is smaller than the area of the central portion of the pad exposed by the perforations; After the exposure holes of the cover layer are formed, each of the exposure holes of the cover layer is filled with a bump forming material so that the bump forming material in each exposure hole is in an appropriate place. As a bump formed on a corresponding solder pad; and removing the cover layer and forming a metal layer on the bump formed on each solder pad by electroplating so that a conductive bump is formed, Each metal layer extends from a corresponding bump to the surface of the corresponding pad. 2. The method according to item 1 of the scope of patent application, wherein in the step of providing a semiconductor wafer, a plating layer is formed on each pad of the wafer. 3. The method as described in item 1 of the scope of patent application, wherein 1241009_ 六、申請專利範圍 形成材料的步驟中,該凸點形成材料是為摻雜有金、 銀、銅、鋁等導電金屬粉末中之任何一種或多種粉末的 導電膠。 4. 如申請專利範圍第1 項所述之方法,其中,在填注凸點 形成材料的步驟中,該凸點形成材料是為無錯錫膏。 5. 如申請專利範圍第1項所述之方法,其中,在填注凸點 形成材料的步驟中,該凸點形成材料是為塑膠材料。 6. —種形成導電凸塊的方法,包含如下之步驟: 提供一半導體晶元,該半導體晶元具有一焊墊安裝 表面及數個安裝於該焊墊安裝表面上的焊墊; 以光阻材料形成一絕緣層於該半導體晶元的整個焊 墊安裝表面上,該絕緣層係藉著使用光罩的曝光和化學 沖洗等處理來形成有數個曝露該晶元之對應之焊墊之中 央部份的穿孔; 於該絕緣層的每一穿孔内形成一具有與該絕緣層之 表面齊平之表面的光阻材料層,該光阻材料層係藉著使 用光罩的曝光和化學沖洗等處理來形成有數個曝露對應 之焊塾之中央部份的曝露孔,由每一曝露孔所曝露之焊 墊之中央部份的面積係比由穿孔所曝露之焊墊之中央部 份的面積小; 在光阻材料層之曝露孔的形成之後,於該光阻材料 層的每一個曝露孔内係填注有凸點形成材料以致於每一 個曝露孔内的凸點形成材料在適當的處理後作為一個形 成於一對應之焊墊上的凸點;及1241009_ VI. Scope of patent application In the step of forming a material, the bump forming material is a conductive adhesive doped with any one or more powders of conductive metal powders such as gold, silver, copper, and aluminum. 4. The method according to item 1 of the scope of the patent application, wherein in the step of filling the bump forming material, the bump forming material is an error-free solder paste. 5. The method according to item 1 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is a plastic material. 6. A method for forming a conductive bump, comprising the steps of: providing a semiconductor wafer having a pad mounting surface and a plurality of pads mounted on the pad mounting surface; using a photoresist The material forms an insulating layer on the entire pad mounting surface of the semiconductor wafer. The insulating layer is formed by using a photomask exposure and chemical processing to form a central portion of the corresponding pad that exposes the wafer. A photoresist material layer having a surface flush with the surface of the insulation layer is formed in each of the perforations of the insulation layer, and the photoresist material layer is processed by exposure using a photomask and chemical processing To form a plurality of exposure holes that expose the central portion of the corresponding welding pad. The area of the central portion of the pad exposed by each exposure hole is smaller than the area of the central portion of the pad exposed by the perforation; After the exposure holes of the photoresist material layer are formed, each of the exposure holes of the photoresist material layer is filled with a bump-forming material so that the bump-forming material in each exposure hole is in an appropriate place. As a bump formed on a corresponding solder pad after processing; and 1241009_ 六、申請專利範圍 把該光阻材料層移去且在形成於每一焊墊上的凸點 上係以電鍍方式形成一金屬層以致於導電凸塊係被形 成,每一金屬層係從一對應的凸點延伸到對應之焊墊的 表面上。 7. 如申請專利範圍第6項所述之方法,其中,在提供半導 體晶元的步驟中,於該晶元的每一個焊墊上係形成有一 電鍍層。 8. 如申請專利範圍第6 項所述之方法,在移去光阻材料層 及形成金屬層的步驟之後,更包含一個把該絕緣層移去 的步驟。 9. 如申請專利範圍第6 項所述之方法,其中,在填注凸點 形成材料的步驟中,該凸點形成材料是為摻雜有金、 銀、銅、鋁等導電金屬粉末中之任何一種或多種粉末的 導電膠。 1 0.如申請專利範圍第6 項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為無< 鉛錫 膏。 1 1.如申請專利範圍第6 項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為塑膠材 料。 1 2. —種形成導電凸塊的方法,包含如下之步驟: 提供一半導體晶元,該半導體晶元具有一焊墊安 裝表面及數個安裝於該焊墊安裝表面上的焊墊; 以光阻材料形成一絕緣層於該半導體晶元的整個1241009_ 6. Scope of patent application: Remove the photoresist material layer and form a metal layer by electroplating on the bumps formed on each pad so that conductive bumps are formed, and each metal layer is formed from a The corresponding bumps extend onto the surface of the corresponding pad. 7. The method according to item 6 of the scope of patent application, wherein in the step of providing a semiconductor wafer, a plating layer is formed on each pad of the wafer. 8. The method as described in item 6 of the scope of patent application, further comprising a step of removing the insulating layer after the steps of removing the photoresist material layer and forming the metal layer. 9. The method according to item 6 of the scope of patent application, wherein in the step of filling the bump-forming material, the bump-forming material is doped with conductive metal powder such as gold, silver, copper, or aluminum. Any one or more powdered conductive adhesives. 10. The method according to item 6 of the scope of patent application, wherein in the step of filling the bump-forming material, the bump-forming material is a lead-free solder paste. 1 1. The method according to item 6 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is a plastic material. 1 2. A method of forming a conductive bump, comprising the steps of: providing a semiconductor wafer having a pad mounting surface and a plurality of pads mounted on the pad mounting surface; The resist material forms an insulating layer throughout the semiconductor wafer. 第26頁 1241009_ 六、申請專利範圍 焊墊安裝表面,該絕緣層係藉著使用光罩的曝光和化 學沖洗等處理來形成有數個曝露該晶元之對應之焊墊 之中央部份的穿孔; 於該絕緣層的每一個穿孔内係填注有凸點形成材 料以致於每一個穿孔内的凸點形成材料在適當的處理 後作為一個形成於一對應之焊墊上的凸點; 把該絕緣層移去; 在該絕緣層被移去之後,於該晶元的整個焊墊安 裝表面上係以光阻材料形成一保護層以致於該等凸點 係被覆蓋,藉著使用光罩的曝光和化學沖洗等處理, 該保護層係形成有數個用於曝露該等凸點的開孔;及 在形成於每一焊墊上的凸點上係以電鍍方式形 成一金屬層以致於導電凸塊係被形成,每一金屬層係 從一對應的凸點延伸到對應之焊墊的表面上。 1 3 .如申請專利範圍第1 2項所述之方法,其中,在提供半、 導體晶元的步驟中,於該晶元的每一個焊墊上係形成 有一電鍍層。 1 4.如申請專利範圍第1 2項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為摻雜有 金、銀、銅、鋁等導電金屬粉末中之任何一種或多種 粉末的導電膠。 1 5.如申請專利範圍第1 2項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為無鉛錫 膏。Page 26 1241009_ VI. Patent application pad mounting surface, the insulation layer is formed by a number of perforations in the central portion of the corresponding pad that exposes the wafer through exposure and chemical processing using a photomask; A bump forming material is filled in each of the through holes of the insulating layer so that the bump forming material in each of the through holes is treated as a bump formed on a corresponding pad after proper processing; Remove; After the insulating layer is removed, a protective layer is formed on the entire pad mounting surface of the wafer with a photoresist material so that the bumps are covered. The protective layer is formed with a plurality of openings for exposing the bumps, such as chemical washing; and a metal layer is formed on the bumps formed on each pad by electroplating so that the conductive bumps are covered. Formed, each metal layer extends from a corresponding bump to the surface of the corresponding pad. 13. The method according to item 12 of the scope of patent application, wherein in the step of providing a semi-conductor wafer, a plating layer is formed on each pad of the wafer. 14. The method according to item 12 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is doped with conductive metal powders such as gold, silver, copper, and aluminum. Any one or more of the powdered conductive adhesives. 15. The method according to item 12 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is a lead-free solder paste. 第27頁 1241009_ 六、申請專利範圍 1 6.如申請專利範圍第1 2項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為塑膠材 料。 1 7 · —種形成導電凸塊的方法’包含如下之步驟: 提供一半導體晶元,該半導體晶元具有一焊墊安 裝表面及數個安裝於該焊墊安裝表面上的焊墊; 以光阻材料形成一絕緣層於該半導體晶元的整個 焊墊安裝表面,該絕緣層係藉著使用光罩的曝光和化 學沖洗等處理來形成有數個曝露該晶元之對應之焊墊 之中央部份的穿孔; 於該絕緣層的每一個穿孔内係填注有凸點形成材 料以致於每一個穿孔内的凸點形成材料在適當的處理 後作為一個形成於一對應之焊墊上的凸點; 把該絕緣層移去;及 在形成於每一焊墊上的凸點上係以電鍍方式形 成一金屬層以致於導電凸塊係被形成,每一金屬層係 從一對應的凸點延伸到對應之焊墊的表面上。 1 8.如申請專利範圍第1 7項所述之方法,其中,在提供半 導體晶元的步驟中,於該晶元的每一個焊墊上係形成 有一電鍍層。 1 9.如申請專利範圍第1 7項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為摻雜有 金、銀、銅、鋁等導電金屬粉末中之任何一種或多種 粉末的導電膠。Page 27 1241009_ VI. Scope of Patent Application 1 6. The method described in item 12 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is a plastic material. 17. A method of forming conductive bumps includes the following steps: providing a semiconductor wafer having a pad mounting surface and a plurality of pads mounted on the pad mounting surface; The resist material forms an insulating layer on the entire pad mounting surface of the semiconductor wafer. The insulating layer is formed by using a photomask exposure and chemical processing to form a central portion of the corresponding pad that exposes the wafer. Each of the perforations of the insulating layer is filled with a bump-forming material so that the bump-forming material in each of the through-holes is treated as a bump formed on a corresponding pad after appropriate processing; Removing the insulating layer; and forming a metal layer on the bumps formed on each pad by electroplating so that a conductive bump system is formed, and each metal layer system extends from a corresponding bump to a corresponding one On the surface of the pad. 18. The method according to item 17 of the scope of patent application, wherein in the step of providing a semiconductor wafer, a plating layer is formed on each pad of the wafer. 19. The method as described in item 17 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is doped with conductive metal powder such as gold, silver, copper, aluminum and the like Any one or more of the powdered conductive adhesives. 第28頁 ^lfi〇9 2〇申T;範圍 ---一' :形項所述之方法,其中,在填注凸 2】:。 r咳凸點形成材料是為無鉛錫 利範圍第〗7項所述之方法,且 22 :。料的步驟中’該凸點形成材料是為塑膠材凸 提ί::2的方法,包含如下之步驟: 袭表命及數^ ΐ晶兀’1亥半導體晶元具有一焊塾安 以ΐΐ:女裝於該焊塾安裝表面上的焊墊; 楚询焊塾安形成一凸點形成層於該半導體晶元的 緣光和化ίϊΐ面,該凸點形成層係藉著使用光罩的 於讀等焊U等處理來使得僅該凸點形成層之對庫 在妒!央部份的部份被留下作為凸點;及 成〜会墊上的凸點上係以電鑛方式形 於導電凸係被形成,每-金屬層俜 23.如申2應的凸點延伸到對應之焊墊的表面上。 =專利範圍第22項所述之方法,其中 卜曰曰元的步驟中,於該晶元的每 T J仏+ 有—電鍍層。 们谇墊上係形成 ^ 、纲、鐵 之任何一種或多種粉末戒 形成。 2點》方法,其中,在形成ΐ ;肩^是由光阻材料或, #牒又之低價金屬粉末1 4 ·如申請專利範圍第2 3項 點形成層的步驟中 雜有如金、銀、銅 石墨等等的光阻材 I® 1241009 六、申請專利範圍 2 5.如申請專利範圍第2 3項所述之方法,其中,在形成金 屬層的步驟中,金屬層係端視凸點的材料而定來以如 塑膠電鍍、無化學電解電鍍等等般之任何適當的電鍍 方式形成。 2 6.如申請專利範圍第2 3項所述之方法,在形成金屬層之 步驟之前,更包含如下之步驟: 以光阻材料形成一絕緣層於該半導體晶元的整個 焊墊安裝表面上俾可覆蓋該等凸點,藉著使用光罩的 曝光和化學沖洗等處理,該絕緣層係形成有數個曝露 對應之凸點的穿孔。 2 7. —種形成導電凸塊的方法,包含如下之步驟: 提供一半導體晶元,該半導體晶元具有一焊墊安 裝表面及數個安裝於該焊墊安裝表面上的焊墊; 以光阻材料形成一凸點形成層於該半導體晶元的 整個焊墊安裝表面上,藉著使用光罩的曝光和化學沖 洗等處理,僅該凸點形成層之對應於該等焊墊之中央 部份的部份被留下作為凸點; 以光阻材料形成一絕緣層於該半導體晶元的整個 焊墊安裝表面上俾可覆蓋該等凸點,藉著使用光罩的 曝光和化學沖洗等處理,該絕緣層係形成有數個曝露 對應之凸點的穿孔;及 在每一凸點上係以電鍍方式形成一金屬層以致於 導電凸塊係被形成,每一金屬層係從一對應的凸點延 伸到對應之焊墊的表面上。Page 28 ^ lfi〇9 2〇 Shin T; Scope --- a ': the method described in the form item, in which the convex 2] :. The cough bump forming material is the method described in item 7 of the lead-free tin range, and 22 :. In the step of the material, the method of the bump formation material is a plastic material: 2: 2 method, including the following steps: Representation and number ^ ΐ crystal Wu'1 Hai semiconductor wafer has a soldering pin to install : Women's pads on the mounting surface of the welding pad; Chu Xun welding pads form a bump forming layer on the edge and the surface of the semiconductor wafer. The bump forming layer is formed by using a photomask. Processing such as reading and welding to make only the pair of the bump formation layer jealous! The part of the central part is left as a bump; and the bumps on the pad are formed in the form of electricity mining. The conductive bumps are formed, and the bumps of each of the metal layers 俜 23.2 should extend to the surface of the corresponding pads. = The method described in item 22 of the patent scope, wherein in the step of Bu Yueyuan, there is a plating layer for each T J 仏 + of the wafer. Any one or more of powder, gangue, iron, or powder is formed on the pad. 2 points "method, wherein, in the step of forming ΐ; the shoulder ^ is made of a photoresist material or, # 牒 又 的 低价 金属 粉 1 4 The layer forming step such as the point 23 of the patent application is mixed with gold and silver Photoresist material I, copper graphite, etc. 1241009 6. Application for patent scope 2 5. The method described in item 23 of the patent application scope, wherein in the step of forming the metal layer, the metal layer is an end-view bump The material is formed by any suitable plating method such as plastic plating, electroless electrolytic plating, and the like. 2 6. According to the method described in item 23 of the patent application scope, before the step of forming the metal layer, the method further includes the following steps: forming an insulating layer on the entire pad mounting surface of the semiconductor wafer with a photoresist material凸 The bumps can be covered, and the insulation layer is formed with a number of perforations that expose the corresponding bumps through exposure using a photomask and chemical processing. 2 7. —A method for forming a conductive bump, comprising the steps of: providing a semiconductor wafer having a pad mounting surface and a plurality of pads mounted on the pad mounting surface; The resist material forms a bump-forming layer on the entire pad mounting surface of the semiconductor wafer. Through the use of photomask exposure and chemical processing, only the central portion of the bump-forming layer corresponds to the pads. A part of the part is left as a bump; a photoresist material is used to form an insulating layer on the entire pad mounting surface of the semiconductor wafer. The bumps can be covered by exposure and chemical processing using a photomask, etc. Processing, the insulating layer is formed with a plurality of perforations that expose corresponding bumps; and a metal layer is formed on each bump by electroplating so that conductive bumps are formed, and each metal layer is formed from a corresponding The bumps extend onto the surface of the corresponding pad. 1241009_ 六、申請專利範圍 2 8 ·如申請專利範圍第2 7項所述之方法,在形成凸點的步 驟之後,更包含一個於該晶元之每一焊墊之在凸點四 周之表面上以電鑛方式形成一電鑛層的步驟。 2 9 .如申請專利範圍第2 7項所述之方法,其中,在形成凸 點形成層的步驟中,該凸點形成層是由光阻材料或摻 雜有如金、銀、銅、鐵、鋁等等般之低價金屬粉末中 之任何一種或多種粉末或塑膠、石墨等等的光阻材料 形成。 3 0.如申請專利範圍第2 7項所述之方法,其中,在形成金 屬層的步驟中,金屬層係端視凸點的材料而定來以如 塑膠電鍍、無化學電解電鍍等等般之任何適當的電鍍 方式形成。 3 1. —種形成導電凸塊的方法,包含如下之步驟: 提供一封裝基體,該封裝基體具有一用於安裝晶 元的安裝表面及一與該安裝表面相對且佈設有數個以 矩陣形式排列之導電接點的佈設表面; 以光阻材料形成一絕緣層於該封裝基體的整個佈 設表面上,該絕緣層係藉著使用光罩的曝光和化學沖 洗等處理來形成有數個曝露該基體之對應之導電接點 的穿孔; 於該絕緣層的每一個穿孔内係填注有凸點形成材 料以致於每一個穿孔内的凸點形成材料在適當的處理 後作為一凸點;及 把該絕緣層移去且在形成於每一導電接點上的凸1241009_ VI. Scope of patent application 2 8 · As described in item 27 of the scope of patent application, after the step of forming a bump, it further includes a surface of each pad on the wafer around the bump. The step of forming an electric ore layer by electric ore. 29. The method according to item 27 of the scope of patent application, wherein in the step of forming the bump forming layer, the bump forming layer is made of a photoresist material or doped with materials such as gold, silver, copper, iron, Any one or more of low-priced metal powders such as aluminum or the like, or a photoresist material made of plastic, graphite, or the like. 30. The method as described in item 27 of the scope of patent application, wherein in the step of forming the metal layer, the end of the metal layer depends on the material of the bumps, such as plastic plating, non-chemical electrolytic plating, etc. Formed by any suitable plating method. 3 1. A method for forming conductive bumps, including the following steps: providing a package base having a mounting surface for mounting a wafer and a plurality of arrays arranged in a matrix opposite to the mounting surface The conductive contact layout surface; a photoresist material is used to form an insulation layer on the entire layout surface of the package substrate. The insulation layer is formed by exposing using a photomask and chemical washing to form a number of exposed substrates. Corresponding to the perforation of the conductive contact; each of the perforations of the insulating layer is filled with a bump-forming material so that the bump-forming material in each perforation is treated as a bump after proper processing; and the insulation The layer is removed and the bumps formed on each conductive contact 第31頁 1241009 六、申請專利範圍 點上係以電鍍方式形成一金屬層以致於導電凸塊係被 形成,每一金屬層係從一對應的凸點延伸到對應之導 電接點的表面上。 / 3 2.如申請專利範圍第3 1項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為摻雜有 金、銀、銅、鋁等導電金屬粉末中之任何一種或多種 粉末的導電膠。 3 3.如申請專利範圍第3 1項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為無鉛錫 膏。 3 4.如申請專利範圍第3 1項所述之方法,其中,在填注凸 點形成材料的步驟中,該凸點形成材料是為塑膠材 料。 3 5. —種形成導電凸塊的方法,包含如下之步驟: 提供一封裝基體,該封裝基體具有一用於安裝晶 元的安裝表面及一與該安裝表面相對且佈設有數個以 矩陣形式排列之導電接點的佈設表面; 以光阻材料形成一凸點形成層於該封裝基體的整 個佈設表面上,藉著使用光罩的曝光和化學沖洗等處 理,僅該凸點形成層之對應於該等導電接點之中央部 份的部份被留下作為凸點;及 在凸點的形成之後,在每一凸點上係以電鍍方式 形成一金屬層以致於導電凸塊係被形成,每一金屬層 係從一對應的凸點延伸到對應之導電接點的表面上。Page 31 1241009 6. Scope of patent application: A metal layer is formed by electroplating so that conductive bumps are formed. Each metal layer extends from a corresponding bump to the surface of a corresponding conductive contact. / 3 2. The method according to item 31 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is doped with a conductive metal such as gold, silver, copper, or aluminum Any one or more powdered conductive pastes in the powder. 3 3. The method according to item 31 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is a lead-free solder paste. 34. The method according to item 31 of the scope of patent application, wherein in the step of filling the bump forming material, the bump forming material is a plastic material. 3 5. —A method for forming conductive bumps, including the following steps: Provide a package base having a mounting surface for mounting wafers and a plurality of arrays arranged in a matrix opposite to the mounting surface The surface of the conductive contact layout; a photoresist material is used to form a bump formation layer on the entire layout surface of the package substrate. By using a photomask exposure and chemical processing, only the bump formation layer corresponds to A portion of the central portion of the conductive contacts is left as a bump; and after the bumps are formed, a metal layer is formed on each of the bumps by electroplating so that the conductive bumps are formed, Each metal layer extends from a corresponding bump to the surface of a corresponding conductive contact. 1241009__ 六、申請專利範圍 3 6.如申請專利範圍第3 5項所述之方法,其中,在形成凸 點形成層的步驟中,該凸點形成層是由光阻材料或摻 雜有如金、銀、銅、鐵、鋁等等般之低價金屬粉末中 之任何一種或多種粉末或塑膠、石墨等等的光阻材料 形成。 3 7.如申請專利範圍第3 5項所述之方法,其中,在形成金 屬層的步驟中,金屬層係端視凸點的材料而定來以如 塑膠電鍍、無化學電解電鍍等等般之任何適當的電鍍 方式形成。 3 8. —種形成導電凸塊的方法,包含如下之步驟: 提供一封裝基體,該封裝基體具有一用於安裝晶 元的安裝表面及一與該安裝表面相對且佈設有數個以 矩陣形式排列之導電接點的佈設表面; 以導電膠為材料,藉由使用一鋼板的印刷方法, 於該基體之每一導電接點上係形成有一凸點;及 在形成於每一導電接點上的凸點上係以電鍍方式 形成一金屬層以致於導電凸塊係被形成,每一金屬層 係從一對應的凸點延伸到對應之導電接點的表面上。 3 9. —種具有導電凸塊的裝置,包含: 一半導體晶元,該半導體晶元具有一焊墊安裝表 面'及數個安裝於該焊墊安裝表面上的焊墊;及 數個各形成於一對應之焊墊之中央部份上的導電 凸塊,每一導電凸塊包括一形成於一對應之焊墊上的 凸點及一形成於該對應之凸點上且從該對應之凸點延1241009__ VI. Patent Application Range 3 6. The method according to item 35 of the patent application range, wherein in the step of forming the bump forming layer, the bump forming layer is made of a photoresist material or doped with gold, Any one or more of low-priced metal powders such as silver, copper, iron, aluminum, etc., or a photoresist material made of plastic, graphite, etc. 37. The method according to item 35 of the scope of patent application, wherein in the step of forming the metal layer, the end of the metal layer depends on the material of the bumps, such as plastic plating, electroless electroless plating, etc. Formed by any suitable plating method. 3 8. —A method for forming a conductive bump, comprising the steps of: providing a package base having a mounting surface for mounting a wafer and an array surface arranged opposite to the mounting surface and arranged in a matrix form The conductive contact layout surface; a conductive adhesive is used as a material, and a bump is formed on each conductive contact of the substrate by a printing method using a steel plate; and the conductive contact is formed on each conductive contact A metal layer is formed on the bumps by electroplating so that conductive bumps are formed. Each metal layer extends from a corresponding bump to the surface of a corresponding conductive contact. 3 9. A device having a conductive bump, comprising: a semiconductor wafer having a pad mounting surface 'and a plurality of pads mounted on the pad mounting surface; and a plurality of each formed A conductive bump on a central portion of a corresponding solder pad, each conductive bump includes a bump formed on a corresponding solder pad and a bump formed on and from the corresponding bump Delay 1241009 六、申請專利範圍 伸到對應之焊塾之表面上的金屬層。 4 0.如申請專利範圍第3 9項所述之裝置,其中,於該晶元 之每一個焊墊上係形成有一電鑛層。 4 1 .如申請專利範圍第3 9項所述之裝置,其中,該等凸點 係由摻雜有如金、銀、銅、鋁等等般之導電金屬粉末 中之任何一種或多種粉末的導電膠形成。 4 2.如申請專利範圍第3 9項所述之裝置,其中,該等凸點 係由無錯錫膏形成。 4 3.如申請專利範圍第3 9項所述之裝置,其中,該等凸點 係由塑膠材料形成。 4 4.如申請專利範圍第3 9項所述之裝置,其中,該等凸點 係由光阻材料形成。 4 5.如申請專利範圍第3 9項所述之裝置,其中,該等凸點 係由摻雜有如金、銀、銅、鐵、鋁等等般之低價金屬 粉末中之任何一種或多種粉末或塑膠、石墨等等般的 光阻材料形成。 4 6.如申請專利範圍第3 9項所述之裝置,更包含一形成於 該晶元之焊墊安裝表面的絕緣層,該絕緣層具有數個 曝露對應之金屬凸塊的穿孔,每一金屬凸塊的金屬層 係從一對應之凸點延伸到對應之焊墊的表面上。 4 7. —種具有導電凸塊的裝置,包含: 一半導體晶元,該半導體晶元具有一焊墊安裝表 面及數個安裝於該焊墊安裝表面上的焊墊; 數個各形成於一對應之焊墊之中央部份上的凸1241009 6. Scope of patent application The metal layer extended to the surface of the corresponding welding pad. 40. The device according to item 39 of the scope of patent application, wherein an electric ore layer is formed on each pad of the wafer. 41. The device according to item 39 of the scope of patent application, wherein the bumps are conductively doped with any one or more powders of conductive metal powders such as gold, silver, copper, aluminum, etc. Gum formation. 4 2. The device according to item 39 of the scope of the patent application, wherein the bumps are formed of an error-free solder paste. 4 3. The device according to item 39 of the scope of patent application, wherein the bumps are formed of a plastic material. 4 4. The device according to item 39 of the scope of patent application, wherein the bumps are formed of a photoresist material. 4 5. The device according to item 39 of the scope of patent application, wherein the bumps are made of any one or more of low-priced metal powders such as gold, silver, copper, iron, aluminum, etc. Powder or plastic, graphite and other photoresist materials. 4 6. The device according to item 39 of the scope of the patent application, further comprising an insulating layer formed on the mounting surface of the pad of the wafer, the insulating layer having a plurality of perforations exposing the corresponding metal bumps, each The metal layer of the metal bump extends from a corresponding bump to the surface of the corresponding pad. 4 7. —A device with conductive bumps, comprising: a semiconductor wafer having a pad mounting surface and a plurality of pads mounted on the pad mounting surface; a plurality of each formed on a The convex part on the central part of the corresponding pad 1241009 六、申請專利範圍 點:及 數個金屬層,每一金屬層係形成於一對應之凸點 上且係從該對應之凸點延伸到對應之焊墊的表面上, 每一金屬層與對應的凸點共同形成一導電凸塊。 4 8.如申請專利範圍第4 7項所述之裝置,更包含數個電鍍 層,每一電鍍層係形成於一對應之焊墊之在凸點四周 的表面上。 4 9.如申請專利範圍第4 7項所述之裝置,更包含一絕緣1241009 6. Scope of patent application: and several metal layers, each metal layer is formed on a corresponding bump and extends from the corresponding bump to the surface of the corresponding pad, each metal layer and The corresponding bumps together form a conductive bump. 4 8. The device according to item 47 of the scope of patent application, further comprising a plurality of electroplated layers, each of which is formed on a surface of a corresponding solder pad around the bump. 4 9. The device described in item 47 of the scope of patent application, further comprising an insulation 層,該絕緣層係形成於該晶元的焊墊安裝表面上且具 有數個用於曝露對應之導電凸塊的穿孔。 5 0. —種具有導電凸塊的裝置,包含: 一封裝基體,該封裝基體具有一用於安裝晶元的 安裝表面及一與該安裝表面相對且佈設有數個以矩陣 形式排列之導電接點的佈設表面;及 數個各形成於該基體之一對應之導電接點上的導 電凸塊,每一導電凸塊包括一形成於一對應之導電接 點上的凸點及一形成於該對應之凸點上且從該對應之 凸點延伸到對應之導電接點之表面上的金屬層。The insulating layer is formed on the pad mounting surface of the wafer and has a plurality of through holes for exposing the corresponding conductive bumps. 5 0. A device with conductive bumps, comprising: a package base having a mounting surface for mounting a wafer and a plurality of conductive contacts arranged in a matrix form opposite to the mounting surface And a plurality of conductive bumps each formed on one of the conductive contacts corresponding to the base, each conductive bump including a bump formed on a corresponding conductive contact and a bump formed on the corresponding A metal layer on the bump and extending from the corresponding bump to the surface of the corresponding conductive contact. 5 1.如申請專利範圍第5 0項所述之裝置,其中,該等凸點 係由摻雜有金、銀、銅、鋁等等般之導電金屬粉末中 之任何一種或多種粉末的導電膠形成。 5 2.如申請專利範圍第5 0項所述之裝置,其中,該等凸點 係由無鉛錫膏形成。 5 3.如申請專利範圍第5 0項所述之裝置,其中,該等凸點51. The device as described in item 50 of the scope of patent application, wherein the bumps are conductively doped with any one or more powders of conductive metal powders such as gold, silver, copper, aluminum and the like. Gum formation. 5 2. The device according to item 50 of the scope of patent application, wherein the bumps are formed of a lead-free solder paste. 5 3. The device as described in item 50 of the scope of patent application, wherein the bumps 第35頁 T24100Q_ 六、申請專利範圍 係由塑膠材料形成。 5 4.如申請專利範圍第5 0項所述之裝置,其中,該等凸點 係由光阻材料形成。 5 5.如申請專利範圍第5 0項所述之裝置,其中,該等凸點 係由摻雜有如金、銀、銅、鐵、鋁等等般之低價金屬 粉末中之任何一種或多種粉末或塑膠、石墨等等般的 光阻材料形成。Page 24 T24100Q_ VI. Scope of patent application It is made of plastic materials. 54. The device according to item 50 of the scope of patent application, wherein the bumps are formed of a photoresist material. 5 5. The device according to item 50 of the scope of patent application, wherein the bumps are made of any one or more of low-priced metal powders such as gold, silver, copper, iron, aluminum, etc. Powder or plastic, graphite and other photoresist materials. 第36頁Page 36
TW92112165A 2002-11-22 2003-05-02 Method for forming conductive bump and device having such made conductive bump TWI241009B (en)

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